PIC18F25K80-E/SS - Microchip Technology

 2011 Microchip Technology Inc. DS80519D-page 1

PIC18F66K80

The PIC18F66K80 family devices that you have

received conform functionally to the current Device

Data Sheet (DS39977D), except for the anomalies

des c ribed in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata describ ed in this document will be addressed

in future revisions of the PIC18F66K80 s ilicon.

Data Sheet clarifications and corrections start on

page 8, following the discussion o f silicon issues.

The silicon revision level can be identified using the

current version of MPLAB® IDE and Microchip’s pro-

grammers, debuggers and emulation tools, which are

available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 3 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 3 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debug ger >Se le ct Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect). Depending on the devel-

opment tool used, the part number and Device

Revisio n ID valu e appear in th e Output window.

The DEVREV values for the various PIC18F66K80

silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A4). Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID(1)Revision ID for Silicon Revision(2)

A2 A3 A4

PIC18F66K80 60E0

2h 3h 4h

PIC18F65K80 6140

PIC18F46K80 6100

PIC18F45K80 6160

PIC18F26K80 6120

PIC18F25K80 6180

PIC18LF66K80 61C0

PIC18LF65K80 6220

PIC18LF46K80 61E0

PIC18LF45K80 6240

PIC18LF26K80 6200

PIC18LF25K80 6260

Note 1: The Devi ce IDs (DEVID and DEVREV) are located at the last two implemented addresses of con f iguration

memory sp ace. They are shown in hexadecimal in the format, “DEVID DEVREV”.

2: Refer to the “PIC18F66K80 Flash Programming Specification” (DS39972) for detailed information on

Device and Revision IDs fo r your specific device.

PIC18F66K80 Family

Silicon Errata and Data Sheet Clarification

PIC18F66K80

DS80519D-page 2  2011 Microchip Technology Inc.

TABLE 2: SILICON ISSUE SUMMARY

Module Feature Item

Number Issue Summary Affected Revisions(1)

A2 A3 A4

Analog-to-Digit al

Converter (A/D) A/D

Performance 1. The 12-bit A/D performance is outside of

data sheet’s A/D Converter specificatio ns. XXX

EUSART Synchronous

Transmit 2. When using the Synchronous Transmit

mode, transmitted data may become cor-

rupted if using the TXxIF bit to determine

when to load the TXREGx register.

ECCP Auto-Shutdown 3. The tri-st ate setting of the auto-shu t down

feature in the enhanced PWM wil l not

successfully driv e the pin to tri-st ate.

XXX

ECAN CAN Clock

Source Selection 4. CLKSEL bit in the CIOCON register is

modifiable while the ECAN module is

active.

Ultra Low-Power

Sleep Sleep Entry 5. Entering Ultra Low-Power Sleep mode by

setting RETEN = 0 and SRETEN = 1, will

cause the part to not be program mable

through ICSP™.

IPD and IDD Ma ximum Limit 6. Maximum current lim it s may be higher

than specified in Table 31-2 of the dat a

sheet.

Reset (BOR) Enable/Disable

An unexpected Rese t may occur if the

Brown-out Reset module (BOR) is dis-

abled, and then re-enabled, when the

High/Low-Voltage Detectio n module

(HLVD) is not enabl ed

(HLVDCON<4> = 0).

XXX

ECAN EWIN 8. The enhanced windo w address feature,

EWIN<4:0>, in the ECANCON register , will

not move the BnC ON 0<n<5 registers into

the access wi ndow of RAM.

MCLRE Master Clear

Enable 9. The Master Clear pin will not be readabl e

when MCLRE is set to of f for all 28-pin part

variants (PIC18F2XK80).

XXX

Timer1/

Timer3 Gated Enable 10. Timer1 and Ti me r3 gate co ntrol will not

function up to the spe ed of FOSC when the

TxCON is set to the sy stem c lock

(TxCON<7:6> = 01).

Note 1: Only those issues indi cated in the la st colum n apply to the c urre nt silico n revision .

 2011 Microchip Technology Inc. DS80519D-page 3

PIC18F66K80

Silicon Errata Issues

1. Mo dule: Analog- to-Digital Converter (A/D)

The 12-bit A/D performance is outside of the

data sheet’s A/D Converter specifications.

When used as a 12-bit A/D, the possible issues

are high offset error, up to a maximum of

±25 LSB s; high DNL err or, up to a m aximum of

+6.0/-4.0 LSBs; and multiple missing codes, up

to a maximum of twenty. Users should ev aluate

the 12-bit A/D performance in their application

using the suggested work around below. See

Table 3 for guidance specifications.

The 12-bit A/D issues will be fixed in future

revisions of this part. Reduced bit resolution

specifications can be derived by dividing, as

appropriate. For instance, 10-bit guidance is

obtained by dividing the parameters in Table 3

by four.

A/D Offset

The A/D may have high offset error, up to a

maximum of ± 25 LSB s ; it can be use d i f t he A/D

is calibrated for the offs et.

Work around

Calibrate for offset in Single-Ended mode by

connecting A/D +ve input to ground and taking

the A/D reading. This will be the offset of the

device and can be used to compensate for the

subseq uen t A / D read in gs on the actual inputs.

TABLE 3: A/D CONVERTER CHARACTERISTICS

Affected Silicon Revisions

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (A4).

Param

No. Sym Characteristic Min Typ Max Units Conditions

A01 NRResolution — — 12 bit VREF  5.0V

A03 EIL Integral Linearity Error — — ±10.0 LSb VREF  5.0V

A04 EDL Differential Linearity Error — — +6.0/-4.0 LSb VREF  5.0V

A06 EOFF Offset Error — — ±25 LSb VREF  5.0V

A07 EGN Gain Error — — ±15 LSb VREF  5.0V

A10 — Monotonicity(1)—VSS  VAIN VREF

A20 VREF Reference Voltage Range

(VREFH – VREFL)3—AV

DD – AVSS V

A21 VREFH Reference Voltage High AVSS + 3.0V — AVDD + 0.3V V

A22 VREFL Reference Voltage Low AVSS – 0.3V — AVDD – 3.0V V

A25 VAIN Analog Input Voltage VREFL —VREFH V

Note 1: The A/D convers io n resul t neve r decre as es with an inc r ea se in the inp ut vol t ag e .

A2 A3 A4

XXX

PIC18F66K80

DS80519D-page 4  2011 Microchip Technology Inc.

2. Module: EUSART

In Synchronous T ransmit mode, data may be cor-

rupted if using the TXxIF bit to determine when to

load the TXREGx register. One or more of the

intended transmi t messa ges ma y be inco rrec t.

Work around

A fixed de lay added before load ing the TXR EGx

may not be a reliable work around. When load-

ing the T XREGx, ch eck that the TRMT bit insid e

of the TXSTAx register is set instead of ch ecking

the TXxIF bit. The following code can be used:

while(!TXSTAxbits.TRMT);

// wait to lo ad TXREG x unti l TRMT i s set

Affected Silicon Revisions

3. Module: ECCP

The tri-state setting of the auto-shutdown

featur e, in the enhanced PWM, will not success-

fully dri ve the pin to tri-state . The pin w i ll rem ai n

an outpu t and should not b e driven externally. All

tri-state settings will be affected.

Work around

Use one of the other two auto-shutdown states

available, as outlined in the data sheet.

Affected Silicon Revisions

4. Module: ECAN

The CLKSEL bit in the CIOCON register rema ins

modifiable while the ECAN module is not in Con-

figuration mode. Accidental state changes of this

bit will result in immediate bit clock changes that

will affe ct all nodes on the bus.

Work around

While the ECAN module is in Run mode, do not

modify the state of the CLKSEL bit in the

CIOCO N register unl ess the C AN modul e is first

changed into Configuration mode.

Affected Silicon Revisions

5. Module: Ultra Low-Power Sleep

Entering Ultra Low-Power Sleep mode by setting

RETEN = 0 and SRETEN = 1, w ill caus e the p art

to not be programm able through ICSP. This is sue

occurs when the RETEN fuse bit in

CONFIG1L<0> is cleared to ‘0’, the SRETEN bit

in the WDTCON register is s et to ‘1’ and a SLEEP

instruction is executed within the first 350 s of

code execution. This happens after a Reset

event, causing the part to enter Ultra Low-Power

Sleep mode.

Work around

Use norm al Sleep and Low -Power Sleep modes

only, or on any Reset, ensure that at least

350 s passes before executing a SLEEP

instr u cti o n wh e n ULP is ena bl e d. To ensu r e t he

Ultra Low-Po wer Sleep mode is not enabled, the

RETEN fuse bit in CONFIG1L<0> should be set

to a ‘1’, and the SRETEN bit in the WDTCON

code can be used:

//This will ensure the RETEN fuse is set to 1

#pragma config RETEN = OFF

//This will ensure the SRETEN bit is 0

WDTCONbits.SRETEN = 0;

If the Ultra Low-Power Sleep mode is needed,

then the user must ensure that the minimum

time, before the first SLEEP instruction is

execute d, is grea ter than 350 s.

Affected Silicon Revisions

A2 A3 A4

XXX

A2 A3 A4

 2011 Microchip Technology Inc. DS80519D-page 5

PIC18F66K80

6. Module: IPD and IDD

The IPD and IDD limits do not match the data

sheet. The IPD values, shown in bold in

Section 31.2 “DC Characteristics: Power-

Down and Supply Current PIC18F66K80

Family (Industrial/Extended)” (below), reflect

the updated silicon maximum limits.

All IDD maximum limits will equal 2.8 times the

value lis ted in the data sheet.

Affected Silicon Revisions

A2 A3 A4

31.2 DC Characteristi cs: Power-Down and Supply Current

PIC18F66K80 Family (Industrial/Extended)

PIC18F66K80

(Industrial/Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Device Typ Max Units Conditions

Power-Down Current (IPD)(1)

PIC18LFXXK80 0.008 7µA -40°C

VDD = 1.8V(4)

(Sleep mode)

Regulator Disabled

0.013 7µA +25°C

0.035 9µA +60°C

0.218 10 µA +85°C

312 µA ±125ºC

PIC18LFXXK80 0.014 8µA -40°C

VDD = 3.3V(4)

(Sleep mode)

Regulator Disabled

0.034 8µA +25°C

0.092 9µA +60°C

0.312 10 µA +85°C

416 µA ±125ºC

PIC18FXXK80 0.2 9µA -40°C VDD = 3.3V

(Sleep mode)

Regulator Enabled

0.23 9µA +25°C

0.32 10 µA +60°C

0.51 11 µA +85°C

518 µA ±125ºC

PIC18FXXK80 0.22 10 µA -40°C

VDD = 5V(5)

(Sleep mode)

Regulator Enabled

0.24 10 µA +25°C

0.34 11 µA +60°C

0.54 12 µA +85°C

520 µA ±125ºC

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the

part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta

current disabled (such as WDT, SOSC oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: For LF devices, RETEN (CONFIG1L<0>) = 1.

5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.

PIC18F66K80

DS80519D-page 6  2011 Microchip Technology Inc.

7. Module: Reset (BOR)

An unex pecte d Reset may occur i f the B rown-

out Rese t module (BOR) is disabled, and then

re-enabled, when the High/Low-Voltage

Detection module (HLVD) is not enabled

(HLVDCON<4> = 0). This issue affects

BOR modes: BOREN<1:0> = 10 and

BOREN<1:0> = 01. In both of these modes, if

the BOR module is re-enabled while th e device is

active, unexpected Resets may be generated.

Work around

If BOR is required and power consumptio n is not

an issue, use BOREN<1:0> = 11. For

BOREN<1:0> = 10 mode, either switch to

BOREN<1:0> = 11 mode or enable the HLVD

(HLVDCON<4> = 1) prior to entering Sleep. If

power co nsumption is an is sue and low powe r is

desired, do not use BOREN<1:0> = 10 mode.

Instead, use BOREN<1:0> = 01 and follow the

steps below when entering and exiting Sleep.

1. Disab le BOR by cl eari ng SBORE N

(RCON<6> = 0).

WDTCON bi ts .S BO RE N = 0;

2. Enter Sleep mode (if desired).

Sleep();

3. After e xiting Sleep mode (if ente red) , enable th e

HLVD bit (HLVDCON<4> = 1).

HLVDCONbits.HLVDEN = 1;

4. Wait for the internal reference voltage (TIRVST)

to st abi li ze (typ ic all y 25 s).

while(!HLVDCONbits.IRVST);

5. Re-enable BOR by setting SBOREN

(RCON<6> = 1).

WDTCON bi ts .S BO RE N = 1;

6. Disable the HLVD by clearing HLVDEN

(HLVDCON<4> = 0).

HLVDCONbits.HLVDEN = 0;

Affected Silicon Revisions

8. Module: ECAN

The enhanced window address feature,

EWIN<4:0>, in the ECANCON register, will not

move the BnCON 0<n<5 registers into the

acces s window of RAM. Th e rest of the re gisters

in B0 through B5 will be transferred into the

access bank successfully. This feature is only

available in Mode 1 and Mode 2; Mode 0

applications will not be affected.

Work around

1. Set the ECANCON register EWIN bits to the

desired buffer .

ECANCONbits.EWIN = Buffer_Selection;

2. Decode the desired buffer to each individual

Buffer Control register, BnCON 0<n<5.

switch( Buffer_Selection )

{

//EWIN code for Buffer B0

case 18:

break;

//EWIN code for Buffer B5

case 23:

break;

default:

break;

}

3. Process information in the selected buffer

control register. Note that the BnCON 0<n<5

Control registers can be set up for either

transmit or receive operations.

case 18:

//Save B0CON and clear flags

being processed

temp = B0CON;

//clear any flags

break;

4. Continue processing the rest of the buffer in the

windowed loca tion.

Affected Silicon Revisions

A2 A3 A4

XXX

A2 A3 A4

 2011 Microchip Technology Inc. DS80519D-page 7

PIC18F66K80

9. Module: MCLRE

The Master Clear pin will not be readable when

MCLRE is set to off for all 28-pin part variants

(PIC18F2XK80). When the MCLRE bit,

CONFIG3H<7>, is cleared on 28-pin devices,

the MC LR pin will be disabled but input data will

not be available on RE3.

Work around

None.

Affected Silicon Revisions

10. Module: Timer1/Timer3

Timer1 and Timer3 gate control will not function

up to the speed of FOSC when the TxCON is set

to the system c lock (T xCON <7:6> = 01). Results

will always be at the resolution of FOSC/4,

although the internal FOSC has been selected as

the clock source.

Work around

Use the external clock input pin setting,

TxCON<7:6> = 10 and TxCON<3> = 0.

Affected Silicon Revisions

A2 A3 A4

XXXA2 A3 A4

PIC18F66K80

DS80519D-page 8  2011 Microchip Technology Inc.

Data Sheet Clarifications

The foll owing ty pographic corrections and clar ification s

are to be note d fo r the latest version of th e device data

sheet (DS39977D):

1. Module: RXFCON Registers

Table 6-1 o n Pag e 116 of the Da ta Sh eet sh oul d

show the fol lowi ng r egi ste r addres s es:

E47h-RXFCON1

E46h-RXFCON0

2. Module: RXFCON Registers

Table 6-2 on Pag e 125 of the Da ta Sheet sh ould

show the fol lowi ng r egi ste r addres s es:

E47h-RXFCON1

E46h-RXFCON0

3. M odule: Listen Only Mode

Page 441, Section 27 .3.4 “ Liste n O nly Mode ”

will be revised to:

Listen Only mode provides a means for the

PIC18F66K80 family devices to receive all mes-

sages, including messages with errors. This

mode can be used for bus monitor applications

or for detecting the baud rate in ‘hot plugging’

situati ons. For Auto-Baud D etecti on, it is neces-

sary that there are at least two other nodes

which are communicating with each other. The

baud rate c an be dete cted em piric ally by testin g

different values until valid messages are

received. The Listen Only mode is a silent

mode, me aning no messag es will be transmitte d

while in this state, including error flags or

Acknowledge signals. In Listen Only mode,

both valid and invalid messages will be

received regardless of RXMn bit settings.

The filters and masks can still be used to

allow only particular valid messages to be

loaded into the Receive registers, or the filter

masks can be set to al l zeros to allow a mes-

sage with any identifier to pass. All invalid

messages will be received in this mode,

regardless of filters and masks or RXMn

Receive Buffer mode bits. T he e rror coun ters

are reset and deactivated in this state. The

Listen Only mode is activated by setting the

mode request bits in the CANCON register.

Note: Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

 2011 Microchip Technology Inc. DS80519D-page 9

PIC18F66K80

4. Module: A/D Converter Characteristics

The values in Table 31-25 reflect the updated A/D

Conv erter C haracte ristic s. The new in formati on is

shown in bold text.

TABLE 31-25: A/D CONVERTER CHARACTERISTICS: PIC18F66K80

(INDUSTRIAL/EXTENDED)

5. Module: HLVD

Note 1 under Register 26-1: HLVDCON, on

page 387, should direct to Parameter D420:

Note 1: For the electrical specifications, see Parameter D420 in Section 31.0 “Electrical Characteristics”.

6. Module: Power-up Timer Period

Table 31-11 on page 572 of the data sheet,

Parameter 33 TPWRT will be revised to a typical value

of 1.0 ms.

Param

No. Sym Characteristic Min Typ Max Units Conditions

A01 NRResolution — — 12 bit VREF  5.0V

A03 EIL I ntegral Linearity Error — <±1 ±6.0 LSB VREF 5.0V

A04 EDL Differential Linearity Error — <±1 +3.0/-1.0 LSB VREF 5.0V

A06 EOFF Offset Error — <±1 ±9.0 LSB VREF 5.0V

A07 EGN Gain Error — <±1 ±8.0 LSB VREF 5.0V

A10 — Monotonicity(1)——VSS  VAIN  VREF

A20 VREF Reference Voltage Range

(VREFH – VREFL)3—V

DD – VSS V For 12-bit resolution

A21 VREFH Reference Voltage High AVSS + 3.0V — AVDD + 0.3V V For 12-bit resolution

A22 VREFL Reference Voltage Low AVSS – 0.3V — AVDD – 3.0V V For 12-bit resolution

A25 VAIN Analog Input Voltage VREFL —VREFH V

A28 AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V

A29 AVSS Analog Supply Voltage VSS – 0.3 — VSS + 0. 3 V

A30 ZAIN Recommended

Impedance of Analog

Voltage Source

——2.5k

A50 IREF VREF Input Current(2) —

——

—5

150 A

ADuring VAIN acquis it ion.

During A/D con version cycl e.

Note 1: The A/D conversion result never decreases with an increase in the input voltage.

2: VREFH current is from the RA3/AN3/V REF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from

the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.

PIC18F66K80

DS80519D-page 10  2011 Microchip Technology Inc.

APPENDIX A: DOCUMENT

REVISION HISTORY

Rev A Document (2/2011)

Initial release of this document; issued for revision,

A2. Includes silicon issues 1 (Analog-to-Digital Con-

verter), 2 (EUSART), 3 (ECCP), 4 (ECAN), 5 (Ultra

Low-P ower Sl ee p) and 6 ( IPD and IDD).

Rev B Document (4/2011)

Added sil ico n is sue s 7 (Re set – BOR) an d 8 (EC AN ).

Added data sheet clarifications 1, 2 (RXFCON

Registe rs ) and 3 (L ist en Only Mod e) .

Rev C Document (9/2011)

Adde d Table 3, 10-Bit A/D Converter Characteristics

to silicon issue 1 (Analog-to-Digital Converter). Added

silicon issues 9 (MCLRE) and 10 (Timer1/Timer3).

Added data sheet clarifications 4 (A/D Converter

Characteristics) and 5 (HLVD).

Rev D Document (12/2011)

Added silicon revision A4; includes issues 1 (Analog-

to-Digit al Converter – A/D), 3 (ECCP), 7 (Reset – BOR)

issues 9 (MCLRE). Added data sheet clarification

6 (Power-up Timer Period).

Update d data sheet re vision leve l to “D”. Al l previous

clarifi catio ns car rie d int o th is revi sio n.

 2011 Microchip Technology Inc. DS80519D-page 11

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce

and may be supers eded by updates . I t is you r r es ponsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPL AB, PIC , PIC micro, PI C START,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, M XLA B, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance , TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-879-6

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS80519D-page 12  2011 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasc a , IL

Tel: 630-285-0071

Fax: 630-285-0075

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Osaka

Tel: 81-66-152-7160

Fax: 81-66-152-9310

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Ka ohs iung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangko k

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Worldwide Sales and Service

11/29/11