Products and specifications discussed herein are subject to change by Micron without notice.
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Features
PDF: 09005aef80e119b2/Source: 09005aef80e11976 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
DD9C16_32_64x72.fm - Rev. D 1/08 EN 1©2003 Micron Technology, Inc. All rights reserved.
DDR SDRAM RDIMM
MT9VDDT1672 – 128MB1
MT9VDDT3272 – 256MB2
MT9VDDT6472 – 512MB2
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 184-pin, registe red dual in-line memory module
(RDIMM)
• Tall and standard height PCB modules
• Fast data transfer rates: PC2100 or PC2700
• 128MB (16 Meg x 72), 256MB (32 Meg x 72), and
512MB (64 Meg x 72)
• Supports EC C error detection and correction
•V
DD = VDDQ = +2.5V
VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pi pelined double data rate (DDR)
2n-prefetch architectur e
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-sy nchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Si n gle rank
• Selectab le burst lengths (BL): 2, 4, or 8
• Auto precharge option
• A uto refresh and self refresh modes: 15.625µs
(128MB) and 7.8125µs (256MB and 512MB)
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge cont acts
184-Pin RDIMM Figures
Figure 1: Tall-Height Layout
(MO-206-EA R/C A)
Figure 2: Standard-Height Layout
(MO-206-CA R/C L)
Notes: 1. End of life.
2. Not recommended for new designs.
3. Contact Micron for industrial temperature
module offerings.
4. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
Options Marking
• Operating temperature3
–Commercial (0°C ≤ TA ≤ +70°C) None
–Industrial (–40°C ≤ TA ≤ +85°C) I
•Package
–184-pin DIMM (standard) G
–184-pin DIMM (Pb-free) Y
• Memory clock, sp eed, CAS latency4
–6.0ns (167 MHz), 333 MT/s, CL = 2.5 -335
–7.5ns (133 MHz), 266 MT/s, CL = 2.0 -262
–7.5ns (133 MHz), 266 MT/s, CL = 2.0 -26A
–7.5ns (133 MHz), 266 MT/s, CL = 2.5 -265
PCB height: 43.18mm (1.7in)
P
CB height: 30.48mm (1.2in)
PDF: 09005aef80e119b2/Source: 09005aef80e11976 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
DD9C16_32_64x72.fm - Rev. D 1/08 EN 2©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Features
Notes: 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT9VDDT3272G-335G3.
Table 1: Key Timing Parameters
Speed
Grade Industry
Nomenclature
Data Rate (MT/s) tRCD
(ns) tRP
(ns) tRC
(ns) NotesCL = 2.5 CL = 2
-335 PC2700 333 266 18 18 60 1
-262 PC2100 266 266 15 15 60
-26A PC2100 266 266 20 20 65
-265 PC2100 266 200 20 20 65
Table 2: Addressing
Parameter 128MB 256MB 512MB
Refresh count 4K 8K 8K
Row address 4K (A0–A11) 8K (A0–A12) 8K (A0–A12)
Device bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Device configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8)
Column address 1K (A0–A9) 1K (A0–A9) 2K (A0–A9, A11)
Module rank address 1 (S0#) 1 (S0#) 1 (S0#)
Table 3: Part Numbers and Timing Parameters – 128MB Modules
Base device: MT46V16M8,1 128Mb DDR SDRAM
Part Number2Module
Density Configuration Module
Bandwidth Memory Clock/
Data Rate Clock Cycles
(CL-tRCD-tRP)
MT9VDDT1672G-335__ 128MB 16 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 3-3-3
MT9VDDT1672Y-335__ 128MB 16 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 3-3-3
MT9VDDT1672G-26A__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDT1672G-265__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDT1672Y-265__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
Table 4: Part Numbers and Timing Parameters – 256MB Modules
Base device: MT46V32M8,1 256Mb DDR SDRAM
Part Number2Module
Density Configuration Module
Bandwidth Memory Clock/
Data Rate Clock Cycles
(CL-tRCD-tRP)
MT9VDDT3272G-335__ 256MB 32 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3
MT9VDDT3272G-262__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDT3272G-26A__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDT3272Y-26A__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDT3272G-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDT3272Y-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
PDF: 09005aef80e119b2/Source: 09005aef80e11976 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
DD9C16_32_64x72.fm - Rev. D 1/08 EN 3©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Features
Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT9VDDT3272G-335G3.
Table 5: Part Numbers and Timing Parameters – 512MB Modules
Base device: MT46V64M8,1 512Mb DDR SDRAM
Part Number2Module
Density Configuration Module
Bandwidth Memory Clock/
Data Rate Clock Cycles
(CL-tRCD-tRP)
MT9VDDT6472G-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDT6472Y-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDT6472G-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDT6472Y-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDT6472G-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDT6472Y-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
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DD9C16_32_64x72.fm - Rev. D 1/08 EN 4©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Notes: 1. Pin 115 is NC for 128MB and A12 for 256MB and 512MB.
Table 6: Pin Assignments
184-Pin DDR RDIMM Front 184-Pin DDR RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1V
REF 24 DQ17 47 DQS8 70 VDD 93 VSS 116 VSS 139 VSS 162 DQ47
2 DQ0 25 DQS2 48 A0 71 NC 94 DQ4 117 DQ21 140 DM8 163 NC
3V
SS 26 VSS 49 CB2 72 DQ48 95 DQ5 118 A11 141 A10 164 VDDQ
4 DQ1 27 A9 50 VSS 73 DQ49 96 VDDQ 119 DM2 142 CB6 165 DQ52
5DQS028DQ1851CB374 VSS 97 DM0 120 VDD 143 VDDQ166DQ53
6 DQ2 29 A7 52 BA1 75 NC 98 DQ6 121 DQ22 144 CB7 167 NC
7V
DD 30 VDDQ53DQ3276 NC 99 DQ7122 A8 145 VSS 168 VDD
8 DQ3 31 DQ19 54 VDDQ77VDDQ100VSS 123 DQ23 146 DQ36 169 DM6
9 NC 32 A5 55DQ3378DQS6 101 NC 124 V
SS 147DQ37170DQ54
10 RESET# 33 DQ24 56 DQS4 79 DQ50 102 NC 125 A6 148 VDD 171 DQ55
11 VSS 34 VSS 57 DQ34 80 DQ51 103 NC 126 DQ28 149 DM4 172 VDDQ
12 DQ8 35 DQ25 58 VSS 81 VSS 104 VDDQ 127 DQ29 150 DQ38 173 NC
13 DQ9 36 DQS3 59 BA0 82 NC 105 DQ12 128 VDDQ 151 DQ39 174 DQ60
14 DQS1 37 A4 60 DQ35 83 DQ56 106 DQ13 129 DM3 152 VSS 175 DQ61
15 VDDQ38 VDD 61 DQ40 84 DQ57 107 DM1 130 A3 153 DQ44 176 VSS
16 NC 39 DQ26 62 VDDQ85 VDD 108 VDD 131 DQ30 154 RAS# 177 DM7
17 NC 40 DQ27 63 WE# 86 DQS7 109 DQ14 132 VSS 155DQ45178DQ62
18 VSS 41 A2 64 DQ41 87 DQ58 110 DQ15 133 DQ31 156 VDDQ179DQ63
19 DQ10 42 VSS 65 CAS# 88 DQ59 111 NC 134 CB4 157 S0# 180 VDDQ
20 DQ11 43 A1 66 VSS 89 VSS 112 VDDQ 135 CB5 158 NC 181 SA0
21 CKE0 44 CB0 67 DQS5 90 NC 113 NC 136 VDDQ 159 DM5 182 SA1
22 VDDQ 45 CB1 68 DQ42 91 SDA 114 DQ20 137 CK0 160 VSS 183 SA2
23 DQ16 46 VDD 69 DQ43 92 SCL 1151NC/A12 138 CK0# 161 DQ46 184 VDDSPD
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DD9C16_32_64x72.fm - Rev. D 1/08 EN 5©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Pin Assignments and Descriptions
Table 7: Pin Descriptions
Symbol Type Description
A0–A12 Input Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bi t (A10) for READ/WRITE commands, to
select one location out of th e memory ar ray in the respe ctive device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET comma nd. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command . A0–A11 (128MB) and A0–A12 (256MB, 512MB).
BA0, BA1 Input Bank address: BA0 and BA1 de fine the device ban k to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All contro l, co mmand, and
address input signals are sampled on the crossing of the positive edge of CK
and the negative edge of CK#. Ou tput d ata (DQ and DQS) is referenced to the
crossings of CK and CK#.
CKE0 Input Clock enable: CKE enables (regis tered HIGH) and disables (registered LOW)
the internal clock, input buffers, and output dr ivers.
DM0–DM8 Input Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, du ring a write
access. DM is sampled on both edges of DQS. Although DM pins are input-only ,
the DM loading is designed to match that of the DQ and DQS pins.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW .
This signal can be used during power-up to ensure that CKE is LOW and DQ are
High-Z.
S0# Input Chip selects: S# (registered LOW) enables and (registered HIGH) disables the
command decoder.
SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the
presence-detect device.
SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
CB0–CB7 I/O Check bits.
DQ0–DQ63 I/O Data input/output: Data bus.
DQS0–DQS8 I/O Data strobe: Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data . Used to capture dat a.
SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
VDD/VDDQ Supply Power supply: +2.5V ±0.2V.
VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
VREF Supply SSTL_2 reference voltage (VDD/2).
VSS Supply Ground.
NC – No connect: These pins are not connected on the module.
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DD9C16_32_64x72.fm - Rev. D 1/08 EN 6©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Functional Block Diagram
Functional Block Diagram
Figure 3: Functional Block Diagram
S0#
BA0, BA1
A0–A11/A12
RAS#
RS0#
RBA0, RBA1: DDR SDRAM
RA0–RA11/RA12: DDR SDRAM
RRAS#: DDR SDRAM
RCAS#: DDR SDRAM
RCKE0: DDR SDRAM
RWE#: DDR SDRAM
CAS#
CKE0
WE#
V
REF
V
SS
DDR SDRAM
DDR SDRAM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U17
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U19
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U21
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
RS0#
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
R
e
g
i
s
t
e
r
s
PLL
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
Register x 2
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQS0DM4
DQS4
DM1
DQS1DM5
DQS5
DM2
DQS2DM6
DQS6
DM CS# DQS
U15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM CS# DQS DM CS# DQS
DM CS# DQS
DM3
DQS3DM7
DQS7
DM8
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
V
DD
/V
DD
QDDR SDRAM
CK0
CK0#
U12
U11, U13
SPD EEPROM
V
DDSPD
A0
SA0
SPD EEPROM SDA
A1
SA1
A2
SA2
WP
SCL
U10
V
SS
RESET#
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DD9C16_32_64x72.fm - Rev. D 1/08 EN 7©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
General Description
General Description
The MT9VDDT1672, MT9VDDT3272, and MT9VDDT6472 are high-speed, CMOS
dynamic random access 128MB, 256MB, and 512MB memory modules organized in a
x72 configuration. These modules use DDR SDRA M devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate archi t ecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules oper ate from differential clock inputs (CK and CK#) ; the crossi ng
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and ad dress signals ar e r egister ed at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Register and PLL Operation
These DDR SDRAM modules operate in register ed mode, where the control, command,
and address input signals are latched in the registers on the rising clock edge and sent to
the DDR SDRAM devices on the following rising clock edge (data access is delayed by
one clock cycle). A phase-lock lo op (PLL) on the module receives and redrives the differ-
ential clock signals (CK, CK#) to the DDR SDRAM devices. The r egister(s) and PLL reduce
clock, control, command, and addr ess signal loading b y isolating DRAM from the system
controller. PLL clock timing is defined b y JEDEC specific ations and ensur ed b y use of the
JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect. The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes are programmed by Micron to identify the module type and various
SDRAM organizations and timing parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/WRITE operations between the master
(system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using
the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide
eight unique DIMM/EEPROM addresses. Wr ite protect (WP) is tied to VSS on the
module, permanently disabling hardware write protect.
PDF: 09005aef80e119b2/Source: 09005aef80e11976 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
DD9C16_32_64x72.fm - Rev. D 1/08 EN 8©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
Electrical Specifications
S tresses greater than those listed in Table8 may cause permanent damage to the
module. This is a stre ss rating only, and functional operation of the module at these or
any other conditions outside thos e ind icated on the device data shee t is not impl ie d .
Exposure to absolute maximum rating conditions for extended periods may adversely
affect reli ability.
Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available
on Micron’s Web site.
Input Capacitance
Micron encourages designers to simulate the performance of the module to achieve
optimum values. Simulations are significantly more accurate and realistic than a gross
estimation of module capacitance when inductance and delay parameters associated
with trace lengths are used in simulations. JEDEC modules are currently designed using
simulations to cl ose timing budget s.
Component AC Timing and Operating Conditions
Recommended AC operating conditions are gi ven in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in Table 9.
Table 8: Absolute Maximum Ratings
Symbol Parameter Min Max Units
VDD/VDDQVDD/VDDQ supply voltage relative to VSS –1.0 +3.6 V
VIN, VOUT Voltage on any pin relative to VSS –0.5 +3.2 V
IIInput leakage current; Any input 0V ≤ VIN ≤ VDD;
VREF inpu t 0V ≤ VIN ≤ 1.35V (All other pin s not under
test = 0V)
Address inputs,
RAS#, CAS#, WE#, BA,
S#, CKE
–5 +5 µA
CK, CK# –10 +10
DM –2 +2
IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are
disabled DQ, DQS –5 +5 µA
TADRAM ambient operating temperature1Commercial 0 +70 °C
Industrial –40 +85 °C
Table 9: Module and Component Speed Grades
DDR components meet or exceed the listed module speed grades
Module Speed Grade Component Speed Grade
-335 -6
-262 -75E
-26A -75Z
-265 -75
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DD9C16_32_64x72.fm - Rev. D 1/08 EN 9©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
IDD Specifications
Table 10: IDD Specifications and Conditions – 128MB
Values are shown for the MT46V16M8 DD R SDRAM only and are compu t ed from values specified in the
128Mb (16 Meg x 8) component data sheet
Parameter/Condition Symbol -335 -26A/
-265 Units
Operating one bank active-precharge current:
tRC = tRC (MIN);
tCK = tCK (MIN); DQ, DM, and DQ S inp uts changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD0 1,125 945 mA
Operating one bank active-read-precharge current: BL = 2;
tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1 1,215 1,080 mA
Precharge power-down standby current: All device banks idle; Power-
down mode; tCK = tCK (MIN); CKE = LOW IDD2P 27 27 mA
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock cycle;
V
IN
=V
REF
for DQ, DM, and DQS
IDD2F 405 360 mA
Active power-down standby current: One device bank active; Power-
down mode; tCK = tCK (MIN); CKE = LOW IDD3P 225 180 mA
Active standby curr ent: CS# = HIGH; CKE = HIGH; One device bank active;
tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle; Address and other control inputs changing once per cl ock
cycle
IDD3N 450 405 mA
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Add ress and control in puts changing once per clock cycle;
tCK = tCK (MIN); IOUT =0mA
IDD4R 1,260 1,125 mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
IDD4W 1,260 1,080 mA
Auto refresh current tREFC = tRFC (MIN) IDD5 2,385 1,980 mA
tREFC = 15.625µs IDD5A 45 45
Self refresh current: CKE ≤ 0.2V IDD62718mA
Operating bank interleave read current: F our device bank interleavi ng
reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN);
Address and con trol inputs change on ly during active READ or WRITE
commands
IDD7 3,195 2,925 mA
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DD9C16_32_64x72.fm - Rev. D 1/08 EN 10 ©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
Table 11: IDD Specifications and Conditions – 256MB
Values are shown for the MT46V32M8 DD R SDRAM only and are compu t ed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition Symbol -335 -262 -26A/
-265 Units
Operating one bank active-precharge current:
tRC = tRC (MIN);
tCK = tCK (MIN); DQ, DM, and DQ S inp uts changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD0 1,125 1,125 1,080 mA
Operating one bank active-read-precharge current: BL = 2;
tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1 1,530 1,440 1,305 mA
Precharge power-down standby current: All device banks idle; Power -
down mode; tCK = tCK (MIN); CKE = LOW IDD2P 36 36 36 mA
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock
cycle; V
IN
=V
REF
for DQ, DM, and DQS
IDD2F 450 405 405 mA
Active power-down standby current: One device bank active; Power-
down mode; tCK = tCK (MIN); CKE = LOW IDD3P 270 225 225/
270 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQ S inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cyc l e
IDD3N 540 450 450 mA
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT =0mA
IDD4R 1,575 1,350 1,350 mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
IDD4W 1,575 1,350 1,350 mA
Auto refresh current tREFC = tRFC (MIN) IDD5 2,295 2,115 2,115/
2,205 mA
tREFC = 7.8125µs IDD5A 54 54 54
Self refresh current: CKE ≤ 0.2V IDD6363636mA
Operating bank interleave read current: F our device bank
interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK
(MIN); Address and control in pu ts change only during active READ or
WRITE commands
IDD7 3,690 3,150 3,150/
3,285 mA
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DD9C16_32_64x72.fm - Rev. D 1/08 EN 11 ©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Electrical Specifications
Table 12: IDD Specifications and Conditions – 512MB
Values are shown for the MT46V64M8 DD R SDRAM only and are compu t ed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition Symbol -262 -26A/
-265 Units
Operating one bank active-precharge current:
tRC = tRC (MIN);
tCK = tCK (MIN); DQ, DM, and DQ S inp uts changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD0 1,170 1,035 mA
Operating one bank active-read-precharge current: BL = 2;
tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1 1,440 1,305 mA
Precharge power-down standby current: All device banks idle; Power -
down mode; tCK = tCK (MIN); CKE = LOW IDD2P 45 45 mA
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock
cycle; V
IN
=V
REF
for DQ, DM, and DQS
IDD2F 405 360 mA
Active power-down standby current: One device bank active; Power-
down mode; tCK = tCK (MIN); CKE = LOW IDD3P 315 270 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQ S inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cyc l e
IDD3N 450 405 mA
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT =0mA
IDD4R 1,485 1,305 mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
IDD4W 1,395 1,215 mA
Auto refresh current tREFC = tRFC (MIN) IDD5 2,610 2,520 mA
tREFC = 7.8125µs IDD5A 90 90
Self refresh current: CKE ≤ 0.2V IDD645 45 mA
Operating bank interleave read current: F our device bank
interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN);
tCK = tCK (MIN); Address and control inputs change only during active
READ or WRITE commands
IDD7 3,600 3,150 mA
PDF: 09005aef80e119b2/Source: 09005aef80e11976 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
DD9C16_32_64x72.fm - Rev. D 1/08 EN 12 ©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Register and PLL Specifications
Register and PLL Specifications
Notes: 1. Timing and switching specifications for the register listed above are critical for proper oper-
ation of the DDR SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module. Detailed information for this register is available in
JEDEC standard JESD82.
Table 13: Register Specifications
SSTV16859 devices or equivalent JESD82-4B
Parameter Symbol Pins Condition Min Max Units
DC high-level
input voltage VIH(DC) Control,
command, address SSTL_25 VREF(DC) + 150 – mV
DC low-level
input voltage VIL(DC) Control,
command, address SSTL_25 – VREF(DC) – 150 mV
AC high-level
input voltage VIH(AC) Control,
command, address SSTL_25 VREF(DC) + 310 VDD mV
AC low-level
input voltage VIL(AC) Control,
command, address SSTL_25 – VREF(DC) – 310 mV
Output high voltage VOH Parity output LVCMOS VDD – 0.2 – V
Output low voltage VOL Parity output LVCMOS – 0.2 V
Input current IIAll pins VI = VDDQ or VSSQ–5.0 +5.0µA
Static standby IDD All pins RESET# = VSSQ (IO = 0) – 100 µA
Static operating IDD All pins RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
IO = 0
–Varies by
manufacturer mA
Dynamic operating
(clock tree) IDDD n/a RESET# = VDD, V I = VIH(AC)
or VIL(AC), IO = 0; CK and
CK# switching 50 percent
duty cycle
–Varies by
manufacturer µA
Dynamic operating
(per each input) IDDD n/a RESET# = VDD, VI = V IH(AC)
or VIL(AC), IO = 0; CK and
CK# switching 50 percent
duty cycle; One data in put
switching at tC K/2, 50
percent duty cycle
–Varies by
manufacturer µA
Input capacitance
(per device, per pin) CIAll inputs except
RESET# VI = VREF ±250mV;
VDDQ = 1.8V 2.5 3.5 pF
Input capacitance
(per device, per pin) CIRESET# VI = VDDQ or VSSQ–Varies by
manufacturer pF
PDF: 09005aef80e119b2/Source: 09005aef80e11976 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
DD9C16_32_64x72.fm - Rev. D 1/08 EN 13 ©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Register and PLL Specifications
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC standard JESD82-1A.
Table 14: PLL Specifications
CVF857 device or equivalent JESD82-1A
Parameter Symbol Min Max Units
DC high-level input voltage VIH 1.7 VDDQ + 0.3 V
DC low-level input voltage VIL –0.3 0.7 V
Input voltage (limits) VIN –0.3 VDDQ + 0.3 V
Input differential-pair cross voltage VIX (VDDQ/2) - 0.2 (VDDQ/2) + 0.2 V
Input differential voltage VID(DC)0.36 VDDQ + 0.6 V
Input differential voltage VID(AC)0.70 VDDQ + 0.6 V
Input current II–10 +10 µA
Dynamic supply current IDDPD – 200 µA
Dynamic supply current IDDQ – 300 µA
Dynamic supply current IADD –12mA
Input capacitance CIN 2.0 3.5 pF
Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter Symbol Min Max Units
Stabilization time tL– 100µs
Input clock slew rate tslr(i) 1.0 4.0 V/ns
SSC modulation fr equency – 30 50 kH z
SSC clock input frequen cy deviatio n – 0 –0.50 %
PLL loop bandwi dth (–3dB from unity gain) – 2.0 – MHz
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DD9C16_32_64x72.fm - Rev. D 1/08 EN 14 ©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
Table 16: Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage VDDSPD 2.3 3.6 V
Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs VIL –1.0 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA VOL –0.4V
Input leakage current: VIN = GND to VDD ILI –10µA
Output leakage current: VOUT = GND to VDD ILO –10µA
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB –30µA
Power supply current: SCL clock frequency = 100 kHz ICC –2.0mA
Table 17: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start tBUF 1.3 – µs
Data-out hold time tDH 200 – ns
Clock/data fall time tF – 300 ns 2
Clock/data rise ti me tR – 300 ns 2
Data-in hold time tHD:DAT 0 – µs
Start condition hold time tH:STA 0.6 – µs
Clock HIGH period tHIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs tI–50ns
Clock LOW period tLOW 1.3 – µs
SCL clock frequency fSCL – 400 kHz
Data-in setup time tSU:DAT 100 – ns
Start condition setup time tSU:STA 0.6 – µs 3
Stop condition setup time tSU:STO 0.6 – µs
WRITE cycle time tWRC – 10 ms 4
PDF: 09005aef80e119b2/Source: 09005aef80e11976 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
DD9C16_32_64x72.fm - Rev. D 1/08 EN 15 ©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Module Dimensions
Module Dimensions
Figure 4: 184-Pin DDR RDIMM – Tall-Height Layout
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JED EC MO document for addi-
tional design dimensions.
43.31 (1.705)
43.05 (1.695)
Pin 1
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.3 (0.091) TYP
6.35 (0.25) TYP
120.65 (4.75)
TYP
1.27 (0.05)
TYP
2.2 (0.087) TYP 1.02 (0.04)
TYP
2.0 (0.079) R
(4X)
0.90 (0.035) R
Pin 92
Front view
1.37 (0.054)
1.17 (0.046)
133.50 (5.256)
133.20 (5.244)
64.77 (2.55)
TYP 49.53 (1.95)
TYP
10.0 (0.394)
TYP
4.0 (0.157)
MAX
Back view
Pin 184 Pin 93
U1 U3 U5
U11 U12
U7
U13
U9
U10
U15 U17 U19 U21
1.0 (0.039) TYP
73.41 (2.89)
TYP
3.8 (0.15) TYP
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-39 00
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respec-
tive owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
128MB, 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM
RDIMM
PDF: 09005aef80e119b2/Source: 09005aef80e11976 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
DD9C16_32_64x72.fm - Rev. D 1/08 EN 16 ©2003 Micron Technology, Inc. All rights reserved.
Figure 5: 184-Pin DDR RDIMM – Standard-Height Layout
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JED EC MO document for addi-
tional design dimensions.
U1 U3
U11
U12
U5 U7 U9
U15 U17
U13
U10
U19 U21
1.37 (0.054)
1.17 (0.046)
4.0 (0.157)
MAX
30.61 (1.205)
30.35 (1.195)
17.78 (0.70)
TYP
Front view
133.50 (5.256)
133.20 (5.244)
Back view
Pin 184 Pin 93
Pin 1
2.3 (0.091) TYP
6.35 (0.25) TYP
120.65 (4.75)
TYP
1.27 (0.05)
TYP
2.2 (0.087) TYP 1.02 (0.04)
TYP
2.0 (0.079) R
(4X)
0.90 (0.035) R
Pin 92
64.77 (2.55)
TYP 49.53 (1.95)
TYP
10.0 (0.394)
TYP
1.0 (0.039) TYP
73.41 (2.89)
TYP
3.8 (0.15) TYP
