18-Bit, 2 MSPS/1 MSPS/500 kSPS,
Easy Drive, Differential SAR ADCs
Data Sheet
AD4003/AD4007/AD4011
Rev. C Document Feedback
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FEATURES
Throughput: 2 MSPS/1 MSPS/500 kSPS options
INL: ±1.0 LSB (±3.8 ppm) maximum
Guaranteed 18-bit no missing codes
Low power
4.9 mW/MSPS, 2.4 mW at 500 kSPS, VDD only
8 mW/MSPS, 80 µW at 10 kSPS, 16 mW at 2 MSPS total
SNR: 100.5 dB at fIN = 1 kHz, 99 dB at fIN = 100 kHz
Oversampled SNR:
103.5 dB at 1.0 MSPS, OSR =2
130.5 dB at 1.9 kSPS, OSR = 1024
THD: −123 dB at fIN = 1 kHz; −100 dB at fIN = 100 kHz
SINAD: 89 dB at fIN = 1 MHz
Easy Drive
Greatly reduced input kickback
Input current reduced to 0.5 μA/MSPS
Long acquisition phase, ≥79% of cycle time at 1 MSPS
Input span compression for single-supply operation
Input overvoltage clamp protection sinks up to 50 mA
Differential input range: ±VREF
VREF input range from 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
First conversion accurate, no latency/pipeline delay
Fast conversion time allows low SPI clock rates
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
Ability to daisy-chain multiple ADCs
Guaranteed operation: −40°C to +125°C
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
Pin compatible with AD4000/AD4004/AD4008 family
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
14957-001
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4003/
AD4007/
AD4011
18-BIT
SAR
ADC
SERIAL
INTERFACE
VIO
REF VDD
VREF
0
VREF
0
VREF/2
VREF/2 HIGH-Z
MODE
CLAMP SPAN
COMPRESSION
TURBO
MODE
STATUS
BITS
2.4V TO 5.1V 1.8V
10µF
1.8V TO 5V
3-WIRE O R
4-WIRE
SPI INTERFACE
(DAIS Y CHAIN, CS)
Figure 1.
GENERAL DESCRIPTION
The AD4003/AD4007/AD4011 are high accuracy, high speed,
low power, 18-bit, Easy Drive, precision successive approximation
register (SAR) analog-to-digital converters (ADCs). The high
throughput allows both accurate capture of high frequency signals
and decimation to achieve higher SNR, while also reducing
antialiasing filter challenges.
Easy Drive features reduce signal chain complexity and power
consumption, and enable higher channel density. The reduced
input current, particularly in high-Z mode, coupled with a long
signal acquisition phase, eliminates the need for a dedicated high
power, high speed ADC driver, which broadens the range of low
power precision amplifiers that can drive these ADCs directly
(see Figure 2). The input span compression feature enables the
ADC driver amplifier and the ADC to operate off common supply
rails without the need for a negative supply while preserving the
full ADC code range. The input overvoltage clamp protects the
ADC inputs against overvoltages, minimizes disturbance on the
reference pin, and eliminates the need for external protection
diodes.
The low serial peripheral interface (SPI) clock rate (75 MHz for
the AD4003 in turbo mode) reduces the digital input/output
power consumption, broadens processor options, and simplifies
the task of sending data across digital isolation.
The SPI-compatible versatile serial interface features seven different
programmable modes with an optional busy indicator. Using
the SDI input, several ADCs can be daisy-chained on a single
3-wire bus. The AD4003/AD4007/AD4011 are compatible with
1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate supply, VIO.
–15
–12
–9
–6
–3
0
3
6
9
12
15
–5 –4 –3 –2 –1 012345
INPUT CURRENT (μA)
INPUT DIFFERENTIAL VOLTAGE (V)
HIG H- Z DIS ABLED, 2M S P S
HIG H- Z ENABL E D, 2MSP S
14957-443
Figure 2. Input Current vs. Input Differential Voltage
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 2 of 38
TABLE OF CONTENTS
Features ............................................................................................... 1
Applications ........................................................................................ 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Circuit Information .................................................................... 17
Converter Operation .................................................................. 18
Transfer Functions...................................................................... 18
Applications Information .............................................................. 19
Typical Application Diagrams .................................................. 19
Analog Inputs .............................................................................. 20
Driver Amplifier Choice ........................................................... 22
Ease of Drive Features ............................................................... 23
Voltage Reference Input ............................................................ 24
Power Supply ............................................................................... 24
Digital Interface .......................................................................... 25
Register Read/Write Functionality........................................... 26
Status Word ................................................................................. 28
CS Mode, 3-Wire Turbo Mode ................................................. 29
CS Mode, 3-Wire Without Busy Indicator ............................. 30
CS Mode, 3-Wire with Busy Indicator .................................... 31
CS Mode, 4-Wire Turbo Mode ................................................. 32
CS Mode, 4-Wire Without Busy Indicator ............................. 33
CS Mode, 4-Wire with Busy Indicator .................................... 34
Daisy-Chain Mode ..................................................................... 35
Layout Guidelines....................................................................... 36
Evaluating the AD4003/AD4007/AD4011 Performance ...... 36
Outline Dimensions ....................................................................... 37
Ordering Guide .......................................................................... 38
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 3 of 38
REVISION HISTORY
4/2019—Rev. B to Rev. C
Added Figure 2; Renumbered Sequentially ................................... 1
Changes to Features Section and General Description Section ..... 1
10/2017—Rev. A to Rev. B
Changes to Features and General Description .............................. 1
Moved Figure 1 .................................................................................. 1
Changes to Specifications Section and Table 1.............................. 4
Changes to Endnote 1 and Endnote 2, Table 1 .............................. 6
Changes to Timing Specifications Section, CNV or SDI Low to
SDO D17 (MSB) Valid Delay (CS Mode) Parameter, Table 2 .... 7
Changes to Endnote 3, Table 2 ........................................................ 7
Changes to Analog Input Parameter, Table 5 ................................ 9
Added Endnote 2, Table 5 ................................................................ 9
Changes to Figure 4 and Table 7 ................................................... 10
Changes to Typical Performance Characteristics Section ......... 11
Reorganized Typical Performance Characteristics Section ....... 11
Changes to Figure 19 and Figure 19 Caption .............................. 13
Changes to Figure 25 Caption through Figure 27 Caption and
Changes to Figure 28 ...................................................................... 14
Changes to Circuit Information Section and Table 8 ................. 17
Changes to Converter Operations Section and Table 9 ............. 18
Changes to Endnote 1 and Endnote 2, Table 9 ............................ 18
Changes to Applications Information Section ............................ 19
Moves Figure 38; Renumbered Sequentially ............................... 20
Change to Analog Input Section ................................................... 20
Changes to Input Overvoltage Clamp Section ................................... 21
Changes to High Frequency Input Signals Section, Multiplexed
Applications Section, Driver Amplifier Choice Section, RC Filter
Values Section, Figure 39, and Figure 40 Caption ............................. 22
Changes to High-Z Mode Section, Figure 42, Figure 43, and
Figure 43 Caption ............................................................................ 23
Changes to Voltage Reference Input Section, Figure 44 Caption,
Figure 45, Figure 46 Caption, and Figure 47 ............................... 24
Changes to Digital Interface Section, Power Supply Section, and
Figure 48 Caption ............................................................................ 25
Changes to Read/Write Functionality Section, Table 12, and
Table 14 ............................................................................................. 26
Changes to Figure 49 ...................................................................... 27
Changes to Status Word Section and Table 15 ............................ 28
Changes to CS Mode, 4-Wire Turbo Mode Section ....................... 32
Changes to CS Mode, 4-Wire Without Busy Indicator Section ..... 33
Changes to CS Mode, 4-Wire With Busy Indicator Section ...... 34
Change to Daisy-Chain Mode Section ......................................... 35
Changes to Evaluating the AD4003/AD4007/AD4011
Performance Section ....................................................................... 36
Changes to Ordering Guide ........................................................... 38
7/2017—Rev. 0 to Rev. A
Added AD4007 and AD4011 ............................................ Universal
Changes to Features Section and General Description ................ 1
Moved Figure 1 .................................................................................. 3
Changes to Specifications Section .................................................. 4
Changes to Table 1 ............................................................................ 4
Changes to Timing Specifications Section .................................... 7
Changes to Table 2 ............................................................................ 7
Changes to Absolute Maximum Ratings Section ......................... 9
Added Endnote 2 and Endnote 3, Table 6 ..................................... 9
Changes to Typical Performance Characteristics Section ......... 11
Changes to Figure 11 and Figure 14 ............................................. 12
Changes to Figure 19 and Figure 21 ............................................. 13
Added Figure 25 and Figure 26; Renumbered Sequentially ...... 14
Moved Terminology Section ......................................................... 16
Changes to Terminology Section .................................................. 16
Changes to Circuit Information Section and Table 8 ................. 17
Moved Figure 38 .............................................................................. 22
Changes to High Frequency Input Signals Section .................... 22
Added Multiplexed Applications Section .................................... 22
Added Figure 41 .............................................................................. 23
Moved Figure 42 .............................................................................. 23
Changes to High-Z Mode Section and Figure 43 ....................... 23
Changes to Voltage Reference Input Section ............................... 24
Changes to Figure 48, Digital Interface Section, and Table 11 ....... 25
Changes to CS Mode, 3-Wire Turbo Mode Section ................... 29
Added Figure 53 .............................................................................. 29
Changes to CS Mode, 4-Wire Turbo Mode Section ................... 32
Added Figure 59 .............................................................................. 32
Change to CS Mode, 4-Wire with Busy Signal Indicator
Section .............................................................................................. 34
Changes to Layout Guidelines Section and Evaluating the
AD4003/AD4007/AD4011 Performance Section ....................... 36
Updated Outline Dimensions ........................................................ 37
Changes to Ordering Guide ........................................................... 38
10/2016—Revision 0: Initial Version
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 4 of 38
SPECIFICATIONS
VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression
disabled, turbo mode enabled, and sampling frequency fS = 2 MSPS for the AD4003, fS = 1 MSPS for the AD4007, and fS = 500 kSPS for
the AD4011, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUT
Voltage Range
IN+ voltage (VIN+) − IN− voltage
(VIN−)
−V
REF
+V
REF
V
Span compression enabled −VREF × 0.8 +VREF × 0.8 V
Operating Input Voltage VIN+, VIN− to GND −0.1 VREF + 0.1 V
Span compression enabled 0.1 × VREF 0.9 × VREF V
Common-Mode Input Range VREF/2 − 0.125 VREF/2 VREF/2 + 0.125 V
Common-Mode Rejection Ratio (CMRR)
f
IN
= 500 kHz
68
dB
Analog Input Current Acquisition phase, T = 25°C 0.3 nA
High-Z mode enabled, converting
dc input at 2 MSPS
1 µA
THROUGHPUT
Complete Cycle
AD4003 500 ns
AD4007 1000 ns
AD4011
2000
ns
Conversion Time 270 290 320 ns
Acquisition Phase1
AD4003 290 ns
AD4007 790 ns
AD4011 1790 ns
Throughput Rate2
AD4003 0 2 MSPS
AD4007 0 1 MSPS
AD4011 0 500 kSPS
Transient Response3 250 ns
DC ACCURACY
No Missing Codes 18 Bits
Integral Nonlinearity Error (INL) −1.0 ±0.4 +1.0 LSB
−3.8
±1.52
+3.8
ppm
Differential Nonlinearity Error (DNL) −0.75 ±0.3 +0.75 LSB
Transition Noise 0.8 LSB
Zero Error −7 +7 LSB
Zero Error Drift4 −0.21 +0.21 ppm/°C
Gain Error −26 ±3 +26 LSB
Gain Error Drift4 −1.23 +1.23 ppm/°C
Power Supply Sensitivity VDD = 1.8 V ± 5% 1.5 LSB
1/f Noise5 Bandwidth = 0.1 Hz to 10 Hz 6 µV p-p
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 5 of 38
Parameter Test Conditions/Comments Min Typ Max Unit
AC ACCURACY
Dynamic Range 101 dB
Total RMS Noise 31.5 µV rms
fIN = 1 kHz, −0.5 dBFS, VREF = 5 V
Signal-to-Noise Ratio (SNR)
99
100.5
dB
Spurious-Free Dynamic Range (SFDR) 122 dB
Total Harmonic Distortion (THD) −123 dB
Signal-to-Noise-and-Distortion Ratio
(SINAD)
98.5 100 dB
Oversampled Dynamic Range Oversampling ratio (OSR) = 256,
VREF = 5 V
122 dB
fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V
SNR 93.5 94.5 dB
SFDR 122 dB
THD −119 dB
SINAD 93 94 dB
fIN = 100 kHz, −0.5 dBFS, VREF = 5 V
SNR 99 dB
THD −100 dB
SINAD 96.5 dB
fIN = 400 kHz, −0.5 dBFS, VREF = 5 V
SNR
91.5
dB
THD −94 dB
SINAD 90 dB
−3 dB Input Bandwidth 10 MHz
Aperture Delay 1 ns
Aperture Jitter 1 ps rms
REFERENCE
Voltage Range, VREF 2.4 5.1 V
Current
AD4003 2 MSPS 1.1 mA
AD4007 1 MSPS 0.5 mA
AD4011 500 kSPS 0.26 mA
INPUT OVERVOLTAGE CLAMP
IN+/IN− Current, IIN+/IIN− VREF = 5 V 50 mA
VREF = 2.5 V 50 mA
VIN+/VIN− at Maximum IIN+/IIN− VREF = 5 V 5.4 V
VREF = 2.5 V 3.1 V
V
IN+
/V
IN−
Clamp On/Off Threshold
V
REF
= 5 V
5.25
5.4
V
VREF = 2.5 V 2.68 2.8 V
Deactivation Time 360 ns
REF Current at Maximum IIN+/IIN− VIN+/VIN− > VREF 100 µA
DIGITAL INPUTS
Logic Levels
Input Low Voltage, VIL VIO > 2.7 V −0.3 +0.3 × VIO V
VIO ≤ 2.7 V −0.3 +0.2 × VIO V
Input High Voltage, VIH VIO > 2.7 V 0.7 × VIO VIO + 0.3 V
VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V
Input Low Current, IIL −1 +1 µA
Input High Current, IIH −1 +1 µA
Input Pin Capacitance 6 pF
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 6 of 38
Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL OUTPUTS
Data Format Serial 18 bits, twos complement
Pipeline Delay Conversion results available immediately
after completed conversion
Output Low Voltage, VOL ISINK = 500 µA 0.4 V
Output High Voltage, VOH ISOURCE = −500 µA VIO − 0.3 V
POWER SUPPLIES
VDD
1.71
1.8
1.89
V
VIO 1.71 5.5 V
Standby Current VDD = 1.8 V, VIO = 1.8 V, T = 25°C 1.6 µA
Power Dissipation VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V
10 kSPS, high-Z mode disabled 80 µW
500 kSPS, high-Z mode disabled 4 4.7 mW
1 MSPS, high-Z mode disabled 8 9.3 mW
2 MSPS, high-Z mode disabled 16 18.5 mW
500 kSPS, high-Z mode enabled 5 6.2 mW
1 MSPS, high-Z mode enabled 10 12.3 mW
2 MSPS, high-Z mode enabled 20 24.5 mW
VDD Only
500 kSPS, high-Z mode disabled
2.4
mW
1 MSPS, high-Z mode disabled 4.9 mW
2 MSPS, high-Z mode disabled 9.5 mW
REF Only 500 kSPS, high-Z mode disabled 1.4 mW
1 MSPS, high-Z mode disabled 2.8 mW
2 MSPS, high-Z mode disabled 5.5 mW
VIO Only
500 kSPS, high-Z mode disabled
0.1
mW
1 MSPS, high-Z mode disabled 0.4 mW
2 MSPS, high-Z mode disabled 1.0 mW
Energy per Conversion 8 nJ/sample
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +125 °C
1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4003, 1 MSPS for the AD4007, and 500 kSPS for the AD4011.
2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy.
4 The minimum and maximum values are guaranteed by characterization, but not production tested.
5 See the 1/f noise plot in Figure 24.
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 7 of 38
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression
disabled, turbo mode enabled, and sampling frequency fS = 2 MSPS for the AD4003, fS = 1 MSPS for the AD4007, and fS = 500 kSPS for
the AD4011, unless otherwise noted. See Figure 3 for the timing voltage levels.
Table 2. Digital Interface Timing
Parameter Symbol Min Typ Max Unit
CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE tCONV 270 290 320 ns
ACQUISITION PHASE1 tACQ
AD4003 290 ns
AD4007 790 ns
AD4011 1790 ns
TIME BETWEEN CONVERSIONS tCYC
AD4003 500 ns
AD4007 1000 ns
AD4011 2000 ns
CNV PULSE WIDTH (CS MODE)2 tCNVH 10 ns
SCK PERIOD (CS MODE)3 tSCK
VIO > 2.7 V 9.8 ns
VIO > 1.7 V 12.3 ns
SCK PERIOD (DAISY-CHAIN MODE)4 tSCK
VIO > 2.7 V 20 ns
VIO > 1.7 V 25 ns
SCK LOW TIME tSCKL 3 ns
SCK HIGH TIME tSCKH 3 ns
SCK FALLING EDGE TO DATA REMAINS VALID DELAY tHSDO 1.5 ns
SCK FALLING EDGE TO DATA VALID DELAY tDSDO
VIO > 2.7 V 7.5 ns
VIO > 1.7 V 10.5 ns
CNV OR SDI LOW TO SDO D17 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE) tEN
VIO > 2.7 V 10 ns
VIO > 1.7 V 13 ns
CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY tQUIET1 190 ns
LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY
5
t
QUIET2
60
ns
CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tDIS 20 ns
SDI VALID SETUP TIME FROM CNV RISING EDGE tSSDICNV 2 ns
SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE)
t
HSDICNV
2
ns
SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) tHSCKCNV 12 ns
SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tSSDISCK 2 ns
SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSDISCK 2 ns
1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4003, 1 MSPS for the AD4007, and 500 kSPS for the AD4011.
2 For turbo mode, tCNVH must match the tQUIET1 minimum.
3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
4 A 50% duty cycle is assumed for SCK.
5 See Figure 23 for SINAD vs. tQUIET2.
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 8 of 38
Table 3. Register Read/Write Timing
Parameter Symbol Min Typ Max Unit
READ/WRITE OPERATION
CNV Pulse Width1 tCNVH 10 ns
SCK Period tSCK
VIO > 2.7 V 9.8 ns
VIO > 1.7 V 12.3 ns
SCK Low Time tSCKL 3 ns
SCK High Time tSCKH 3 ns
READ OPERATION
CNV Low to SDO D17 MSB Valid Delay tEN
VIO > 2.7 V 10 ns
VIO > 1.7 V 13 ns
SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns
SCK Falling Edge to Data Valid Delay
t
DSDO
VIO > 2.7 V 7.5 ns
VIO > 1.7 V 10.5 ns
CNV Rising Edge to SDO High Impedance tDIS 20 ns
WRITE OPERATION
SDI Valid Setup Time from SCK Rising Edge tSSDISCK 2 ns
SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns
CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns
CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns
1 For turbo mode, tCNVH must match the tQUIET1 minimum.
X% VIO
1
Y% VIO
1
V
IH2
V
IL2
V
IL2
V
IH2
t
DELAY
t
DELAY
1
FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
2
MINIMUM V
IH
AND MAXI MUM V
IL
USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 1.
14957-002
Figure 3. Voltage Levels for Timing
Table 4. Achievable Throughput for Different Modes of Operation
Parameter Test Conditions/Comments Min Typ Max Unit
THROUGHPUT, CS MODE
3-Wire and 4-Wire Turbo Mode fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS
f
SCK
= 80 MHz, VIO < 2.7 V
2
MSPS
3-Wire and 4-Wire Turbo Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS
fSCK = 80 MHz, VIO < 2.7 V 1.78 MSPS
3-Wire and 4-Wire Mode fSCK = 100 MHz, VIO ≥ 2.7 V 1.75 MSPS
fSCK = 80 MHz, VIO < 2.7 V 1.62 MSPS
3-Wire and 4-Wire Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 1.59 MSPS
f
SCK
= 80 MHz, VIO < 2.7 V
1.44
MSPS
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 9 of 38
ABSOLUTE MAXIMUM RATINGS
Note that the input overvoltage clamp cannot sustain the
overvoltage condition for an indefinite amount of time.
Table 5.
Parameter Rating
Analog Inputs
IN+, IN− to GND1 −0.3 V to VREF + 0.4 V
or ± 130 mA2
Supply Voltage
REF, VIO to GND −0.3 V to +6.0 V
VDD to GND −0.3 V to +2.1 V
VDD to VIO −6 V to +2.4 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature Soldering
260°C reflow as per
JEDEC J-STD-020
Electrostatic Discharge (ESD) Ratings
Human Body Model (HBM) 4 kV
Machine Model 200 V
Field Induced Charged Device Model 1.25 kV
1 See the Analog Inputs section for an explanation of IN+ and IN−.
2 Current condition tested over a 10 ms time interval.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 6. Thermal Resistance
Package Type1 θJA2 θJC3 Unit
RM-10 147 38 °C/W
CP-10-9
114
33
°C/W
1 Test Condition 1: thermal impedance simulated values are based upon use
of 2S2P JEDEC PCB. See the Ordering Guide.
2 θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
3 θJC is the junction to case thermal resistance.
ESD CAUTION
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 10 of 38
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD4003/
AD4007
TOP VIEW
(Not to Scale)
14957-003
Figure 4. 10-Lead MSOP Pin Configuration
REF
VDD
IN+
IN–
GND
VIO
SDI
SCK
SDO
CNV
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
THIS CONNECTION IS NOT REQUIRED TO
MEET THE SPECIFIED PERFORMANCE.
1
2
3
4
5
10
9
8
7
6
14957-004
AD4003/
AD4007/
AD4011
TOP VIEW
(Not to Scale)
Figure 5. 10-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 REF AI
Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be
decoupled closely to the GND pin with a 10 µF X7R ceramic capacitor.
2 VDD P
1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 F ceramic
capacitor.
3 IN+ AI Differential Positive Analog Input. See the Differential Input Considerations section.
4 IN− AI Differential Negative Analog Input. See the Differential Input Considerations section.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
9 SDI DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word
on SDI on the rising edge of SCK.
10 VIO P Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 F ceramic capacitor.
N/A2 EPAD P Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet
the specified performance.
1 AI is analog input, P is power, DI is digital input, and DO is digital output.
2 N/A means not applicable.
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 11 of 38
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 1.8 V; VIO = 3.3 V; VREF = 5 V; T = 25°C, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling
frequency fS = 2 MSPS for the AD4003, fS = 1 MSPS for the AD4007, and fS = 500 kSPS for the AD4011, unless otherwise noted.
1.0
0.8
0.4
0
0.6
0.2
–0.2
–0.6
–0.4
–0.8
–1.0 032768 65536 131072 19660898304 163840 229376 262144
INL (LSB)
CODE
+125°C
+25°C
–40°C
14957-200
Figure 6. INL vs. Code for Various Temperatures, VREF = 5 V
1.0
0.8
0.4
0
0.6
0.2
–0.2
–0.6
–0.4
–0.8
–1.0
INL (LSB)
+125°C
+25°C
–40°C
032768 65536 131072 19660898304 163840 229376 262144
CODE
14957-201
Figure 7. INL vs. Code for Various Temperatures, VREF = 2.5 V
0.8
0.6
0
0.4
0.2
–0.2
–0.6
–0.4
–0.8
INL (LSB)
HIG H-Z E NABLED
SPAN COMPRESSION ENABLED
032768 65536 131072 19660898304 163840 229376 262144
CODE
14957-202
Figure 8. INL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V
0.4
0
0.3
0.2
0.1
–0.1
–0.3
–0.2
–0.4
DNL ( LSB)
+125°C
+25°C
–40°C
032768 65536 131072 19660898304 163840 229376 262144
CODE
14957-203
Figure 9. DNL vs. Code for Various Temperatures, VREF = 5 V
0.4
0
0.3
0.2
0.1
–0.1
–0.3
–0.2
–0.4
DNL ( LSB)
+125°C
+25°C
–40°C
032768 65536 131072 19660898304 163840 229376 262144
CODE
14957-204
Figure 10. DNL vs. Code for Various Temperatures, VREF = 2.5 V
1.8
1.5
0.9
1.1
1.7
1.3
1.4
1.0
1.6
1.2
0.8
TRANSITION NOISE (LSB)
2.5 4.54.03.53.0 5.0
REFERENCE VOLTAGE (V)
+125°C
+25°C
–40°C
14957-206
Figure 11. Transition Noise vs. Reference Voltage for Various Temperatures
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 12 of 38
4.5M
2.0M
3.5M
4.0M
3.0M
2.5M
1.5M
0.5M
1.0M
0
131062
131064
131068
131072
131066
131070
131076
131077
131081
131074
131079
131063
131067
131071
131065
131069
131075
131080
131073
131078
CODE COUNT
CODE
V
REF
= 2.5V
V
REF
= 5V
14957-205
Figure 12. Histogram of a DC Input at Code Center, VREF = 2.5 V and VREF = 5 V
0
–60
–160
–120
–20
–100
–80
–140
–40
–180
FUNDAM E NTAL AM P LITUDE (dB)
100 100k10k1k 1M
FREQUENCY ( Hz )
V
REF
= 5V
SNR = 100. 33dB
THD = –123.99d B
SINAD = 100.31d B
14957-207
Figure 13. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT), Wide
View, VREF = 5 V
0
–60
–160
–120
–20
–100
–80
–140
–40
–180
FUNDAM E NTAL AM P LITUDE (dB)
1k 100k10k 1M
FREQUENCY ( Hz )
V
REF
= 5V
SNR = 98. 37dB
THD = –98.52d B
SINAD = 95.58d B
14957-210
Figure 14. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View
4.5M
2.0M
3.5M
4.0M
3.0M
2.5M
1.5M
0.5M
1.0M
0
131062
131064
131068
131072
131066
131070
131076
131077
131081
131074
131079
131063
131067
131071
131065
131069
131075
131080
131073
131078
CODE CO UNT
CODE
V
REF
= 2.5V
V
REF
= 5V
14957-208
Figure 15. Histogram of a DC Input at Code Transition, VREF = 2.5 V and
VREF = 5 V
0
–60
–160
–120
–20
–100
–80
–140
–40
–180
FUNDAM E NTAL AM P LITUDE (dB)
100 100k10k1k 1M
FREQUENCY ( Hz )
V
REF
= 2.5V
SNR = 95. 01dB
THD = –118.60d B
SINAD = 94.99d B
14957-209
Figure 16. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, VREF = 2.5 V
0
–60
–160
–120
–20
–100
–80
–140
–40
–180
FUNDAM E NTAL AM P LITUDE (dB)
1k 100k10k 1M
FREQUENCY ( Hz )
V
REF
= 5V
SNR = 91. 22dB
THD = –91.97d B
SINAD = 89.15d B
14957-213
Figure 17. 400 kHz, −0.5 dBFS Input Tone FFT, Wide View
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 13 of 38
102
97
99
100
101
98
95
96
94
16.6
15.4
15.6
15.8
16.0
16.2
16.4
SNR, S INAD (d B)
ENOB ( Bits)
2.4 4.84.53.9 4.23.63.33.02.7 5.1
REFERENCE VOLTAGE (V)
ENOB
SINAD
SNR
14957-219
Figure 18. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Reference
Voltage
–40 100806040200–20 120
100.8
100.0
100.4
100.6
100.2
99.6
99.8
99.4
16.42
16.22
16.24
16.26
16.28
16.30
16.32
16.34
16.36
16.38
16.40
SNR, S INAD (d B)
ENOB ( Bits)
TEMPERATURE (°C)
ENOB
SINAD
SNR
14957-222
Figure 19. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz
135
130
120
110
125
115
105
100
95
SNR (dB)
DECIMATION RATE
DYNAMIC RANGE
f
IN
= 1kHz
f
IN
= 10kHz
14957-212
1 2 4 8 16 32 64 128 256 512 1024
Figure 20. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS
–114
–124
–120
–118
–116
–122
–128
–126
–130
133
126
127
128
130
129
131
132
THD (dB)
SFDR ( dB)
2.4 4.84.53.9 4.23.63.33.0
2.7 5.1
REFERENCE VOLTAGE (V)
SFDR
THD
14957-216
Figure 21. THD and SFDR vs. Reference Voltage
–114.0
–114.5
–116.5
–115.5
–115.0
–116.0
–117.0
–117.5
118.0
117.9
117.4
117.7
117.8
117.6
117.2
117.3
117.5
117.1
117.0
THD (dB)
SFDR ( dB)
–40 100806040200–20 120
TEMPERATURE (°C)
THD
SFDR
14957-225
Figure 22. THD and SFDR vs. Temperature, fIN = 1 kHz
101
100
98
96
99
97
95
SINAD (dB)
010 20 30 40 50 60 70 80
tQUIET2 (ns)
VI O = 1. 89V
VIO = 3.6V
VIO = 5.5V
14957-215
Figure 23. SINAD vs. tQUIET2
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 14 of 38
60
58
55
56
59
57
54
ADC OUTPUT RE ADING ( µ V )
0 985 6 74321 10
TIME (Seconds)
14957-217
Figure 24. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples
Averaged per Reading
8
7
3
5
6
4
1
2
0
OPE RATI NG CURRENT ( mA)
VDD HIGH-Z DIS ABLED
VDD HIGH-Z ENABL E D
REF HIG H- Z DIS ABLED
REF HIG H- Z ENABL E D
VIO HIGH-Z DISABLED
VIO HIGH-Z ENABLED
–40 1008060
40200
–20 120
TEMPERATURE (°C)
14957-223
Figure 25. Operating Current vs. Temperature, AD4003, 2 MSPS
0
0.5
1.0
1.5
2.0
2.5
–40 –20 020 40 60 80 100 120
OPERATING CURRENT ( mA)
VDD HIGH-Z ENABL E D
VDD HIGH-Z DIS ABLED
REF HIG H- Z ENABL E D
REF HIG H- Z DIS ABLED
VIO HIGH-Z ENABLED
VIO HIGH-Z DISABLED
TEMPERATURE (°C)
14957-325
Figure 26. Operating Current vs. Temperature, AD4011, 500 kSPS
10
–4
4
8
0
2
6
–2
–8
–6
–10
ZE RO ERRO R AND GAIN E RROR (L S B)
–40 100
8060
40
200
–20 120
TEMPERATURE (°C)
PFS GAI N E RROR
NFS GAI N E RROR
ZERO ERROR
14957-221
Figure 27. Zero Error and Gain Error vs. Temperature Positive Full Scale (PFS)
and Negative Full Scale (NFS)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–40 –20 020 40 60 80 100 120
OPERATI NG CURRENT ( mA)
TEMPERATURE (°C)
VDD HIGH-Z ENABL E D
VDD HIGH-Z DIS ABLED
REF HIG H- Z ENABL E D
REF HIG H- Z DIS ABLED
VIO HIGH-Z ENABLED
VIO HIGH-Z DISABLED
14957-326
Figure 28. Operating Current vs. Temperature, AD4007, 1 MSPS
1.2
REF ERE NCE CURRE NT (mA)
2.4 4.84.53.9 4.23.63.3
3.02.7 5.1
REFERENCE VOLTAGE (V)
14957-218
0
0.2
0.4
0.6
0.8
1.0
2MSPS
1MSPS
500kSPS
Figure 29. Reference Current vs. Reference Voltages
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 15 of 38
25.0
20.0
10.0
15.0
5.0
22.5
17.5
7.5
12.5
2.5
0
STANDBY CURRE NT (µA)
–40 10080
6040200–20 120
TEMPERATURE (°C)
14957-226
Figure 30. Standby Current vs. Temperature
23
21
13
17
19
15
9
11
7
5
tDSDO
(n s)
0100
80
6040 200
180160
14020 220
120
LO AD CAP ACIT ANCE ( pF)
VIO = 5V
VIO = 3.3V
VIO = 1.8V
14957-224
Figure 31. tDSDO vs. Load Capacitance
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 16 of 38
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line (see Figure 33).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
0 V, and the actual voltage producing the midscale output code,
0 LSB.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) occurs at a level
½ LSB above nominal negative full scale (−4.999981 V for the
±5 V range). The last transition (from 011 … 10 to 011 … 11)
occurs for an analog voltage 1½ LSB below the nominal full
scale (+4.999943 V for the ±5 V range). The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
ENOB is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured. The value for dynamic range is
expressed in decibels. It is measured with a signal at −60 dBFS
so that it includes all noise sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to acquire a
full-scale input step to ±1 LSB accuracy.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
the common-mode voltage of IN+ and IN− of frequency, f.
CMRR (dB) = 10log(PADC_IN/PADC_OUT)
where:
PADC_IN is the common-mode power at the frequency, f, applied
to the IN+ and IN− inputs.
PADC_OUT is the power at the frequency, f, in the ADC output.
Power Supply Rejection Ratio (PSRR)
PSRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
the ADC VDD supply of frequency, f.
PSRR (dB) = 10 log(PVDD_IN/PADC_OUT)
where:
PVDD_IN is the power at the frequency, f, at the VDD pin.
PADC_OUT is the power at the frequency, f, in the ADC output.
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 17 of 38
THEORY OF OPERATION
COMP CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUTCODE
CNV
CC2C65,536C 4C
131,072C
LSB SW+
MSB
LSB SW–
MSB
CC2C65,536C 4C131,072C
IN+
REF
GND
IN–
14957-007
Figure 32. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD4003/AD4007/AD4011 are high speed, low power,
single-supply, precise, 18-bit ADCs based on a SAR architecture.
The AD4003 is capable of converting 2,000,000 samples per
second (2 MSPS), the AD4007 is capable of converting 1,000,000
samples per second (1 MSPS), and the AD4011 is capable of
converting 500,000 samples per second (500 kSPS). The power
consumption of the AD4003/AD4007/AD4011 scales with
throughput, because they power down in between conversions.
When operating at 10 kSPS, for example, they typically
consume 80 μW, making them ideal for battery-powered
applications. The AD4003/ AD4007/AD4011 also have a valid
first conversion after being powered down for long periods,
which can further reduce power consumed in applications in
which the ADC does not need to be constantly converting.
The AD4003/AD4007/AD4011 provide the user with an
on-chip, track-and-hold and do not exhibit any pipeline delay
or latency, making them ideal for multiplexed applications.
The AD4003/AD4007/AD4011 incorporate a multitude of
unique ease of use features that result in a lower system power
and footprint.
The AD4003/AD4007/AD4011 each have an internal voltage
clamp that protects the device from overvoltage damage on the
analog inputs.
The analog input incorporates circuitry that reduces the nonlinear
charge kickback seen from a typical switched capacitor SAR input.
This reduction in kickback, combined with a longer acquisition
phase, means reduced settling requirements on the driving
amplifier. This combination allows the use of lower bandwidth
and lower power amplifiers as drivers. It has the additional benefit
of allowing a larger resistor value in the input RC filter and a
corresponding smaller capacitor, which results in a smaller RC
load for the amplifier, improving stability and power dissipation.
High-Z mode can be enabled via the SPI interface by programming
a register bit (see Table 14). When high-Z mode is enabled, the
ADC input has a low input charging current at low input signal
frequencies as well as improved distortion over a wide frequency
range up to 100 kHz. For frequencies greater than 100 kHz and
multiplexing, disable high-Z mode.
For single-supply applications, a span compression feature
creates additional headroom and footroom for the driving
amplifier to access the full range of the ADC.
The fast conversion time of the AD4003/AD4007/AD4011, along
with turbo mode, allows low clock rates to read back conversions,
even when running at their respective maximum throughput
rates. Note that for the AD4003, the full throughput rate of
2 MSPS can be achieved only with turbo mode enabled.
The AD4003/AD4007/AD4011 can interface with any 1.8 V to 5 V
digital logic family. They are available in a 10-lead MSOP or a tiny
10-lead LFCSP that allows space savings and flexible configura-
tions.
The AD4003/AD4007/AD4011 are pin for pin compatible
with some of the 14-/16-/18-/20-bit precision SAR ADCs listed
in Table 8.
Table 8. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs
Bits 100 kSPS 250 kSPS
400 kSPS to
500 kSPS ≥1000 kSPS
201
AD40202
181 AD7989-12 AD76912 AD76902,
AD7989-52,
AD40112
AD40032,
AD79822,
AD79842,
AD40072
161 AD7684 AD76872 AD76882,
AD76932,
AD79162
AD4001,
AD4005,
AD79152
163 AD7680,
AD7683,
AD7988-12
AD76852,
AD7694
AD76862,
AD7988-52
AD40082
AD40002,
AD40042,
AD79802,
AD7983
143 AD7940 AD79422 AD79462 Not applicable
1 True differential.
2 Pin for pin compatible.
3 Pseudo differential.
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 18 of 38
CONVERTER OPERATION
The AD4003/AD4007/AD4011 are SAR-based ADCs using a
charge redistribution sampling digital-to-analog converter
(DAC). Figure 32 shows the simplified schematic of the ADC.
The capacitive DAC consists of two identical arrays of 18 binary
weighted capacitors, which are connected to the comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via the SW+ and
SW− switches. All independent switches connect the other
terminal of each capacitor to the analog inputs. Therefore, the
capacitor arrays are used as sampling capacitors and acquire the
analog signal on the IN+ and IN− inputs.
When the acquisition phase is complete and the CNV input
goes high, a conversion phase initiates. When the conversion
phase begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. The differential voltage between the IN+ and
IN− inputs captured at the end of the acquisition phase is applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and VREF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4, …, VREF/262,144). The
control logic toggles these switches, starting with the MSB, to
bring the comparator back into a balanced condition. After the
completion of this process, the control logic generates the ADC
output code and a busy signal indicator.
Because the AD4003, AD4007, and AD4011 have on-board
conversion clocks, the serial clock (SCK) is not required for the
conversion process.
TRANSFER FUNCTIONS
The ideal transfer characteristics for the AD4003/AD4007/
AD4011 are shown in Figure 33 and Table 9.
100...000
100...001
100...010
011...101
011...110
011...111
ADC CODE (TWOS COMPL EMENT)
ANALO G I NP UT
+FS R – 1.5 L S B
+FS R – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 L S B
14957-008
Figure 33. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
Table 9. Output Codes and Ideal Input Voltages
Description Analog Input, VREF = 5 V VREF = 5 V with Span Compression Enabled Digital Output Code (Hex)
FSR − 1 LSB
+4.999962 V
+3.999969 V
0x1FFFF
1
Midscale + 1 LSB +38.15 µV +30.5 µV 0x00001
Midscale 0 V 0 V 0x00000
Midscale − 1 LSB −38.15 µV −30.5 µV 0x3FFFF
−FSR + 1 LSB −4.999962 V −3.999969 V 0x20001
−FSR −5 V −4 V 0x200002
1 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with the span compression disabled and above 0.8 ×VREF with the span
compression enabled).
2 This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF with the span compression disabled and above 0.8 ×VREF with the span
compression enabled).
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 19 of 38
APPLICATIONS INFORMATION
TYPICAL APPLICATION DIAGRAMS
Figure 34 shows an example of the recommended connection
diagram for the AD4003/AD4007/AD4011 when multiple supplies
are available. This configuration is used for best performance
because the amplifier supplies can be selected to allow the
maximum signal range.
Figure 35 shows a recommended connection diagram when
using a single-supply system. This setup is preferable when only
a limited number of rails are available in the system and power
dissipation is of critical importance.
Figure 36 shows a recommended connection diagram when
using a fully differential amplifier.
C
R
V+
REF VDD VIO
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4003/
AD4007/
AD4011
3-WIRE/4-WIRE
INTERFACE
1.8V
1.8V TO 5V
V
+≥+6.5
V
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
V– ≤ –0.5V
HOST
SUPPLY
0.1µF 0.1µF
5V
C
R
V–
V+
V–
AMP
AMP
V
REF
0V
V
REF
0V
V
CM
= V
REF
/2
V
CM
= V
REF
/2
REF
LDO
AMP
V
CM
= V
REF
/2
10µF
10kΩ
10kΩ
14957-009
Figure 34. Typical Application Diagram with Multiple Supplies
C
R
REF VDD VIO
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4003/AD4007/
AD4011
2
1.8V
1.8V TO 5V
V
+=5V
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
HOST
SUPPLY
0.1µF 0.1µF
100nF 100nF
4.096V
C
R
AMP
AMP
0.9 × V
REF
0.1 × V
REF
0.9 × V
REF
0.1 × V
REF
V
CM
= V
REF
/2
V
CM
= V
REF
/2
REF
1
LDO
AMP
V
CM
= V
REF
/2
10µF
1
10kΩ
10kΩ
1
SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X7R).
2
SPAN COMPRESSION MODE ENABLED.
3
SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION.
3-WIRE/4-WIRE
INTERFACE
14957-010
3
Figure 35. Typical Application Diagram with a Single Supply
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 20 of 38
10µF
REF VDD VIO
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4003/AD4007/
AD4011
3-WIRE/4-WIRE
INTERFACE
1.8V
1.8V TO 5V
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
4.096V
0.1µF
V
OCM
R3
1kΩ
+IN
V+
–IN
–OUT
+OUT
R4
1kΩ
10kΩ
10kΩ
R2
1kΩ
R
R
DIFFERENTIAL
AMPLIFIER
R1
1kΩ
0.1µF
V
CM
= V
REF
/2
HOST
SUPPLY
V–
C
C
REF
V+ = 5V
LDO
AMP
V
REF
0
V
CM
= V
REF
/2
V
REF
0
V
CM
= V
REF
/2
0.1µF
14957-011
V
CM
= V
REF
/2
Figure 36. Typical Application Diagram with a Fully Differential Amplifier
REF VDD VIO
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4003/AD4007/
AD4011
1.8V TO 5V
+IN
–IN
R4
1kΩ
DIFFERENTIAL
AMPLIFIER
R1
1kΩ
V–
AMP
+V
REF
–V
REF
0V
1.8V
10µF
R3
1kΩ
V+
–OUT
+OUT
R2
1kΩ
R
R
0.1µF
VREF/2
HOST
SUPPLY
C
C
REF
V+ = 5V
LDO
10kΩ
10kΩ
V
OCM
4.096V
0.1µF 0.1µF
3-WIRE/4-WIRE
INTERFACE
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
14957-012
V
CM
= V
REF
/2
Figure 37. Typical Application Diagram for Single-Ended to Differential Conversion with a Fully Differential Amplifier
ANALOG INPUTS
Figure 38 shows an equivalent circuit of the analog input
structure, including the overvoltage clamp of the AD4003/
AD4007/AD4011.
14957-013
CEXT
REXT
VIN
REF
D1
IN+/IN–
GND
CLAMP
0V TO 15V RIN CIN
D2
CPIN
Figure 38. Equivalent Analog Input Circuit
Input Overvoltage Clamp Circuit
Most ADC analog inputs, IN+ and IN−, have no overvoltage
protection circuitry apart from ESD protection diodes. During
an overvoltage event, an ESD protection diode from an analog
input pin (IN+ or IN−) pin to REF forward biases and shorts
the input pin to REF, potentially overloading the reference or
causing damage to the device. The AD4003/AD4007/AD4011
internal overvoltage clamp circuit with a larger external resistor
(REXT = 200 Ω) eliminates the need for external protection
diodes and protects the ADC inputs against dc overvoltages.
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 21 of 38
In applications where the amplifier rails are greater than VREF
and less than ground, it is possible for the output to exceed the
input voltage range of the device. In this case, the AD4003/
AD4007/AD4011 internal voltage clamp circuit ensures that the
voltage on the input pin does not exceed VREF + 0.4 V and
prevents damage to the device by clamping the input voltage in a
safe operating range and by avoiding disturbance of the reference,
which is particularly important for systems that share the
reference among multiple ADCs.
If the analog input exceeds the reference voltage by 0.4 V, t h e
internal clamp circuit turns on and the current flows through
the clamp into ground, preventing the input from rising further
and potentially causing damage to the device. The clamp turns
on before D1 (see Figure 38) and can sink up to 50 mA of current.
When the clamp is active, it sets the overvoltage (OV) clamp flag
bit in the register that can be read back (see Table 14), which is
a sticky bit that must be read to be cleared. The status of the
clamp can also be checked in the status bits using the OV clamp
flag (see Table 15). The clamp circuit does not dissipate static
power in the off state. Note that the clamp cannot sustain the
overvoltage condition for an indefinite amount of time.
The external RC filter is usually present at the ADC input to
band limit the input signal. During an overvoltage event,
excessive voltage is dropped across REXT and REXT becomes part
of a protection circuit. The REXT value can vary from 200 Ω to
20 kΩ for 15 V protection. The CEXT value can be as low as 100
pF for correct operation of the clamp. See Table 1 for input
overvoltage clamp specifications.
Differential Input Considerations
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
Figure 39 shows the common-mode rejection capability of the
AD4003/AD4007/AD4011 over frequency. It is important to
note that the differential input signals must be truly antiphase in
nature, 180° out of phase, which is required to keep the common-
mode voltage of the input signal within the specified range
around VREF/2 as shown in Table 1.
72
71
70
69
68
67
66
CMRR (dB)
100 1k 10k 100k 1M
FREQUENCY ( Hz )
14957-303
Figure 39. CMRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C
Switched Capacitor Input
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 40 pF and
is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are open, the
input impedance is limited to CPIN. RIN and CIN make a single-
pole, low-pass filter that reduces undesirable aliasing effects and
limits noise.
RC Filter Values
The RC filter value (represented by R and C in Figure 34 to
Figure 37) and driving amplifier can be selected depending on
the input signal bandwidth of interest at the full throughput.
Lower input signal bandwidth means that the RC cutoff can be
lower, thereby reducing noise into the converter. For optimum
performance at various throughputs, use the recommended RC
values (200 Ω, 180 pF) and the ADA4807-1.
The RC values shown in Table 10 are chosen for ease of drive con-
siderations and greater ADC input protection. The combination
of a large R value (200 Ω) and small C value results in a reduced
dynamic load for the amplifier to drive. The smaller value of C
means less stability and phase margin concerns with the amplifier.
The large value of R limits the current into the ADC input when
the amplifier output exceeds the ADC input range.
Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths
Input Signal Bandwidth (kHz) R (Ω) C (pF) Recommended Amplifier Recommended Fully Differential Amplifier
<10 See the High-Z Mode section ADA4940-1
<200 200 180 ADA4807-1 ADA4940-1
>200 200 120 ADA4897-1 ADA4932-1
Multiplexed 200 120 ADA4897-1 ADA4932-1
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 22 of 38
DRIVER AMPLIFIER CHOICE
Although the AD4003/AD4007/AD4011 are easy to drive, the
driver amplifier must meet the following requirements:
• The noise generated by the driver amplifier must be kept
low enough to preserve the SNR and transition noise perfor-
mance of the AD4003/AD4007/AD4011. The noise from
the driver is filtered by the single-pole, low-pass filter of
the AD4003/AD4007/AD4011 analog input circuit made
by RIN and CIN or by the external filter, if one is used. Because
the typical noise of the AD4003/AD4007/AD4011 is
31.5 µV rms, the SNR degradation due to the amplifier is
+µ
µ
=
−22
)(
2
π
V)(31.5
V 31.5
log20
N
dB3
LOSS
Nef
SNR
where:
f−3 dB is the input bandwidth, in megahertz, of the
AD4003/AD4007/AD4011 (10 MHz) or the cutoff
frequency of the input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp in
nV/√Hz.
• For ac applications, the driver must have a THD performance
commensurate with the AD4003/AD4007/AD4011.
• For multichannel multiplexed applications, the driver
amplifier and the analog input circuit of the AD4003/
AD4007/AD4011 must settle for a full-scale step onto the
capacitor array at an 18-bit level (0.000384%, 3.84 ppm). In
the data sheet of the amplifier, settling at 0.1% to 0.01% is
more commonly specified. This setting may differ
significantly from the settling time at an 18-bit level and
must be verified prior to driver selection.
Single to Differential Driver
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4940-1 single-ended to differential
driver allows a differential input to the device. The schematic is
shown in Figure 37.
High Frequency Input Signals
The AD4003/AD4007/AD4011 ac performance over a wide
input frequency range using a 5 V reference voltage is shown in
Figure 40 and Figure 41. Unlike other traditional SAR ADCs,
the AD4003/AD4007/AD4011 maintain exceptional ac perfor-
mance for input frequencies up to the Nyquist frequency with
minimal performance degradation. Note that the input frequency
is limited to the Nyquist frequency of the sample rate in use.
102
96
90
100
92
94
98
88
17.0
15.5
16.5
14.5
15.0
16.0
14.0
SNR, S INAD (dB)
ENOB (Bit s)
1k 100k10k 1M
INPUT F RE QUENCY ( Hz )
ENOB
SINAD
SNR
14957-211
Figure 40. SNR, SINAD, and ENOB vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V,
VREF = 5 V, 25°C
–90
–105
–95
–115
–110
–100
–120
120
105
115
95
100
110
90
THD ( dB)
SF DR ( dB)
1k 100k10k 1M
INPUT F RE QUENCY ( Hz )
THD
SFDR
14957-214
Figure 41. THD and SFDR vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V,
VREF = 5 V, 25°C
Multiplexed Applications
The AD4003/AD4007/AD4011 significantly reduce system
complexity and cost for multiplexed applications that require
superior performance in terms of noise, power, and throughput.
Figure 42 shows a simplified block diagram of a multiplexed
data acquisition system including a multiplexer, an ADC driver,
and the precision SAR ADC.
SAR ADC
ADC
DRIVER
MULTIPLEXER
SENSORS
R
R
RCC
C
C
14957-341
Figure 42. Multiplexed Data Acquisition Signal Chain Using the
AD4003/AD4007/AD4011
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 23 of 38
Switching multiplexer channels typically results in large voltage
steps at the ADC inputs. To ensure an accurate conversion result,
the step must be given adequate time to settle before the ADC
samples its inputs (on the rising edge of CNV). The settling
time is dependent on the drive circuitry (multiplexer and ADC
driver), RC filter values, and the time when the multiplexer
channels are switched. Switch the multiplexer channels imme-
diately after tQUIET1 has elapsed from the start of the conversion
to maximize settling time while preventing corruption of the
conversion result. To avoid conversion corruption, do not
switch the channels during the tQUIET1 time. If the analog inputs
are multiplexed during the quiet conversion time (tQUIET1), the
current conversion may be corrupted.
EASE OF DRIVE FEATURES
Input Span Compression
In single-supply applications, it is desirable to use the full range
of the ADC; however, the amplifier can have some headroom and
footroom requirements, which can be a problem, even if it is a
rail-to-rail input and output amplifier. The AD4003/AD4007/
AD4011 include a span compression feature, which increases
the headroom and footroom available to the amplifier by reducing
the input range by 10% from the top and bottom of the range
while still accessing all available ADC codes (see Figure 43). The
SNR decreases by approximately 1.9 dB (20 × log(8/10)) for the
reduced input range when span compression is enabled. Span
compression is disabled by default but can be enabled by writing to
the relevant register bit (see the Digital Interface section).
14957-300
ADC
V
REF
= 4.096V
DIGITAL OUTPUT
ALL 2
N
CODES
+FSR
–FSR
90% OF V
REF
= 3.69V
10% OF V
REF
= 0.41V
ANALOG
INPUT
5V
IN+/IN–
Figure 43. Span Compression
High-Z Mode
The AD4003/AD4007/AD4011 incorporate high-Z mode, which
reduces the nonlinear charge kickback when the capacitor DAC
switches back to the input at the start of acquisition. Figure 44
shows the input current of the AD4003/AD4007/AD4011 with
high-Z mode enabled and disabled. The low input current makes
the ADC easier to drive than the traditional SAR ADCs available in
the market, even with high-Z mode disabled. The input current
reduces further to submicroampere range when high-Z mode is
enabled. The high-Z mode is disabled by default but can be enabled
by writing to the register (see Table 14). Disable high-Z mode for
input frequencies above 100 kHz or when multiplexing.
–15
–12
–9
–6
–3
0
3
6
9
12
15
–5 –4 –3 –2 –1 012345
INPUT CURRENT (μA)
INPUT DIFFERENTIAL VOLTAGE (V)
HIG H-Z DISABL E D, 2MSP S
HIG H-Z DISABL E D, 1MSP S
HIG H-Z DISABL E D, 500kSPS
HIG H-Z E NABLED, 2M S P S
HIG H-Z E NABLED, 1M S P S
HIG H-Z E NABLED, 500kS P S
14957-343
Figure 44. Input Current vs. Input Differential Voltage, VDD = 1.8 V
VIO = 3.3 V, VREF = 5 V, 25°C
To achieve the optimum data sheet performance from high
resolution precision SAR ADCs, system designers are often
forced to use a dedicated high power, high speed amplifier to
drive the traditional switched capacitor SAR ADC inputs for
their precision applications, which is commonly encountered in
designing a precision data acquisition signal chain. The benefits
of high-Z mode are low input current for slow (<10 kHz) or dc
type signals and improved distortion (THD) performance over
a frequency range of up to 100 kHz. High-Z mode allows a
choice of lower power and lower bandwidth precision amplifiers
with a lower RC filter cutoff to drive the ADC, removing the need
for dedicated high speed ADC drivers, which saves system power,
size, and cost in precision, low bandwidth applications. High-Z
mode allows the amplifier and RC filter in front of the ADC to be
chosen based on the signal bandwidth of interest and not based
on the settling requirements of the switched capacitor SAR ADC
inputs.
Additionally, the AD4003/AD4007/AD4011 can be driven with a
much higher source impedance than traditional SARs, which
means the resistor in the RC filter can have a value 10 times larger
than previous SAR designs and, with high-Z mode enabled, can
tolerate even larger impedance. Figure 45 shows the THD per-
formance for various source impedances with high-Z mode
disabled and enabled.
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 24 of 38
–85
–90
–100
–110
–95
–105
–115
–120
–125
THD ( dB)
110 20
INPUT F RE QUENCY ( KHz )
1kΩ HIGH-Z DISABLED
1kΩ HIGH-Z ENABLED
510Ω HIGH-Z DISABLED
510Ω HIGH-Z ENABLED
150Ω HIGH-Z DISABLED
150Ω HIGH-Z ENABLED
14957-228
Figure 45. THD vs. Input Frequency for Various Source Impedance, VDD = 1.8
V, VIO = 3.3 V, VREF = 5 V, 25°C
Figure 46 and Figure 47 show the AD4003/AD4007/AD4011
SNR and THD performance using the ADA4077-1 (supply
current per amplifier (ISY) = 400 µA) and ADA4610-1
(ISY = 1.5 mA per amplifier) precision amplifiers when driving the
AD4003/AD4007/AD4011 at full throughput for high-Z mode
enabled and disabled with various RC filter values. These amplifiers
achieve 96 dB to 99 dB typical SNR and better than −110 dB
THD with high-Z enabled. THD is approximately 10 dB better
with high-Z mode enabled, even for large R values. SNR maintains
close to 99 dB even with a very low RC filter bandwidth cutoff.
When high-Z mode is enabled, the ADC consumes approximately
2 mW per MSPS extra power; however, this is still significantly
lower than using dedicated ADC drivers like the ADA4807-1.
For any system, the front end usually limits the overall ac/dc
performance of the signal chain. It is evident from the data sheets
of the selected precision amplifiers, shown in Figure 46 and
Figure 47, that their own noise and distortion performance
dominates the SNR and THD specification at a certain input
frequency.
Long Acquisition Phase
The AD4003/AD4007/AD4011 also feature a very fast
conversion time of 290 ns, which results in a long acquisition
phase. The acquisition is further extended by a key feature of the
AD4003/AD4007/AD4011; the ADC returns back to the
acquisition phase typically 100 ns before the end of the conversion.
This feature provides an even longer time for the ADC to acquire
the new input voltage. A longer acquisition phase reduces the
settling requirement on the driving amplifier, and a lower
power/bandwidth amplifier can be chosen. The longer acquisition
phase means that a lower RC filter (represented by R and C in
Figure 34 and Figure 37) cutoff can be used, which means a
noisier amplifier can also be tolerated. A larger value of R can
be used in the RC filter with a corresponding smaller value of C,
reducing amplifier stability concerns without affecting distortion
performance significantly. A larger value of R also results in
reduced dynamic power dissipation in the amplifier.
See Table 10 for details on setting the RC filter bandwidth and
choosing a suitable amplifier.
100
97
91
85
94
88
82
76
79
73
70 260kHz
1.3kΩ
470pF
498kHz
680Ω
470pF
2.27MHz
390Ω
180pF
1.3MHz
680Ω
180pF
4.42MHz
200Ω
180pF
SNR (d B)
RC FI LT E R BANDWIDTH (Hz)
RESISTOR (Ω), CAPACITOR (pF)
ADA4077-1 HIGH-Z DIS ABLED
ADA4077-1 HIGH-Z ENABL E D
ADA4610-1 HIGH-Z DIS ABLED
ADA4610-1 HIGH-Z ENABL E D
14957-227
Figure 46. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers,
fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V, VIO =
3.3 V, VREF = 5 V, 25°C
–80
–84
–92
–100
–88
–96
–104
–112
–108
–116
–120
THD ( dB)
260kHz
1.3kΩ
470pF
498kHz
680Ω
470pF
2.27MHz
390Ω
180pF
1.3MHz
680Ω
180pF
4.42MHz
200Ω
180pF
RC FI LT E R BANDWIDTH (Hz)
RESISTOR (Ω), CAPACITOR (pF)
ADA4077-1 HIGH-Z DIS ABLED
ADA4077-1 HIGH-Z ENABL E D
ADA4610-1 HIGH-Z DIS ABLED
ADA4610-1 HIGH-Z ENABL E D
14957-229
Figure 47. THD vs. RC Filter Bandwidths for Various Precision ADC Drivers,
fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled) VDD = 1.8 V, VIO =
3.3 V, VREF = 5 V, 25°C
VOLTAGE REFERENCE INPUT
A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate
for the optimum performance of the reference input.
For higher performance and lower drift, use a reference such as
the ADR4550. Use a low power reference such as the ADR3450
at the expense of a slight decrease in the noise performance. It is
recommended to use a reference buffer, such as the ADA4807-1,
between the reference and the ADC reference input. It is important
to consider the optimum capacitance necessary to keep the
reference buffer stable as well as to meet the minimum ADC
requirement stated previously in this section (that is, a 10 μF
ceramic chip capacitor, CREF).
POWER SUPPLY
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 25 of 38
The AD4003/AD4007/AD4011 use two power supply pins: a core
supply (VDD) and a digital input/output interface supply (VIO).
VIO allows direct interface with any logic between 1.8 V and
5.5 V. To reduce the number of supplies needed, VIO and VDD
can be tied together for 1.8 V operation. The ADP7118 low noise,
CMOS, low dropout (LDO) linear regulator is recommended to
power the VDD and VIO pins. The AD4003/AD4007/AD4011
are independent of power supply sequencing between VIO and
VDD. Additionally, the AD4003/AD4007/AD4011 are insensitive
to power supply variations over a wide frequency range, as
shown in Figure 48.
80
75
70
65
60
55
50
PSRR ( dB)
100 1k 10k 100k 1M
FREQUENCY ( Hz )
14957-302
Figure 48. PSRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C
The AD4003/AD4007/AD4011 power down automatically at
the end of each conversion phase; therefore, the power scales
linearly with the sampling rate. This feature makes the device
ideal for low sampling rates (even a few samples per second)
and battery-powered applications. Figure 49 shows the
AD4003/AD4007/AD4011 total power dissipation and
individual power dissipation for each rail.
100k
100
10k
1
10
1k
0.1
0.01
POWER DISSIPATION (µW)
10 1M 2M100k10k1k100
THROUGHP UT (SP S )
VDD
VIO
REF
TOTAL POWER
14957-220
POWER DISSIPATIO N MEASUREMENTS
APPLY TO EACH PRO DUCT OV E R IT S
SPECIF IED T HROUGHP UT RANGE .
Figure 49. Power Dissipation vs. Throughput, VDD = 1.8 V, VIO = 3.3 V,
VREF = 5 V, 25°C
DIGITAL INTERFACE
Although the AD4003/AD4007/AD4011 have a reduced
number of pins, they offer flexibility in their serial interface
modes. The AD4003/AD4007/AD4011 can also be programmed
via 16-bit SPI writes to the configuration registers.
When in CS mode, the AD4003/AD4007/AD4011 are compatible
with SPI, QSPI™, MICROWIRE®, digital hosts, and DSPs. In this
mode, the AD4003/AD4007/AD4011 can use either a 3-wire or
4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections, which is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates the
conversions, to be independent of the readback timing (SDI).
This interface is useful in low jitter sampling or simultaneous
sampling applications.
The AD4003/AD4007/AD4011 provide a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line, similar to a shift register.
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. CS mode is selected if
SDI is high, and daisy-chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, daisy-chain mode is always selected.
In either 3-wire or 4-wire mode, the AD4003/AD4007/AD4011
offer the option of forcing a start bit in front of the data bits. This
start bit can be used as a busy signal indicator to interrupt the
digital host and trigger the data reading. Otherwise, without a
busy indicator, the user must time out the maximum conversion
time prior to readback.
The busy indicator feature is enabled in CS mode if CNV or SDI
is low when the ADC conversion ends.
The state of the SDO on power-up is either low or high-Z
depending on the states of CNV and SDI, as shown in Table 11.
Table 11. State of SDO on Power-Up
CNV SDI SDO
0 0 Low
0 1 Low
1 0 Low
1 1 High-Z
The AD4003/AD4007/AD4011 have turbo mode capability in
both 3-wire and 4-wire mode. Turbo mode is enabled by writing
to the configuration register and replaces the busy indicator feature
when enabled. Turbo mode allows a slower SPI clock rate, making
interfacing simpler. The maximum throughput of 2 MSPS for
the AD4003 can be achieved only with turbo mode enabled and
a minimum SCK rate of 75 MHz. The SCK rate must be
sufficiently fast to ensure the conversion result is clocked out
before another conversion is initiated. The minimum required
SCK rate for an application can be derived based on the sample
period (tCYC), the number of bits that must be read (including
data and optional status bits), and the digital interface mode
being used. Timing diagrams and explanations for each digital
interface mode are given in the digital modes of operation sections
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 26 of 38
below (see the CS Mode, 3-Wire Turbo Mode section through
the CS Mode, 4-Wire with Busy Indicator section).
Status bits can also be clocked out at the end of the conversion
data if the status bits are enabled in the configuration register.
There are six status bits in total as described in Table 12.
The AD4003/AD4007/AD4011 are configured by 16-bit SPI
writes to the desired configuration register. The 16-bit word can
be written via the SDI line while CNV is held low. The 16-bit word
consists of an 8-bit header and 8-bit register data. For isolated
systems, the ADuM141D is recommended, which can support the
75 MHz SCK rate requires to run the AD4003 at its full
throughput of 2 MSPS.
REGISTER READ/WRITE FUNCTIONALITY
The AD4003/AD4007/AD4011 register bits are programmable,
and their default statuses are shown in Table 12. The register
map is shown in Table 14. The OV clamp flag is a read only
sticky bit, and it is cleared only if the register is read and the
overvoltage condition is no longer present. The OVE
A clamp flag
gives an indication of overvoltage condition when it is set to 0.
Table 12. Register Bits
Register Bits Default Status
AOVE
A Clamp Flag 1 bit, 1 = inactive (default)
Span Compression 1 bit, 0 = disabled (default)
High-Z Mode 1 bit, 0 = disabled (default)
Turbo Mode 1 bit, 0 = disabled (default)
Enable Six Status Bits
1 bit, 0 = disabled (default)
All access to the register map must start with a write to the 8-bit
command register in the SPI interface block. The AD4003/
AD4007/AD4011 ignore all 1s until the first 0 is clocked in
(represented by AWENE
A in Figure 50, Figure 51, and Table 13); the
value loaded into the command register is always a 0 followed
by seven command bits. This command determines whether
that operation is a write or a read. The AD4003/AD4007/
AD4011 command register is shown in Table 13.
Table 13. Command Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AWENE R/AWE 0 1 0 1 0 0
All register read/writes must occur while CNV is low. Data on
SDI is clocked in on the rising edge of SCK. Data on SDO is
clocked out on the falling edge of SCK. At the end of the data
transfer, SDO is put in a high impedance state on the rising edge of
CNV if daisy-chain mode is not enabled. If daisy-chain mode is
enabled, SDO goes low on the rising edge of CNV. Register reads
are not allowed in daisy-chain mode.
A register write requires three signal lines: SCK, CNV, and SDI.
During a register write, to read the current conversion results
on SDO, the CNV pin must be brought low after the conversion
is completed; otherwise, the conversion results may be incorrect
on SDO. However, the register write occurs regardless.
The LSB of each configuration register is reserved because a user
reading 16-bit conversion data may be limited to a 16-bit SPI
frame. The state of SDI on the last bit in the SDI frame may be
the state that then persists when CNV rises. Because interface
mode is partly set based on the SDI state when CNV rises, in
this scenario, the user may need to set the final SDI state.
The timing diagrams in Figure 50 through Figure 52 show how
data is read and written when the AD4003/AD4007/AD4011
are configured in register read, write, and daisy-chain mode.
Table 14. Register Map
ADDR[1:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
0x0 Reserved Reserved Reserved Enable six
status bits
Span
compression
High-Z
mode
Turbo
mode
AOVE
A clamp flag (read only
sticky bit)
0xE1
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 27 of 38
t
CYC
t
SCK
t
DIS
t
SCKL
t
SCKH
t
SCNVSCK
t
SSDISCK
t
HSDISCK
t
CNVH
t
EN
CNV
SCK 12 3 4567
01
1
010100
B0
B1
B2
B3
B4B5
B6
WEN R/W 0101ADDR[1:0]
8 9 10 11 12 13 14 15 16
SDI
SDO
t
HSDO
t
DSDO
B7 X
1
D17 D16 D15 D14 D13 D12 D11 D10
14957-021
1
X INDICAT E S A DON’T CARE BI T.
Figure 50. Register Read Timing Diagram
1
CONVE RS IO N RE S ULT ON D17:0
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t
CYC
t
SCK
t
SCKL
t
SCKH
t
SCNVSCK
t
SSDISCK
t
HSDISCK
t
CNVH1
EN
CNV
SCK 12345
0 0
1
0 1 0 1 0 0
WEN R/W 01 0 1 ADDR[1:0]
910 11 12 13 14 15 16 17 18
SDI
SDO
B0B1B2
B3B4B5
B6B7
t
HSDO
t
DSDO
t
HCNVSCK
1
THE US E R M US T W AIT
t
CONV
TI ME W HE N RE ADING BACK THE CO NV E RS ION RE S ULT AND DOING A REGIS TER W RITE AT THE S AM E TIM E .
14957-022
Figure 51. Register Write Timing Diagram
SDIA
SDOA/SDIB
SDOB
00
COMM AND ( 0x14)
0 0COMM AND ( 0x14)
0 0COMM AND ( 0x14)
tCYC
tSCK
tSCKL
tSCKH
tSCNVSCK
CNV
SCK 124
tDIS
tCNVH
DATA (0xAB)
DATA (0xAB)
14957-023
Figure 52. Register Write Timing Diagram, Daisy-Chain Mode
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 28 of 38
28BSTATUS WORD
The 6-bit status word can be appended to the end of a conversion
result, and the default conditions of these bits are shown in Table
15. The status bits must be enabled in the register setting. When
the AOVE
A clamp flag is a 0, it indicates an overvoltage condition. The
AOVE
A clamp flag status bit updates on a per conversion basis.
The SDO line returns to high impedance after the sixth status
bit is clocked out (except in daisy-chain mode). The user is not
required to clock out all status bits to start the next conversion.
The serial interface timing for ACSE
A mode, 3-wire without busy
indicator, including status bits, is shown in Figure 53.
Table 15. Status Bits (Default Conditions)
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AOVE
A clamp flag Span compression High-Z mode Turbo mode Reserved Reserved
SDO D17 D16 D15 D1 D0
SCK 1 2 3 16 17 18
t
SCK
t
SCKL
t
SCKH
tHSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
23 24
t
QUIET2
STATUS BI TS B[ 5: 0]
b1
t
DIS
b0
22
t
CONV
14957-024
Figure 53. ACSE
A Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram Including Status Bits (SDI High)
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 29 of 38
ACSE
A MODE, 3-WIRE TURBO MODE
This mode is typically used when a single AD4003/AD4007/
AD4011 device is connected to an SPI-compatible digital host. It
provides additional time during the end of the ADC conversion
process to clock out the previous conversion result, providing a
lower SCK rate. The AD4003 can achieve a throughput rate of
2 MSPS only when turbo mode is enabled and using a minimum
SCK rate of 75 MHz. With turbo mode enabled, the AD4007 can
also achieve its maximum throughput rate of 1 MSPS with a
minimum SCK rate of 25 MHz, and the AD4011 can achieve its
maximum throughput rate of 500 kSPS with a minimum SCK
rate of 11 MHz. The connection diagram is shown in Figure 54,
and the corresponding timing diagram is shown in Figure 55.
This mode replaces the 3-wire with busy indicator mode by
programming the turbo mode bit, Bit 1 (see Table 14).
When SDI is forced high, a rising edge on CNV initiates a
conversion. The previous conversion data is available to read
after the CNV rising edge. The user must wait tQUIET1 time after
CNV is brought high before bringing CNV low to clock out the
previous conversion result. The user must also wait tQUIET2 time
after the last falling edge of SCK to when CNV is brought high.
When the conversion is complete, the AD4003/AD4007/AD4011
enter the acquisition phase and power down. When CNV goes
low, the MSB is output to SDO. The remaining data bits are
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 18th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
AD4003/
AD4007/
AD4011
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
14957-425
Figure 54. ACSE Mode, 3-Wire Turbo Mode Connection Diagram (SDI High)
SDI = 1
tCYC
CNV
ACQUISITION ACQUISITION
t
ACQ
tSCK
tSCKL
CONVERSION
SCK
D0D1D15D16D17
SDO
tEN
tHSDO
123 16 17 18
tDSDO tDIS
tSCKH
tQUIET1 QUIET2
CONV
14957-029
Figure 55. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 30 of 38
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is typically used when a single AD4003/AD4007/
AD4011 device is connected to an SPI-compatible digital host.
The connection diagram is shown in Figure 56, and the
corresponding timing diagram is shown in Figure 57.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. After a
conversion is initiated, it continues until completion irrespective of
the state of CNV. This feature can be useful, for instance, to bring
CNV low to select other SPI devices, such as analog multiplexers;
however, CNV must be returned high before the minimum
conversion time elapses and then held high for the maximum
possible conversion time to avoid the generation of the busy
signal indicator.
When the conversion is complete, the AD4003/AD4007/
AD4011 enter the acquisition phase and power down. When
CNV goes low, the MSB is output onto SDO. The remaining data
bits are clocked by subsequent SCK falling edges. The data is valid
on both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 18th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
There must not be any digital activity on SCK during the
conversion.
AD4003/AD4007/
AD4011
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
14957-025
Figure 56. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDO D17 D16 D15 D1 D0
tDIS
SCK 1 2 3 16 17 18
tSCK
tSCKL
tSCKH
t
HSDO
tDSDO
CNV
CONVERSIONACQUISITION
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
tQUIET2
tCONV
14957-026
Figure 57. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High)
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 31 of 38
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is typically used when a single AD4003/AD4007/
AD4011 device is connected to an SPI-compatible digital host
with an interrupt input (IRQ).
The connection diagram is shown in Figure 58, and the
corresponding timing diagram is shown in Figure 59.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. SDO
is maintained in high impedance until the completion of the
conversion irrespective of the state of CNV. Prior to the minimum
conversion time, CNV can select other SPI devices, such as analog
multiplexers; however, CNV must be returned low before the
minimum conversion time elapses and then held low for the
maximum possible conversion time to guarantee the generation
of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up resistor of 1 kΩ
on the SDO line, this transition can be used as an interrupt
signal to initiate the data reading controlled by the digital host.
The AD4003/AD4007/AD4011 then enter the acquisition phase
and power down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate,
provided it has an acceptable hold time. After the optional 19th
SCK falling edge or when CNV goes high (whichever occurs
first), SDO returns to high impedance.
If multiple AD4003/AD4007/AD4011 devices are selected at the
same time, the SDO output pin handles this contention without
damage or induced latch-up. Meanwhile, it is recommended to
keep this contention as short as possible to limit extra power
dissipation.
There must not be any digital activity on the SCK during the
conversion.
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
IRQ
VIO
1kΩ
AD4003/AD4007/
AD4011
14957-027
Figure 58. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDO D17 D16 D1 D0
t
DIS
SCK 1 2 3 17 18 19
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
QUIET2
14957-028
Figure 59. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High)
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 32 of 38
CS MODE, 4-WIRE TURBO MODE
This mode is typically used when a single AD4003/AD4007/
AD4011 is connected to an SPI-compatible digital host. It provides
additional time during the end of the ADC conversion process
to clock out the previous conversion result, giving a lower SCK
rate. The AD4003 can achieve a throughput rate of 2 MSPS only
when turbo mode is enabled and using a minimum SCK rate of
75 MHz. With turbo mode enabled, the AD4007 can also achieve
its maximum throughput rate of 1 MSPS with a minimum SCK
rate of 25 MHz, and the AD4011 can achieve its maximum
throughput rate of 500 kSPS with a minimum SCK rate of 11 MHz.
The connection diagram is shown in Figure 60, and the corre-
sponding timing diagram is shown in Figure 61.
This mode replaces the 4-wire with busy indicator mode by
programming the turbo mode bit, Bit 1 (see Table 14).
With SDI high, a rising edge on CNV initiates a conversion.
The previous conversion data is available to read after the CNV
rising edge. The user must wait tQUIET1 time after CNV is brought
high before bringing SDI low to clock out the previous conversion
result. The user must also wait tQUIET2 time after the last falling
edge of SCK to when CNV is brought high.
When the conversion is complete, the AD4003/AD4007/AD4011
enter the acquisition phase and power down. The ADC result
can be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 18th SCK
falling edge or when SDI goes high (whichever occurs first), SDO
returns to high impedance.
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
IRQ
VIO
1kΩ
CS1
AD4003/
AD4007/
AD4011
14957-432
Figure 60. CS Mode, 4-Wire Turbo Mode Connection Diagram
ACQUISITION
SDO
SCK
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
t
CYC
t
SCK
t
SCKL
t
EN
t
HSDO
1 2 3 16 17 18
t
DSDO
t
DIS
t
SCKH
D17 D16 D15 D1 D0
t
QUIET1
t
QUIET2
t
ACQ
CONVERSION
t
CONV
14957-034
Figure 61. CS Mode, 4-Wire Turbo Mode Timing Diagram
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 33 of 38
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is typically used when multiple AD4003/AD4007/
AD4011 devices are connected to an SPI-compatible digital host.
A connection diagram example using two AD4003/AD4007/
AD4011 devices is shown in Figure 62, and the corresponding
timing diagram is shown in Figure 63.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low. Prior to the minimum conversion time, SDI can select
other SPI devices, such as analog multiplexers; however, SDI
must be returned high before the minimum conversion time
elapses and then held high for the maximum possible conversion
time to avoid the generation of the busy signal indicator.
When the conversion is complete, the AD4003/AD4007/
AD4011 enter the acquisition phase and power down. Each
ADC result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided it has an acceptable hold time.
After the 18th SCK falling edge or when SDI goes high (whichever
occurs first), SDO returns to high impedance and another
AD4003/AD4007/AD4011 can be read.
DEVICE A
CONVERT
DATA I N
CLK
DIGITAL HOST
CS1
CS2
14957-030
SDI SDO
CNV
SCK
AD4003/AD4007/
AD4011 AD4003/AD4007/
AD4011
DEVICE B
SDI SDO
CNV
SCK
Figure 62. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO D17 D16 D15 D1 D0
tDIS
SCK 1 2 3 34 35 36
tHSDO tDSDO
tEN
CONVERSIONACQUISITION
tCONV
CYC
tACQ
ACQUISITION
SDI ( CS 1)
CNV
tSSDICNV
tHSDICNV
D1
16 17
tSCK
tSCKL
tSCKH
D0 D17 D16
19 2018
SDI ( CS 2)
tQUIET2
14957-031
Figure 63. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 34 of 38
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is typically used when a single AD4003/AD4007/
AD4011 device is connected to an SPI-compatible digital host
with an interrupt input (IRQ), and when it is desired to keep
CNV, which samples the analog input, independent of the signal
used to select the data reading. This independence is particularly
important in applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 64, and the
corresponding timing diagram is shown in Figure 65.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low. Prior to the minimum conversion time, SDI can
select other SPI devices, such as analog multiplexers; however,
SDI must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high impedance
to low impedance. With a pull-up resistor of 1 kΩ on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD4003/
AD4007/AD4011 then enter the acquisition phase and power
down. The data bits are then clocked out, MSB first, by subsequent
SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
it has an acceptable hold time. After the optional 19th SCK
falling edge or when SDI goes high (whichever occurs first),
SDO returns to high impedance.
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
IRQ
VIO
1kΩ
CS1
14957-032
AD4003/AD4007/
AD4011
Figure 64. CS Mode, 4-Wire with Busy Indicator Connection Diagram
SDO D17 D16 D1 D0
t
DIS
SCK 1 2 3 17 18 19
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
t
QUIET2
14957-033
Figure 65. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 35 of 38
DAISY-CHAIN MODE
Use this mode to daisy-chain multiple AD4003/AD4007/AD4011
devices on a 3-wire or 4-wire serial interface. This feature is useful
for reducing component count and wiring connections, for
example, in isolated multiconverter applications or for systems
with a limited interfacing capacity. Data readback is analogous
to clocking a shift register.
A connection diagram example using two AD4003/AD4007/
AD4011 devices is shown in Figure 66, and the corresponding
timing diagram is shown in Figure 67.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects daisy-chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD4003/AD4007/AD4011 enter the
acquisition phase and power down. The remaining data bits
stored in the internal shift register are clocked out of SDO by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
rising edges. Each ADC in the daisy-chain outputs its data MSB
first, and 18 × N clocks are required to read back the N ADCs.
The data is valid on both SCK edges. The maximum conversion
rate is reduced because of the total readback time.
It is possible to write to each ADC register in daisy-chain mode.
The timing diagram is shown in Figure 52. This mode requires
4-wire operation because data is clocked in on the SDI line with
CNV held low. The same command byte and register data can
be shifted through the entire chain to program all ADCs in the
chain with the same register contents, which requires 8 × (N + 1)
clocks for N ADCs. It is possible to write different register contents
to each ADC in the chain by writing to the furthest ADC in the
chain, first using 8 × (N + 1) clocks, and then the second furthest
ADC with 8 × N clocks, and so forth until reaching the nearest
ADC in the chain, which requires 16 clocks for the command
and register data. It is not possible to read register contents in
daisy-chain mode; however, the six status bits can be enabled if
the user wants to determine the ADC configuration. Note that
enabling the status bits requires six extra clocks to clock out the
ADC result and the status bits per ADC in the chain. Turbo
mode cannot be used in daisy-chain mode.
CONVERT
DATA I N
CLK
DIGITAL HOST
DEVICE BDEVICE A
SDI SDO
CNV
SCK
SDI SDO
CNV
SCK
14957-036
AD4003/AD4007/
AD4011 AD4003/AD4007/
AD4011
Figure 66. Daisy-Chain Mode Connection Diagram
SDO
A
= SDI
B
D
A
17
D
B
17 D
B
16 D
B
15
D
A
16 D
A
15 D
A
1 D
A
0
D
A
1 D
A
0
D
B
1 D
B
0
SCK 1 2 3 34 35 36
t
SSDISCK
t
HSDISCK
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
16 17
t
SCK
t
SCKL
t
SCKH
19 2018
SDI
A
= 0
SDO
B
D
A
17 D
A
16
t
HSDO
t
DSDO
t
QUIET2
t
HSCKCNV
t
DIS
t
QUIET2
t
EN
14957-037
Figure 67. Daisy-Chain Mode Serial Interface Timing Diagram
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 36 of 38
LAYOUT GUIDELINES
The PCB that houses the AD4003/AD4007/AD4011 must be
designed so that the analog and digital sections are separated and
confined to certain areas of the board. The pinout of the AD4003/
AD4007/AD4011, with its analog signals on the left side and its
digital signals on the right side, eases this task.
Avoid running digital lines under the device because they couple
noise onto the die, unless a ground plane under the AD4003/
AD4007/AD4011 is used as a shield. Fast switching signals,
such as CNV or clocks, must not run near analog signal paths.
Avoid crossover of digital and analog signals.
At least one ground plane must be used. It can be common or
split between the digital and analog sections. In the latter case,
join the planes underneath the AD4003/AD4007/AD4011
devices.
The AD4003/AD4007/AD4011 voltage reference input (REF)
has a dynamic input impedance. Decouple the REF pin with
minimal parasitic inductances by placing the reference decoupling
ceramic capacitor close to (ideally right up against) the REF and
GND pins and connect them with wide, low impedance traces.
Finally, decouple the VDD and VIO power supplies of the
AD4003/AD4007/AD4011 with ceramic capacitors, typically
0.1 μF placed close to the AD4003/AD4007/AD4011 and
connected using short, wide traces to provide low impedance
paths and to reduce the effect of glitches on the power supply lines.
An example of the AD4003 layout following these rules is shown in
Figure 68 and Figure 69. Note that the AD4007/AD4011 layout
is equivalent to the AD4003 layout.
EVALUATING THE AD4003/AD4007/AD4011
PERFORMANCE
Other recommended layouts for the AD4003/AD4007/AD4011
are outlined in the user guide of the evaluation board for the
AD4003 (EVAL-AD4003FMCZ). The evaluation board package
includes a fully assembled and tested evaluation board with the
AD4003 documentation, and software for controlling the board
from a PC via the EVAL-SDP-CH1Z. The EVAL-AD4003FMCZ
can also be used to evaluate the AD4007/AD4011 by limiting
the throughput to 1 MSPS/500 kSPS in its software (see UG-1042).
14957-038
Figure 68. Example Layout of the AD4003 (Top Layer)
14957-039
Figure 69. Example Layout of the AD4003 (Bottom Layer)
Data Sheet AD4003/AD4007/AD4011
Rev. C | Page 37 of 38
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 70. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 M AX
0.02 NO M
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
COPLANARITY
0.08
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20 M IN
PKG-004362
08-20-2018-C
FOR PRO P E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATION AND
FUNCTION DESCRIPT IONS
SECTION OF THIS DATA SHEET.
PIN 1
INDICATORAR EAOPTIO NS
(SEEDETAIL A)
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
AREA
SEATING
PLANE
Figure 71. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
AD4003/AD4007/AD4011 Data Sheet
Rev. C | Page 38 of 38
ORDERING GUIDE
Model1,2
Integral
Nonlinearity (INL)
Temperat ur e
Range
Ordering
Quantity Package Description
Package
Option
Marking
Code
AD4003BRMZ ±1.0 LSB −40°C to +125°C Tube, 50 10-Lead MSOP RM-10 C8C
AD4003BRMZ-RL7 ±1.0 LSB −40°C to +125°C Reel, 1000 10-Lead MSOP RM-10 C8C
AD4003BCPZ-RL7 ±1.0 LSB −40°C to +125°C Reel, 1500 10-Lead LFCSP CP-10-9 C8C
AD4007BRMZ ±1.0 LSB −40°C to +125°C Tube, 50 10-Lead MSOP RM-10 C8R
AD4007BRMZ-RL7 ±1.0 LSB −40°C to +125°C Reel, 1000 10-Lead MSOP RM-10 C8R
AD4007BCPZ-RL7 ±1.0 LSB −40°C to +125°C Reel, 1500 10-Lead LFCSP CP-10-9 C8R
AD4011BCPZ-RL7 ±1.0 LSB −40°C to +125°C Reel, 1500 10-Lead LFCSP CP-10-9 C8V
EVAL-AD4003FMCZ AD4003 Evaluation Board
Compatible with EVAL-SDP-CH1Z
1 Z = RoHS Compliant Part.
2 The EVAL-AD4003FMCZ can also be used to evaluate the AD4007 and AD4011 by setting the throughput to 1 MSPS and 500 kSPS in its software, respectively (see
UG-1042).
©2016–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14957-0-4/19(C)
