1
LT1640L/LT1640H
1640lhfb
Negative Voltage
Hot Swap Controller
■
Allows Safe Board Insertion and Removal
from a Live – 48V Backplane
■
Operates from –10V to – 80V
■
Programmable Inrush Current
■
Programmable Electronic Circuit Breaker
■
Programmable Overvoltage Protection
■
Programmable Undervoltage Lockout
■
Power Good Control Output
The LT
®
1640L/LT1640H is an 8-pin, negative voltage Hot
Swap
TM
controller that allows a board to be safely inserted
and removed from a live backplane. Inrush current is
limited to a programmable value by controlling the gate
voltage of an external N-channel pass transistor. The pass
transistor is turned off if the input voltage is less than the
programmable undervoltage threshold or greater than the
overvoltage threshold. A programmable electronic circuit
breaker protects the system against shorts. The PWRGD
(LT1640L) or PWRGD (LT1640H) signal can be used to
directly enable a power module. The LT1640L is designed
for modules with a low enable input and the LT1640H for
modules with a high enable input.
The LT1640L/LT1640H is available in 8-pin PDIP and SO
packages.
■
Central Office Switching
■
–48V Distributed Power Systems
■
Negative Power Supply Control
Hot Swap is a trademark of Linear Technology Corporation.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Input Inrush Current
1640 F06b
V
EE
V
DD
LT1640L
SENSE
C1
†
150nF
25V
C2
†
3.3nF
100V
C3
0.1µF
100V
C4
100µF
100V
Q1
IRF530
R2
10Ω
5%
R3
†
18k
5%
1N4148
R4
†
562k
1%
R5
†
9.09k
1%
R6
†
10k
1%
R1
†
0.02Ω
5%
4
OV
GND
GND (SHORT PIN)
3
2
–48V
OV = 71V
*
* DIODES INC. SMAT70A
†
THESE COMPONENTS ARE APPLICATION
SPECIFIC AND MUST BE SELECTED BASED
UPON OPERATING CONDITIONS AND DESIRED
PERFORMANCE. SEE APPLICATIONS
INFORMATION.
UV = 37V
UV
56
8
7
1
GATE DRAIN
PWRGD
1640 TA01
V
OUT+
SENSE
+
TRIM
SENSE
–
V
OUT–
V
IN–
ON/OFF
LUCENT
JW050A1-E
V
IN+
2
95V
8
7
6
5
1
4
+
C5
100µF
16V
+
43
21
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
INRUSH
CURRENT
1A/DIV
GATE – V
EE
10V/DIV
DRAIN
50V/DIV
V
EE
50V/DIV
5ms/DIV
CONTACT
BOUNCE
2
LT1640L/LT1640H
1640lhfb
ABSOLUTE MAXIMUM RATINGS
W
WW
U
Supply Voltage (V
DD
– V
EE
) .................... –0.3V to 100V
DRAIN, PWRGD, PWRGD Pins ............... –0.3V to 100V
SENSE, GATE Pins.................................... –0.3V to 20V
UV, OV Pins .............................................. –0.3V to 60V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LT1640LC/LT1640HC ............................. 0°C to 70°C
LT1640LI/LT1640HI .......................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
(Note 1), All Voltages Referred to VEE
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC
V
DD
Supply Operating Range ●10 80 V
I
DD
Supply Current UV = 3V, OV = V
EE
, SENSE = V
EE
●1.3 5 mA
V
CB
Circuit Breaker Trip Voltage V
CB
= (V
SENSE
– V
EE
)●40 50 60 mV
I
PU
GATE Pin Pull-Up Current Gate Drive On, V
GATE
= V
EE
●–30 –45 –60 µA
I
PD
GATE Pin Pull-Down Current Any Fault Condition 24 50 70 mA
I
SENSE
SENSE Pin Current V
SENSE
= 50mV –20 µA
∆V
GATE
External Gate Drive (V
GATE
– V
EE
), 15V ≤ V
DD
≤ 80V ●10 13.5 18 V
(V
GATE
– V
EE
), 10V ≤ V
DD
< 15V ●6815 V
V
UVH
UV Pin High Threshold Voltage UV Low to High Transition ●1.213 1.243 1.272 V
V
UVL
UV Pin Low Threshold Voltage UV High to Low Transition ●1.198 1.223 1.247 V
V
UVHY
UV Pin Hysteresis 20 mV
I
INUV
UV Pin Input Current V
UV
= V
EE
●–0.02 –0.5 µA
V
OVH
OV Pin High Threshold Voltage OV Low to High Transition ●1.198 1.223 1.247 V
V
OVL
OV Pin Low Threshold Voltage OV High to Low Transition ●1.165 1.203 1.232 V
V
OVHY
OV Pin Hysteresis 20 mV
I
INOV
OV Pin Input Current V
OV
= V
EE
●–0.03 –0.5 µA
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted.
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
S8 PART MARKING
LT1640LCN8
LT1640LCS8
LT1640LIN8
LT1640LIS8
1640L
1640LI
TJMAX = 125°C, θJA = 120°C/W (N8)
TJMAX = 125°C, θJA = 150°C/W (S8)
1
2
3
4
8
7
6
5
TOP VIEW
V
DD
DRAIN
GATE
SENSE
PWRGD
OV
UV
V
EE
N8 PACKAGE
8-LEAD PDIP S8 PACKAGE
8-LEAD PLASTIC SO
ORDER PART
NUMBER
S8 PART MARKING
LT1640HCN8
LT1640HCS8
LT1640HIN8
LT1640HIS8
1640H
1640HI
TJMAX = 125°C, θJA = 120°C/W (N8)
TJMAX = 125°C, θJA = 150°C/W (S8)
1
2
3
4
8
7
6
5
TOP VIEW
V
DD
DRAIN
GATE
SENSE
PWRGD
OV
UV
V
EE
N8 PACKAGE
8-LEAD PDIP S8 PACKAGE
8-LEAD PLASTIC SO
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LT1640L/LT1640H
1640lhfb
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
PG
Power Good Threshold V
DRAIN
– V
EE
, High to Low Transition 1.1 1.4 2.0 V
V
PGHY
Power Good Threshold Hysteresis 0.4 V
I
DRAIN
Drain Input Bias Current V
DRAIN
= 48V ●10 50 500 µA
V
OL
PWRGD Output Low Voltage PWRGD (LT1640L), (V
DRAIN
– V
EE
) < V
PG
I
OUT
= 1mA ●0.48 0.8 V
I
OUT
= 5mA 1.50 3.0 V
PWRGD Output Low Voltage PWRGD (LT1640H), V
DRAIN
= 5V
(PWRGD – DRAIN) I
OUT
= 1mA ●0.75 1.0 V
I
OH
Output Leakage PWRGD (LT1640L), V
DRAIN
=48V, ●0.05 10 µA
V
PWRGD
= 80V
R
OUT
Power Good Output Impedance PWRGD (LT1640H), (V
DRAIN
– V
EE
) < V
PG
●2 6.5 kΩ
(PWRGD to DRAIN)
AC
t
PHLOV
OV High to GATE Low Figures 1, 2 1.7 µs
t
PHLUV
UV Low to GATE Low Figures 1, 3 1.5 µs
t
PLHOV
OV Low to GATE High Figures 1, 2 5.5 µs
t
PLHUV
UV High to GATE High Figures 1, 3 6.5 µs
t
PHLSENSE
SENSE High to Gate Low Figures 1, 4 2 3 4 µs
t
PHLPG
DRAIN Low to PWRGD Low (LT1640L) Figures 1, 5 0.5 µs
DRAIN Low to (PWRGD – DRAIN) High (LT1640H) Figures 1, 5 0.5 µs
t
PLHPG
DRAIN High to PWRGD High (LT1640L) Figures 1, 5 0.5 µs
DRAIN High to (PWRGD – DRAIN) Low (LT1640H) Figures 1, 5 0.5 µs
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to V
EE
unless otherwise
specified.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
1.3
1.4
1.5
60 100
1640 G01
1.2
1.1
020 40 80
1.6
1.7
1.8
Supply Current vs Supply Voltage
TEMPERATURE (°C)
–50 –25
1.0
SUPPLY CURRENT (mA)
1.1
1.2
1.3
1.4
1.6
0255075
1640 G02
100
1.5
Supply Current vs Temperature
SUPPLY VOLTAGE (V)
0
6
GATE VOLTAGE (V)
7
9
10
11
40 80 100
15
1640 G03
8
20 60
12
13
14
Gate Voltage vs Supply Voltage
4
LT1640L/LT1640H
1640lhfb
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Gate Voltage vs Temperature
TEMPERATURE (°C)
12.0
GATE VOLTAGE (V)
13.0
14.0
15.0
12.5
13.5
14.5
–25 0 75
1640 G04
100–50 25 50
TEMPERATURE (°C)
–50
48
TRIP VOLTAGE (mV)
49
51
52
53
55
250 50
1640 G05
50
54
100
–25 75
TEMPERATURE (°C)
–50
GATE PULL-UP CURRENT (µA)
48
47
46
45
44
43
42
41
40 75
1640 G06
–25 10050250
V
GATE
= 0V
Gate Pull-Up Current
vs Temperature
Gate Pull-Down Current
vs Temperature
TEMPERATURE (°C)
–50
GATE PULL-DOWN CURRENT (mA)
49
52
55
75
1640 G07
46
43
40 –25 0 25 50 100
V
GATE
= 2V
PWRGD Output Low Voltage
vs Temperature (LT1640L)
TEMPERATURE (°C)
–50
PWRGD OUTPUT LOW VOLTAGE (V)
0.3
0.4
0.5
75
1640 G08
0.2
0.1
0–25 25
050 100
I
OUT
= 1mA
TEMPERATURE (°C)
–50
2
OUTPUT IMPEDANCE (kΩ)
3
4
5
6
7
8
–25 2505075
1640 G09
100
V
DRAIN
– V
EE
> 2.4V
PWRGD Output Impedance
vs Temperature (LT1640H)
Circuit Breaker Trip Voltage
vs Temperature
pin which pulls the module’s enable pin low, forcing it off.
When V
DRAIN
drops below V
PG
, the PWRGD sink current
is turned off and a 6.5k resistor is connected between
PWRGD and DRAIN, allowing the module’s pull-up cur-
rent to pull the enable pin high and turn on the module.
OV
(Pin 2): Analog Overvoltage Input. When OV is pulled
above the 1.223V low to high threshold, an overvoltage
condition is detected and the GATE pin will be immediately
pulled low. The GATE pin will remain low until OV drops
below the 1.203V high to low threshold.
PIN FUNCTIONS
UUU
PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin
will toggle when V
DRAIN
is within V
PG
of V
EE
. This pin can
be connected directly to the enable pin of a power module.
When the DRAIN pin of the LT1640L is above V
EE
by more
than V
PG
, the PWRGD pin will be high impedance, allowing
the pull-up current of the module’s enable pin to pull the
pin high and turn the module off. When V
DRAIN
drops
below V
PG
, the PWRGD pin sinks current to V
EE
, pulling
the enable pin low and turning on the module.
When the DRAIN pin of the LT1640H is above V
EE
by more
than V
PG
, the PWRGD pin will sink current to the DRAIN
5
LT1640L/LT1640H
1640lhfb
PIN FUNCTIONS
UUU
UV (Pin 3): Analog Undervoltage Input. When UV is
pulled below the 1.223V high to low threshold, an under-
voltage condition is detected and the GATE pin will be
immediately pulled low. The GATE pin will remain low
until UV rises above the 1.243 low to high threshold.
The UV pin is also used to reset the electronic circuit
breaker. If the UV pin is cycled low and high following the
trip of the circuit breaker, the circuit breaker is reset and
a normal power-up sequence will occur.
V
EE
(Pin 4): Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between V
EE
and
SENSE, the circuit breaker will trip when the voltage
across the resistor exceeds 50mV. Noise spikes of less
than 2µs are filtered out and will not trip the circuit
breaker.
If the circuit breaker trip current is set to twice the normal
operating current, only 25mV is dropped across the
sense resistor during normal operation. To disable the
circuit breaker, V
EE
and SENSE can be shorted together.
GATE (Pin 6): Gate Drive Output for the External
N-Channel. The GATE pin will go high when the following
start-up conditions are met: the UV pin is high, the OV pin
is low and (V
SENSE
– V
EE
) < 50mV. The GATE pin is pulled
high by a 45µA current source and pulled low with a
50mA current source.
DRAIN (Pin 7): Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel and the V
–
pin
of the power module. When the DRAIN pin is below V
PG
,
the PWRGD or PWRGD pin will toggle.
V
DD
(Pin 8): Positive Supply Voltage Input. Connect this
pin to the higher potential of the power supply inputs and
the V
+
pin of the power module. The input supply voltage
ranges from 10V to 80V.
BLOCK DIAGRA
W
–
+
–
+
+
–
+
–
DRAIN
1640 BD
GATESENSEV
EE
V
EE
V
PG
OUTPUT
DRIVE PWRGD/PWRGD
50mV
V
CC
V
DD
REF
REF
UV
OV
LOGIC
AND
GATE DRIVE
V
CC
AND
REFERENCE
GENERATOR
–
+
–
+
6
LT1640L/LT1640H
1640lhfb
TEST CIRCUIT
PWRGD/PWRGD VDD
V+
5V
OV
VDRAIN
48V
R
5k
DRAIN
LT1640L/LT1640H
UV GATE
VEE SENSE
VSENSE
1640 F01
VUV
VOV
+
–
Figure 1. Test Circuit
2V
1V
1640 F02
t
PHLOV
1.223V
0V
OV
GATE 1V
1.203V
t
PLHOV
TIMING DIAGRAMS
WUW
Figure 2. OV to GATE Timing
2V
1V
1640 F03
t
PHLUV
1.223V
0V
UV
GATE 1V
1.243V
t
PLHUV
Figure 3. UV to GATE Timing
Figure 4. SENSE to GATE Timing
1V
1640 F04
t
PHLSENSE
50mV
SENSE
GATE
1.8V
1V
1640 F05
0V
VPWRGD – VDRAIN = 0V
DRAIN
PWRGD 1V
1.4V
1.8V
1V
tPLHPG
VEE
VEE
DRAIN
PWRGD 1V
1.4V
tPHLPG
tPLHPG tPHLPG
Figure 5. DRAIN to PWRGD/PWRGD Timing
7
LT1640L/LT1640H
1640lhfb
APPLICATIONS INFORMATION
WUUU
Hot Circuit Insertion
When circuit boards are inserted into a live – 48V backplane,
the bypass capacitors at the input of the board’s power
module or switching power supply can draw huge tran-
sient currents as they charge up. The transient currents
can cause permanent damage to the board’s components
and cause glitches on the system power supply.
The LT1640 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module off until its
input voltage is stable and within tolerance.
+
VEE
VDD
LT1640H PWRGD
UV = 37V
OV = 71V
SENSE
C1
150nF
25V
C3
0.1µF
100V
C4
100µF
100V C5
100µF
16V
Q1
IRF530
R2
10Ω
5%
R3
18k
5%
C2
3.3nF
100V
R4
562k
1%
R5
9.09k
1%
R6
10k
1%
R1
0.02Ω
5%
4
3
2OV
GND
GND
–48V
UV
56
8
7
1
GATE DRAIN
VICOR
VI-J3D-CY
VOUT+
VOUT–
VIN+5V
1640 F06a
GATE IN
VIN–
+
(SHORT PIN)
*
* DIODES INC. SMAT70A
2× 1N4148
43
21
Power Supply Ramping
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a, all waveforms are with respect to
the V
EE
pin of the LT1640). R1 provides current fault
detection and R2 prevents high frequency oscillations.
Resistors R4, R5 and R6 provide undervoltage and over-
voltage sensing. By ramping the gate of Q1 up at a slow
rate, the surge current charging load capacitors C3 and C4
can be limited to a safe value when the board makes
connection.
Resistor R3 and capacitor C2 act as a feedback network to
accurately control the inrush current. The inrush current
can be calculated with the following equation:
I
INRUSH
= (45µA • C
L
)/C2
where C
L
is the total load capacitance, C3 + C4 + module
input capacitance.
Figure 6a. Inrush Control Circuitry
8
LT1640L/LT1640H
1640lhfb
APPLICATIONS INFORMATION
WUUU
Capacitor C1 and resistor R3 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C1 and R3, capacitor C2 would pull the gate of Q1
up to a voltage roughly equal to V
EE
• C2/C
GS
(Q1) before
the LT1640 could power up and actively pull the gate low.
By placing capacitor C1 in parallel with the gate capaci-
tance of Q1 and isolating them from C2 using resistor R3
the problem is solved. The value of C1 should be:
VV
VCC
INMAX TH
TH GD
−
•+
()
2
where V
TH
is the MOSFET’s minimum gate threshold and
V
INMAX
is the maximum operating input voltage.
R3’s value is not critical and is given by (V
INMAX
+ ∆V
GATE
)/
5mA.
The waveforms are shown in Figure 6b. When the power
pins make contact, they bounce several times. While the
contacts are bouncing, the LT1640 senses an undervoltage
condition and the GATE is immediately pulled low when
the power pins are disconnected.
Once the power pins stop bouncing, the GATE pin starts to
ramp up. When Q1 turns on, the GATE voltage is held
constant by the feedback network of R3 and C2. When the
DRAIN voltage has finished ramping, the GATE pin then
ramps to its final value.
Figure 6b. Inrush Control Waveforms
1640 F06b
INRUSH
CURRENT
1A/DIV
GATE – V
EE
10V/DIV
DRAIN
50V/DIV
V
EE
50V/DIV
5ms/DIV
CONTACT
BOUNCE
9
LT1640L/LT1640H
1640lhfb
APPLICATIONS INFORMATION
WUUU
V
EE
V
DD
LT1640L PWRGD
SENSE
C1
150nF
25V
C
L
100µF
100V
Q1
IRF530
R2
10Ω
5%
R3
18k
5%
C2
3.3nF
100V
R4
562k
1%
R5
9.09k
1%
R6
10k
1%
R1
0.02Ω
5%
4
3
2
OV = 71V
GND
–48V
UV = 37V
OV
UV
5
C3 6
8
1
GATE DRAIN
1640 F08
+
7
1N4148
GND (SHORT PIN)
*
* DIODES INC. SMAT70A
R7
43
21
Figure 8. Extending the Short-Circuit Protection DelayFigure 7. Start-Up Into a Short Circuit
1640 F07
Electronic Circuit Breaker
The LT1640 features an electronic circuit breaker function
that protects against short circuits or excessive supply
currents. By placing a sense resistor between the V
EE
and
SENSE pin, the circuit breaker will be tripped whenever the
voltage across the sense resistor is greater than 50mV for
more than 3µs as shown in Figure 7.
Note that the circuit breaker threshold should be set
sufficiently high to account for the sum of the load current
and the inrush current. If the load current can be controlled
by the PWRGD/PWRGD pin (as in Figure 6a), the threshold
can be set lower, since it will never need to accommodate
inrush current and load current simultaneously.
When the circuit breaker trips, the GATE pin is immediately
pulled to V
EE
and the external N-channel turns off. The
GATE pin will remain low until the circuit breaker is reset
by pulling UV low, then high or cycling power to the part.
If more than 3µs deglitching time is needed to reject
current noise, an external resistor and capacitor can be
added to the sense circuit as shown in Figure 8. R7 and C3
act as a lowpass filter that will slow down the SENSE pin
voltage from rising too fast. Since the SENSE pin will
source current, typically 20µA, there will be a voltage drop
on R7. This voltage will be counted into the circuit breaker
trip voltage just as the voltage across the sense resistor.
A small resistor is recommended for R7. A 100Ω for R7
will cause a 2mV error. The following equation can be used
to estimate the delay time at the SENSE pin:
tRCIn Vt Vt
VVt
O
iO
=
–•• –()– ( )
–()
1
Where V(t) is the circuit breaker trip voltage, typically
50mV. V(t
O
) is the voltage drop across the sense resistor
before the short or over current condition occurs. V
i
is the
voltage across the sense resistor when the short current
or over current is applied on it.
Example: A system has a 1A current load and a 0.02Ω
sense resistor is used. An extended delay circuit needs to
be designed for a 50µs delay time after the load jumps to
5A. In this case:
V(t) = 50mV
V(t
O
) = 20mV
V
i
= 5A • 0.02Ω = 100mV
If R7 = 100Ω, then C3 = 1µF.
INRUSH
CURRENT
2A/DIV
GATE – V
EE
4V/DIV
V
EE
50V/DIV
4ms/DIV
10
LT1640L/LT1640H
1640lhfb
APPLICATIONS INFORMATION
WUUU
Under some conditions, a short circuit at the output can
cause the input supply to dip below the UV threshold,
resetting the circuit breaker immediately.
The LT1640 then cycles on and off repeatedly until the
short is removed. This can be minimized by adding a
deglitching delay to the UV pin with a capacitor from UV to
V
EE
. This capacitor forms an RC time constant with the
resistors at UV, allowing the input supply to recover before
the UV pin resets the circuit breaker.
A circuit that automatically resets the circuit breaker after
a current fault is shown in Figure 9.
Transistors Q2 and Q3 along with R7, R8, C4 and D1 form
a programmable one-shot circuit. Before a short occurs,
the GATE pin is pulled high and Q3 is turned on, pulling
node 2 to V
EE
. Resistor R8 turns off Q2. When a short
occurs, the GATE pin is pulled low and Q3 turns off. Node
2 starts to charge C4 and Q2 turns on, pulling the UV pin
low and resetting the circuit breaker. As soon as C4 is fully
charged, R8 turns off Q2, UV goes high and the GATE
starts to ramp up. Q3 turns back on and quickly pulls node
2 back to V
EE
. Diode D1 clamps node 3 one diode drop
below V
EE
. The duty cycle is set to 10% to prevent Q1 from
overheating.
VEE
VDD
LT1640L PWRGD
SENSE
C1
150nF
25V
C4
1µF
100V C3
100µF
100V
Q1
IRF530
R2
10Ω
5%
R8
510k
5%
R3
18k
5%
C2
3.3nF
100V
R4
562k
1%
R7
1M
5%
R5
19.1k
1%
R9
10k
1%
R6
562k
1%
Q3
ZVN3310
Q2
2N2222
D1
1N4148
R1
0.02Ω
5%
4
3
2OV
–48V
UV
56
8
7
1
GATE DRAIN
1640 F09a
3
2
+
GND
(SHORT PIN)
GND
*
* DIODES INC. SMAT70A
1N4148
43
21
Figure 9. Automatic Restart After Current Fault
1640 F09b
NODE 2
50V/DIV
GATE
2V/DIV
1s/DIV
11
LT1640L/LT1640H
1640lhfb
APPLICATIONS INFORMATION
WUUU
Undervoltage and Overvoltage Detection
The UV (Pin 3) and OV (Pin 2) pins can be used to detect
undervoltage and overvoltage conditions at the power
supply input. The UV and OV pins are internally connected
to analog comparators with 20mV of hysteresis. When the
UV pin falls below its threshold or the OV pin rises above
its threshold, the GATE pin is immediately pulled low. The
GATE pin will be held low until UV is high and OV is low.
The undervoltage and overvoltage trip voltages can be
programmed using a three resistor divider as shown in
Figure 10a. With R4 = 562k, R5 = 9.09k and R6 = 10K, the
undervoltage threshold is set to 37V and the overvoltage
threshold is set to 71V. The resistor divider will also gain
up the 20mV hysteresis at the UV pin and OV pin to 0.6V
and 1.2V at the input respectively.
More hysteresis can be added to the UV threshold by
connecting resistor R3 between the UV pin and the GATE
pin as shown in Figure 10b.
Figure 10a. Undervoltage and Overvoltage Sensing
V
EE
V
DD
LT1640L
LT1640H
R4
R5
R6
4
1640 F10a
OV
GND
GND
3
2
–48V
UV
8
V
UV
= 1.223 R4 + R5+ R6
R5 + R6
()
V
OV
= 1.223 R4 + R5+ R6
R6
()
(SHORT PIN)
V
EE
V
DD
LT1640L/LT1640H
SENSE
C1
150nF
25V
Q1
IRF530
R6
10Ω
5%
R1
562k
1%
R3
1.62M
1%
R2
16.9k
1%
R4
506k
1%
R5
8.87k
1%
R1
0.02Ω
5%
4
2
3
UV = 37.6V
UV = 43V
GND
GND
–48V
UV
OV
56
8
GATE
1640 F10b
OV = 71V
(SHORT PIN)
*
* DIODES INC. SMAT70A
43
21
Figure 10b. Programmable Hysteresis for Undervoltage Detection
12
LT1640L/LT1640H
1640lhfb
The new threshold voltage when the input moves from low
to high is:
VV
R R RR RR
RR
UV LH UVH,•••
•
=++
23 13 12
23
where V
UVH
is typically 1.243V.
The new threshold voltage when the input moves from
high to low is:
VV
R R RR RR
RR VR
R
UV HL UVL GATE, •••
•–•=++
23 13 12
23
1
3
where V
UVL
is typically 1.223V.
The new hysteresis value will be:
VVR R RR RR
RR VR
R
HYS UVHY GATE
=++
+
23 13 12
23
1
3
•••
••
With R1 = 562k, R2 = 16.9k and R3 = 1.62M, V
GATE
= 13.5V
and V
UVHY
= 20mV, the undervoltage threshold will be 43V
(from low to high) and 37.6V (from high to low). The
hysteresis is 5.4V. A separate resistor divider should be
used to set the overvoltage threshold given by:
APPLICATIONS INFORMATION
WUUU
VV
RR
R
OV OVH
=+
45
5
With R4 = 506k, R5 = 8.87k and V
OVH
= 1.223V, the
overvoltage threshold will be 71V.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly en-
able a power module when the input voltage to the module
is within tolerance. The LT1640L has a PWRGD output for
modules with an active low enable input, and the LT1640H
has a PWRGD output for modules with an active high
enable input.
When the DRAIN voltage of the LT1640H is high with
respect to V
EE
(Figure 11), the internal transistor Q3 is
turned off and R7 and Q2 clamp the PWRGD pin one diode
drop (≈0.7V) above the DRAIN pin. Transistor Q2 sinks
the module’s pull-up current and the module turns off.
When the DRAIN voltage drops below V
PG
, Q3 will turn on,
shorting the bottom of R7 to DRAIN and turning Q2 off.
The pull-up current in the module then flows through R7,
pulling the PWRGD pin high and enabling the module.
+
V
EE
V
DD
LT1640H
SENSE
C1
C3
Q1
R2 R3 C2
R4
R5
R6
R1
4
3
2OV
GND
–48V
UV
56
8
1
7
GATE
1640 F11
PWRGD
DRAIN
V
EE
R7
6.5k Q2
–
+
V
PG
Q3
ACTIVE HIGH
ENABLE MODULE
V
OUT+
V
OUT–
V
IN+
V
IN–
ON/OFF
GND (SHORT PIN)
*
* DIODES INC. SMAT70A
2× 1N4148
43
21
+
–
Figure 11. Active High Enable Module
13
LT1640L/LT1640H
1640lhfb
Figure 13. Using PWRGD to Drive an Optoisolator
V
EE
V
DD
LT1640L PWRGD
SENSE
C1
150nF
25V
C3
100µF
100V
Q1
IRF530
R2
10Ω
5%
R7
51k
5%
R3
18k
5%
C2
3.3nF
100V
R4
562k
1%
R5
9.09k
1%
R6
10k
1%
R1
0.02Ω
5%
4
3
2OV
GND
–48V
UV
56
8
7
1MOC207
GATE DRAIN
1640 F13
PWRGD
+
GND (SHORT PIN)
*
1N4148
* DIODES INC. SMAT70A
43
21
APPLICATIONS INFORMATION
WUUU
+
V
EE
V
DD
LT1640L
SENSE
C1
C3
Q1
R2 R3 C2
R4
R5
R6
R1
4
3
2OV
GND
GND
–48V
UV
56
8
1
7
GATE
ACTIVE LOW
ENABLE MODULE
V
OUT+
V
OUT–
V
IN+
1640 F12
V
IN–
PWRGD
DRAIN
V
PG
V
EE
ON/OFF
–
+
(SHORT PIN)
*
* DIODES INC. SMAT70A
1N4148
43
21
+
–
Q2
Figure 12. Active Low Enable Module
When the DRAIN voltage of the LT1640L is high with
respect to V
EE
, the internal pull-down transistor Q2 is off
and the PWRGD pin is in a high impedance state (Fig-
ure␣ 12). The PWRGD pin will be pulled high by the module’s
internal pull-up current source, turning the module off.
When the DRAIN voltage drops below V
PG
, Q2 will turn on
and the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED or
optoisolator to indicate that the power is good as shown
in Figure 13.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 15.5V,
the GATE pin voltage is regulated at 13.5V above V
EE
. If the
supply voltage is less than 15.5V, the GATE voltage will be
about 2V below the supply voltage. At the minimum 10V
supply voltage, the gate voltage is guaranteed to be greater
than 6V. The gate voltage will be no greater than 18V for
supply voltages up to 80V.
14
LT1640L/LT1640H
1640lhfb
PACKAGE DESCRIPTION
U
N8 1098
0.100
(2.54)
BSC
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
12 34
8765
0.255 ± 0.015*
(6.477 ± 0.381)
0.400*
(10.160)
MAX
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.035
–0.015
+0.889
–0.381
8.255
()
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
15
LT1640L/LT1640H
1640lhfb
PACKAGE DESCRIPTION
U
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 1298
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
16
LT1640L/LT1640H
1640lhfb
LINEAR TECHNOLOGY CORPORATION 1998
LT/TP 1101 1.5K REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
TYPICAL APPLICATION
U
Using an EMI Filter Module
Many applications place an EMI filter module in the power
path to prevent switching noise of the module from being
injected back onto the power supply. A typical application
using the Lucent FLTR100V10 filter module is shown in
Figure 14. When using a filter, an optoisolator is required
to prevent common mode transients from destroying the
PWRGD and ON/OFF pins.
PART NUMBER DESCRIPTION COMMENTS
LTC®1421 Dual Channel, Hot Swap Controller Operates from 3V to 12V
LTC1422 High Side Drive, Hot Swap Controller in SO-8 System Reset Output with Programmable Delay
LT1640A –48V Hot Swap Controller in SO-8 LT1640 Pin Compatible, Improved Drain Pin Ruggedness
LT1641 48V Hot Swap Controller Foldback Analog Current Limit
LTC1642 Fault Protected Hot Swap Controller Operates Up to 16.5V, Protected to 33V
LTC1643 PCI Hot Swap Controller 3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1645 Dual Hot Swap Controller Operates from 1.2V to 12V, Power Sequencing
LTC1646 CompactPCITM Hot Swap Controller 3.3V, 5V Supplies, 1V Precharge, Local PCI Reset Logic
LTC1647 Dual Hot Swap Controller Dual ON Pins for Supplies from 3V to 15V
LTC4211 Low Voltage Hot Swap Controller 2.5V to 16.5V, Dual Level Circuit Breaker, Active Inrush Limiting
LT4250 –48V Hot Swap Controller in SO-8 LT1640 Pin Compatible, Active Current Limiting
LTC4251 –48V Hot Swap Controller in SOT-23 Active Current Limiting, Fast Circuit Breaker for Short-Circuit Faults
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group
RELATED PARTS
+
V
EE
V
DD
LT1640L
PWRGD
SENSE
C1
150nF
25V
C2
3.3nF
100V
C3
0.1µF
100V
C4
0.1µF
100V
C6
0.1µF
100V
C5
100µF
100V
C7
100µF
16V
Q1
IRF530
R2
10Ω
5%
R3
18k
5%
R7
51k
5%
R4
562k
1%
R5
9.09k
1%
R6
10k
1%
R1
0.02Ω
5%
4
OV
GND
(SHORT PIN)
GND
3
2
–48V
UV
5
6
8
7
1
GATE
DRAIN
LUCENT
JW050A1-E
V
OUT+
SENSE
+
TRIM
SENSE
–
V
OUT–
V
IN+
95V
1640 F14
8
7
6
5
3
1
2
4
ON/OFF
CASE
V
IN–
V
OUT+
V
OUT–
V
IN+
CASE
V
IN–
+
LUCENT
FLTR100V10
*
1N4148
1N4003
MOC207
* DIODES INC. SMAT70A
43
21
Figure 14. Typical Application Using a Filter Module
