1/11Septe mber 2001
■MEDIUM SPEED OPERATION : 12 MHz
(Typ.) CLOCK RATE AT VDD - VSS = 10 V
■FULLY STATIC OPERATION
■8 MASTER-SLAVE FLIP - FL O PS PL U S
OUTPUT BUFFERING AND CONTROL
GATING
■QUIESCENT CURRENT SPECIFIED UP TO
20V
■5V, 10V AND 15V PARAMETRIC RATINGS
■INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
■100% TESTED FOR QUIESCENT CURRENT
■MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRI PTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4021B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is an 8-stage parallel or serial input/
serial output register having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single
SERIAL data input, and individual parallel "JAM"
inputs to each register stage. Each regist er stage
is a D-type, m aster-slave flip-flop in addi tion to an
output from stage 8, "Q" outputs are also available
from stages 6 and 7. Serial entry is synchronous
with the clock but parallel entry is asynchronous.
In this device, entry is controlled by the
PARALLEL/SERIAL CONTROL input. When the
PARA LLEL/SERIA L CONTROL input is low, dat a
is serially shifted into the 8-stage register
synchronously with the positive transition of he
clock line. When the PARALLEL/SERIAL
CONTROL input is high, data is jammed into the
8-stage register via the parallel input lines and
synchronous with the positive transition of the
clock line, the CLOCK input of the internal stage is
"forced" when asynchronous parallel entry is
made. Register expansion using multiple package
is permitted.
HCF4021B
ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS
SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER
PIN CONNECTION
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4021BEY
SOP HCF4021BM1 HCF4021M013TR
DIP SOP