5962R0724903VXC - Intersil Corporation

Radiation Hardened, High Performance Industry

Standard Single-Ended Current Mode PWM Controller

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

The ISL7884xASRH is a high performance, radiation hardened

drop-in replacement for the popular 28C4x and 18C4x PWM

controllers suitable for a wide range of power conversion

applications including boost, flyback, and isolated output

configurations. Its fast signal propagation and output

switching characteristics make this an ideal product for

existing and new designs.

Features include up to 13.2V operation, low operating current,

90µA typical start-up current, adjustable operating frequency

to 1MHz, and high peak current drive capability with 50ns rise

and fall times.

Specifications for Rad Hard QML devices are controlled by the

Defense Logistics Agency Land and Maritime (DLA). The SMD

numbers listed in the ordering information must be used when

ordering.

Detailed Electrical Specifications for the ISL788xASRH are

contained in SMD 5962-07249. A “hot-link” is provided on our

website for downloading.

Features

• Electrically Screened to DLA SMD # 5962-07249

• QML Qualified Per MIL-PRF-38535 Requirements

• 1A MOSFET Gate Driver

• 90µA Typical Start-up Current, 125µA Max

• 35ns Propagation Delay Current Sense to Output

• Fast Transient Response with Peak Current Mode Control

• 9V to 13.2V Operation

• Adjustable Switching Frequency to 1MHz

• 50ns Rise and Fall Times with 1nF Output Load

• Trimmed Timing Capacitor Discharge Current for Accurate

Deadtime/Maximum Duty Cycle Control

• 1.5MHz Bandwidth Error Amplifier

• Tight Tolerance Voltage Reference Over Line, Load and

Temperature

• ±3% Current Limit Threshold

• Pb-Free Available (RoHS Compliant)

Applications

• Current Mode Switching Power Supplies

• Isolated Buck and Flyback Regulators

• Boost Regulators

• Direction and Speed Control in Motors

• Control of High Current FET Drivers

PART NUMBER RISING UVLO MAX. DUTY CYCLE

ISL78840ASRH 7.0 100%

ISL78841ASRH 7.0 50%

ISL78843ASRH 8.4V 100%

ISL78845ASRH 8.4V 50%

Pin Configurations

ISL78840ASRH, ISL78841ASRH,

ISL78843ASRH, ISL78845ASRH

(8 LD FLATPACK)

TOP VIEW

ISL78840ASRH, ISL78841ASRH,

ISL78843ASRH, ISL78845ASRH

(8 LD SBDIP)

TOP VIEW

1COMP

RTCT

VREF

VDD

OUT

GND

COMP

RTCT

VREF

VDD

OUT

GND

April 5, 2012

FN6991.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

2FN6991.2

April 5, 2012

Ordering Information

ORDERING NUMBER PART NUMBER

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free) PKG. DWG. #

ISL78840ASRHVX/SAMPLE ISL78840ASRHVX/SAMPLE -55 to +125 Die

ISL78840ASRHF/PROTO ISL78840ASRHF/PROTO (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

5962R0724901QXC ISL78840ASRHQF (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

5962R0724901VXC ISL78840ASRHVF (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

ISL78840ASRHD/PROTO ISL78840ASRHD/PROTO (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

5962R0724901QPC ISL78840ASRHQD (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

5962R0724901VPC ISL78840ASRHVD (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

ISL78841ASRHVX/SAMPLE ISL78841ASRHVX/SAMPLE -55 to +125 Die

ISL78841ASRHF/PROTO ISL78841ASRHF/PROTO (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

5962R0724902QXC ISL78841ASRHQF (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

5962R0724902VXC ISL78841ASRHVF (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

ISL78841ASRHD/PROTO ISL78841ASRHD/PROTO (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

5962R0724902QPC ISL78841ASRHQD (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

5962R0724902VPC ISL78841ASRHVD (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

ISL78843ASRHVX/SAMPLE ISL78843ASRHVX/SAMPLE -55 to +125 Die

ISL78843ASRHF/PROTO ISL78843ASRHF/PROTO (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

5962R0724903QXC ISL78843ASRHQF (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

5962R0724903VXC ISL78843ASRHVF (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

ISL78843ASRHD/PROTO ISL78843ASRHD/PROTO (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

5962R0724903QPC ISL78843ASRHQD (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

5962R0724903VPC ISL78843ASRHVD (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

ISL78845ASRHVX/SAMPLE ISL78845ASRHVX/SAMPLE -55 to +125 Die

ISL78845ASRHF/PROTO ISL78845ASRHF/PROTO (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

5962R0724904QXC ISL78845ASRHQF (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

5962R0724904VXC ISL78845ASRHVF (Notes 1, 2) -55 to +125 8 Ld Flatpack K8.A

ISL78845ASRHD/PROTO ISL78845ASRHD/PROTO (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

5962R0724904QPC ISL78845ASRHQD (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

5962R0724904VPC ISL78845ASRHVD (Notes 1, 2) -55 to +125 8 Ld SBDIP D8.3

NOTES:

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations.

2. For Moisture Sensitivity Level (MSL), please see device information page for ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH. For

more information on MSL please see techbrief TB363.

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

3FN6991.2

April 5, 2012

Functional Block Diagram

150k

100k

VDD

OUT

RTCT

GND

VREF

PWM

COMPARATOR

RESET

DOMINANT

2.5V

ENABLE

8.4mA

2.9V

1.0V

OSCILLATOR

COMPARATOR

<10ns

START/STOP

UV COMPARATOR

VREF

100mV

ERROR

AMPLIFIER

VREF

COMP

VREF

UV COMPARATOR

4.65V 4.80V

A = 0.5

CLOCK

1.1V

CLAMP

VF TOTAL = 1.15V

VREF FAULT

OKVDD

36k

ISL78841A,

ONLY

ISL78845A

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

4FN6991.2

April 5, 2012

Typical Application - 48V Input Dual Output Flyback

VIN+

VIN-

RETURN

36V TO 75V

VR1

+1.8V

+3.3V

R3 C4

CR6

R22

CR2

CR5

CR4

C17

R21

R16

C14

C13 R15

R19

R17 R18

R20

C15 C16

C12

C11

R13

R10

CR1

C21

C19

C22

C20

ISL7884xASRH

VDD

RTCT

FB OUT

COMP VREF

GND

R26

R27

R28

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

5FN6991.2

April 5, 2012

Typical Application - Boost Converter

VIN+

VIN-

CR1

VIN+

ISL7884xASRH

OUT

RTCT

COMP VREF

VDD

GND

+VOUT

RETURN

C10

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

6FN6991.2

April 5, 2012

Absolute Maximum Ratings Thermal Information

Supply Voltage VDD Without Ion Beam . . . . . . . . . . . .GND -0.3V to +30.0V

Supply Voltage VDD Under Ion Beam . . . . . . . . . . . . . .GND -0.3V to +14.7V

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VDD + 0.3V

Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 6.0V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

ESD Rating

Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV

Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V

Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

Recommended Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage (Typical Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 13.2V

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

8 Ld Flatpack Package (Notes 3, 5) 140 15

8 Ld SBDIP Package (Notes 4, 5) 98 15

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Radiation Information

Maximum Total Dose

(Dose Rate = 50 - 100radSi/s) . . . . . . . . . . . . . . . . . . . . . 100 krads (Si)

SEB (No Burnout) (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . 80Mev/mg/cm2

SEL (No latchup) (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 80Mev/mg/cm2

SET (Regulated VOUT within ±3%) (Note 9) . . . . . . . . . . . . 40Mev/mg/cm2

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. For θJC, the "case temp" location is the center of the ceramic on the package underside.

6. All voltages are with respect to GND.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic on page 3 and page 4. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF, TA = -55 to +125°C. Typical values are at TA= +25°C. Boldface limits apply over

the operating temperature range, -55 to +125°C.

PARAMETER TEST CONDITIONS

MIN

(Note 10) TYP

MAX

(Note 10) UNITS

UNDERVOLTAGE LOCKOUT

START Threshold ISL78840A, ISL78841A 6.5 7.0 7.5 V

ISL78843A, ISL78845A 8.0 8.4 9.0 V

STOP Threshold ISL78840A, ISL78841A 6.1 6.6 6.9 V

ISL78843A, ISL78845A 7.3 7.6 8.0 V

Hysteresis ISL78840A, ISL78841A -0.4 -V

ISL78843A, ISL78845A -0.8 -V

Start-up Current, IDD VDD < START Threshold -90 125 µA

VDD < START Threshold, 100krad -300 500 µA

Operating Current, IDD (Note 7) -2.9 4.0 mA

Operating Supply Current, IDIncludes 1nF GATE loading -4.75 5.5 mA

REFERENCE VOLTAGE

Overall Accuracy Over line (VDD = 9V to 13.2V), load of

1mA and 10mA, temperature

4.925 5.000 5.050 V

Long Term Stability TA = +125°C, 1000 hours (Note 8) - 5 - mV

Current Limit, Sourcing -20 --mA

Current Limit, Sinking 5--mA

CURRENT SENSE

Input Bias Current VCS = 1V -1.0 -1.0 µA

Input Signal, Maximum 0.97 1.00 1.03 V

Gain, ACS = ΔVCOMP/ΔVCS 0 < VCS < 910mV, VFB = 0V 2.75 2.82 3.15 V/V

CS to OUT Delay -35 55 ns

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

7FN6991.2

April 5, 2012

ERROR AMPLIFIER

Open Loop Voltage Gain (Note 8) -90 -dB

Unity Gain Bandwidth (Note 8) -1.5 -MHz

Reference Voltage, VREF VFB = VCOMP 2.475 2.500 2.530 V

FB Input Bias Current, FBIIB VFB = 0V -1.0 -0.2 1.0 µA

COMP Sink Current VCOMP = 1.5V, VFB = 2.7V 1.0 --mA

COMP Source Current VCOMP = 1.5V, VFB = 2.3V -0.4 --mA

COMP VOH VFB = 2.3V 4.80 -VREF V

COMP VOL VFB = 2.7V 0.4 -1.0 V

PSRR Frequency = 120Hz, VDD = 9V to 13.2V

(Note 8)

-80 -dB

OSCILLATOR

Frequency Accuracy Initial, TA = +25°C 48 51 53 kHz

Frequency Variation with VDD TA= +25°C, (f13.2V - f9V)/f12V -0.21.0%

Temperature Stability (Note 8) -5-%

Amplitude, Peak-to-Peak Static Test -1.75 -V

RTCT Discharge Voltage (Valley Voltage) Static Test -1.0 -V

Discharge Current RTCT = 2.0V 6.5 7.8 8.5 mA

OUTPUT

Gate VOH VDD to OUT, IOUT = -100mA -1.0 2.0 V

Gate VOL OUT to GND, IOUT = 100mA -1.0 2.0 V

Peak Output Current COUT = 1nF (Note 8) -1.0 -A

Rise Time COUT = 1nF -35 60 ns

Fall Time COUT = 1nF -20 40 ns

OUTPUT OFF state leakage VDD = 5V --50 µA

PWM

Maximum Duty Cycle

(ISL78840A, ISL78843A)

COMP = VREF 94.0 96.0 -%

Maximum Duty Cycle

(ISL78841A, ISL78845A)

COMP = VREF 47.0 48.0 -%

Minimum Duty Cycle COMP = GND --0%

NOTES:

7. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.

8. Limits established by characterization and are not production tested.

9. SEE tests performed with VREF bypass capacitor of 0.22µF and FSW = 200kHz. SEB/L tests done on a standalone open loop configuration. SET tests

done in a closed loop configuration. For SEL no hard latch requiring manual intervention were observed. For more information see:

ISL7884xASRH SEE Test Report.

10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic on page 3 and page 4. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF, TA = -55 to +125°C. Typical values are at TA= +25°C. Boldface limits apply over

the operating temperature range, -55 to +125°C. (Continued)

PARAMETER TEST CONDITIONS

MIN

(Note 10) TYP

MAX

(Note 10) UNITS

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

8FN6991.2

April 5, 2012

Pin Descriptions

RTCT - This is the oscillator timing control pin. The operational

frequency and maximum duty cycle are set by connecting a

resistor, RT, between VREF and this pin and a timing capacitor,

CT, from this pin to GND. The oscillator produces a sawtooth

waveform with a programmable frequency range up to 2.0MHz.

The charge time, tC, the discharge time, tD, the switching

frequency, f, and the maximum duty cycle, DMAX, can be

approximated from Equations 1 through 4:

The formulae have increased error at higher frequencies due to

propagation delays. Figure 4 may be used as a guideline in

selecting the capacitor and resistor values required for a given

switching frequency for the ISL78841ASRH, ISL78845ASRH. The

value for the ISL78840ASRH, ISL78843ASRH will be twice that

shown in Figure 4.

COMP - COMP is the output of the error amplifier and the input of

the PWM comparator. The control loop frequency compensation

network is connected between the COMP and FB pins.

FB - The output voltage feedback is connected to the inverting

input of the error amplifier through this pin. The non-inverting

input of the error amplifier is internally tied to a reference

voltage.

CS - This is the current sense input to the PWM comparator. The

range of the input signal is nominally 0V to 1.0V and has an

internal offset of 100mV.

GND - GND is the power and small signal reference ground for all

functions.

OUT - This is the drive output to the power switching device. It is a

high current output capable of driving the gate of a power

MOSFET with peak currents of 1.0A. This GATE output is actively

held low when VDD is below the UVLO threshold.

VDD - VDD is the power connection for the device. The total supply

current will depend on the load applied to OUT. Total IDD current

is the sum of the operating current and the average output

current. Knowing the operating frequency, f, and the MOSFET

gate charge, Qg, the average output current can be calculated

from Equation 5:

Typical Performance Curves

FIGURE 1. FREQUENCY vs TEMPERATURE FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE

FIGURE 3. EA REFERENCE vs TEMPERATURE FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN

-60 -40 -20 0 20 40 60 80 100 120 140

0.98

0.99

1.00

1.01

TEMPERATURE (°C)

NORMALIZED FREQUENCY

-60 -40 -20 0 20 40 60 80 100

0.995

0.996

0.997

0.998

0.999

1.000

1.001

TEMPERATURE (°C)

NORMALIZED VREF

140120

-60 -40 -20 0 20 40 60 80 100 120 140

0.996

0.997

0.998

1.000

1.001

TEMPERA TURE (°C)

NORMALIZED EA REFERENCE

110100

100

103

RT (kΩ)

FREQUENCY (k Hz)

100pF

220pF

330pF

470pF

1.0nF

2.2nF

3.3nF

4.7nF

6.8nF

(EQ. 1)

tC0.533 RT CT⋅⋅≈

tDRT–CT In 0.008 RT 3.83–⋅

0.008 RT 1.71–⋅

--------------------------------------------- ⎠

⎞

⎝

⎛

⋅⋅≈(EQ. 2)

f1t

CtD

+()⁄=(EQ. 3)

Cf⋅=(EQ. 4)

IOUT Qg f×=(EQ. 5)

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

9FN6991.2

April 5, 2012

To optimize noise immunity, bypass VDD to GND with a ceramic

capacitor as close to the VDD and GND pins as possible.

VREF - The 5.00V reference voltage output. +1.0/-1.5% tolerance

over line, load and operating temperature. The recommended

bypass to GND cap is in the range 0.1µF to 0.22µF. A typical

value of 0.15µF can be used.

Functional Description

Features

The ISL7884xASRH current mode PWM makes an ideal choice

for low-cost flyback and forward topology applications. With its

greatly improved performance over industry standard parts, it is

the obvious choice for new designs or existing designs which

require updating.

Oscillator

The ISL7884xASRH has a sawtooth oscillator with a

programmable frequency range to 2MHz, which can be

programmed with a resistor from VREF and a capacitor to GND on

the RTCT pin. (Please refer to Figure 4 for the resistor and

capacitance required for a given frequency).

Soft-Start Operation

Soft-start must be implemented externally. One method,

illustrated below, clamps the voltage on COMP.

The COMP pin is clamped to the voltage on capacitor C1 plus a

base-emitter junction by transistor Q1. C1 is charged from VREF

through resistor R1 and the base current of Q1. At power-up C1 is

fully discharged, COMP is at ~0.7V, and the duty cycle is zero. As

C1 charges, the voltage on COMP increases, and the duty cycle

increases in proportion to the voltage on C1. When COMP

reaches the steady state operating point, the control loop takes

over and soft-start is complete. C1 continues to charge up to

VREF and no longer affects COMP. During power-down, diode D1

quickly discharges C1 so that the soft-start circuit is properly

initialized prior to the next power-on sequence.

Gate Drive

The ISL7884xASRH is capable of sourcing and sinking 1A peak

current. To limit the peak current through the IC, an optional

external resistor may be placed between the totem-pole output of

the IC (OUT pin) and the gate of the MOSFET. This small series

resistor also damps any oscillations caused by the resonant tank

of the parasitic inductances in the traces of the board and the

FET’s input capacitance. TID environment of >50krads requires

the use of a bleeder resistor of 10k from the OUT pin to GND.

Slope Compensation

For applications where the maximum duty cycle is less than 50%,

slope compensation may be used to improve noise immunity,

particularly at lighter loads. The amount of slope compensation

required for noise immunity is determined empirically, but is

generally about 10% of the full scale current feedback signal. For

applications where the duty cycle is greater than 50%, slope

compensation is required to prevent instability.

Slope compensation may be accomplished by summing an

external ramp with the current feedback signal or by subtracting

the external ramp from the voltage feedback error signal. Adding

the external ramp to the current feedback signal is the more

popular method.

From the small signal current-mode model [1] it can be shown

that the naturally-sampled modulator gain, Fm, without slope

compensation is calculated in Equation 6:

where Sn is the slope of the sawtooth signal and tsw is the

duration of the half-cycle. When an external ramp is added, the

modulator gain becomes Equation 7:

where Se is slope of the external ramp and becomes Equation 8:

The criteria for determining the correct amount of external ramp

can be determined by appropriately setting the damping factor of

the double-pole located at the switching frequency. The

double-pole will be critically damped if the Q-factor is set to 1,

over-damped for Q < 1, and under-damped for Q > 1. An

under-damped condition may result in current loop instability.

where D is the percent of on-time during a switching cycle.

Setting Q = 1 and solving for Se yields Equation 10:

Since Sn and Se are the on-time slopes of the current ramp and

the external ramp, respectively, they can be multiplied by tON to

obtain the voltage change that occurs during tON.

where Vn is the change in the current feedback signal (ΔI) during

the on-time and Ve is the voltage that must be added by the

external ramp.

FIGURE 5. SOFT-START

VREF

COMP

GND

ISL7884xASRH

D1R1

Fm 1

Sntsw

------------------

=(EQ. 6)

Fm 1

Sn Se+()tsw

-------------------------------------1

mcSntsw

--------------------------

== (EQ. 7)

mc1Se

-------

+= (EQ. 8)

πmc1D–()0.5–()

-------------------------------------------------

=(EQ. 9)

Sn1

---0.5+

⎝⎠

⎛⎞

1D–

------------- 1–

⎝⎠

⎛⎞

=(EQ. 10)

VeVn1

---0.5+

⎝⎠

⎛⎞

1D–

------------- 1–

⎝⎠

⎛⎞

=(EQ. 11)

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

10 FN6991.2

April 5, 2012

For a flyback converter, Vn can be solved in terms of input

voltage, current transducer components, and primary

inductance, yielding Equation 12:

where RCS is the current sense resistor, Tsw is the switching

period, Lp is the primary inductance, VIN is the minimum input

voltage, and D is the maximum duty cycle.

The current sense signal at the end of the ON time for CCM

operation is Equation 13:

where VCS is the voltage across the current sense resistor, Ls is

the secondary winding inductance, and IO is the output current at

current limit. Equation 13 assumes the voltage drop across the

output rectifier is negligible.

Since the peak current limit threshold is 1.00V, the total current

feedback signal plus the external ramp voltage must sum to this

value when the output load is at the current limit threshold as:

shown in Equation 14.

Substituting Equations 12 and 13 into Equation 14 and solving

for RCS yields Equation 15:

Adding slope compensation is accomplished in the

ISL7884xASRH using an external buffer transistor and the RTCT

signal. A typical application sums the buffered RTCT signal with

the current sense feedback and applies the result to the CS pin

as shown in Figure 6.

Assuming the designer has selected values for the RC filter (R6

and C4) placed on the CS pin, the value of R9 required to add the

appropriate external ramp can be found by superposition.

The factor of 2.05 in Equation 16 arises from the peak amplitude

of the sawtooth waveform on RTCT minus a base-emitter junction

drop. That voltage multiplied by the maximum duty cycle is the

voltage source for the slope compensation. Rearranging to solve

for R9 yields Equation 17:

The value of RCS determined in Equation 15 must be rescaled so

that the current sense signal presented at the CS pin is that

predicted by Equation 13. The divider created by R6 and R9

makes this necessary.

Example:

VIN = 12V

VO = 48V

Ls = 800µH

Ns/Np = 10

Lp = 8.0µH

IO = 200mA

Switching Frequency, fsw = 200kHz

Duty Cycle, D = 28.6%

R6 = 499Ω

Solve for the current sense resistor, RCS, using Equation 15.

RCS = 295mΩ

Determine the amount of voltage, Ve, that must be added to the

current feedback signal using Equation 12.

Ve = 92.4mV

Using Equation 17, solve for the summing resistor, R9, from CT to

CS.

R9 = 2.67kΩ

Determine the new value of RCS (R’CS) using Equation 18.

R’CS = 350mΩ

Additional slope compensation may be considered for design

margin. The above discussion determines the minimum external

ramp that is required. The buffer transistor used to create the

external ramp from RTCT should have a sufficiently high gain

(>200) so as to minimize the required base current. Whatever

base current is required reduces the charging current into RTCT

and will reduce the oscillator frequency.

VeDT⋅SW VIN RCS

⋅⋅

---------------------------------------------------- 1

---0.5+

⎝⎠

⎛⎞

1D–

------------- 1–

⎝⎠

⎛⎞

=V(EQ. 12)

VCS NSRCS

⋅

------------------------ IO1D–()VOT⋅⋅

2Ls

----------------------------------------------

⎝⎠

⎜⎟

⎛⎞

=V(EQ. 13)

VeVCS

+1V=(EQ. 14)

RCS 1

sw VIN

⋅⋅

---------------------------------

---0.5+

1D–

------------------1–

⎝⎠

⎜⎟

⎛⎞

⋅Ns

-------IO1D–()VOTsw

⋅⋅

2Ls

----------------------------------------------

⎝⎠

⎜⎟

⎛⎞

⋅+

---------------------------------------------------------------------------------------------------------------------------------------------------------

(EQ. 15)

RTCT

ISL78843ASRH

VREF

FIGURE 6. SLOPE COMPENSATION

Ve2.05D R6

⋅

R6R9

----------------------------

=V(EQ. 16)

R92.05D Ve

–()R6

⋅

----------------------------------------------

=Ω(EQ. 17)

R′CS R6R9

---------------------RCS

⋅=(EQ. 18)

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

11 FN6991.2

April 5, 2012

Fault Conditions

A Fault condition occurs if VREF falls below 4.65V. When a Fault

is detected, OUT is disabled. When VREF exceeds 4.80V, the Fault

condition clears, and OUT is enabled.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the device.

A good ground plane must be employed. A unique section of the

ground plane must be designated for high di/dt currents

associated with the output stage. VDD should be bypassed

directly to GND with good high frequency capacitors.

References

[1] Ridley, R., “A New Continuous-Time Model for Current Mode

Control”, IEEE Transactions on Power Electronics, Vol. 6,

No. 2, April 1991.

Die Map

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

12 FN6991.2

April 5, 2012

Products

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address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

on intersil.com: ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev.

DATE REVISION CHANGE

February 28, 2012 FN6991.2 Pg 10 - Updated Equations 13 and 15 – Changed fSW to TSW. Changed Equation 14 – added“V” to 1 making it 1V.

Paragraph under Equation 12, changed fSW is the switching frequency to TSW is the switching period.

November 9, 2011 Converted to new datasheet template.

Added Abs Max, Thermal Information, and MIN/MAX data for Electrical Spec table. Added boldface over-temp limit

notes.

Pg 14: Replaced POD K8.A rev 1 with rev 2. Changes as follows: : In Side View, added 0.045 (1.14) dimension and

removed "MIN" label from 0.026(0.66) dimension

April 22, 2010 FN6991.1 Added Electrical Spec Table showing only the typical values. Removed boldface over-temp limit notes.

April 8, 2010 Added SBDIP parts, pinout and Flatpack & SBDIP PODs.

December 21, 2009 FN6991.0 Initial pre-release

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

13 FN6991.2

April 5, 2012

Package Outline Drawing

K8.A

8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

Rev 2, 12/10

LEAD FINISH

SIDE VIEW

TOP VIEW

-D-

-C-

0.265 (6.75)

0.115 (2.92)

0.026 (0.66)

0.265 (6.73)

SEATING AND

0.180 (4.57)

0.03 (0.76) MIN

BASE PLANE

-H-

0.09 (0.23)

0.005 (0.13)

PIN NO. 1

ID AREA

0.050 (1.27 BSC)

0.022 (0.56)

0.015 (0.38)

MIN 0.245 (6.22)

0.070 (1.18)

0.170 (4.32) 0.370 (9.40)

0.250 (6.35)

0.04 (0.10)

0.245 (6.22)

1. adjacent to pin one and shall be located within the shaded area shown.

The manufacturer’s identification shall not be used as a pin one

identification mark. Alternately, a tab may be used to identify pin one.

2. of the tab dimension do not apply.

3. The maximum limits of lead dimensions (section A-A) shall be

measured at the centroid of the finished lead surfaces, when solder

dip or tin plate lead finish is applied.

5. shall be molded to the bottom of the package to cover the leads.

6. meniscus) of the lead from the body. Dimension minimum shall

be reduced by 0.0015 inch (0.038mm) maximum when solder dip

lead finish is applied.

NOTES:

0.015 (0.38)

0.008 (0.20)

PIN NO. 1

ID OPTIONAL 1 2

Dimensioning and tolerancing per ANSI Y14.5M - 1982.

Controlling dimension: INCH.

Index area: A notch or a pin one identification mark shall be located

If a pin one identification mark is used in addition to a tab, the limits

Measure dimension at all four corners.

For bottom-brazed lead packages, no organic or polymeric materials

Dimension shall be measured at the point of exit (beyond the

SECTION A-A

BASE

METAL

0.007 (0.18)

0.004 (0.10)

0.009 (0.23)

0.004 (0.10)

0.019 (0.48)

0.015 (0.38) 0.0015 (0.04)

MAX

0.022 (0.56)

0.015 (0.38)

0.045 (1.14)

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6991.2

April 5, 2012

For additional products, see www.intersil.com/product_tree

Ceramic Dual-In-Line Metal Seal Packages (SBDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

5. Dimension Q shall be measured from the seating plane to the

base plane.

6. Measure dimension S1 at all four corners.

7. Measure dimension S2 from the top of the ceramic body to the

nearest metallization or lead.

8. N is the maximum number of terminal positions.

9. Braze fillets shall be concave.

10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

11. Controlling dimension: INCH.

bbb C A - B

SEATING

BASE

PLANE

-D-

-A-

-C-

-B-

aaa CA - BM DS S

ccc CA - BMDS S

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

eA/2

D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)

8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 0.405 - 10.29 -

E 0.220 0.310 5.59 7.87 -

e 0.100 BSC 2.54 BSC -

eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 5

S1 0.005 - 0.13 - 6

S2 0.005 - 0.13 - 7

α90o105o90o105o-

aaa - 0.015 - 0.38 -

bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2

N8 88

Rev. 0 4/94