TM
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FEATURES
APPLICATIONS
PVDD Supply Voltage − V
0
30
60
90
120
150
180
210
240
270
300
330
0 5 10 15 20 25 30 35 40 45 50
TC = 75°C
THD+N at 10%
PO − Output Power − W
G001
8 Ω
6 Ω
4 Ω
DESCRIPTION
TAS5261
SLES188 – AUGUST 2006
315-W Mono BTL Digital Amplifier Power Stage
The TAS5261 has complete protection circuitry•Total Output Power
integrated on chip, safeguarding the device and– 125 W Into 8 Ωat <0.09% THD+N
speakers against fault conditions that could damage– 220 W Into 6 Ωat 10% THD+N
the system. These protection features areshort-circuit protection, overcurrent protection,– 315 W Into 4 Ωat 10% THD+N
undervoltage protection, and a loss of pulse-width•110-dB SNR (A-Weighted with TAS5518
modulation (PWM) input signal (PWM Activitymodulator)
Detector).•Supports Pulse-Width Modulation (PWM)
A power-on reset (POR) circuit is used to eliminateFrame Rates of 192 kHz to 384 kHz
power-supply sequencing that is normally required•Resistor-Programmable Current Limit
for most H-bridge designs.•Integrated Self-Protection Circuit Including:
OUTPUT POWER– Under Voltage Protection
vs– Over Temperature Warning and Error
PVDD_x SUPPLY VOLTAGE– Over Load Protection– Short Circuit (OC) Protection– PWM Activity Dectector•Power-On Reset (POR) to Eliminate SystemPower-Supply Sequencing•Thermally-Enhanced Package DKD (36-pinPSOP3)
•EMI Compliant When Used WithRecommended System Design•Error Reporting 3.3-V and 5-V Compliant
•AV Receivers
•DVD Receivers
•Mini/Micro Component Systems•Home Theater Systems
The TAS5261 is a high-performance, integratedmono digital amplifier power stage designed to drive4- Ωto 8- Ωspeakers with low harmonic distortion.This system requires only a simple, passivedemodulation filter to deliver high-quality,high-efficiency audio amplification.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DEVICE INFORMATION
1
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36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
BST_A
GVDD_A
OTW
SD
RESET
PWM_A
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_B
VDD
GND
GVDD_B
BST_B
PVDD_A
PVDD_A
PVDD_A
PGND
PGND
PGND
OUT_A
OUT_A
OUT_A
OUT_B
OUT_B
OUT_B
PGND
PGND
PGND
PVDD_B
PVDD_B
PVDD_B
DKDPACKAGE
(TOP VIEW)
P0018-02
TAS5261
SLES188 – AUGUST 2006
The TAS5261 is available in a thermally-enhanced 36-pin PSOP3 PowerPAD™ package. The heat slug islocated on the top side of the device for convenient thermal coupling to a heat sink.
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DISSIPATION RATINGS
Protection Mode
TAS5261
SLES188 – AUGUST 2006
PARAMETER CONDITION TYPICAL (DKD)
R
θJC
BTL channel (four transistors) 0.6 °C/WR
θJC
One transistor 2.38 °C/WPad area 80 mm
2
Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.
Table 1. Protection ModesMODE PINS
PROTECTION MODEM3
(1)
M2 M1
0 0 0 Full protection (default)
0 0 1 Reserved
0 1 0 OC latching mode
0 1 1 Reserved
(1) M3 is reserved and always should be connected to board GND.
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TAS5261
SLES188 – AUGUST 2006
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME PIN NO.
AGND 9 I Analog groundBST_A 1 P Bootstrap, A sideBST_B 18 I Bootstrap, B sideGND 8, 16 I Power groundGVDD_A 2 P Gate-drive voltage supply, A sideGVDD_B 17 I Gate-drive voltage supply, B sideM1 13 I Mode-selection 1 (LSB)M2 12 I Mode-selection 2 (MSB)M3 11 I ReservedOC_ADJ 7 I Overcurrent threshold programmingOTW 3 O Overtemperature warning. Open drain, active low.OUT_A 28, 29, 30 O Output, half-bridge AOUT_B 25, 26, 27 O Output, half-bridge B22, 23, 24, 31,PGND P Power ground32, 33PWM_A 6 I PWM for half-bridge APWM_B 14 I PWM Input for half-bridge BPVDD_A 34, 35, 36 P PVDD supply for half-bridge APVDD_B 19, 20, 21 P PVDD supply for half-bridge BRESET 5 I Reset. Active low.SD 4 O Shutdown. Open drain, active low.VDD 15 I Input power supplyVREG 10 O Internal voltage regulator
4
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B0101-01
PVDD(0–50V)
Mono
BTL
H-Bridge
Hardwire
Mode
Control
Hardwire
Mode
Control
M1
M1
M2
M2
M3
M3
System
Microcontroller
RESET_H-Bridge
SD
OTW
OTW
SD
RESET
Hardwire
Over-
current
Limit
Hardwire
Over-
current
Limit
PVDD
Power-Supply
Decoupling
PVDD
Power-Supply
Decoupling
GVDD,VDD,
andVREG
Power-Supply
Decoupling
GVDD,VDD,
andVREG
Power-Supply
Decoupling
6
6
6
6
2
2
GVDD(12V)andVDD(12V)
GVDD(12V)andVDD(12V)
GND
GND
PVDD(0–50V)
System
Power
Supplies
50V
12V
GND
AC
Bootstrap
Capacitors
Bootstrap
Capacitors
BST_A
BST_A
BST_B
BST_B
R2
L2
PWM_B
RESET
Shutdown
Overtemp_warning
R1
L1
TAS55XX
Left
Output
Right
Output
PWM_A
H-Bridge
Output
H-Bridge
Output
PVDD_A,B
VDD
VREG
GND
GND
GVDD_A,B
GND_A,B
OC_ADJ
Mono
BTL
H-Bridge
PWM_B
RESET
Shutdown
Overtemp_warning
PWM_A
PVDD_A,B
VDD
VREG
GND
GND
GVDD_A,B
GND_A,B
OC_ADJ
2nd-Order
L-COutput
Filterfor
Each
H-Bridge
2nd-Order
L-COutput
Filterfor
Each
H-Bridge
OUT_A
OUT_A
OUT_B
OUT_B
4–8
(3 Min)
W
W
4–8
(3 Min)
W
W
TAS5261
SLES188 – AUGUST 2006
Figure 1. Typical System Block Diagram
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TEMP
SENSE
M1
M2
AGND
OC_ADJ
VREG VREG
VDD
GVDD_B
M3
POWER-UP
RESET UVP
GND
PWM_B OUT_B(x3)
PGND (x3)
PVDD_B(x3)
BST_B
TIMING
CONTROL GATE-DRIVECONTROL
PWM
RECEIVER
OVER-LOAD
PROT.
GVDD_A
PWM
ACTIVITY
DETECTOR
CB3C
GVDD_B
CURRENT
SENSE
GVDD_A
PWM_A OUT_A (x3)
PGND (x3)
PVDD_A (x3)
BST_A
TIMING
CONTROL
CONTROL GATE-DRIVE
PWM
RECEIVER
PROTECTION & I/O LOGIC
OTW
SD
RESET
TAS5261
SLES188 – AUGUST 2006
Figure 2. Functional Block Diagram
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Absolute Maximum Ratings
(1)
TAS5261
SLES188 – AUGUST 2006
ORDERING INFORMATION
T
A
PACKAGE DESCRIPTION
0°C to 70 °C TAS5261DKD 36-pin PSOP3
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD to AGND –0.3 13.2 VGVDD_x to AGND –0.3 13.2 VPVDD_x to PGND_x
(2)
–0.3 71 VOUT_x to PGND_x
(2)
–0.3 71 VBST_x to PGND_x
(2)
–0.3 79.7 VBST_x to GVDD_x
(2)
–0.3 66.5 VVREG to AGND –0.3 4.2 VPGND_x to GND –0.3 0.3 VPGND_x to AGND –0.3 0.3 VGND to AGND –0.3 0.3 VPWM_x, OC_ADJ, M1, M2, M3 to AGND –0.3 4.2 VRESET, SD, OTW to AGND –0.3 7 VMaximum continuous sink current ( SD, OTW) 9 mAMaximum operating junction temperature range, T
J
0 150 °CStorage temperature range, T
stg
–65 150 °CLead temperature 1,6 mm (1/16 in) from case for 10 s 260 °CMinimum pulse duration, low – minimum pulse width must be ensured by the PWM processor 50 ns
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are only stressratings, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
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RECOMMENDED OPERATING CONDITIONS
AUDIO CHARACTERISTICS
TAS5261
SLES188 – AUGUST 2006
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PVDD_x Half-bridge supply voltage 0 50 52.5 VGVDD_x Gate-drive power supply 10.8
(1)
12 13.2 VVDD Digital regulator supply voltage 10.8
(1)
12 13.2 VR
L
Resistive load impedance, bridge-tied load (BTL) 4-16 ΩR
L
Resistive load impedance, BTL, R
OC
= 22k Ω, PVDD = 50V, (no current limiting) 3 ΩMinimum output filter inductance under both operating and short-circuit conditions,L
DEM
5 10 µHwith appropriate OC_ADJ resistor valuef
S
PWM frame rate 192 384 kHzt
(low)
Minimum low-state pulse duration per PWM frame, noise shaper enabled 50 nsC
BS
Bootstrap capacitor, selected value supports f
s
= 192 kHz to 384 kHz 33 nFR
BS
Bootstrap series resistor - 1/4 W 1.5 Ω4.7 ΩRC
BS
Bootstrap snubber - 1/4 W
470 pFUltra-Fast Recovery Clamping Diode, Average forward current = 1A, MaximumD
CLMP
15 nSrepetitive reverse voltage = 200V (ES1D, mfg:Fairchild)D
TVS
Transient Voltage Suppressor, 600W @ 1mS (P6SMB62AT3, mfg: ON Semiconductor) 62 VC
PVDD
PVDD Close Decoupling Capacitor, two capacitors 100 nFR
AGND
AGND resistor - 1/4 W 3.3 ΩR Optional external pullup resistor to +3.3V or +5 V for SD and OTW 3.3 4.7 k ΩT
J
Junction temperature 0 125 °C
(1) GVDD operation below 10.8 V significantly reduces efficiency of the output MOSFET stage and requires a larger heatsink. For thepurpose of noise margin, the UVP level is set lower to provide an increased noise margin, however, TI recommends a nominal dcvoltage of 12 V for GVDD.
Audio frequency = 1 kHz, PVDD_x = 50 V, GVDD_x = 12 V, VDD = 12 V, R
L
= 8 Ω, f
s
= 384 kHz, OC_ADJ = 22 k Ω,T
C
= 75 °C, output filter is L
DEM
= 10 µH, C
L
= 1 µF (unless otherwise noted). Audio performance is recorded as a chipset,TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and systemconfiguration are in accordance with recommended design guidelines.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
L
= 8 Ω, f = 1 kHz 125P
O
Unclipped power output R
L
= 6 Ω, f = 1 kHz 165 WR
L
= 4 Ω, f = 1 kHz 235R
L
= 8 Ω, f = 1 kHz, THD = 10% 165R
L
= 6 Ω, f = 1 kHz, THD = 10% 220P
O
Maximum power output WR
L
= 4 Ω, f = 1 kHz, THD = 10% 315R
L
= 3 Ω, f = 1 kHz, CBC allowed 400Total harmonic distortion + noise, 1 W to 125 W, RL=8 Ω, AES17 filter,THD+N 0.09 %AES 17 filter Unclipped
Ratio of 1-FFS to 0-FFS input,SNR Signal-to-noise ratio
(1)
110 dBA-weighted filterDNR Dynamic range –60-dBFS input, A-weighted filter 110 dBPWM switching frequency 384 kHz,VOO Output offset voltage –15 15 mVMeasured on speaker terminalsPower dissipation due to idle lossesP
idle
P
O
= 0 W, Output switching
(2)
2 W(I
PVDD_X
)
(1) SNR is calculated relative to the 0 dBFS input level.(2) Actual system idle losses are also affected by core losses of output inductors.
8
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ELECTRICAL CHARACTERISTICS
TAS5261
SLES188 – AUGUST 2006
Audio frequency = 1 kHz, PVDD_x = 50 V, GVDDx = 12 V, VDD = 12 V, R
L
= 8 Ω, f
s
= 384 kHz, OC_ADJ = 22 k Ω,T
C
= 75 °C, output filter is L
DEM
= 10 µH, C
L
= 1 µF (unless otherwise noted). AC performance is recorded as a chipset,TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and systemconfiguration are in accordance with recommended design guidelines.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Internal Voltage Regulator and Current Consumption
Voltage regulator,VREG 3.3 Vonly used as reference node
Operating, 50% duty cycle 7.7I
VDD
VDD supply current mAIdle, reset mode 6.750% duty cycle 15GVDD_x gate-supply currentI
GVDD_x
mAper half bridge
Idle, reset mode 1.550% duty cycle 23 mAI
PVDD_x
Half-bridge idle current
Reset mode ( RESET = 1),
100 µANo switching
Output-Stage MOSFETs
R
DSON,LS
Drain-to-source resistance, low side T
J
= 25 °C, LDMOS only 40 m ΩR
DSON,HS
Drain-to-source resistance, high side T
J
= 25 °C, LDMOS only 40 m Ω
I/O Protection
V
UVP,POS
Undervoltage protection limit, GVDD_x 8.5 VOTW Overtemperature warning 125 °COTW
hys
OTW hysteresis 25 °COTE Overtemperature error threshold 155 °COTE
hys
OTE hysteresis 30 °COTE-OTW
Temperature delta between OTW and OTE 30 °Cdifferential
OLPC Overload protection time constant f
PWM
= 384 kHz 20 msResistor programmable high endI
OC
Overcurrent limit response
(1)
15 16 17 Awith OC_ADJ = 22 k Ω
(1)
R
OC
Programming resistor 22 100 k ΩConnected when RESET is high toPulldown resistor at the output of eachR
PD
provide a charge path for the 2.5 k Ωhalf-bridge
bootstrap capacitorPWM PWM Activity Detector Lack of transition of any PWM input 13 µs
(1) DC measurement with 1-ms pulse
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ELECTRICAL CHARACTERISTICS
TAS5261
SLES188 – AUGUST 2006
GVDD_x = 12 V ±10%, VDD = 12 V ±10%, T
J
= 25 °C (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
Logic-Level and Open-Drain Outputs
V
IH
High-level input voltage Static 2 VV
IL
Low-level input voltage Static 0.8 VStatic, High PWM_A, High PWM_B,
45 65High M1, High M2, High M3Static, Low PWM_A, Low PWM_B,
–10 10I
lkg
(1)
Input leakage current µALow M1, Low M2, Low M3Static, High RESET 20 40Static, Low RESET –70 –50Internal pulldown to AGNDR
INT-PD
50 k Ωfor PWM_A and PWM_B inputsR
INT-PU
Internal pullup resistance on OTW and SD Resistor to VREG 20 28 33 k ΩInternal pullup resistor 2.4 VREGV
OH
High-level output voltage VExternal pullup of 3.3 k Ωto 5 V 2.5 4.9V
OL
Low-level output voltage I
O
= 4 mA 0.4 VFANOUT Device fanout ( OTW, SD) External pullup to 5 V 10 Devices
(1) Pullup and pulldown resistors affect the leakage current.
10
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TYPICAL CHARACTERISTICS
Red - 4 Ohm
Blue - 6 Ohm
Magenta - 8 Ohm
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
T
H
D
+
N
%
80m 300200m 500m 1 2 5 10 20 50 100 200
Output Power W
PVDD Supply Voltage − V
0
25
50
75
100
125
150
175
200
225
250
0 5 10 15 20 25 30 35 40 45 50
TC = 75°C
PO − Output Power − W
G003
8 Ω
6 Ω
4 Ω
TAS5261
SLES188 – AUGUST 2006
blk
TOTAL HARMONIC DISTORTION + NOISEvsOUTPUT POWER
Figure 3.
OUTPUT POWER UNCLIPPED OUTPUT POWERvs vsPVDD_x SUPPLY VOLTAGE PVDD_x SUPPLY VOLTAGE
Figure 4. Figure 5.
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PO − Output Power − W
0
20
40
60
80
100
0 20 40 60 80 100 120
TC = 25°C
Two Channels
Efficiency − %
G004
PO − Output Power − W
0
1
2
3
4
5
6
7
8
9
10
11
12
0 25 50 75 100 125
Power Loss − W
G005
TC = 25°C
TC − Case Temperature − °C
0
50
100
150
200
250
300
350
0 25 50 75 100 125
THD+N at 10%
PO − Output Power − W
G006
8 Ω
6 Ω
4 Ω
TAS5261
SLES188 – AUGUST 2006
TYPICAL CHARACTERISTICS
blk (continued)
SYSTEM EFFICIENCY SYSTEM POWER LOSSvs vsOUTPUT POWER OUTPUT POWER
Figure 6. Figure 7.
SYSTEM OUTPUT POWER
vsCASE TEMPERATURE
Figure 8.
12
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-150
+0
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
N
o
i
s
e
A
m
p
l
i
t
u
d
e
-
d
B
r
0 22k1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 13k 14k 15k 16k 17k 18k 19k 20k 21k
f - Frequency - kHz
TAS5261
SLES188 – AUGUST 2006
TYPICAL CHARACTERISTICS
blk (continued)
NOISE AMPLITUDE
vsFREQUENCY
Figure 9.
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APPLICATION INFORMATION
Typical Application Schematic
TAS5261
SLES188 – AUGUST 2006
14
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Recommended Printed Circuit Board (PCB) Layout
PCB Requirements
TAS5261
SLES188 – AUGUST 2006
APPLICATION INFORMATION (continued)
•2-oz copper (FR-4) recommended•PVDD voltage and capacitor selection in accordance with the data sheet
Figure 10. PCB (Top Layer)
Figure 11. PCB (Bottom Layer)
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THEORY OF OPERATION
Power Supplies
System Power-Up/Power-Down Sequence
Powering Up
Powering Down
TAS5261
SLES188 – AUGUST 2006
PCB placement, and routing. As indicated, each halfbridge has independent power-stage supply pins(PVDD_x). For optimal electrical performance, EMITo facilitate system design, the TAS5261 needs only
compliance, and system reliability, it is important thata 12-V supply in addition to a typical 50-V
each PVDD_x pin is decoupled with two 100-nFpower-stage supply. An internal voltage regulator
ceramic capacitors placed as close as possible toprovides suitable voltage levels for the digital and
each supply pin on the same side of the PCB as thelow-voltage analog circuitry. Additionally, all circuitry
TAS5261 location. It is recommended to follow therequiring a floating voltage supply, e.g., the high-side
PCB layout of the TAS5261 reference design. Forgate drive, is accommodated by built-in bootstrap
additional information on the recommended powercircuitry requiring only a few external capacitors.
supply and required components, see the applicationdiagrams given in this data sheet.To provide outstanding electrical and acousticcharacteristics, the PWM signal path, including gate
The 12-V supply should be powered from adrive and output stage, is designed as identical,
low-noise, low-output-impedance voltage regulator.independent half bridges. For this reason, each half
Likewise, the 50-V power-stage supply is assumed tobridge has separated gate-drive supply (GVDD_x),
have low output impedance and low noise. Thebootstrap pins (BST_x) and power-stage supply pins
internal POR circuit eliminates the need for(PVDD_x). Furthermore, an additional pin (VDD) is
power-supply sequencing. Moreover, the TAS5261 isprovided as power supply for all common circuits.
fully protected against erroneous power-stage turnAlthough supplied from the same 12-V source, it is
on due to parasitic gate charging. Thus,highly recommended to separate GVDD_x and VDD
voltage-supply ramp rates (dv/dt) are noncriticalon the printed circuit board (PCB) by RC filters (see
within the specified range (see the Recommendedapplication diagram for details). These RC filters
Operating Conditions section of this data sheet).provide the recommended high-frequency isolation.Special attention should be paid to placing alldecoupling capacitors as close to their associatedpins as possible. In general, inductance between thepower-supply pins and decoupling capacitors mustbe avoided. (See reference board documentation for There is no power-up sequence is required for theadditional information.) TAS5261. The outputs of the H-bridge remain in ahigh-impedance state until the gate-drive supplyFor a properly functioning bootstrap circuit, a small
voltage (GVDD_x) and VDD voltage are above theceramic capacitor must be connected from each
undervoltage protection (UVP) voltage threshold (seebootstrap pin (BST_x) to the power-stage output pin
the Electrical Characteristics section of this data(OUT_x). When the power-stage output is low, the
sheet). Although not specifically required, it isbootstrap capacitor is charged through an internal
recommended to hold RESET in a low state whilediode connected between the gate-drive
powering up the device. This allows an internalpower-supply pin (GVDD_x) and the bootstrap pin.
circuit to charge the external bootstrap capacitors byWhen the power-stage output voltage is high, the
enabling a weak pulldown of the half-bridge output.bootstrap capacitor voltage is shifted above theoutput voltage potential and, thus, provides a While powering up the TAS5261, RESET should besuitable voltage supply for the high-side gate driver. held low.In an application with PWM switching frequencies inthe range of 352 kHz to 384 kHz, it is recommendedto use 33-nF ceramic capacitors, size 0603 or 0805,
There is no power-down sequence is required for thefor the bootstrap capacitor. These 33-nF capacitors
TAS5261. The device remains fully operational asensure sufficient energy storage, even during
long as the gate-drive supply (GVDD_x) voltage andminimal PWM duty cycles, to keep the high-side
VDD voltage are above the undervoltage protectionpower-stage FET (LDMOS) fully started during all of
(UVP) threshold level (see the Electricalthe remaining part of the PWM cycle. In an
Characteristics section of this data sheet). Althoughapplication running at a reduced switching frequency,
not specifically required, it is a good practice to holdgenerally 250 kHz to 192 kHz, the bootstrap
RESET low during power down, thus, preventingcapacitor might need to be increased in value.
audible artifacts including pops and clicks.Special attention should be paid to the power-stagepower supply – this includes component selection,
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Error Reporting Over Current (OC) Protection With Current
Device Protection System
TAS5261
SLES188 – AUGUST 2006
Limiting and Overload DetectionThe SD and OTW pins are both active-low,open-drain outputs. Their function is for The device has independent, fast-reacting currentprotection-mode signaling to a PWM controller or detectors with programmable trip threshold (OCother system-control device. Any fault resulting in threshold) on all high-side and low-side power-stagedevice shutdown is signaled by the SD pin going low. FETs. See Table 3 for OC-adjust resistor values. TheLikewise, OTW goes low when the device junction detector outputs are closely monitored by twotemperature exceeds 115 °C. (see Table 2 ). protection systems. The first protection systemcontrols the power stage in order to prevent theTable 2. Error Reporting output current from further increasing. For instance, itperforms a current-limiting function rather thanSD OTW DESCRIPTION
prematurely shutting down during combinations ofOver Temperature (OTE) or Over
high-level music transients and extreme speaker0 0
Load (OLP) or Under Voltage (UVP)
load impedance drops. If the high-current situationOver Load (OLP), PWM Activity
persists, i.e., the power stage is being overloaded, a0 1
Dectector, or Under Voltage (UVP)
second protection system triggers a latchingOver Temperature Warning. Junction
shutdown, resulting in the power stage being set in1 0
temperature higher than 125 °C.
the high-impedance (Hi-Z) state.Normal operation. Junction1 1
temperature lower than 125 °C.
Table 3. OC-Adjust Resistor ValuesIt should be noted that asserting RESET low forces
CURRENT BEFORE OC OCCURSOC-ADJUST
(A)the SD and OTW signals high, independent of faults
RESISTOR VALUES
(k Ω)
(1)being present. It is recommended to monitor the
MIN TYP MAXOTW signal using the system microcontroller and
22 15 16 17respond to an overtemperature warning signal by, for
27 12 13 14example, turning down the volume to prevent further
47 7 8 8heating of the device resulting in device shutdown
68 5 5 6( OTW). To reduce external component count, aninternal pullup resistor to 3.3 V is provided on both
100 3 4 4the SD and OTW outputs. Level compliance for 5-V
(1) Resistor tolerance is ±5%.logic can be obtained by adding external pullupresistors to 5 V (see the Electrical Characteristics
For lowest-cost bill of materials in terms ofsection of this data sheet for further specifications).
component selection, the OC threshold currentshould be limited, considering the power outputrequirement and minimum load impedance.Higher-impedance loads require a lower OCThe TAS5261 contains advanced protection circuitry
threshold.carefully designed to facilitate system integration andease of use, as well as safeguarding the device from
The demodulation filter inductor must retain apermanent failure due to a wide range of fault
minimum of 5-H inductance at twice the selected OCconditions, such as short circuit, overload, and
threshold current.undervoltage. The TAS5261 responds to a fault by
Most inductors have decreasing inductance withimmediately setting the power stage in a
increasing temperature and increasing currenthigh-impedance state (Hi-Z) and asserting the SD
(saturation). To some degree, an increase inpin low. In situations other than overload, the device
temperature naturally occurs when operating at highautomatically recovers when the fault condition has
output currents, due to inductor core losses and thebeen removed (e.g., the voltage supply has
dc resistance of the inductor copper winding. Aincreased). For highest possible reliability, recovering
thorough analysis of inductor saturation and thermalfrom an overload fault requires external reset of the
properties is strongly recommended.device no sooner than 1 s after the shutdown (seethe Device Reset section of this data sheet).
Setting the OC threshold too low might cause issues,such as lack of enough output power and/orunexpected shutdowns due to sensitive overloaddetection.
In general, it is recommended to follow closely theexternal component selection and PCB layout asgiven in the Application Information section of thisdata sheet.
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Device Reset
Over Temperature (OTE) Protection
PWM Activity Detector
Under Voltage Protection (UVP) and
Modulation Index Setting
TAS5261
SLES188 – AUGUST 2006
For added flexibility, the OC threshold is VDD or GVDD_x pin results in all half-bridge outputsprogrammable within a limited range using a single immediately being set in the high-impedance stateexternal resistor connected between the OC_ADJ pin (Hi-Z) and SD being asserted low. The deviceand AGND. It should be noted that a properly automatically resumes operation when all supplyfunctioning overcurrent detector assumes the voltages have increased above the UVP threshold.presence of a properly designed demodulation filterat the power-stage output. Short-circuit protection isnot provided directly at the output pins of the power
When RESET is asserted low, the output FETs in allstage but only on the speaker terminals (after the
half bridges are forced into a high-impedance statedemodulation filter). It is required to follow certain
(Hi-Z). During this reset time, a resistor is connectedguidelines when selecting the OC threshold and an
between OUT_x and PGND pins, in order to chargeappropriate demodulation inductor.
the bootstrap capacitor.
Asserting RESET input low removes faultinformation. A rising-edge transition on the resetThe TAS5261 has a two-level,
input allows the device to resume operation after antemperature-protection system that asserts an
overload fault.active-low warning signal ( OTW) when the devicejunction temperature exceeds the OTW level statedin the parametric table. If the device junctiontemperature exceeds the OTE level stated in the
The PWM Activity Detector logic monitors individualparametric table, the device is put into thermal
PWM inputs. If one or more inputs are stuck in eithershutdown, resulting in all half-bridge outputs being
a high state or a low state for more than a definedset in the high-impedance state (Hi-Z) and SD being
length of time, the entire device is shut down.asserted low. OTE is latched in this case. To clear
The PWM Activity Detector is not latched and normalthe OTE latch, reset must be asserted. Thereafter,
operation resumes when PWM activity is present onthe device resumes normal operation.
the PWM inputs. When an invalid PWM frame isdetected, the PWM Activity Detector respondsimmediately (no delay). The TAS5261 resumesPower-On Reset (POR)
operation as soon as valid PWM signals are present.The UVP and POR circuits of the TAS5261 fully
The PWM Activity Detector is reported as a low onprotect the device in any power-up/down and
the SD pin.brownout situation. While powering up, the PORcircuit resets the overload circuit (OLP) and ensuresthat all circuits are fully operational when theGVDD_x and VDD supply voltages reach the UVP
96.1% is the recommended setting for thelevel stated in the parametric table. Although
modulation index limit of the PWM when driving theGVDD_x and VDD are independently monitored, a
TAS5261. The following shows modulation indexsupply-voltage drop below the UVP threshold on any
limit registers and setting value in hexadecimal for TImodulators.
TAS5508/TAS5518: 0x16h at 04h
TAS5086: 0x10h at 04h
18
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TAS5261DKD ACTIVE HSSOP DKD 36 29 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TAS5261DKDG4 ACTIVE HSSOP DKD 36 29 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TAS5261DKDR ACTIVE HSSOP DKD 36 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TAS5261DKDRG4 ACTIVE HSSOP DKD 36 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TAS5261DKDR HSSOP DKD 36 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jun-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5261DKDR HSSOP DKD 36 500 337.0 343.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jun-2009
Pack Materials-Page 2
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