NXP Semiconductors Technical Data Document Number: MPC17531A Rev. 10.0, 7/2016 700 mA dual H-Bridge motor driver with 3.0 V compatible logic I/O The 17531A is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar step motors and/or brush DC motors (e.g., cameras and disk drive head positioners). The 17531A operates from 2.0 to 8.6 V using the internal charge pump, with independent control of each H-Bridge, via a parallel MCU interface. The device features built-in shoot-through current protection and an undervoltage shutdown function. The 17531A has four operating modes: Forward, Reverse, Brake, and Tri-state (high-impedance). The 17531A has a low total RDS(on) of 1.2 (max at 25 C). The 17531A efficiently drives many types of micromotors with low power dissipation owing to its low output resistance and high output slew rates. The HBridge outputs can be independently pulse width modulated (PWM'ed) at up to 200 kHz for speed/torque and current control. This device is powered by SMARTMOS technology. 17531A DUAL H-BRIDGE EV SUFFIX (PB-FREE) 98ASA10616D 20-PIN VMFP EP SUFFIX (PB-FREE) 98ASA00474D 24-PIN QFN Bottom View EJ SUFFIX (PB-FREE) 98ASA00887D 20-PIN TSSOP WITH EXPOSED PAD Features * * * * * * * * Low total RDS(on) 0.8 (Typ), 1.2 (Max) at 25 C Output current 0.7 A (DC) Shoot-through current protection circuit PWM control input frequency up to 200 kHz Built-in charge pump circuit Low power consumption Undervoltage detection and shutdown circuit Power save mode with current draw 2.0 A MPC17531A 3.0 V 5.0 V 5.0 V VDD VM1 VM2 C1L C1H C2L C2H CRES OUT1A OUT1B OUT2A OUT2B MCU IN1A IN1B IN2A IN2B PSAVE LGND N S PGND1,2 Figure 1. 17531A Simplified application diagram (c) 2016 NXP B.V. Bipolar Step Motor ORDERABLE PARTS Orderable parts Table 1. Orderable part variations (1) Part number Temperature (TA) MPC17531ATEP MPC17531ATEV/EL Package 24 QFN (2) -20 C to 65 C MPC17531ATEJ 20 VMFP 20 TSSOP (exposed pad) Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. 2. Not recommended for new designs. 17531A 2 NXP Semiconductors INTERNAL BLOCK DIAGRAM Internal block diagram CRES C2H Charge Pump C1H C1L C2L Low-voltage Shutdown VDD VM1 IN1A OUT1A H-Bridge OUT1B IN1B VDD PSAVE Control Logic PGND1 Level Shifter Predriver VM2 IN2A OUT2A H-Bridge OUT2B IN2B PGND2 LGND Figure 2. 17531A Simplified internal block diagram 17531A NXP Semiconductors 3 PIN CONNECTIONS 15 7 14 8 13 9 12 10 11 IN2B 6 24 23 22 21 20 19 18 PSAVE 2 17 NC VM2 OUT2A 3 16 OUT2B PGND1 4 15 PGND2 OUT1A 5 14 OUT1B NC 6 13 10 11 12 20-Pin VMFP and 20-Pin TSSOP 7 8 9 C2L C1L 16 IN2A 5 LGND 17 1 C1H 4 NC C2H 18 VDD 19 3 Transparent top view CRES 2 LGND IN2A IN2B VM2 OUT2B PGND2 OUT1B C2L C1L CIH IN1A 20 VM1 1 NC VDD IN1A IN1B PSAVE OUT2A PGND1 OUT1A VM1 CRES C2H IN1B Pin connections 24-Pin QFN Figure 3. Pin connections A functional description of each pin can be found in the Functional Pin Description section beginning on page 9. Table 2. 17531A, pin definitions Pin number 20-Pin VMFP, 20-Pin TSSOP Pin number 24-Pin QFN Pin name Formal name 1 22 VDD Logic Supply 2 23 IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 6, Truth table, page 8). 3 24 IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 6, Truth table, page 8). 4 2 PSAVE Power Save 5 3 OUT2A H-Bridge Output 2A 6 4 PGND1 Power Ground 1 7 5 OUT1A H-Bridge Output 1A 8 8 VM1 9 9 CRES Predriver Power Supply 10 10 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole). 11 11 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole). 12 12 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole). 13 13 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole). 14 14 OUT1B H-Bridge Output 1B 15 15 PGND2 Power Ground 2 16 16 OUT2B 17 17 VM2 18 19 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 6, Truth table, page 8). 19 20 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 6, Truth table, page 8). Definition Control circuit power supply pin. Logic input controlling power save mode. Output A of H-Bridge channel 2. High-current power ground 1. Output A of H-Bridge channel 1. Motor Drive Power Supply 1 Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). H-Bridge Output 2B Internal triple charge pump output as predriver power supply. Output B of H-Bridge channel 1. High-current power ground 2. Output B of H-Bridge channel 2. Motor Drive Power Supply 2 Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). 20 21 LGND Logic Ground N/A 1, 6, 7, 17 NC -- - N/A - - Low-current logic signal ground. No Connect Exposed pad on 20-Pin TSSOP 17531A 4 NXP Semiconductors ELECTRICAL CHARACTERISTICS Electrical characteristics Maximum ratings Table 3. Maximum ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol VM VCRES Ratings Value Unit Motor Supply Voltage -0.5 to 11.0 V Charge Pump Output Voltage -0.5 to 14.0 V VDD Logic Supply Voltage -0.5 to 5.0 V VIN Signal Input Voltage -0.5 to VDD + 0.5 V IO Driver Output Current * Continuous * Peak 0.7 1.4 A 1200 150 V IOPK VESD1 VESD2 ESD Voltage * Human Body Model * Machine Model Notes (3) (4) TJ Operating Junction Temperature -20 to 150 C TA Operating Ambient Temperature -20 to 65 C TSTG Storage Temperature Range -65 to 150 C RJA Thermal Resistance 50 C/W (5) Power Dissipation * WMFP * QFN 1.0 2.5 W (6) Pin Soldering Temperature 260 C (7) Note 8 C (7), (8) PD TSOLDER TPPRT Peak Package Reflow Temperature During Reflow Notes 3. TA = 25 C, 10 ms pulse width at 200 ms intervals. 4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 5. QFN24: 45 x 30 x 1 [mm] glass EPOXY board mount. (See: recommended heat pattern) VMFP16: 37 x 50 x 1.6 [mm] glass EPOXY board mount. When the exposed pad is bonded, Rsj is not performed. Maximum at TA = 25 C. When the exposed pad is bonded, Rsj is not performed. 6. 7. 8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. NXP's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 17531A NXP Semiconductors 5 ELECTRICAL CHARACTERISTICS Static electrical characteristics Table 4. Static electrical characteristics Characteristics noted under conditions TA = 25 C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes 2.0 5.0 8.6 V (9) - - 10 V (10) (11) Power input V VM-CP Motor Supply Voltage (Using Internal Charge Pump) VM-NCP Motor Supply Voltage (VCRES Applied Externally) CRES - VM Gate Drive Voltage - Motor Supply Voltage (VCRES Applied Externally) 5.0 6.0 - V VDD Logic Supply Voltage 2.7 3.0 3.6 V IQM Driver Quiescent Supply Current * No Signal Input * Power Save Mode - - - - 100 1.0 A IQVDD Logic Quiescent Supply Current * No Signal Input * Power Save Mode - - - - 1.0 1.0 mA A (12) Operating Power Supply Current * Logic Supply Current * Charge Pump Circuit Supply Current - - - - 3.0 0.7 mA (13) (14) 1.0 1.6 2.5 V (15) (16) V (14) IQM-PSAVE IQVDD-PSAVE I I VDD CRES VDDDET Low VDD Detection Voltage RDS(ON) Driver Output ON Resistance - 0.8 1.2 Gate Drive Voltage * No Current Load 12 13 13.5 8.5 9.2 - 0.01 0.1 1.0 F 0 - VDD V VDD x 0.7 - - -1.0 - - - - - 50 - VDD x 0.3 1.0 - 100 V V A A A Gate drive V V CRES Gate Drive Ability (Internally Supplied) I CRESLOAD CCP * CRES = -1.0 mA Recommended External Capacitance (C1L - C1H, C2L - C2H, CRES - GND) V Control logic VIN Logic Input Voltage VIH VIL IIH IIL Logic Inputs (2.7 V < VDD < 3.3 V) * High Level Input Voltage * Low Level Input Voltage * High Level Input Current * Low Level Input Current * PSAVE Pin Input Current Low IIL- PSAVE Notes 9. Gate drive voltage VCRES is generated internally. 2 x VDD + VM must be < VCRES MAX (13.5 V). 10. No internal charge pump used. VCRES is applied from an external source. 11. RDS(ON) is not guaranteed if VCRES - VM < 5.0 V. Also, function is not guaranteed if VCRES - VM < 3.0 V. 12. IQVDD includes the current to pre-driver circuit. 13. I VDD includes the current to predriver circuit at fIN = 100 kHz. 14. At fIN = 20 kHz. 15. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. VCRES is applied from an external source. 2 x VDD + VM must be < VCRES MAX (13.5 V). 16. IO = 0.7 A source + sink. 17531A 6 NXP Semiconductors ELECTRICAL CHARACTERISTICS Dynamic electrical characteristics Table 5. Dynamic electrical characteristics Characteristics noted under conditions TA = 25 C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes - - 200 kHz s (17) Input f IN Pulse Input Frequency tR Input Pulse Rise Time - - 1.0 (18) tF Input Pulse Fall Time - - 1.0 (18) s (19) Propagation Delay Time * Turn-ON Time * Turn-OFF Time - - 0.1 0.1 0.5 0.5 s (20) t VGON Charge Pump Wake-up Time - 1.0 3.0 ms (21) t VDDDET Low Voltage Detection Time - - 10 ms Output t PLH t PHL Notes 17. 18. 19. 20. 21. Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Output load is 8.0 DC. CCP = 0.1 F. Timing diagrams IN1, IN2, PSAVE 50% tPLH tPHL 90% OUTA, OUTB 10% Figure 4. tPLH, tPHL, and tPZH timing V DDDETon VDD 0.8 V V 2.5 V DDDEToff 50% tV tV DDDET DDDET 90% 0% (<1.0 A) IM Figure 5. Low voltage detection timing 17531A NXP Semiconductors 7 ELECTRICAL CHARACTERISTICS VDD t VGON V CRES 11 V Figure 6. Charge pump timing Table 6. Truth table INPUT OUTPUT Charge pump and low voltage detector PSAVE IN1A IN2A IN1B IN2B OUT1A OUT2A OUT1B OUT2B L L L L L RUN L H L H L RUN L L H L H RUN L H H Z Z RUN H X X Z Z STOP H = High. L = Low. Z = High-impedance. X = Don't care. PSAVE pin is pulled up to VDD with internal resistance. 17531A 8 NXP Semiconductors FUNCTIONAL DESCRIPTION Functional description Introduction The 17531A is a monolithic dual H-Bridge ideal for portable electronic applications to control bipolar step motors and brush DC motors, such as those found in camera lens assemblies, camera shutters, and optical disk drives. The device features an on-board charge pump, as well as built-in shoot-through current protection and under-voltage shutdown. The 17531A has four operating modes: Forward, Reverse, Brake, and Tri-state (high-impedance). The MOSFETs comprising the output bridge have a total source + sink RDS(ON) 1.2 . The 17531A can simultaneously drive two brush DC motors or one bipolar step motor. The drivers are designed to be PWMed at frequencies up to 200 kHz. Functional pin description Logic supply (VDD) The VDD pin carries the logic supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins. Logic input control (IN1A, IN1B, IN2A, and IN2B) These logic input pins control each H-Bridge output. IN1A logic HIGH = OUT1A HIGH. However, if all inputs are taken HIGH, the outputs bridges are both tri-stated (refer to Table 6, Truth table, page 8). Power save (PSAVE) The PSAVE pin is a HIGH = TRUE power save mode input. When PSAVE = HIGH, all H-Bridge outputs (OUT1A, OUT1B, OUT2A, and OUT2B) are tri-stated (High-Z), regardless of logic inputs (IN1A, IN1B, IN2A, and IN2B) states, and the internal charge pump and low voltage detection current are shut off to save power. H-Bridge output (OUT1A, OUT1B, OUT2A, and OUT2B) These pins provide connection to the outputs of each of the internal H-Bridges (see Figure 2, 17531A Simplified internal block diagram, page 3). Motor drive power supply (VM1 and VM2) The VM pins carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the loads attached between the OUTput pins. All VM pins must be connected together on the printed circuit board. Charge pump (C1L and C1H, C2L and C2H) These two pairs of pins, the C1L and C1H, and the C2L and C2H, connect to the external bucket capacitors required by the internal charge pump. The typical value for the bucket capacitors is 0.1 F. Predriver power supply (CRES) The CRES pin is the output of the internal charge pump. Its output voltage is approximately three times of VDD voltage. The VCRES voltage is power supply for the internal predriver circuit of H-Bridges. Power ground (PGND) Power ground pins. They must be tied together on the PCB. Logic ground (LGND) Logic ground pin. 17531A NXP Semiconductors 9 TYPICAL APPLICATIONS Typical applications Figure 7 shows a typical application for the 17531A. When applying the gate voltage to the CRES pin from an external source, be sure to connect it via a resistor equal to or greater than RG = VCRES / 0.02 . The internal charge pump of this device is generated from the VDD supply; therefore, care must be taken to provide sufficient gate-source voltage for the high side MOSFETs when VM >> VDD (e.g., VM = 5.0 V, VDD = 3.3 V), in order to ensure full enhancement of the high side MOSFET channels. 17531A 3.3 V VCRES < 14 V RG > VCRES /0.02 NC NC NC NC C1L VDD C1H C2L C2H 5.0 V VM OUT1A CRES RG 0.01 F OUT1B OUT2A IN1A IN1B MCU IN2A IN2B OUT2B PSAVE GND NC = No Connect Figure 7. 17531A typical application diagram CEMF snubbing techniques Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients via placing a capacitor or zener at the supply pin (VM) (see Figure 8). PCB layout When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground pins to ensure proper filtering from transients. For all high current paths, use wide copper traces and the shortest possible distances. 3.3 V 5.0 V 17531A VDD VM 3.3 V 5.0 V 17531A VDD VM C1L C1L C1H C1H C2L C2H OUT C2L C2H OUT CRES CRES OUT GND OUT GND Figure 8. CEMF snubbing techniques 17531A 10 NXP Semiconductors PACKAGING Packaging Package dimensions For the most current package revision, visit www.NXP.com and perform a keyword search using the "98A" drawing number listed. 17531A NXP Semiconductors 11 PACKAGING 17531A 12 NXP Semiconductors PACKAGING 17531A NXP Semiconductors 13 PACKAGING 17531A 14 NXP Semiconductors PACKAGING 17531A NXP Semiconductors 15 PACKAGING 17531A 16 NXP Semiconductors PACKAGING 17531A NXP Semiconductors 17 PACKAGING 17531A 18 NXP Semiconductors PACKAGING 17531A NXP Semiconductors 19 PACKAGING 17531A 20 NXP Semiconductors REVISION HISTORY Revision history Revision Date 2.0 9/2005 * * Implemented Revision History page Converted to Freescale format 3.0 2/2008 * Corrected Table 2, Pin Definitions on page 4 4.0 5/2009 * Corrected Note 7, in Static Electrical Characteristics table 5.0 10/2013 * * * Updated package drawings Corrected ordering information table to MPC17531ATEP and MPC17531ATEV/EL Added new back page and document properties 6.0 10/2013 * Corrected packaging information on page 1 7.0 11/2014 * * Changed the QFN 98A to 98ASA00474D per PCN 16331 Corrected errors in ordering information 8.0 3/2015 * Corrected unit typo for Logic Quiescent Supply Current 7/2015 * * * Added 98ASA00887D package information and updated tables where applicable Added MPC17531ATEJ to the ordering information Updated as per PCN # 16724 8/2015 * Corrected the 98A package information for 20-pin TSSOP 10/2015 * * * Added EP notation for TSSOP package. Fixed notations for TSSOP in Orderable parts and Pin connections. Updated Packaging 98A drawing for TSSOP 7/2016 * Updated to NXP document form and style 9.0 10.0 Description of changes 17531A NXP Semiconductors 21 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. Home Page: NXP.com There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits Web Support: http://www.nxp.com/support products herein. based on the information in this document. NXP reserves the right to make changes without further notice to any NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. (c) 2016 NXP B.V. Document Number: MPC17531A Rev. 10.0 7/2016