(R) ADS-932 (R) 16-Bit, 2MHz Sampling A/D Converters INNOVATION and EXCELLENCE FEATURES * * * * * * * * * 16-bit resolution 2MHz sampling rate Functionally complete No missing codes over full military temperature range Edge-triggered 5V supplies, 1.85 Watts Small, 40-pin, ceramic TDIP 87dB SNR, -88dB THD Ideal for both time and frequency-domain applications INPUT/OUTPUT CONNECTIONS PIN GENERAL DESCRIPTION The low-cost ADS-932 is a 16-bit, 2MHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-932 has been optimized to achieve a signal-to-noise ratio (SNR) of 87dB and a total harmonic distortion (THD) of -88dB. Packaged in a 40-pin TDIP, the functionally complete ADS-932 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The ADS-932 only requires the rising edge of the start convert pulse to operate. Requiring only 5V supplies, the ADS-932 dissipates 1.85 Watts. The device is offered with a bipolar (2.75V) analog input range or a unipolar (0 to -5.5V) input range. Models are available for use in either commercial (0 to +70C) or military (-55 to +125C) operating temperature ranges. A proprietary, auto-calibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. Typical applications include medical imaging, radar, sonar, communications and instrumentation. FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN +3.2V REF. OUT UNIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST DIGITAL GROUND FIFO/DIR FIFO READ FSTAT1 FSTAT2 START CONVERT BIT 16 (LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 FUNCTION NO CONNECTION NO CONNECTION +5V ANALOG SUPPLY -5V SUPPLY ANALOG GROUND COMP. BITS OUTPUT ENABLE OVERFLOW EOC +5V DIGITAL SUPPLY DIGITAL GROUND BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 10 FSTAT1 11 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 8 FIFO/DIR 9 FIFO/READ 29 BIT 1 (MSB) ANALOG GROUND 4, 36 DIGITAL GROUND 7, 30 +5V DIGITAL SUPPLY 31 -5V SUPPLY 37 +5V ANALOG SUPPLY 38 NO CONNECTION OFFSET ADJUST 5 OFFSET ADJUST CKT. 39, 40 ANALOG INPUT 3 S/H 27 BIT 2 26 BIT 3 25 BIT 4 3-STATE OUTPUT REGISTER POWER and GROUNDING CUSTOM GATE ARRAY PRECISION +3.2V REFERENCE 2-PASS ANALOG-TO-DIGITAL CONVERTER 28 BIT 1 (MSB) +3.2V REF. OUT 1 24 BIT 5 23 BIT 6 22 BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 13 BIT 16 (LSB) START CONVERT 12 EOC 32 TIMING AND CONTROL LOGIC 34 OUTPUT ENABLE 33 OVERFLOW COMP. BITS 35 Figure 1. ADS-932 Functional Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2756 Fax: (508)339-6356 * E-mail:sales@datel.com * Internet: www.datel.com (R) ADS-932 ABSOLUTE MAXIMUM RATINGS PARAMETERS +5V Supply (Pins 31, 38) -5V Supply (Pin 37) Digital Inputs (Pins 8, 9, 12, 34, 35) Analog Input (Pin 3) Bipolar Unipolar Lead Temperature (10 seconds) (R) PHYSICAL/ENVIRONMENTAL LIMITS UNITS 0 to +6 0 to -6 -0.3 to +VDD +0.3 Volts Volts Volts Volts Volts Volts C 5 -10 to +5 +300 PARAMETERS MIN. TYP. MAX. UNITS 0 -55 -- -- +70 +125 C C -- -- -65 4 18 -- -- -- +150 C/Watt C/Watt C Operating Temp. Range, Case ADS-932MC ADS-932MM Thermal Impedance jc ca Storage Temperature Range Package Type Weight 40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams) FUNCTIONAL SPECIFICATIONS (TA = +25C, VCC = 5V, +VDD = +5V, 2MHz sampling rate, and a minimum 3 minute warm-up unless otherwise specified.) +25C ANALOG INPUTS Input Voltage Ranges Unipolar Bipolar Input Resistance (pin 3) Input Resistance (pin 2) Input Capacitance 0 to +70C MIN. TYP. MAX. -- -- 655 418 -- 0 to -5.5 2.75 687 426 10 -- -- -- -- 15 +2.0 -- -- -- 40 -- -- -- -- 250 -- -- -0.95 -- -- -- -- 16 MIN. -55 to +125C TYP. MAX. -- -- -- -- -- 0 to -5.5 2.75 685 400 10 -- -- -- -- 15 -- +0.8 +20 -20 -- +2.0 -- -- -- 40 -- -- -- -- 250 16 1 0.5 0.1 0.1 0.1 0.1 -- -- -- +1.0 0.3 0.2 0.3 0.3 -- -- -- -0.95 -- -- -- -- 16 -- -- -90 -90 -81 -81 -- -- -88 -87 83 82 MIN. TYP. MAX. UNITS -- -- -- -- -- 0 to -5.5 2.75 685 400 10 -- -- -- -- 15 Volts Volts pF -- +0.8 +20 -20 -- +2.0 -- -- -- 40 -- -- -- -- 250 -- +0.8 +20 -20 -- Volts Volts A A ns 16 1.5 0.5 0.15 0.2 0.2 0.15 -- -- -- +1.0 0.5 0.4 0.5 0.5 -- -- -- -0.95 -- -- -- -- 16 16 2 0.5 0.5 0.5 0.4 0.5 -- -- -- +1.5 0.8 0.9 0.9 0.9 -- Bits LSB LSB %FSR %FSR %FSR % Bits -- -- -90 -90 -81 -81 -- -- -88 -88 -80 -80 dB dB -80 -80 -- -- -88 -87 -80 -80 -- -- -85 -84 -78 -77 dB dB 87 86 -- -- 83 82 87 86 -- -- 80 80 85 84 -- -- dB dB 79 78 -- 84 84 83 -- -- -- 79 78 -- 84 84 83 -- -- -- 76 76 -- 82 82 83 -- -- -- dB dB Vrms -- -89 -- -- -89 -- -- -89 -- dB -- -- 7.8 7.1 -- -- -- -- 7.8 7.1 -- -- -- -- 7.8 7.1 -- -- MHz MHz -- -- -- -- 90 77 +8 5 -- -- -- -- -- -- -- -- 90 77 +8 5 -- -- -- -- -- -- -- -- 90 77 +8 5 -- -- -- -- dB V/s ns ps rms 200 225 -- 200 225 -- 200 225 -- ns DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Start Convert Positive Pulse Width STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (-0.5dB) dc to 500kHz 500kHz to 1MHz Total Harmonic Distortion (-0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (w/o distortion, -0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (& distortion, -0.5dB) dc to 500kHz 500kHz to 1MHz Noise Two-Tone Intermodulation Distortion (fin = 200kHz, 240kHz, fs = 2MHz, -0.5dB) Input Bandwidth (-3dB) Small Signal (-20dB input) Large Signal (-0.5dB input) Feedthrough Rejection (fin = 1MHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to 0.001%FSR, 5.5V step) 2 (R) (R) DYNAMIC PERFORMANCE (Cont.) Overvoltage Recovery Time A/D Conversion Rate ADS-932 MIN. +25C TYP. MAX. MIN. 0 TO +70C TYP. -55 TO +125C TYP. MAX. -- 2 250 -- 500 -- -- 2 3.15 -- -- +3.2 30 5 3.25 -- -- +2.4 -- -- -- -- -- -- -- -- +0.4 -4 +4 -- -- 10 -- -- 10 -- -- Straight Binary, Complementary Binary, Complementary Offset Binary, Complementary Two's Complement, Offset Binary, Two's Complement +4.75 -4.75 +5.0 -5.0 +5.25 -5.25 +4.75 -4.75 +5.0 -5.0 +5.25 -5.25 +4.9 -4.9 -- -140 -- -- +225 -135 1.85 -- 260 -- 2.0 0.07 -- -140 -- -- +225 -135 1.85 -- 260 -- 2.0 0.07 -- -140 -- -- MAX. MIN. UNITS 250 -- 500 -- -- 2 250 -- 3.15 -- -- +3.2 30 5 3.25 -- -- 3.15 -- -- +3.2 30 5 3.25 -- -- Volts ppm/C mA +2.4 -- -- -- -- -- -- -- -- +0.4 -4 +4 +2.4 -- -- -- -- -- -- -- -- +0.4 -4 +4 Volts Volts mA mA 10 ns +5.0 -5.0 +5.25 -5.25 Volts Volts +225 -135 1.85 -- 260 -- 2.0 0.07 mA mA Watts %FSR/%V 500 -- ns MHz ANALOG OUTPUT Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Delay, Falling Edge of Enable to Output Data Valid Output Coding POWER REQUIREMENTS Power Supply Ranges +5V Supply -5V Supply Power Supply Currents +5V Supply -5V Supply Power Dissipation Power Supply Rejection Footnotes: All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warm-up periods. The device must be continuously converting during this time. There is a slight degradation in performance when operating the device in the unipolar mode. Effective bits is equal to: When COMP. BITS (pin 35) is low, logic loading "0" will be -350A. This is the time required before the A/D output data is valid once the analog input is back within the specified range. This time is only guaranteed if the input does not exceed 4.75V (bipolar) or +2 to -7.5V (unipolar). (SNR + Distortion) - 1.76 + Full Scale Amplitude 20 log Actual Input Amplitude 6.02 A 1MHz clock with a positive pulse width is used for all production testing. See Timing Diagram for more details. 40ns < Start Pulse < 175ns or 280ns < Start Pulse < 460ns The minimum supply voltages of +4.9V and -4.9V for VDD are required for -55C operation only. The minimum limits are +4.75V and -4.75V when operating at +125C. TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-932 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (4, 7, 30 and 36) directly to a large analog ground plane beneath the package. 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-932 (see Tables 2a and 2b). When this pin has a TTL logic "0" applied, it complements all of the ADS-932's digital outputs. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. Bypass all power supplies and the +3.2V reference output to ground with 4.7F tantalum capacitors in parallel with 0.1F ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). 2. The ADS-932 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid. 3 (R) ADS-932 (R) When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1's or when the input equals or exceeds the voltage that produces all 0's. When COMP BITS is activated, the above conditions are reversed. If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-932. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. 8. When configuring the ADS-932 for the unipolar mode, Pin 1 (+3.2V REF.) should be connected to Pin 2 (Unipolar) through a non-inverting op-amp. For precision DC applications an OP-07 type amplifier is recommended, while AC applications requiring the lowest level of harmonic distortion should consider the AD9631. When configuring the ADS-932 for the bipolar mode, Pin 2 (Unipolar) should be physically disconnected from the surrounding circuitry. This will help prevent noise from coupling into the A/D. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. INTERNAL FIFO OPERATION The ADS-932 contains an internal, user-initiated, 18-bit, 16word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and overflow bits. Pins 8 (FIFO/ DIR) and 9 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs. FIFO Reset Feature At any time, the FIFO can be reset to an empty state by putting the ADS-932 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals. When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-932 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-932's digital data path. FIFO Status, FSTAT1 and FSTAT2 Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11). FIFO Write and Read Modes Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO. CONTENTS Empty (0 words) <half full (<8 words) half-full or more (8 words) Full (16 words) FSTAT1 0 0 1 1 FSTAT2 1 0 0 1 Table 1. FIFO Delays DELAY PIN TRANSITION Direct mode to FIFO enabled 8 FIFO enabled to direct mode 8 FIFO READ to output data valid 9 0 FIFO READ to status update when changing from <half full (1 word) to empty 9 1 FIFO READ to status update when changing from half full (8 words) to <half full (7 words) 9 0 FIFO READ to status update when changing from full (16 words) to half full (15 words) 9 0 Falling edge of EOC to status update when writing first word into empty FIFO 32 1 Falling edge of EOC to status update when changing FIFO from <half full (7 words) to half full (8 words) 32 1 Falling edge of EOC to status update when filling FIFO with 16th word 32 1 0 1 4 MIN. TYP. MAX. UNITS - 10 20 ns 0 1 - 10 20 ns - - 40 ns 0 - - 20 ns 1 - - 110 ns - - 190 ns 0 - - 190 ns 0 - - 110 ns 0 - - 28 ns 1 1 (R) (R) ADS-932 CALIBRATION PROCEDURE 12) so that the converter is continuously converting. Connect the converter per Figure 2. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed to compensate for the ADS-932's initial accuracy errors and may not be able to compensate for additional system errors. 2. For unipolar or bipolar zero/offset adjust, apply -42V to the ANALOG INPUT (pin 3). 3. For bipolar inputs, adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). For unipolar inputs, adjust the offset potentiometers until all output bits are 0's and the LSB flickers between 0 and 1 with Pin 35 tied high (straight binary) or until all bits are 1's and the LSB flickers between 0 and 1 with pin 35 tied low (complementary binary). A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. 4. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the trimpot until the output code flickers between all 0's and all 1's. For the ADS-932, offset adjusting is normally accomplished when the analog input is 0 minus 1/2 LSB (-42V). See Table 2b for the proper bipolar output coding. Gain Adjust Procedure Gain adjusting is accomplished when the analog input is at nominal full scale minus 11/2 LSB's (+2.749874V). 1. Apply +2.749874V to the ANALOG INPUT (pin 3). 2. For bipolar inputs adjust the gain potentiometer until all output bits are 0's and the LSB flickers between a 1 and 0 with pin 35 tied high (complementary offset binary) or until all output bits are 1's and the LSB flickers between a 1 and 0 with pin 35 tied low (offset binary). Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain adjustment. Zero/Offset Adjust Procedure 3. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the gain trimpot until the output code flickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110. 1. Apply a train of pulses to the START CONVERT input (pin 20k +5V 20k -5V +5V 6 GAIN ADJUST +5V 31 4.7F 0.1F 33 OVERFLOW 32 EOC 29 BIT 1 (MSB) 28 BIT 1 (MSB) 27 BIT2 26 BIT 3 +5V DIGITAL 25 24 23 22 +5V ANALOG -5V 0.1F 4.7F 37 -5V 34 ENABLE 8 FIFO/DIR 10 FSTAT1 2 UNIPOLAR 11 FSTAT2 1 +3.2V REF. OUT ADS-932 15 BIT 14 14 BIT 15 13 BIT 16 (LSB) CONNECT for UNIPOLAR MODE 6.8F ANALOG INPUT 3 FIFO READ 9 START CONVERT 12 COMP. BITS 35 0.1F BIT 4 BIT 5 BIT 6 BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 ANALOG 4, 36 GROUND + 4.7F 5 OFFSET ADJUST DIGITAL 7, 30 GROUND 38 + +5V 0.1F -5V 4.7F Figure 2. Bipolar Connection Diagram 5 +5V (R) ADS-932 THERMAL REQUIREMENTS underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70C and -55 to +125C. All room-temperature (TA = +25C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL's HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Converters," or contact DATEL directly, for additional information. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically insulating, thermally-conductive "pads" may be installed N N+1 N+2 N+3 START CONVERT 100ns typ. Acquisition Time 225ns typ. 20ns typ. Hold INTERNAL S/H 275ns typ. 75ns typ. 45ns typ. EOC 260ns typ. Conversion Time 20ns typ. OUTPUT Data N-4 Valid DATA 440ns typ. Data N-3 Valid 60ns typ. Data N-1 Valid Data N-2 Valid Invalid Data Invalid Data Notes: 1. Scale is approximately 50ns per division. fs = 2MHz. 2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the A/D. 3. The start convert positive pulse width must be between either 40 and 175nsec or 280 and 460nsec (when sampling at 1MHz) to ensure proper operation. For sampling rates lower than 1MHz, the start pulse can be wider than 460nsec, however a minimum pulse width low of 40nsec should be maintained. A 1MHz clock with a 100nsec positive pulse width is used for all production testing. Figure 3. ADS-932 Timing Diagram 0 -10 Amplitude Relative to Full Scale (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 0 100 200 300 400 500 600 700 800 Frequency (kHz) (fs = 2MHz, fin = 975kHz, Vin = -0.5dB, 16,384-point FFT) Figure 4. FFT Analysis of ADS-932 6 900 1000 (R) 7 7 2MHZ 8 14 8 9 14 B1 1 C9 2.2F DGND R3 20mH L3 20mH L2 ADS-932 EVALUATION BOARD SG4 AGND C13 2.2F 20mH AGND C11 2.2F L1 1 20mH 3.3k 2.2F C7 DGND +15V DGND +5VA -15V -5VA +5VD 2 6 5 C10 1 33pF 2 1 74HCT74 U1 SG5 AGND OFFSET ADJUST +5VA -5VA +5VD +5VF 2 AGND AGND C2 2.2F C1 2.2F SG3 25 23 21 19 17 15 13 11 9 7 5 3 1 J1 3 2 1 DGND DGND C6 2.2F +5VF 3 2 4 +5VF 6 L4 P2 0.1F 4 7 SG2 SG1 26 24 22 20 18 16 14 12 10 8 6 4 2 50 R6 AR1 C5 DGND START CONVERT 7 1 X1 13 74HCT74 U1 DGND 11 12 10 3 2 R2 3 1 -5VA R4 20k +5VA DGND SG9 RD FIF 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B9 B10 B11 B12 B13 B14 B15 LSB START FSTAT2 FSTAT1 READ FIFO/DIR DGND GAIN OFFSET AGND ANA IN AGND +3.2VREF AGND C3 0.1F 3 1 -5VA R5 20k DGND U6 UUT 38 39 40 COMP AGND 21 22 23 24 25 26 27 28 29 30 31 32 33 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 +5VD COMP -5VA +5VA DGND C15 0.1F 12 13 11 FST1 7 74HC86 U5 14 74HC86 8 U5 FST2 DGND +5VF 9 10 74HC86 1 3 U5 EOC 2 B8 B7 B6 B5 B4 B3 B2 MSB MSB DGND +5VD EOC OF 34 35 36 -5VA 37 +5VA NC NC ENABLE C4 2.2F +5VF AB2 AB1 C16 0.1F AB8 +5VF AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 DGND C8 0.1F DGND C17 0.1F +5VF AB7 AB6 AB5 AB4 DGND AB3 +5VF 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 11 20 11 20 11 20 Figure 5. ADS-932 Evaluation Board Schematic. 2 +5VA GAIN ADJUST 74HC86 4 6 START U5 CONVERT 5 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 -15V -5VA +15V +5VA SG6 SG8 SG7 U2 10 U3 U4 1 10 1 10 1 DGND 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 B9 B10 B11 B12 B13 B14 B15 +5VD FIF RD DGND COMP START B16 (LSB) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1(MSB) AGND 19 21 23 25 27 29 31 13 15 17 1 3 5 7 9 FST2 FST1 1 2 3 1 2 3 J5 J4 1 2 3 J3 FIFO/DIR READ COMPLIM ENABLE FIF/DIR N.C. READ DGND AGND C21 2.2F +5VA C12 2.2F COMPLIM ENABLE DGND DGND DGND DGND DGND DGND DGND EOC OVRFLW B1B MSB 1 2 3 J2 2 4 6 8 10 12 11 14 16 18 P1 20 22 24 26 28 30 32 33 -5VA AGND C14 2.2F +5VD DGND 34 C20 0.1F +5VA C19 0.1F -5VA AGND 0.1F 0.1F DGND C18 0.1F +5VD B16 (LSB) DGND B8 B7 B6 B5 B4 B3 B2 B1 (MSB) DGND 19 B1B MSB 18 OVRFLW 17 16 15 14 13 12 (R) AGND DGND 2 AGND +5VF B2 ANALOG INPUT AMPLIFIER OPTION AGND R1 74HCT573 74HCT573 74HCT573 (R) ADS-932 (R) ADS-932 (R) Table 2a. Setting Output Coding Selection (Pin 35) OUTPUT FORMAT PIN 35 LOGIC LEVEL Complementary Offset Binary 1 Offset Binary 0 Complementary Two's Complement (Using MSB, pin 29) 1 Two's Complement (Using MSB, pin 29) 0 Straight Binary Complimentary Binary 1 0 Table 2b. Output Coding STRAIGHT BINARY UNIPOLAR SCALE INPUT RANGE 0 to -5.5V MSB -FS+1 LSB -FS +1 1/2 LSB -7/8 FS -3/4 FS -1/2 FS -1/2FS-1/2LSB -1/4 FS -1/8 FS -1 LSB -1/2 LSB 0 -5.499916 -5.499874 -4.812500 -4.125000 -2.750000 -2.749958 -1.375000 -0.687500 -0.000084 -0.000042 0.000000 1111 1111 1111 LSB "1" to "0" 1110 0000 0000 1100 0000 0000 1000 0000 0000 0111 1111 1111 0100 0000 0000 0010 0000 0000 0000 0000 0000 LSB "0" to "1" 0000 0000 0000 COMP. BINARY OUTPUT CODING LSB 1111 0000 0000 0000 1111 0000 0000 0001 0000 OFFSET BINARY MSB LSB 0000 0000 0000 LSB "0" to "1" 0001 1111 1111 0011 1111 1111 0111 1111 1111 1000 000 000 1011 1111 1111 1101 1111 1111 1111 1111 1111 LSB "1" to "0" 1111 1111 1111 MSB 0000 0111 1111 1111 1111 0000 1111 1111 1110 0110 0100 0000 1111 1100 1010 1000 1111 1000 COMP. OFF. BIN. LSB 1111 1111 LSB "1" to "0" 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 LSB "0" to "1" 0000 0000 MSB 1111 1000 0000 0000 0000 1111 0000 0000 0001 1001 1011 1111 0000 0011 0101 0111 0000 0111 TWO'S COMP. 0 to -5.5V 2.75V Input Pin Pin 3 Pin 3 8 0000 1111 1111 1111 0000 1111 1111 1110 1111 COMP. TWO'S COMP. Table 3. Input Connections Input Range 0000 0000 LSB "0" to "1" 1111 1111 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 1111 1111 LSB "1" to "0" 1111 1111 LSB Connect Pin 1 To Pin 2 Pin 2 is No Connect INPUT RANGE 2.75V +2.749916 +2.749874 +2.062500 +1.375000 0.000000 -0.000084 -1.375000 -2.062500 -2.749916 -2.749958 -2.750000 BIPOLAR SCALE +FS -1 LSB +FS -1 1/2 LSB +3/4 FS +1/2 FS 0 -1 LSB -1/2 FS -3/4 FS -FS +1 LSB -FS + 1/2 LSB -FS (R) (R) ADS-932 Number of Occurrences DNL (LSB's) 0.74 -0.56 0 0 Codes 65,536 Digital Output Code Figure 6. ADS-932 Histogram and Differential Nonlinearity 4410 4000 3000 2000 1000 0 Digital Output Code Figure 7. ADS-932 Grounded Input Histogram This histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-932. 9 65,536 (R) ADS-932 (R) MECHANICAL DIMENSIONS INCHES (mm) 2.12/2.07 (53.85/52.58) 40 Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) 0.010 (0.254) 3 place decimal (.XXX) 0.005 (0.127) 21 Lead Material: Kovar alloy 1.11/1.08 (28.20/27.43) 1 Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 20 0.100 TYP. (2.540) 1.900 0.008 (48.260) 0.245 MAX. (6.223) PIN 1 INDEX ( ON TOP) 0.200/0.175 (5.080/4.445) 0.015/0.009 (0.381/0.229) 0.210 MAX. (5.334) 0.900 0.010 (22.86) 0.110/0.090 (2.794/2.286) 0.018 0.002 (0.457) 0.110/0.090 (2.794/2.286 SEATING PLANE 0.035/0.015 (0.889/0.381) 0.045/0.035 (1.143/0.889) ORDERING INFORMATION MODEL OPERATING TEMP. RANGE ACCESSORIES ADS-932MC ADS-932MM 0 to +70C -55 to +125C ADS-B932 HS-40 Evaluation Board (without ADS-932) Heat Sink for all ADS-932 models Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL. (R) (R) INNOVATION and EXCELLENCE ISO 9001 R E G I S T E R E D DS-0308A DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000, (800) 233-2756 Fax: (508) 339-6356 Internet: www.datel.com E-mail: sales@datel.com Data sheet fax back: (508) 261-2857 01/2000 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01 DATEL GmbH Munchen, Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.