LM5060MMX/NOPB - NATIONAL SEMICONDUCTOR

LM5060

January 16, 2012

High-Side Protection Controller with Low Quiescent

Current

General Description

The LM5060 high-side protection controller provides intelli-

gent control of a high-side N-Channel MOSFET during normal

on/off transitions and fault conditions. In-rush current is con-

trolled by the nearly constant rise time of the output voltage.

A power good output indicates when the output voltage reach-

es the input voltage and the MOSFET is fully on. Input Under-

Voltage Lock-Out, with hysteresis, is provided as well as

programmable input Over-Voltage Protection. An enable in-

put provides remote On / Off control. The programmable

Under-Voltage Lock-Out input can be used as second enable

input for safety redundancy. A single capacitor programs the

initial start-up VGS fault detection delay time, the transition

VDS fault detection delay time, and the continuous Over-Cur-

rent VDS fault detection delay time. When a detected fault

condition persists longer than the allowed fault delay time, the

MOSFET is latched off until either the Enable input or the Un-

der-Voltage Lock-Out input is toggled low and then high.

Features

■Available in Automotive grade / AEC Q-100

■Wide operating input voltage range: +5.5V to +65V

■Less than 15 µA quiescent current in disabled mode

■Controlled output rise time for safe connection of

capacitive loads

■Charge pump gate driver for external N-Channel MOSFET

■Adjustable Under-Voltage Lock-Out (UVLO) with

hysteresis

■UVLO serves as second enable input for systems

requiring safety redundancy

■Programmable fault detection delay time

■MOSFET latched off after load fault is detected

■Active low open drain POWER GOOD (nPGD) output

■Adjustable input Over-Voltage Protection (OVP)

■Immediate restart after Over-Voltage shutdown

Applications

■Automotive Body Electronics

■Industrial Power Distribution and Control

Package

■10-Lead MINI-SOIC

Typical Application

30104201

LM5060 High-Side Protection Controller with Low Quiescent Current

Connection Diagram

30104202

10-Lead MINI-SOIC Package (MSOP)

NS Package Number MUB10A

Ordering Information

Order Number Grade Package Type NSC Package Drawing Supplied As

LM5060MM Standard 10 Lead MSOP MUB10A 1000 Units on Tape and

Reel

LM5060MMX Standard 10 Lead MSOP MUB10A 3500 Units on Tape and

Reel

LM5060Q1MM Automotive 10 Lead MSOP MUB10A 1000 Units on Tape and

Reel

LM5060Q1MMX Automotive 10 Lead MSOP MUB10A 3500 Units on Tape and

Reel

Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.

Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard. Automotive Grade products are identified

with the letter Q. For more information go to http://www.national.com/automotive.

Pin Descriptions

No. Name Description Applications Information

1 SENSE Input Voltage Sense A constant current sink (16 μA typical) at the SENSE pin flows through an external resistor to

set the threshold for fault detection.

2 VIN Supply Voltage Input

The operating voltage range is 5.5V to 65V. The internal power-on-reset (POR) circuit typically

switches to the active state when the VIN pin is greater than 5.1V. A small ceramic bypass

capacitor close to this pin is recommended to suppress noise.

3 OVP

Over-Voltage

Protection Comparator

Input

An external resistor divider from the system input voltage sets the Over-Voltage turn-off

threshold. The GATE pin is pulled low when OVP exceeds the typical 2.0V threshold, but the

controller is not latched off. Normal operation resumes when the OVP pin falls below typically

1.76V.

4 UVLO Under-Voltage Lock-

Out Comparator Input

The UVLO pin is used as an input Under-Voltage Lock-Out by connecting this pin to a resistor

divider between input supply voltage and ground. The UVLO comparator is activated when EN

is high. A voltage greater than typically 1.6V at the UVLO pin will release the pull down devices

on the GATE pin and allow the output to gradually rise. A constant current sink (5.5 µA typical)

is provided to guarantee the UVLO pin is low in an open circuit condition.

5 EN Enable Input

A voltage less than 0.8V on the EN pin switches the LM5060 to a low current shutdown state.

A voltage greater than 2.0V on the EN pin enables the internal bias circuitry and the UVLO

comparator. The GATE pin pull-up bias is enabled when both EN and UVLO are in the high

state. A constant current sink (6 µA typical) is provided to guarantee the EN pin is low in an

open circuit condition.

6 GND Circuit ground

7 TIMER Timing capacitor

An external capacitor connected to this pin sets the VDS fault detection delay time. If the TIMER

pin exceeds the 2.0V threshold condition, the LM5060 will latch off the MOSFET and remain

off until either the EN, UVLO or VIN (POR) input is toggled low and then high.

www.ti.com 2

LM5060

No. Name Description Applications Information

8 nPGD Fault Status An open drain output. When the external MOSFET VDS decreases such that the OUT pin

voltage exceeds the SENSE pin voltage, the nPGD indicator is active (low = no fault).

9 OUT Output VoltageSense Connect to the output rail (external MOSFET source). Internally used to detect VDS and VGS

conditions.

10 GATE Gate drive output

Connect to the external MOSFET’s gate. A charge-pump driven constant current source (24

µA typical) charges the GATE pin. An internal zener clamps the GATE pin at typically 16.8V

above the OUT pin. The ΔV/Δt of the output voltage can be reduced by connecting a capacitor

from the GATE pin to ground.

3 www.ti.com

LM5060

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

VIN to GND (Note 4, Note 5)-0.3V to 75V

SENSE, OUT to GND (Note 6) -0.3V to 75V

GATE to GND (Note 4, Note 6) -0.3V to 75V

EN, UVLO to GND (Note 5) -0.3V to 75V

nPGD, OVP to GND -0.3V to 75V

TIMER to GND -0.3V to 7V

ESD Rating, HBM (Note 2) 2 kV

Storage Temperature −65°C to + 150°C

Peak Reflow Temperature(Note 3) 260°C

Junction Temperature 150°C

Operating Ratings (Note 1)

VIN Supply Voltage 5.5V to 65V

EN Voltage 0.0V to 65V

UVLO Voltage 0.0V to 65V

nPGD Off Voltage 0V to 65V

nPGD Sink Current 0mA to 5mA

Junction Temperature Range −40°C to + 125°C

Electrical Characteristics Unless otherwise stated the following conditions apply: VIN = 14V, EN =2.00V, UVLO

=2.00V, OVP = 1.50V, and TJ = 25°C. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating

junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical

correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.

Symbol Parameter Conditions Min Typ Max Units

VIN Pin

IIN-EN Input Current, Enabled Mode - 1.4 1.7 mA

IIN-DIS Input Current, Disabled Mode EN = 0.50V - 9 15 µA

IIN-STB Input Current, Standby Mode UVLO = 0.00V - 0.56 0.80 mA

POREN Power On Reset Threshold at VIN VIN Rising - 5.1 5.46 V

POREN-HYS POREN Hysteresis VIN Falling - 500 - mV

OUT Pin

IOUT-EN OUT Pin Bias Current, Enabled OUT = VIN, Normal Operation 5.0 811.0 µA

IOUT-DIS

OUT Pin Leakage Current, Disabled

(Note 4)Disabled, OUT = 0V, SENSE = VIN - 0 - μA

SENSE Pin

ISENSE Threshold Programming Current SENSE Pin Bias Current 13.6 16 18.0 µA

VOFFSET VDS Comparator Offset Voltage SENSE - OUT Voltage for Fault Detection -7.0 07.0 mV

IRATIO ISENSE and IOUT-EN Current Ratio ISENSE / IOUT-EN 1.70 2.0 2.30

OVP Input

OVPTH OVP Threshold OVP Pin Threshold Voltage Rising 1.88 2.0 2.12 V

OVPHYS OVP Hysteresis - 240 - mV

OVPDEL OVP Delay Time Delay from OVP Pin > OVPTH to GATE low - 9.6 - µs

OVPBIAS OVP Pin Bias Current OVP = 1.9V - 0 0.50 µA

UVLO Input

UVLOTH UVLO Threshold UVLO Pin Threshold Voltage Rising 1.45 1.6 1.75 V

UVLOHYS UVLO Hysteresis 120 180 230 mV

UVLOBIAS UVLO Pin Pull-Down Current 3.8 5.5 7.2 µA

EN Input

ENTHH High-level input voltage 2.00 - - V

ENTHL Low-level input voltage - - 0.80 V

ENHYS EN Threshold Hysteresis - 200 - mV

ENBIAS EN Pin Pull-down current - 6 8.0 µA

Gate Control (GATE Pin)

IGATE

Gate Charge (Sourcing) Current

On-state On-state 17 24 31 µA

IGATE-OFF

Gate Discharge (Sinking) Current

Off state UVLO = 0.00V - 2.2 - mA

IGATE-FLT

Gate Discharge (Sinking) Current

Fault state OUT < SENSE - 80 - mA

www.ti.com 4

LM5060

Symbol Parameter Conditions Min Typ Max Units

VGATE

Gate output voltage in normal

operation

GATE - VIN Voltage

GATE Pin Open 10 12 14 V

VGATE-TH

VGS Status Comparator Threshold

voltage

GATE - OUT threshold voltage for TIMER

voltage reset and TIMER current change 3.50 56.50 V

VGATE-CLAMP

Zener Clamp between GATE Pin and

OUT Pin IGATE-CLAMP = 0.1mA - 16.8 - V

Timer (TIMER Pin)

VTMRH Timer Fault Threshold TIMER Pin Voltage Rising - 2.0 - V

VTMRL Timer Re-enable Threshold TIMER pin Voltage Falling - 0.30 - V

ITIMERH Timer Charge Current for VDS Fault TIMER Charge current after Start-Up.

VGS = 6.5V 8.5 11 13.0 µA

ITIMERL Timer Start-Up Charge Current TIMER Charge current during Start-Up.

VGS = 3.5V 4.0 67.0 µA

ITIMERR Timer Reset Discharge Current TIMER Pin = 1.5V 4.4 68.2 mA

tFAULT Fault to GATE Low delay TIMER Pin > 2.0V

No load on GATE pin - 5 - µs

Power Good (nPGD Pin)

PGDVOL Output low voltage ISINK = 2 mA - 80 205 mV

PGDIOH Off leakage current VnPGD = 10V - 0.02 1.00 µA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including in-operability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should

not be operated beyond such conditions. For guaranteed specifications and conditions, see the Electrical Characteristics table.

Note 2: The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Applicable standard is JESD-22–A114–C.

Note 3: Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Reflow temperature profiles are different for

lead-free and non-lead-free packages. Refer to the Packaging Data Book available from National Semiconductor, or : www.national.com/analog/packaging

Note 4: The GATE pin voltage is typically 12V above the VIN pin when the LM5060 is enabled. Therefore, the Absolute Maximum Rating for VIN (75V) applies

only when the LM5060 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 75V.

Note 5: The minimum voltage of -1V is allowed if the current is limited to below -25 mA. Also it is assumed that the negative voltage on the pins only occur during

reverse battery condition when a positive supply voltage (Vin) is not applied.

Note 6: The minimum voltage of -25V is allowed if the current is limited to below -25 mA. Also it is assumed that the negative voltage on the pins only occur during

reverse battery condition when a positive supply voltage (VIN) is not applied.

5 www.ti.com

LM5060

Typical Performance Characteristics

VIN Pin Current

vs. VIN Pin Voltage

30104203

VGATE, VIN Voltage

vs. Input Voltage

30104204

OUT Pin Current (IOUT-EN)

vs. VIN Voltage

30104205

GATE Current (IGATE)

vs VIN Voltage

30104206

SENSE Current (ISENSE)

vs VIN Voltage

30104207

nPGD Low Voltage (PGDVOL

vs Sink Current

30104208

www.ti.com 6

LM5060

GATE Pull-Down Current Off (IGATE-OFF)

vs. GATE Voltage

30104209

EN Threshold Voltage (ENTH)

vs. Temperature

30104210

UVLO Threshold Voltage (UVLOTH)

vs. Temperature

30104259

GATE Pull-Down Current Fault (IGATE-FLT)

vs. GATE Voltage

30104211

UVLO, EN Current

vs. Temperature

30104212

OVP Threshold (OVPTH), Hysteresis (OVPHYS)

vs. Temperature

30104213

7 www.ti.com

LM5060

VGS Comparator Threshold Voltage (VGATE-TH)

vs. Temperature

30104214

VDS Comparator Offset Voltage (VOFFSET)

vs. Temperature

30104215

GATE Current (IGATE)

vs. Temperature

30104216

GATE Output Voltage (VGATE)

vs. Temperature

30104217

Gate Pull-Down Current - Fault (IGATE-FLT)

vs. Temperature

30104218

VIN Pin Current (IEN)

vs EN Voltage

30104219

www.ti.com 8

LM5060

nPGD Low Voltage (PGDVOL)

vs. Temperature

30104220

9 www.ti.com

LM5060

Block Diagram

30104221

www.ti.com 10

LM5060

30104222

FIGURE 1. Basic Application Circuit

Functional Description

The LM5060 is designed to drive an external high-side N-

channel MOSFET. Over-Current protection is implemented

by sensing the voltage drop across the MOSFET. When an

adjustable voltage drop threshold is exceeded, and an ad-

justable time period has elapsed, the MOSFET is disabled.

Over-Voltage Protection (OVP) and Under-Voltage Lock-Out

(UVLO) monitoring of the input line is also provided. A low

state on the enable pin will turn off the N-channel MOSFET

and switch the LM5060 into a very low quiescent current off

state. An active low power good output pin is provided to re-

port the status of the N-channel MOSFET. The waiting time

before the MOSFET is turned off after a fault condition is de-

tected can be adjusted with an external timer capacitor. Since

the LM5060 uses a constant current source to charge the gate

of the external N-channel MOSFET, the output voltage rise

time can be adjusted by adding external gate capacitance.

This is useful when starting up into large capacitive loads.

POWER-UP SEQUENCE

The basic application circuit is shown in Figure 1 and a normal

start-up sequence is shown in Figure 2. Start-up of the

LM5060 is initiated when the EN pin is above the (ENTHH)

threshold (2.0V). At start-up, the timer capacitor is charged

with a 6 µA (typical) current source while the gate of the ex-

ternal N-channel MOSFET is charged through the GATE pin

by a 24 µA (typical) current source.

When the gate-to-source voltage (VGS) reaches the VGATE-

TH threshold (typically 5V) the VGS sequence ends, the timer

capacitor is quickly discharged to 0.3V, and begins charging

the timer capacitor with a11 µA current source.

The timer capacitor will charge until either the VDS Compara-

tor indicates that the drain-to-source voltage (VDS) has been

reduced to a nominal value (i.e. no fault) or the voltage on the

timer capacitor has reached the VTMRH threshold (i.e. fault).

The VDS Comparator monitors the voltage difference between

the SENSE pin and the OUT pin. The SENSE pin voltage is

user programmed to be lower than the input supply voltage

by selecting a suitable sense resistor value. When the OUT

pin voltage exceeds the voltage at the SENSE pin, the nPGD

pin is asserted low (i.e. no fault) and the timer capacitor is

discharged.

STATUS CONDITIONS

Output responses of the LM5060 to various input conditions

is shown in Table 1. The input parameters include Enable

(EN), Under-Voltage Lock-Out (UVLO), Over-Voltage Protec-

tion (OVP), input voltage (VIN), Start-Up Fault (VGS) and Run

Fault (VDS) conditions. The output responses are the VIN pin

current consumption, the GATE charge current, the TIMER

capacitor charge (or discharge) current, the GATE discharge

current if the timer capacitor voltage has reached the VTMRH

threshold (typically 2V), as well as the status of nPGD.

11 www.ti.com

LM5060

30104223

FIGURE 2. Voltages During Normal Start Up Sequence

TABLE 1. Overview of Operating Conditions

Input Conditions Outputs Status

EN UVLO OVP

(typ)

VIN

(typ) SENSE-OUT GATE-

OUT

VIN

Current

(typ)

GATE Current

(typ) TIMER GATE after

TIMER > 2V

nPG

L L - >5.10V NA NA 0.009 mA 2.2 mA sink Low NA NA Disabled

L H - >5.10V NA NA 0.009 mA 2.2 mA sink Low NA NA Disabled

H L <2V >5.10V SENSE>OUT NA 0.56 mA 2.2 mA sink Low NA HStandby

SENSE<OUT L

H L >2V >5.10V SENSE>OUT NA 0.56 mA 80 mA sink Low NA HStandby

SENSE<OUT L

H H <2V >5.10V SENSE>OUT <5V 1.4 mA 24 µA source 6 µA source 80 mA sink H Enabled

SENSE<OUT Low NA L

H H <2V >5.10V SENSE>OUT >5V 1.4 mA 24 µA source

11 µA

source 80 mA sink H Enabled

SENSE<OUT Low NA L

H H >2V >5.10V SENSE>OUT NA 1.4 mA 80 mA sink Low NA HOver

Voltage

SENSE<OUT L

H H <2V <5.10V NA NA 1.4 mA 2.2 mA sink

(See Note†) Low NA H Power on

reset

Note †: The 2.2 mA sink current is valid for with the VIN pin ≥ 5.1V. When the VIN pin < 5.1V the sink current is lower. See ‘GATE Pin Off Current vs. VIN’ plot

in Typical Performance Characteristics.

GATE CONTROL

A charge pump provides bias voltage above the input and

output voltage to enhance the N-Channel MOSFET’s gate.

When the system voltage is initially applied and both EN and

UVLO are above their respective thresholds, the GATE pin is

charged by the 24 µA (typical) current source. During normal

operating conditions, the GATE pin voltage is clamped to ap-

proximately 16.8V above the OUT pin (i.e. VGS) by an internal

zener.

When either the UVLO input or the EN input is low, or when

VIN is below the Power-On Reset voltage of 5.10V (typical),

the GATE pin is discharged with a 2.2 mA (typical) current

sink.

When the timer capacitor is charged up to the VTMRH threshold

(typically 2V) a fault condition is indicated and the gate of the

external N-Channel MOSFET is discharged at a 80 mA (typ-

ical) rate . Additionally, when the OVP pin voltage is higher

than the OVPTH threshold (typically 2V) a fault is indicated and

the gate of the external N-Channel MOSFET is discharged at

the same 80 mA (typical) rate.

FAULT TIMER

An external capacitor connected from the TIMER pin to the

GND pin sets the fault detection delay time. If the voltage on

the TIMER capacitor reaches the VTMRH threshold (2V typical)

a fault condition is indicated. The LM5060 will latch off the

MOSFET by discharging the GATE pin at a 80mA (typical)

www.ti.com 12

LM5060

rate, and will remain latched off until either the EN pin, the

UVLO pin, or the VIN pin is toggled low and then high.

The block diagram of the LM5060 shows the details of the

TIMER pin. There are three relevant components to the

TIMER pin’s function:

1. A constant 6 µA (typical) current source driving the

TIMER pin. This current source is active when EN,

UVLO, and VIN are all high.

2. A second current source (5 µA typical) is activated, for a

total charge current of 11 µA (typical), only when the

VGS sequence has completed successfully.

3. A pull-down current sink for the TIMER pin which resets

the timer by discharging the timer capacitor. If EN, UVLO

or VIN is low, or when OVP is high, the timer capacitor is

discharged.

When the VDS Fault Comparator detects a fault, (SENSE

pin voltage higher than OUT pin voltage) the timer

capacitor pull down is disabled and the timer capacitor is

allowed to charge at the 11 µA (typical) rate.

During Start-Up, the timer behaves as follows:

After applying sufficient system voltage and enabling the

LM5060 by pulling the EN and UVLO pins high, the timer ca-

pacitor will be charged with a 6 µA (typical) current source.

The timer capacitor is discharged when the voltage difference

between the GATE pin and the OUT pin (i.e. VGS of the ex-

ternal N-Channel MOSFET) reaches the VGATE-TH threshold

(typically 5V). After discharging, the timer capacitor is

charged with 11 µA until either the VTMRH threshold (typically

2V) is reached, or the sensed VDS voltage falls below the

threshold of the VDS Fault Comparator, indicating the output

voltage has reached the desired steady state level. The timer

capacitor voltage waveforms are illustrated in Figure 2, Figure

3 and Figure 4.

A timer capacitor is always necessary to allow some finite

amount of time for the gate to charge and the output voltage

to rise during startup. If an adequate timer capacitor value is

not used, then the 6 µA of charge current would cause the

TIMER pin voltage to reach the VTMRH fault threshold (typically

2V) prematurely and the LM5060 will latch off since a fault

condition would have been indicated.

Although not recommended, the timer function can be dis-

abled by connecting the TIMER pin directly to GND. With this

condition the TIMER pin voltage will never reach the VTMRH

fault threshold (2V typical). The end result is that the fault

latch-off protection is completely disabled, while the nPGD pin

will continue to reflect the VDS Fault Comparator output.

VGS CONSIDERATIONS

The VGS Status Comparator shown in the LM5060 block dia-

gram accomplishes two purposes:

1. As the gate of the external MOSFET is charged, the

VGS voltage transitions from cut-off, through an active

region, and into the ohmic region. The LM5060 provides

two fault timer modes to monitor these transitions. The

TIMER pin capacitor is initially charged with a constant

6 µA (typical) until either the MOSFET VGS reaches the

VGATE–TH threshold (typically 5V) indicating that the

MOSFET channel is at least somewhat enhanced, or the

voltage on the TIMER pin reaches the VTMRH threshold

(typically 2V) indicating a fault condition. If the MOSFET

VGS reaches 5V threshold before the TIMER pin reaches

the typical 2V timer fault threshold, the timer capacitor is

then discharged to 300 mV, and then begins charging

with 11 µA current source while the MOSFET transitions

through the active region. The lower timer capacitor

charge current during the initial start-up sequence allows

more time before a fault is indicated. The turn-on time of

the MOSFET will vary with input voltage, load

capacitance, load resistance, as well as the MOSFET

characteristics.

2. Figure 3 shows a start-up waveform with excessive gate

leakage. The initial charge current on the timer capacitor

is 6 µA (typical), while the simultaneous charge current

to the gate is 24 µA (typical). Due to excessive gate

leakage, the 24 µA is not able to charge the gate to the

required typical 5V VGS threshold and the VDS Fault

Comparator will indicate a fault when the timer capacitor

is charged to the VTMRH fault threshold. When the timer

capacitor voltage reaches theVTMRH fault threshold

(typically 2V) the MOSFET gate is discharged at an 80

mA (typical) rate.

30104224

FIGURE 3. Voltages During Startup with VGS Gate Leakage Condition

13 www.ti.com

LM5060

VDS FAULT CONDITION

The LM5060 includes a VDS Fault Comparator that senses the

voltage difference between the SENSE pin and the OUT pin.

If the voltage at the OUT pin falls lower than the voltage at the

SENSE pin, the VDS Fault Comparator will trip and switch the

nPGD pin to a high impedance state. It will also initiate charg-

ing of the capacitor on the TIMER pin with a 6 µA (typical)

current source if VGS is less than than 5V, or a 11 µA (typical)

current source if VGS is higher than 5V. If the voltage on the

TIMER pin reaches the typical 2V fault threshold, the gate of

the N-Channel MOSFET is pulled low with a 80 mA (typical)

sink current. Figure 4 illustrates a VDS fault condition during

start-up. The nPGD pin never switches low because the VDS

fault comparator detects excessive VDS voltage throughout

the entire sequence.

OVER-CURRENT FAULT

The VDS Fault Comparator can be used to implement an Over-

Current shutdown function. The VDS Fault Comparator mon-

itors the voltage difference between the SENSE pin and the

OUT pin. This is, essentially, the same voltage that is across

the N-Channel MOSFET RDS(ON) less the threshold voltage

that is set by the series resistor on the SENSE pin. The value

of capacitor on the TIMER pin, the capacitor charge current

(ITIMERH, 11 uA typical), along with the TIMER pin fault thresh-

old (VTMRH) will determine the how long the N-Channel MOS-

FET will be allowed to conduct excessive current before the

MOSFET is turned-off. When this delay time expires, the gate

is discharged at a 80 mA rate.

The LM5060 is intended for applications where precise cur-

rent sensing is not required, but some level of fault protection

is needed. Examples are applications where inductance or

impedance in the power path limits the current rise in a short

circuit condition.

The Safe Operating Area (SOA) of the external N-Channel

MOSFET should be carefully considered to ensure the peak

drain-to-source current and the duration of the fault delay time

is within the SOA rating of the MOSFET. Also note that the

RDS(ON) variations of the external N-Channel MOSFET will af-

fect the accuracy of the Over-Current detection.

RESTART AFTER OVER-CURRENT FAULT EVENT

When a VDS fault condition has occurred and the TIMER pin

voltage has reached 2V, the LM5060 latches off the external

MOSFET. In order to initiate a restart, either the EN pin, the

VINpin, or the UVLO pin must be toggled low and then high.

30104225

FIGURE 4. Voltages During Startup with VDS Fault Condition

ENABLE

The LM5060 Enable pin (EN) allows for remote On/Off con-

trol. The Enable pin on/off thresholds are CMOS compatible.

The external N-Channel MOSFET can be remotely switched

Off by forcing the EN pin below the lower input threshold,

ENTHL (800 mV). The external N-Channel MOSFET can be

remotely switched On by forcing the EN pin above the upper

input threshold, ENTHH (2.00V). Figure 5 shows the threshold

levels of the Enable pin.

When the EN pin is less than 0.5V (typical) the LM5060 enters

a low current (disabled) state. The current consumption of the

VIN pin in this condition is 9 µA (typical).

30104226

FIGURE 5. Enable Function Threshold Levels

www.ti.com 14

LM5060

UNDER-VOLTAGE LOCK-OUT (UVLO)

The Under-Voltage Lock-Out function will turn off the external

N-Channel MOSFET with a 2.2 mA (typical) current sink at

the GATE pin. Figure 6 shows the threshold levels of the UV-

LO input. A resistor divider as shown in Figure 1 with R10 and

R11 sets the voltage at which the UVLO function engages.

The UVLO pin may also be used as a second enable pin for

applications requiring a redundant, or secondary, shut-down

control. Unlike the EN pin function, the UVLO function does

not switch the LM5060 to the low current (disabled) state.

If the Under-Voltage Lock-Out function is not needed, the

UVLO pin should be connected to the VIN pin. The UVLO pin

should not be left floating as the internal pull-down will keep

the UVLO active.

In addition to the programmable UVLO function, an internal

Power-On-Reset (POR) monitors the voltage at the VIN pin

and turns the MOSFET Off when VIN falls below typically

5.10V.

30104227

FIGURE 6. Under-Voltage Lock-Out Threshold Levels

OVER-VOLTAGE PROTECTION (OVP)

The Over-Voltage Protection function will turn off the external

N-Channel MOSFET if the OVP pin voltage is higher than the

OVPTH threshold (typically 2V). A resistor divider made up

with R8 and R9, shown in Figure 1, sets the Over-Voltage

Protection threshold. An internal 9.6 µs timer filters the output

of the Over-Voltage Comparator to prevent noise from trig-

gering an OVP event. An OVP event lasting longer than

typically 9.6 µs will cause the GATE pin to be discharged with

an 80 mA current sink and will cause the capacitor on the

TIMER pin to be discharged.

If the Over-Voltage Protection function is not needed, the

OVP pin should be connected to GND. The OVP pin should

not be left floating.

RESTART AFTER OVP EVENT

After the OVP function has been activated and the gate of the

external N-Channel MOSFET has been pulled low, the OUT

pin is likely to be low as well. However, an OVP condition will

not cause the VDS Fault Comparator to latch off of the LM5060

because the capacitor on the TIMER pin is also discharged

during an OVP event. After the OVP pin falls below the lower

threshold (typically 1.76V), the LM5060 will re-start as de-

scribed in the normal start-up sequence and shown in Figure

2. The EN, VIN, or UVLO pins do not need to be toggled low

to high to re-enable the MOSFET after an OVP event.

nPGD Pin

The nPGD pin is an open drain connection that indicates

when a VDS fault condition has occurred. If the SENSE pin

voltage is higher than the OUT pin voltage the state of the

nPGD pin will be high impedance. In the typical application,

as shown in Figure 1, the voltage at the nPGD pin will be high

during any VDS fault condition. The nPGD state is indepen-

dent of the fault timer function. The resistance R4 should be

selected large enough to safely limit the current into the nPGD

pin. Limiting the nPGD low state current below 5 mA is rec-

ommended.

15 www.ti.com

LM5060

Application Information

VDS FAULT DETECTION and SELECTING SENSE PIN

RESISTOR RS

The LM5060 monitors the VDS voltage of the external N-

Channel MOSFET. The drain to source voltage threshold

(VDSTH), which is set with the resistor RS, is shown in Figure

VDSTH = (RS x ISENSE) - VOFFSET

The MOSFET drain to source current threshold is:

where RDS(ON) is the resistive drop of the pass element Q1 in

Figure 7, VOFFSET is the offset voltage of the VDS comparator

and ISENSE (16 µA typical) is the threshold programming cur-

rent.

30104229

FIGURE 7. Setting the VDS Threshold

TURN-ON TIME

To slow down the output rise time a capacitor from the GATE

pin to GND may be added. The turn on time depends on the

threshold level of the N-Channel MOSFET, the gate capaci-

tance of the MOSFET as well as the optional capacitance

from the GATE pin to GND. Figure 8 shows the slow down

capacitor C1. Reducing the turn-on time allows the MOSFET

(Q1), to slowly charge a large load capacitance. Special care

must be taken to keep the MOSFET within its safe operating

area. If the MOSFET turns on too slow, the peak power losses

may damage the device.

30104230

FIGURE 8. Turn-On Time Extension

FAULT DETECTION DELAY TIME

To allow the gate of the MOSFET adequate time to change,

and to allow the MOSFET to conduct currents beyond the

protection threshold for a brief period of time, a fault delay

timer function is provided. This feature is important when drive

loads which require a surge of current in excess of the normal

ON current upon start up, or at any point in time, such as

lamps and motors. A single low leakage capacitor (CTIMER)

connected from the TIMER (pin 7), to ground sets the delay

time interval for both the VGS status detection at start-up and

for the subsequent VDS Over-Current fault detection.

When the LM5060 is enabled under normal operating condi-

tions the timer capacitor will begin charging at a 6 μA (typical)

rate while simultaneously charging the gate of the external

MOSFET at a 24 μA (typical) rate. The gate-to-source voltage

(VGS) of the external MOSFET is expected to reach the 5V

(typical) threshold before the timer capacitor has charged to

the VTMRH threshold (2V typical) in order to avoid being shut-

down.

While VGS is less than the typical 5V threshold (VGATE-TH), the

VDS start-up fault delay time is calculated from:

Where ITMRL is typically 6 μA and VTMRH is typically 2V. If the

CTIMER value is 68 nF (0.068μF) the VGS start-up fault delay

time would typically be:

VDS Fault Delay = ((2V x 0.068 μF) / 6 μA) = 23 ms

When the LM5060 has successfully completed the start-up

sequence by reaching a VGS of 5V within the fault delay time

set by the timer capacitor (CTIMER), the capacitor is quickly

discharged to 300mV (typical) and the charge current is in-

creased to 11 μA (typical) while the gate of the external

MOSFET is continued to be charge at a 24 μA (typical) rate.

The external MOSFET may not be fully enhanced at this point

in time and some additional time may be needed to allow the

gate-to-source voltage (VGS) to charge to a higher value. The

drain-to-source voltage (VDS) of the external MOSFET must

fall below the VDSTH threshold set by RS and ISENSE before the

timer capacitor has charged to the VTMRH threshold (2V typi-

cal) to avoid a fault.

When VGS is greater than the typical 5V threshold (VGATE-

TH), the VDS transition fault delay time is calculated from:

www.ti.com 16

LM5060

Where ITMRH is typically 11 μA, VTMRH is typically 2V, and

VTMRL is typically 300 mV. If the CTIMER value is 68 nF

(0.068 μF) the VDS transition fault delay time would typically

be:

VDS Fault Delay = (((2V-0.3V) x 0.068 μF) / 11 μA) = 10 ms

Should a subsequent load current surge trip the VDS Fault

Comparator, the timer capacitor discharge transistor turns

OFF and the 11 μA (typical) current source begins linearly

charging the timer capacitor. If the surge current, with the de-

tected excessive VDS voltage, lasts long enough for the timer

capacitor to charge to the timing comparator threshold

(VTMRH) of typically 2V, the LM5060 will immediately dis-

charge the MOSFET gate and latch the MOSFET off. The

VDS fault delay time during an Over-Current event is calcu-

lated from:

Where ITMRH is typically 11 μA and VTMRH is typically 2V. If the

CTIMER value is 68 nF (0.068 μF) the VDS Over-Current fault

delay time would typically be:

VDS Fault Delay = ((2V x 0.068 μF) / 11 μA) = 12 ms

Since a single capacitor is used to set the delay time for mul-

tiple fault conditions, it is likely that some compromise will

need to be made between a desired delay time and a practical

delay time.

MOSFET SELECTION

The external MOSFET (Q1) selection should be based on the

following criteria:

•The BVDSS rating must be greater than the maximum

system voltage (VIN), plus ringing and transients which can

occur at VIN when the circuit is powered on or off.

•The maximum transient current rating should be based on

the maximum worst case VDS fault current level.

•MOSFETs with low threshold voltages offer the advantage

that during turn on they are more likely to remain within

their safe operating area (SOA) because the MOSFET

reaches the ohmic region sooner for a given gate

capacitance.

•The safe operating area (SOA) of the MOSFET device and

the thermal properties should be considered relative to the

maximum power dissipation possible during startup or

shutdown.

•RDS(ON) should be sufficiently low that the power

dissipation at maximum load current ((IL(MAX))2 x RDS(ON))

does not increase the junction temperature above the

manufacturer’s recommendation.

•If the device chosen for Q1 has a maximum VGS rating less

than 16V, an external zener diode must be added from

gate to source to limit the applied gate voltage. The

external zener diode forward current rating should be at

least 80 mA to conduct the full gate pull-down current

during fault conditions.

INPUT and OUTPUT CAPACITORS

Input and output capacitors are not necessary in all applica-

tions. Any current that the external MOSFET conducts in the

on-state will decrease very quickly as the MOSFET turns off.

All trace inductances in the design including wires and printed

circuit board traces will cause inductive voltage kicks during

the fast termination of a conducting current. On the input side

of the LM5060 circuit this inductive kick can cause large pos-

itive voltage spikes, while on the output side, negative voltage

spikes are generated. To limit such voltage spikes, local ca-

pacitance or clamp circuits can be used. The necessary ca-

pacitor value depends on the steady state input voltage level,

the level of current running through the MOSFET, the induc-

tance of circuit board traces as well as the transition speed of

the MOSFET.

Since the exact amount of trace inductance is hard to predict,

careful evaluation of the circuit board is the best method to

optimize the input or output capacitance or clamp circuits.

UVLO, OVP

The UVLO and OVP thresholds are programmed to enable

the external MOSFET (Q1) when the input supply voltage is

within the desired operating range. If the supply voltage is low

enough that the voltage at the UVLO pin is below the UVLO

threshold, Q1 is switched off by a 2.2 mA (typical) current sink

at the GATE pin, denying power to the load. The UVLO

threshold has approximately 180 mV of hysteresis.

If the supply voltage is high enough that the voltage at the

OVP pin is above the OVP threshold, the GATE pin is pulled

low with a 80 mA current sink. Hysteresis is provided for each

threshold. The OVP threshold has approximately 240 mV of

hysteresis.

Option A: The configuration shown in Figure 9 requires three

resistors (R1, R2, and R3) to set the thresholds.

30104231

FIGURE 9. UVLO and OVP Thresholds Set By R1, R2 and

The procedure to calculate the resistor values is as follows:

1. Select R1 based on current consumption allowed in the

resistor divider, including UVLOBIAS, and consideration of

noise sensitivity. A value less than 100 kΩ is recommended,

with lower values providing improved immunity to variations

in ULVOBIAS.

2. Calculate R3 with the following formula:

17 www.ti.com

LM5060

3. Calculate R2 with the following formula:

VINMIN is the minimum and VINMAX is the maximum input volt-

age of the design specification. All other variables can be

found in the Electrical Characteristics table of this document.

To calculate the UVLO lower threshold including its hysteresis

for falling VIN, use (UVLOTH-UVLOHYS) instead of UVLOTH in

the formulas above. To calculate the OVP lower threshold in-

cluding hysteresis for falling VIN, use (OVPTH-OVPHYS) in-

stead of OVPTH. With three given resistors R1, R2, and R3,

the thresholds can be calculated with the formulas below:

Also in these two formulas, the respective lower threshold

value including the hysteresis is calculated by using (UV-

LOTH-UVLOHYS) instead of UVLOTH, and (OVPTH-OVPHYS)

instead of OVPTH. The worst case thresholds, over the oper-

ating temperature range, can be calculated using the respec-

tive min and max values in bold font in the Electrical

Characteristics .

Option B: UVLO and OVP can be independently adjusted

using two resistor dividers as shown in Figure 10.

30104235

FIGURE 10. Programming the Thresholds with Resistors

R8-R11

Choose the upper UVLO thresholds to ensure operation down

to the lowest required operating input voltage (VINMIN). Select

R11 based on resistive divider current consumption and noise

sensitivity. A value less than 100 kΩ is recommended, with

lower values providing improved immunity to variations in UL-

VOBIAS.

To calculate the UVLO low threshold including its hysteresis,

use (UVLOTH-UVLOHYS) instead of UVLOTH in the formula

above. Choose the lower OVP threshold to ensure operation

up to the highest VIN voltage required (VINMAX). Select R9

based on resistive divider current consumption A value less

than 100 kΩ is recommended.

To calculate the OVP low threshold including hysteresis, use

(OVPTH-OVPHYS) instead of OVPTH. Where the R9-R11 re-

sistor values are known, the threshold voltages are calculated

from the following:

Also in these two formulas, the respective low value including

the threshold hysteresis is calculated by using (UVLOTH-UV-

LOHYS) instead of UVLOTH and (OVPTH-OVPHYS) instead of

OVPTH. The worst case thresholds, over the operating tem-

perature range, can be calculated using the respective mini-

mum and maximum values in bold font in the Electrical

Characteristics .

Option C: The OVP function can be disabled by grounding

the OVP pin. The UVLO thresholds are set as described in

Option B.

POWER GOOD INDICATOR

A resistor between a supply voltage and the nPGD pin limits

the current into the nPGD pin in a logic low condition. A nPGD

pin sink current in the range of 1 mA to 5 mA is recommended.

The example in Figure 11 connects the nPGD pull-up resistor

R4 to the VIN pin. Any positive supply voltage less than 65V

may be used instead of VIN.

30104239

FIGURE 11. Circuitry at the nPGD Pin

www.ti.com 18

LM5060

INPUT BYPASS CAPACITOR

Some input capacitance from the VIN pin to the GND pin may

be necessary to filter noise and voltage spikes from the VIN

rail. If the current through Q1 in Figure 1 is very large a sudden

shutdown of Q1 will cause an inductive kick across the line

input and pc board trace inductance which could damage the

LM5060. In order to protect the VIN pin as well as SENSE,

OVP, UVLO, and nPGD pins from harm, a larger bulk capac-

itor from VIN to GND may be needed to reduce the amplitude

of the voltage spikes. Protection diodes or surge suppressors

may also be used to limit the exposure of the LM5060 pins to

voltages below their maximum operating ratings.

THERMAL CONSIDERATIONS

In normal operation the LM5060 dissipates very little power

so that thermal design may not be very critical. The power

dissipation is typically the 2 mA input current times the input

voltage. If the application is driving a large capacitive load

application, upon shutdown of the LM5060, the load capacitor

may partially, or fully, discharge back through the LM5060

circuitry if no other loads consume the energy of the pre-

charged load capacitor. One application example where en-

ergy is dissipated by the LM5060 is a motor drive application

with a large capacitor load. When the LM5060 is turned off,

the motor might also turn off such that total residual energy in

the load capacitor is conducted through the OUT pin to

ground. The power dissipated within the LM5060 is deter-

mined by the discharge current of 80 mA and the voltage on

the load capacitor.

LARGE LOAD CAPACITANCE

Figure 12 shows an application with a large load capacitance

CL. Assume a worst case turn off scenario where Vin remains

at the same voltage as CL and RL is a high impedance. The

body diode of Q1 will not conduct any current and all the

charge on CL is dissipated through the LM5060 internal cir-

cuitry. The dotted line in Figure 12 shows the path of this

current flow. Initially the power dissipated by the LM5060 is

calculated with the formula:

P = IGATE-FLT x VOUT

Where IGATE-FLT is the sink current of the LM5060 gate control.

In applications with a high input voltage and very large output

capacitance, the discharge current can be limited by an ad-

ditional discharge resistor RO in series with the OUT pin as

shown in Figure 13. This resistor will influence the current limit

threshold, so the value of RS will need to be readjusted.

30104240

FIGURE 12. Discharge Path of Possible Load Capacitor

In applications exposed to reverse polarity on the input and a

large load capacitance on the output, a current limiting resis-

tor in series with the OUT pin is required to protect the

LM5060 OUT pin from reverse currents exceeding 25 mA.

Figure 13 shows the resistor RO in the trace to the OUT pin.

30104241

FIGURE 13. Current Limiting Resistor RO for Special

Cases

If a RO resistor in the OUT path is used, the current sensing

will become less accurate since RO has some variability as

well as the current into the OUT pin. The OUT pin current is

specified in the Electrical Characteristics section as IOUT-EN.

A RO resistor design compromise for protection of the OUT

pin and a maintaining VDS sensing accuracy can be achieved.

See the REVERSE POLARITY PROTECTION WITH A RE-

SISTOR for more details on how to calculate a reasonable

RO value.

REVERSE POLARITY PROTECTION WITH DIODES

Figure 14 shows the LM5060 in an automotive application

with reverse polarity protection. The second N-channel MOS-

FET Q2 is used to prevent the body diode of Q1 from con-

ducting in a reverse VIN polarity situation. The zener diode D3

is used to limit VIN voltage transients which will occur when

Q1 and Q2 are shut off quickly. In some applications the in-

ductive kick is handled by input capacitors and D3 can be

omitted. In reverse polarity protected applications, the input

capacitors will see the reverse voltage. To avoid stressing in-

put capacitors with reverse polarity, a transorb circuit imple-

mented with D3 and D2 may be used. Diode D1 in Figure

14 protects the VIN pin in the event of reverse polarity. The

resistor R1 protects the GATE pin from reverse currents ex-

ceeding 25 mA in the reverse polarity situation. This GATE

resistor would slow down the shutdown of Q1 and Q2 dra-

matically. To prevent a slow turn off in fault conditions, D5 is

added to bypass the current limiting resistor R1. When Q1

and Q2 are turned on, R1 does not cause any delay because

the GATE pin is driven with a 24 µA current source. D6, Q3

and R2 protect Q2 from VGS damage in the event of reverse

input polarity. Diodes D5 and D7 are only necessary if the

output load is highly capacitive. Such a capacitive load in

combination with a high reverse polarity input voltage condi-

tion can exceed the power rating of the internal zener diode

between OUT pin and GATE pin as well as the internal diode

between the OUT pin and SENSE pin. External diodes D5

and D7 should be used in reverse polarity protected applica-

tions with large capacitive loads.

19 www.ti.com

LM5060

Figure 14 Example Circuit Specification

Operating Voltage Range 9V to 24V

Current max 30A

OVP setting 27V typical

UVLO setting 9V typical

30104242

FIGURE 14. Application with Reverse Polarity Protection with Diodes for OUT Pin Protection

REVERSE POLARITY PROTECTION WITH A RESISTOR

An alternative to using external diodes to protect the LM5060

OUT pin in the reverse polarity input condition is a resistor in

series with the OUT pin. Adding an OUT pin resistor may re-

quire modification of the resistor in series with the SENSE pin.

A resistor in series with the OUT pin will limit the current

through the internal zener diode between OUT and GATE as

well as through the diode between OUT and SENSE. The

value of these resistors should be calculated to limit the cur-

rent through the diode across the input terminals of the VDS

fault comparator to be no more than 4 mA. Figure 15 shows

the internal circuitry relevant for calculating the values of the

resistor RO in the OUT path to limit the current into the OUT

pin to 4 mA.

30104243

FIGURE 15. Current Limiting Resistor for Negative SENSE Condition

When calculating the minimum RO resistor required to limit

the current into the OUT pin, the internal current sources of

8 µA and 16 µA may be neglected. The following formulas can

be used to calculate the resistor value RO(MIN) which is nec-

essary to keep the IO current to less than 4 mA.

Case A for situations where VOUT > VIN and reverse polarity

situation is present. See Figure 15. VIN is negative, but the

voltage at the SENSE pin can roughly be assumed to be 0.0V

due to the internal diode from the SENSE pin to GND.

www.ti.com 20

LM5060

In this case, VIN also has to be limited to a negative voltage

so that reverse current through the SENSE pin does not ex-

ceed 25 mA.

30104257

FIGURE 16. Current Limiting Resistor in the OUT Path for OUT > SENSE Condition

Case B for situations where VOUT > VIN and there is no reverse

polarity situation present. See Figure 16. VIN is positive and

VOUT is also positive, but VOUT is higher than VIN:

In this case the voltage on the SENSE pin should not exceed

65V.

Case C for situations where VOUT < VIN and both VIN and

VOUT are positive as well. In such cases there is no risk of

excessive OUT pin current. No current limiting resistors are

necessary. Both the SENSE and OUT voltages should be

limited to less than 65V.

30104258

FIGURE 17. Current Limiting Resistor for Negative OUT Conditions

Case D for situations where VOUT < VIN, while VOUT is negative

and VIN is positive. See Figure 17. RO needs to be selected

to protect the OUT pin from currents exceeding 25 mA.

FAULT DETECTION WITH RS AND RO

Figure 18 shows an example circuit where the OUT pin is

protected against a reverse battery situation with a current

limiting resistor RO. When using resistor RO in the OUT pin

path, the resistor RS has to be selected taking the RO resistor

into account. The LM5060 monitors the VDS voltage of an ex-

21 www.ti.com

LM5060

ternal N-Channel MOSFET. The VDS fault detection voltage

is the drain to source voltage threshold (VDSTH). The formula

below calculates a proper RS resistor value for a desired

VDSTH taking into account the voltage drop across the RO re-

sistor.

VOFFSET is the offset voltage between the SENSE pin and the

OUT pin, ISENSE is the threshold programming current, and

IOUT-EN is the OUT pin bias current. When RS and RO have

been selected, the following formula can be used for VDSTH

min and max calculations:

The MOSFET drain-to-source current threshold is:

Where RDS(ON) is the on resistance of the pass element Q1 in

Figure 1.

CIRCUIT EXAMPLE OF REVERSE POLARITY

PROTECTION WITH RESISTOR

Figure 18 shows an example circuit which is protected against

reverse polarity using resistor R8 instead of the diodes D5

and D7 of Figure 14.

Figure 18 Example Circuit Specification

Operating Voltage Range 9V to 24V

Current max 30A

OVP setting 27V typical

UVLO setting 9V typical

30104251

FIGURE 18. Application with Reverse Polarity Protection with a Resistor for OUT Pin Protection

www.ti.com 22

LM5060

Physical Dimensions inches (millimeters) unless otherwise noted

10-Lead MSOP Package

NS Package Number MUB10A

23 www.ti.com

LM5060

Notes

LM5060 High-Side Protection Controller with Low Quiescent Current

www.ti.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP®Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265