ADVANCE INFORMATION PI74AVC+16501 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 18-Bit Universal Bus Transceiver With 3-State Outputs Product Features Product Description * PI74AVC+16501 is designed for low voltage operation, VCC = 1.65V to 3.6V * True 24mA Balanced Drive @ 3.3V * IOFF supports partial Power-down operation * 3.6V I/O Tolerant inputs and outputs * All outputs contain noise reduction circuitry reducing noise without speed degradation * Industrial operation at 40C to +85C * Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 173 mil wide plastic TVSOP (K) Pericom Semiconductors PI74AVC+series of logic circuits are produced using the Companys advanced 0.35 micron CMOS technology, achieving industry leading speed. The 18-bit PI74AVC+16501 univeral bus transceiver is designed for 1.65V to 3.6V VCC operation. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latch Enable (LEAB and LEBA), and CLOCK (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the highimpedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The Output Enables are complementary (OEAB is active HIGH and OEBA is active LOW) To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Block Diagram 1 PXXXX 04/24/00 ADVANCE INFORMATION PI74AVC+16501 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name OE LE CLK Ax Bx GND VCC Truth Table(1) Description Output Enable Input (Active HIGH) Latch Enable (Active HIGH) Clock Input (Active HIGH) Data I/O Data I/O Ground Power Inputs Product Pin Configuration OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 56 55 GND CLKAB 3 4 5 54 53 52 B1 6 7 8 51 50 49 B3 9 10 48 47 B5 11 12 56-Pin 13 A,K 46 45 44 GND 14 15 16 43 42 B9 41 B11 17 18 40 39 B12 19 20 21 38 37 36 22 23 24 35 34 33 25 26 32 31 27 28 30 29 Output B OEAB LEAB CLKAB A L X X X Z H H X L L H H X H H H L L L H L H H H L H X B0 H L L X B0 Notes: 1. H = High Signal Level L = Low Signal Level Z = High Impedance = LOW-to-HIGH Transition A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA. Output level before the indicated steady-state input conditions were established, provided that CLKAB is HIGH before LEAB goes LOW. Output level before the indicated steady-state input conditions were established. GND B2 VCC B4 B6 B7 B8 B10 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND 2 PXXXX 04/24/00 ADVANCE INFORMATION PI74AVC+16501 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ............................................................................................ 0.5V to +4.6V Input voltage range, VI .................................................................................................... 0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ............................................................ 0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ........................................................................................ 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ............................................................................ 50mA Output clamp current, IOK (VO <0) ...................................................................... 50mA Continuous output current, IO ...................................................................................................... 50mA Continuous current through each VCC or GND ................................................. 100mA Package thermal impedance, JA(3): package A .................................................... 64C/W package K ................................................... 48C/W Storage Temperature range, Tstg .............................................................................. 65C to 150C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. Input & output negative-voltage ratings may be exceeded if the input and output current rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions(1) VC C Supply Voltage M in. M ax. O perating 1.65 3.6 Data retention only 1.2 VC C VC C = 1.2V VIH High- level Input Voltage VC C = 1.65V to 1.95V 0.65 x VC C VC C = 2.3V to 2.7V 1.7 VC C = 3V to 3.6V 2 VC C = 1.2V VIL Low- level Input Voltage VI Input Voltage VO O utput Voltage IOH High- level output current IOL Low- level output current tv Input transition rise or fall rate TA Units Gnd VC C = 1.65V to 1.95V V 0.35 x VC C VC C = 2.3V to 2.7V 0.7 VC C = 3V to 3.6V 0.8 0 3.6 Active State 0 VC C 3- State 0 3.6 VC C = 1.65V to 1.95V 6 VC C = 2.3V to 2.7V 12 VC C = 3V to 3.6V 24 mA VC C = 1.65V to 1.95V 6 VC C = 2.3V to 2.7V 12 VC C = 3V to 3.6V 24 VC C = 1.65V to 3.6V 5 ns/V 85 C 40 O perating free- air temperature Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation. 3 PXXXX 04/24/00 ADVANCE INFORMATION PI74AVC+16501 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over Operating Range, TA = 40C +85C) Te s t Conditions (1) Parame te rs VOH VOL II IOFF IOZ ICC Control Inputs IOH = IOH = IOH = IOH = 100A 6mA 12mA 24mA IOL = IOL = IOL = IOL = 100A 6mA 12mA 24mA VCC M in. VIH = 1.07V VIH = 1.7V VIH = 2V 1.65V to 3.6V 1.65V 2.3V 3V VCC 0.2V 1.2 1.75 2.0 VIH = 0.57V VIH = 0.7V VIH = 0.8V 1.65V to 3.6V 1.65V 2.3V 3V 0.2 0.45 0.55 0.75 3.6V 0 3.6V 3.6V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V 2.5 10 10 40 4 4 6 6 8 8 VI = VCC or GND VI or VO = 3.6V VI = VCC or GND VO = VCC or GND IO = 0 Control Inputs CI VI = VCC or GND Data Inputs CO O utputs VO = VCC or GND M ax. Units V A pF Note: Typical values are measured at TA = 25C. 4 PXXXX 04/24/00 ADVANCE INFORMATION PI74AVC+16501 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted, see Figures 1 thru 4) VCC = 1.5V 0.1V VCC = 1.2 V M in. M ax. M in. M ax. VCC = 1.8V 0.15V M in. M ax. VCC = 2.5V 0.2V M in 180 180 LE High 3 3 CLK high or low 3 3 Data before CLK tsu Setup time Data before LE 1.5 1.2 CLK High 1.5 1.2 CLK Low 1.0 1.0 0.7 0.7 1.4 1.2 Data before CLK th Hold tim CLK High or Low Data after LE Units M ax. M in. M ax. fclock Clock Frequency tw Pulse duration VCC = 3.3V 0.3V MHz ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted, see Figures 1 thru 4) Parame te rs fmax tpd ten tdis ten tdis From (Input) To (Output) A or B LE CLK OEAB OEAB OEBA OEBA B or A VCC = 1.2V M in. M ax. VCC = 1.5V 0.1V M in. M ax. VCC = 1.8V 0.15V M in. M ax. A or B B B A A VCC = 2.5V 0.2V M in. M ax. 180 3.9 4.6 4.9 4.6 5.0 5.0 4.2 VCC = 3.3V 0.3V M in. M ax. 180 2.8 3.3 3.5 3.3 3.7 3.6 3.2 Units MHz ns Operating Characteristics, T A= 25C Parame te rs Cpd Power Dissipation Capacitance Te s t Conditions Outputs Enabled Outputs Disabled Vcc = 1.8V 0.2V Vcc = 2.5V 0.2V Vcc = 3.3V 0.3V Typical Typical Typical TBD TBD TBD TBD TBD TBD CL = 0pF, f = 10 MHz Units pF Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 5 PXXXX 04/24/00 ADVANCE INFORMATION PI74AVC+16501 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.2V AND 1.5V 0.1V 2xVCC S1 2 From Output Under Test CL = 15pF Open GND 2 (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH O pen 2 x VCC GND Load Circuit VCC Timing VCC/2 Input tW 0V tsu VCC VCC/2 Input th VCC/2 0V VCC Data VCC/2 Input VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH Output VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V VCC /2 VCC tPLZ VCC VCC/2 VOL +0.1V VOL tPHZ VCC/2 VOH -0.1V VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 6 PXXXX 04/24/00 ADVANCE INFORMATION PI74AVC+16501 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V 2xVCC 12 k S1 From Output Under Test CL = 30 15pF Open GND 2 1 k (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH O pen 2 x VCC GND Load Circuit VCC Timing VCC/2 Input tW 0V tsu VCC VCC/2 Input th VCC/2 0V VCC Data VCC/2 Input VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH Output VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V VCC /2 VCC tPLZ VCC VCC/2 VOL +0.1V 0.15V VOL tPHZ VCC/2 VOH -0.1V 0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 2. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 7 PXXXX 04/24/00 ADVANCE INFORMATION PI74AVC+16501 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V 2xVCC 500 2 From Output Under Test CL =30 15pF S1 Open GND 500 2 (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH O pen 2 x VCC GND Load Circuit VCC Timing VCC/2 Input tW 0V tsu VCC VCC/2 Input th VCC/2 0V VCC Data VCC/2 Input VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH Output VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V VCC /2 VCC tPLZ VCC VCC/2 VOL +0.15V VOL tPHZ VCC/2 VOH -0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 3. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 8 PXXXX 04/24/00 ADVANCE INFORMATION PI74AVC+16501 18-Bit Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 3.3V 0.3V 2xVCC 500 2 S1 From Output Under Test CL = 30 15pF Open GND 500 2 (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH O pen 2 x VCC GND Load Circuit VCC Timing VCC/2 Input tW 0V tsu VCC VCC/2 Input th VCC/2 0V VCC Data VCC/2 Input VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH Output VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V VCC /2 VCC tPLZ VCC VCC/2 VOL +0.1V 0.3V VOL tPHZ VCC/2 VOH -0.1V 0.3V VOH 0V Voltage Waveforms Enable and Disable Times Figure 4. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 9 PXXXX 04/24/00