1PXXXX 04/24/00
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PI74AVC+16501
18-Bit Universal Bus Transceiver
With 3-State Outputs
Logic Block Diagram
Product Description
Pericom Semiconductors PI74AVC+series of logic circuits are
produced using the Companys advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 18-bit PI74AVC+16501 univeral bus transceiver is designed for
1.65V to 3.6V VCC operation.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latch Enable (LEAB and LEBA), and CLOCK (CLKAB
and CLKBA) inputs. For A-to-B data flow, the device operates in
the transparent mode when LEAB is HIGH. When LEAB is LOW,
the A data is latched if CLKAB is held at a high or low logic level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. When OEAB is HIGH, the
outputs are active. When OEAB is LOW, the outputs are in the high-
impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA,
and CLKBA. The Output Enables are complementary (OEAB is
active HIGH and OEBA is active LOW)
To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pull-up resistor and
OEAB should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Product Features
•PI74AVC+16501 is designed for low voltage operation,
VCC = 1.65V to 3.6V
•True ±24mA Balanced Drive @ 3.3V
•IOFF supports partial Power-down operation
•3.6V I/O Tolerant inputs and outputs
•All outputs contain noise reduction circuitry reducing
noise without speed degradation
•Industrial operation at 40°C to +85°C
•Packages available:
 56-pin 240 mil wide plastic TSSOP (A)
 56-pin 173 mil wide plastic TVSOP (K)
ADVANCE INFORMATION
PI74AVC+16501
18-Bit Universal Bus Transceiver
2PXXXX 04/24/00
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ADVANCE INFORMATION
Pin Name Description
OE Output Enable Input (Active HIGH)
LE Latch Enable (Active HIGH)
CLK Clock Input (Active HIGH)
Ax Data I/O
Bx Data I/O
GND Ground
VCC Power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
Product Pin Description Truth Table(1)
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, CLKBA.
Output level before the indicated steady-state input
conditions were established, provided that CLKAB is HIGH
before LEAB goes LOW.
§ Output level before the indicated steady-state input
conditions were established.
Product Pin Configuration
56-Pin
A,K
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
stupnI
BtuptuO
BAEOBAELBAKLCA
LX X X Z
HH X L L
HH X H H
HL LL
HL HH
HL H X B0
HL L X §0B
PI74AVC+16501
18-Bit Universal Bus Transceiver
3PXXXX 04/24/00
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ADVANCE INFORMATION
Recommended Operating Conditions(1)
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
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LI
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CC
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CC
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I
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CC
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tnerructuptuolevel-woL
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Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other con-
ditions above those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
extended periods may affect reliability.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, VCC ............................................................................................ 0.5V to +4.6V
Input voltage range, VI.................................................................................................... 0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ............................................................ 0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) ........................................................................................ 0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) ............................................................................ 50mA
Output clamp current, IOK (VO <0) ...................................................................... 50mA
Continuous output current, IO...................................................................................................... ±50mA
Continuous current through each VCC or GND .................................................±100mA
Package thermal impedance, θJA(3): package A .................................................... 64°C/W
package K ................................................... 48°C/W
Storage Temperature range, Tstg .............................................................................. 65°C to 150°C
Notes:
1. Input & output negative-voltage ratings may be exceeded if the input and output current rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
PI74AVC+16501
18-Bit Universal Bus Transceiver
4PXXXX 04/24/00
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ADVANCE INFORMATION
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)1(
V
CC
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V
HO
I
HO
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CC
V2.0
V
I
HO
6=m VA
HI
V70.1=V56.12.1
I
HO
21=m VA
HI
V7.1=V3.257.1
I
HO
42=m VA
HI
V2=V30.2
V
LO
I
LO
001= µAV6.3otV56.12.0
I
LO
6=m VA
HI
V75.0=V56.154.0
I
LO
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HI
V7.0= V3.255.0
I
LO
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HI
V8.0=V357.0
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V3.38
Note: Typical values are measured at TA = 25°C.
DC Electrical Characteristics (Over Operating Range, TA = 40°C +85°C)
PI74AVC+16501
18-Bit Universal Bus Transceiver
5PXXXX 04/24/00
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ADVANCE INFORMATION
V
CC
V2.1= V
CC
V5.1=
V1.0±
V
CC
V8.1=
V51.0±
V
CC
V5.2=
V2.0±
V
CC
V3.3=
V3.0± stinU
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Timing Requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Operating Characteristics, TA= 25°C
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PI74AVC+16501
18-Bit Universal Bus Transceiver
6PXXXX 04/24/00
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ADVANCE INFORMATION
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V AND 1.5V ± 0.1V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 1. Load Circuit and Voltage Waveforms
2Ω
2Ω2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
tPLH tPHL 0V
Output
VOH
VOL
VCC/2 VCC/2
VCC/2
VCC
VCC/2
Input
tW
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
V
CC
/2
V
CC
V
CC
/2
0V
V
CC
0V
Timing
Input V
CC
/2
Voltage Waveforms
Setup and Hold Times
PI74AVC+16501
18-Bit Universal Bus Transceiver
7PXXXX 04/24/00
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ADVANCE INFORMATION
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 2. Load Circuit and Voltage Waveforms
2Ω
2Ω2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
tPLH tPHL 0V
Output
VOH
VOL
VCC/2 VCC/2
VCC/2
VCC
VCC/2
Input
tW
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
V
CC
/2
V
CC
V
CC
/2
0V
V
CC
0V
Timing
Input V
CC
/2
Voltage Waveforms
Setup and Hold Times
1 kΩ
1 kΩ
0.15V
0.15V
30
PI74AVC+16501
18-Bit Universal Bus Transceiver
8PXXXX 04/24/00
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ADVANCE INFORMATION
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 3. Load Circuit and Voltage Waveforms
2Ω
2Ω2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.15V
–0.15V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
tPLH tPHL 0V
Output
VOH
VOL
VCC/2 VCC/2
VCC/2
VCC
VCC/2
Input
tW
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
V
CC
/2
V
CC
V
CC
/2
0V
V
CC
0V
Timing
Input V
CC
/2
Voltage Waveforms
Setup and Hold Times
500Ω
500Ω
30
PI74AVC+16501
18-Bit Universal Bus Transceiver
9PXXXX 04/24/00
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ADVANCE INFORMATION
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ± 0.3V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 4. Load Circuit and Voltage Waveforms
2Ω
2Ω2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
tPLH tPHL 0V
Output
VOH
VOL
VCC/2 VCC/2
VCC/2
VCC
VCC/2
Input
tW
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
V
CC
/2
V
CC
V
CC
/2
0V
V
CC
0V
Timing
Input V
CC
/2
Voltage Waveforms
Setup and Hold Times
500Ω
500Ω
0.3V
0.3V
30