TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low rDS(on):
0.1 Ω Typ (Full H-Bridge)
0.22 Ω Typ (Triple Half H-Bridge)
D
Pulsed Current:
12 A Per Channel (Full H-Bridge)
6 A Per Channel (Triple Half H-Bridge)
D
Matched Sense Transistors for Class A-B
Linear Operation
D
Fast Commutation Speed
description
The TPIC1533 is a monolithic power DMOS array
that consists of ten electrically isolated N-channel
enhancement-mode power DMOS transistors, four
of which are configured as a full H-bridge and six as a triple half H-bridge. The lower stage of the full H-bridge
is provided with an integrated sense-FET to allow biasing of the bridge in class A-B operation.
The TPIC1533 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of –40°C to 125°C.
schematic
Q4B
GATE1A
17
OUTPUT1
19
GATE1B
21
Q2A 8
Q2B
6
4
D1 D2
GATE3A
22
OUTPUT3
1
GATE3B
3
D3
GATE4A
Q4A
18
OUTPUT4
11
GATE4B
7
GATE2A
OUTPUT2
GATE2B
Q3B
Q3A
15 10
Q1B
Q1A
Q5B
GATE5A
Q5A
16
OUTPUT5
13
GATE5B
9
14, 24
12
2, 23
GND
SOURCE
VDD1 VDD2 VDD3
Q2C
20
5
6V
GATE2C
SENSE D4 D5 D6
NOTES: A. Terminals 2 and 23 must be externally connected.
B. Terminals 14 and 24 must be externally connected.
C. No output may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT3
GND
GATE3B
GATE2B
SENSE
OUTPUT2
GATE4B
GATE2A
GATE5B
VDD2
OUTPUT4
SOURCE
VDD3
GND
GATE3A
GATE1B
GATE2C
OUTPUT1
GATE4A
GATE1A
GATE5A
VDD1
VDD3
OUTPUT5
DW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings, TC = 25°C (unless otherwise noted)†
Supply-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source-to-GND voltage (Q3A, Q4A, Q5A) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, VGS (Q1A, Q1B, Q2A, Q2B) ±20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, VGS (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) –0.3 V to 20 V. . . . . . . . . . . . . . . . . .
Gate-to-source voltage, VGS (Q2C) –0.7 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous gate-to-source zener-diode current (Q2C) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed gate-to-source zener-diode current (Q2C) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) 3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current (Q2C) 15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) 3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1.5 A. . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q2C) 15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, Imax (Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) 12 A. . . . . . . . .
Pulsed drain current, each output, Imax (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)
(see Note 1 and Figure 25) 6 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, Imax (Q2C) (see Note 1) 60 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation, TC = 70°C (see Note 2 and Figures 24 and 25) 2.86 W. . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%
2. Package mounted in intimate contact with infinite heatsink.
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V
V
GS(th)
Gate-to-source threshold voltage ID = 1 mA,
See Figure 5 VDS = VGS, 1.4 1.7 2.1 V
GS(th)
g
ID = 5 mA, VDS = VGS 1.65 1.95 2.35
VGS(th)match Gate-to-source threshold voltage matching ID = 5 mA, VDS = VGS 75 mV
V(BR) Reverse drain-to-GND breakdown voltage Drain-to-GND current = 250 µA
(D1, D2) 20 V
V(BR)GS Gate-to-source breakdown voltage, Q2C IGS = 100 µA 6 V
V(BR)SG Source-to-gate breakdown voltage, Q2C ISG = 100 µA 0.7 V
VDS(on) Drain-to-source on-state voltage ID = 3 A,
See Notes 3 and 4 VGS = 10 V, 0.3 0.36 V
VFForward on-state voltage, GND-to-VDD1,
GND-to-VDD2 ID = 3 A (D1, D2)
See Notes 3 and 4 1.8 V
VF(SD)
Forward on state voltage source to drain
IS = 2 A, VGS = 0,
See Notes 3 and 4 and Figure 19 1 1.2
V
V
F(SD)
For
w
ard
on
-
state
v
oltage
,
so
u
rce
-
to
-
drain
IS = 3 A, VGS = 0,
See Notes 3 and 4 and Figure 19 1.1 1.3
V
IDSS
Zero gate voltage drain current
V
DS
= 16 V, TC = 25°C 0.05 1
µA
I
DSS
Zero
-
gate
-v
oltage
drain
c
u
rrent
DS ,
VGS = 0 TC = 125°C 0.5 10 µ
A
IGSSF Forward gate current, drain short-circuited
to source VGS = 16 V, VDS = 0 10 100 nA
IGSSR Reverse gate current, drain short-circuited
to source VSG = 16 V, VDS = 0 10 100 nA
Ilk
Leakage current, V
DD1
-to-GND, V
DD2
-to-GND,
VDGND =16V
TC = 25°C 0.05 1
µA
I
lkg
g,
DD1 ,DD2 ,
gate shorted to source
V
DGND =
16
V
TC = 125°C 0.5 10 µ
A
VGS = 10 V,
I
D
= 2 A, TC = 25°C 0.1 0.12
rDS( )
Static drain to source on state resistance
D,
See Notes 3 and 4
and Figure 9 TC = 125°C 0.14 0.18
Ω
r
DS(on)
Static
drain
-
to
-
so
u
rce
on
-
state
resistance
VGS = 10 V,
I
D
= 3 A, TC = 25°C 0.1 0.12
Ω
D,
See Notes 3 and 4
and Figures 7 and 9 TC = 125°C 0.14 0.18
gf
Forward transconductance
VDS = 14 V, ID = 1 A,
See Notes 3 and 4 1.5 2.5
S
g
fs
For
w
ard
transcond
u
ctance
VDS = 14 V, ID = 1.5 A,
See Notes 3 and 4 and Figure 13 2 3
S
Ciss Short-circuit input capacitance, common source 240
Coss Short-circuit output capacitance, common
source VDS = 14 V,
f=1MHz
VGS = 0,
See Figure 17
170 pF
Crss Short-circuit reverse transfer capacitance,
common source
f
=
1
MHz
,
See
Figure
17
130
αsSense-FET drain current ratio VDS = 6 V,
ID(Q2C) = 40 µA100 150 200
NOTES: 3. Technique should limit TJ – TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
trr Reverse-recovery time IS = 1.5 A,
VDS 14 V
VGS = 0,
di/dt 100 A/µs
70 ns
QRR Total diode charge
V
DS =
14
V
,
See Figures 1 and 23
di/dt
=
100
A/
µs, 90 nC
trr Reverse-recovery time IS = 2 A, VGS = 0, 75 ns
QRR Total diode charge
S
VDS = 14V,
GS
di/dt = 100 A/µs, 110 nC
resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(on) T urn-on delay time 20
td(off) Turn-off delay time V
DD
= 14 V, R
L
= 9.1 Ω,t
en
= 10 ns, 30
ns
trRise time
DD ,
tdis = 10 ns,
L,
See Figure 3
en ,
15
ns
tfFall time 25
QgTotal gate charge
V14V
I15A
V10V
5.6 7
Qgs(th) Threshold gate-to-source charge VDS = 14 V,
See Figure 4
ID = 1.5 A, VGS = 10 V, 0.8 1 nC
Qgd Gate-to-drain charge
See
Figure
4
1.4 1.7
LDInternal drain inductance 5
nH
LSInternal source inductance 5
nH
RgInternal gate resistance 0.25 Ω
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V
V
GS(th)
Gate-to-source threshold voltage ID = 1 mA,
See Figure 6 VDS = VGS, 1.4 1.7 2.1 V
GS(th)
g
ID = 5 mA, VDS = VGS 1.65 1.95 2.35
V(BR) Reverse drain-to-GND breakdown voltage Drain-to-GND current = 250 µA (D3) 20 V
VDS(on) Drain-to-source on-state voltage ID = 2 A,
See Notes 3 and 4 VGS = 10 V, 0.44 0.6 V
VFForward on-state voltage, GND-to-VDD3 ID = 1.5 A (D3)
See Notes 3 and 4 1.7 V
VF(SD)
Forward on state voltage source to drain
IS = 1.5 A, VGS = 0
See Notes 3 and 4 and Figure 20 1 1.2
V
V
F(SD)
For
w
ard
on
-
state
v
oltage
,
so
u
rce
-
to
-
drain
IS = 2 A, VGS = 0
See Notes 3 and 4 and Figure 20 1.1 1.3
V
VFForward on-state voltage, GND-to-GATE 3A,
GND-to-GATE4A, GND-to GATE5A ID = 1 mA (D4, D5, D6) 0.5 V
IDSS
Zero gate voltage drain current
V
DS
= 16 V, TC = 25°C 0.05 1
µA
I
DSS
Zero
-
gate
-v
oltage
drain
c
u
rrent
DS ,
VGS = 0 TC = 125°C 0.5 10 µ
A
IGSSF Forward gate current, drain short-circuited to
source VGS = 16 V, VDS = 0 10 100 nA
Ilk
Leakage current, V
DD3
-to-GND, gate shorted to
VDGND =16V
TC = 25°C 0.05 1
µA
I
lkg
g,
DD3 ,g
source
V
DGND =
16
V
TC = 125°C 0.5 10 µ
A
VGS = 10 V,
I
D
= 1.5 A, TC = 25°C 0.22 0.3
rDS( )
Static drain to source on state resistance
D,
See Notes 3 and 4
and Figures 8 and 10 TC = 125°C 0.32 0.4
Ω
r
DS(on)
Static
drain
-
to
-
so
u
rce
on
-
state
resistance
VGS = 10 V,
I
D
= 2 A, TC = 25°C 0.22 0.3
Ω
D,
See Notes 3 and 4
and Figure 10 TC = 125°C 0.32 0.4
gf
Forward transconductance
VDS = 14 V, ID = 500 mA,
See Notes 3 and 4 0.3 0.8
S
g
fs
For
w
ard
transcond
u
ctance
VDS = 14 V, ID = 750 mA,
See Notes 3 and 4 and Figure 14 0.4 0.9
S
Ciss Short-circuit input capacitance, common source 120
Coss Short-circuit output capacitance, common source VDS = 14 V, VGS = 0, 140 p
F
Crss Short-circuit reverse transfer capacitance,
common source f = 1 MHz, See Figure 18 80
F
NOTES: 3: Technique should limit TJ – TC to 10°C maximum.
4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
trr Reverse-recovery time IS = 750 mA,
VDS 14 V
VGS = 0,
di/dt 100 A/µs
45 ns
QRR Total diode charge
V
DS =
14
V
,
See Figures 2 and 23
di/dt
=
100
A/
µs, 45 nC
trr Reverse-recovery time IS = 2 A, VGS = 0, 70 ns
QRR Total diode charge
S
VDS = 14 V,
GS
di/dt = 100 A/µs100 nC
resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(on) T urn-on delay time 18
td(off) Turn-off delay time V
DD
= 14 V, R
L
= 18.7 Ω,t
en
= 10 ns, 25
ns
trRise time
DD ,
tdis = 10 ns,
L,
See Figure 3
en ,
13
ns
tfFall time 20
QgTotal gate charge
V14V
I 750 A
V10V
2.3 3.1
Qgs(th) Threshold gate-to-source charge VDS = 14 V,
See Figure 4
ID = 750 mA, VGS = 10 V, 0.4 0.5 nC
Qgd Gate-to-drain charge
See
Figure
4
0.6 0.9
LDInternal drain inductance 5
nH
LSInternal source inductance 5
nH
RgInternal gate resistance 0.25 Ω
thermal resistance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance See Notes 5 and 8 90
RθJB Junction-to-board thermal resistance See Notes 6 and 8 38 °C/W
RθJP Junction-to-pin thermal resistance See Notes 7 and 8 28
NOTES: 5. Package mounted on a FR4 printed-circuit board with no heat sink.
6. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.
7. Package mounted in intimate contact with infinite heat sink.
8. All outputs with equal power
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
IRM†
25% of IRM†
Reverse di/dt = 100 A/µs
trr(SD)
†IRM = maximum recovery current
– Source-to-Drain Diode Current – AIS
2
1
0
– 1
– 2
– 3
– 4
– 5
Time – ns
0 100 200 300 400 500
VDS = 14 V
VGS = 0
TJ = 25°C
Q1A and Q2A
3
Shaded Area = QRR
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
IRM†
25% of IRM†
Reverse di/dt = 100 A/µs
trr(SD)
†IRM = maximum recovery current
– Source-to-Drain Diode Current – AIS
2
1
0
– 1
– 2
– 3
– 4
– 5
Time – ns
0 100 200 300 400 500
VDS = 14 V
VGS = 0
TJ = 25°C
Q3A, Q4A, and Q5A
3
Shaded Area = QRR
Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
Pulse Generator
50 Ω
Rgen
50 Ω
VGS
VDD = 14 V
DUT
VDS
TEST CIRCUIT
VDD
VDS(on)
tf
td(on) tr
td(off)
VOLTAGE WAVEFORMS
VGS
VDS
RL
CL 30 pF
(see Note A)
tdis
ten
10 V
0 V
NOTE A: CL includes probe and jig capacitance.
Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
10 V
VOLTAGE WAVEFORM
Qgd
Time
Gate Voltage
VGS
12-V
Battery 0.2 µF50 kΩ0.3 µF
Current
Regulator
DUT
Same Type
as DUT
0IG = 100 µA
IG Current-
Sampling Resistor ID Current-
Sampling Resistor
VDD = 14 V
TEST CIRCUIT
Qgs(th)
VDS
Qg
Figure 4. Gate-Charge Test Circuit and Voltage Waveform
TYPICAL CHARACTERISTICS
Figure 5
1.5
1
0.5
0
2
2.5
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– Gate-to-Source Threshold Voltage – V
VGS(th)
TJ – Junction Temperature – °C
– 40 – 20 0 20 40 60 80 100 120 140 160
ID = 5 mA
ID = 1 mA
VDS = VGS
Q1A, Q1B, Q2A, Q2B
ID = 100 µA
Figure 6
1.5
1
0.5
0
2
2.5
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– Gate-to-Source Threshold Voltage – V
VGS(th)
TJ – Junction Temperature – °C
– 40 – 20 0 20 40 60 80 100 120 140 160
ID = 100 µA
ID = 1 mA
VDS = VGS
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
ID = 10 mA
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 7
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
– Static Drain-to-Source
rDS(on)
On-State Resistance – Ω
TJ – Junction Temperature – °C
0.150
0.100
0.050
0
– 40 – 20 0 20 40 60 80 100 120 140 160
ID = 3 A
Q1A, Q1B, Q2A, Q2B
VGS = 10 V
0.125
0.075
0.025
VGS = 12 V
0.175
VGS = 15 V
Figure 8
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
– Static Drain-to-Source
rDS(on)
On-State Resistance – Ω
TJ – Junction Temperature – °C
0.6
0.4
0.2
0
– 40 – 20 0 20 40 60 80 100 120 140 160
ID = 1.5 A
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
VGS = 10 V
0.5
0.3
0.1
VGS = 15 V
VGS = 12 V
Figure 9
10
0.1
0.01
0.01 0.1 1 10 100
VGS = 10 V
VGS = 15 V
– Static Drain-to-SourcerDS(on)
On-State Resistance – Ω
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE
vs
DRAIN CURRENT
VGS = 12 V
ID – Drain Current – A
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
Figure 10
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE
vs
DRAIN CURRENT
– Static Drain-to-SourcerDS(on)
On-State Resistance – Ω
ID – Drain Current – A
0.2
0.18
0.14
0.12
0.1
0.26
0.16
0.1 1 10
0.24
0.22
VGS = 10 V
VGS = 16 V
VGS = 12 V
TJ = 25°C
Q3A, Q3B, Q4A
Q4B, Q5A, Q5B
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 11
4
2
00123456
– Drain Current – A
6
8
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
78910
I
D
V
DS – Drain-to-Source Voltage – V
12 ∆VGS = 0.5 V
(unless otherwise noted)
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
VGS = 3 V
VGS = 4 V
Figure 12
5
4
2
1
0
3
0123456
– Drain Current – A
6
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
78910
I
D
V
GS – Gate-to-Source Voltage – V
VGS = 3 V
VGS = 4 V
VGS = 5 V
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
Figure 13
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
Percentage of Units – %
gfs – Forward Transconductance – S
40
20
10
0
2.2
2.4
2.6
2.9
30
2.3
2.5
2.7
2.8
3
3.2
3.1
3.3
TJ = 25°C
ID = 1.5 A
Q1A, Q1B, Q2A, Q2B
Total Number of Units = 1200
VDS = 14 V
Figure 14
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
Percentage of Units – %
gfs – Forward Transconductance – S
40
20
10
0
0.86
0.88
0.90
0.93
30
0.87
0.89
0.91
0.92
0.94
TJ = 25°C
ID = 750 mA
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
Total Number of Units = 1200
VDS = 14 V
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 15
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
3
2
1
0
4
5
6
1234
8
7
56
0
I
D
– Drain Current – A
VGS – Gate-to-Source Voltage – V
TJ = –40°C
TJ = 25°C
10
9TJ = 125°C
Q1A, Q1B, Q2A, Q2B
12
11
Figure 16
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
3
2
1
0
4
5
6
123456
0
I
D
– Drain Current – A
VGS – Gate-to-Source Voltage – V
7
TJ = 125°C
TJ = –40°C
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
8
Figure 17
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
Capacitance – pF
VDS – Drain-to-Source Voltage – V
200
50 024681012
350
450
500
14 16
400
300
250
150
100
Crss
VGS = 0
f = 1 MHz
TJ = 25°C
Q1A, Q1B,
Q2A, Q2B
Ciss
Coss
Figure 18
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
Capacitance – pF
VDS – Drain-to-Source Voltage – V
230
140
110
20 024681012
260
290
320
14 16 18 20
200
170
80
50
Coss
Crss
Ciss
VGS = 0
f = 1 MHz
TJ = 25°C
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 19
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
ISD– Source-to-Drain Diode Current – A
VSD – Source-to-Drain Voltage – V
0.6
0.4
0.2
0.1
1
0.1 10
1
TJ = –40°C
TJ = 25°C
TJ = 75°C
TJ = 150°C
TJ = 125°C
6
4
2
10 VGS = 0
Q1A, Q1B, Q2A, Q2B
Figure 20
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
ISD– Source-to-Drain Diode Current – A
VSD – Source-to-Drain Voltage – V
0.6
0.4
0.2
0.1
1
0.1 10
1
TJ = –40°C
TJ = 25°C
TJ = 75°C
TJ = 150°C
TJ = 125°C
6
4
2
10 VGS = 0
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
Figure 21
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
VDS – Drain-to-Source Voltage – V
Qg – Gate Charge – nC
012345678
6
4
2
0
8
10
12
VGS – Gate-to-Source Voltage – V
VDD = 10 V
ID = 1.5 A
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
See Figure 4
14
16
6
4
2
0
8
10
12
14
16
910
V
DD = 12 V
VDD = 14 V
VDD = 12 V
Figure 22
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
VDS – Drain-to-Source Voltage – V
Qg – Gate Charge – nC
VGS – Gate-to-Source Voltage – V
0
16
VDD = 14 V
VDD = 12 V
VDD = 10 V
VDD = 12 V
VDD = 14 V
ID = 750 mA
TJ = 25°C
See Figure 4
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
14
12
10
8
6
4
2
0
16
14
12
10
8
6
4
2
0
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
0
80
0 100 200 300
40
20
60
100
400 500
trr – Reverse Recovery Time – ns
Reverse di/dt – A/µs
REVERSE RECOVERY TIME
vs
REVERSE di/dt
IS = 1.5 A
Q1A, Q1B
TJ = 25°C
See Figures 1 and 2
IS = 750 mA
Q3A, Q4A, Q5A
Figure 23
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
10 ms¶
10
1
0.1
100
0.1 1 10 100
1 ms†
500 µs†
VDS – Drain-to-Source Voltage – V
– Maximum Drain Current – A
ÁÁ
ÁÁ
ID
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
θJA‡
DC Conditions
θJC§
TC = 25°C
Q1A, Q1B, Q2A, Q2B
Figure 24
10
1
0.1
100
0.1 1 10 100
VDS – Drain-to-Source Voltage – V
– Maximum Drain Current – A
ÁÁ
ÁÁ
ID
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
θJA‡
θJC§
TC = 25°C
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
DC Conditions
10 ms¶
1 ms†
500 µs
Figure 25
†Less than 10% duty cycle
‡Device is mounted on FR4 printed-circuit board with no heat sink.
§Device is mounted in intimate contact with infinite heat sink.
¶Less than 2% duty cycle
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
†Device mounted on 24 in2, 4 layer FR4 printed-circuit board with no heat sink.
tw – Pulse Duration – s
100
0.0001 0.001
10
1
0.1 0.01 0.1 1 10
tw
tc
ID
0
d = 0.5
d = 0.1
d = 0.02
Single Pulse
d = 0.05
JBθC/W
°
DW PACKAGE†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
– Junction-to-Board Thermal Resistance –
R
DC Conditions
d = 0.01
d = 0.2
100
NOTE A: ZθB(t) = r(t) RθJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 26
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