INTEGRATED CIRCUITS DATA SHEET 74LVC07A Hex buffer with open-drain outputs Product specification Supersedes data of 2003 Feb 25 2003 Nov 11 Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A FEATURES DESCRIPTION * 5 V tolerant inputs and outputs (open drain) for interfacing with 5 V logic * Direct interface with TTL levels The 74LVC07A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 to 5 V environment. * Inputs accept voltages up to 5 V The 74LVC07A provides six non-inverting buffers. * Wide supply voltage range from 1.65 to 5.5 V * CMOS low power consumption * Complies with JEDEC standard no. 8-1A The outputs of the 74LVC07A are open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL PARAMETER tPLZ/tPZL propagation delay nA to nY CI input capacitance CPD power dissipation capacitance per gate CONDITIONS TYPICAL CL = 50 pF; VCC = 3.3 V 2.2 5.0 pF VCC = 3.3 V; notes 1 and 2 6.0 pF Note 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC FUNCTION TABLE See note 1. INPUT OUTPUT nA nY L L H Z Note 1. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 2003 Nov 11 2 UNIT ns Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC07AD -40 to +125 C 14 SO14 plastic SOT108-1 74LVC07APW -40 to +125 C 14 TSSOP14 plastic SOT402-1 74LVC07ABQ -40 to +125 C 14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1A data input 2 1Y data output 3 2A data input 4 2Y data output 5 3A data input 6 3Y data output 7 GND ground (0 V) 8 4Y data output 9 4A data input 10 5Y data output 11 5A data input 12 6Y data output 13 6A data input 14 VCC supply voltage handbook, halfpage handbook, halfpage 1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 2Y 4 3A 1A VCC 1 14 1Y 2 13 6A 2A 3 12 6Y 11 5A 2Y 4 11 5A 5 10 5Y 3A 5 10 5Y 3Y 6 9 4A 3Y 6 9 4A GND 7 8 4Y 07 MNA531 Top view GND(1) 7 8 GND 4Y MBL760 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO14 and TSSOP14. 2003 Nov 11 Fig.2 Pin configuration DHVQFN14. 3 Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A handbook, halfpage 1 1A 1Y 2 3 2A 2Y 4 5 3A 3Y 6 9 4A 4Y 8 handbook, halfpage 1A 2A 3A 4A 11 5A 5Y 10 5A 13 6A 6Y 12 6A MNA535 2 3 1 4 5 1 6 9 1 8 11 1 10 13 1 12 1Y 2Y 3Y 4Y 5Y 6Y Fig.4 IEC logic symbol. Y A GND MNA533 Fig.5 Logic diagram (one gate). 2003 Nov 11 1 MNA534 Fig.3 Logic symbol. handbook, halfpage 1 4 Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage 0 5.5 V Tamb operating ambient temperature tr, tf input rise and fall ratios active mode high-impedance mode 0 5.5 V -40 +125 C VCC = 1.65 to 2.7 V 0 20 ns/V VCC = 2.7 to 5.5 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC supply voltage CONDITIONS MIN. MAX. UNIT -0.5 +6.5 V IIK input diode current VI < 0 - -50 mA VI input voltage note 1 -0.5 +6.5 V IOK output clamping diode current VO < 0 - -50 mA VO output voltage IO output source or sink current active mode; note 1 -0.5 +6.5 V high-impedance mode; note 1 -0.5 +6.5 V VO = 0 to VCC - 50 mA ICC, IGND VCC or GND current - 100 mA Tstg storage temperature -65 +150 C Ptot power dissipation - 500 mW Tamb = -40 to +125 C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO14 packages: above 70 C derate linearly with 8 mW/K. For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K. 2003 Nov 11 5 Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = -40 to +85 C; note 1 VIH VIL HIGH-level input voltage LOW-level input voltage 1.65 to 1.95 VCC - - V 2.3 to 2.7 1.7 - - V 2.7 to 3.6 2.0 - - V 4.5 to 5.5 0.7 x VCC - - V 1.65 to 1.95 - - GND V - - 0.7 V V 2.3 to 2.7 VOL LOW-level output voltage 2.7 to 3.6 - - 0.8 4.5 to 5.5 - - 0.30 x VCC V VI = VIH or VIL IO = 100 A 1.65 to 5.5 - - 0.20 V IO = 4 mA 1.65 - - 0.45 V IO = 8 mA 2.3 - - 0.3 V IO = 12 mA 2.7 - - 0.4 V IO = 24 mA 3.0 - - 0.55 V IO = 32 mA 4.5 - - 0.55 V ILI input leakage current VI = 5.5 V or GND 1.65 to 5.5 - 0.1 5 A IOZ output leakage current VI = VIH; VO = 5.5 V or GND 1.65 to 5.5 - 0.1 10 A Ioff power-off leakage current VI or VO = 5.5 V 0.0 - 0.1 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 - 0.1 10 A ICC additional quiescent supply VI = VCC - 0.6 V; current per input pin IO = 0 2.3 to 5.5 - 5 500 A 2003 Nov 11 6 Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = -40 to +125 C VIH VIL VOL HIGH-level input voltage - - V 2.3 to 2.7 1.7 - - V 2.7 to 3.6 2.0 - - V 4.5 to 5.5 0.7 x VCC - - V GND V 1.65 to 1.95 - LOW-level input voltage LOW-level output voltage 1.65 to 1.95 VCC - 2.3 to 2.7 - - 0.7 V 2.7 to 3.6 - - 0.8 V 4.5 to 5.5 - - 0.30 x VCC V IO = 100 A 1.65 to 5.5 - - 0.20 V IO = 4 mA 1.65 - - 0.45 V IO = 8 mA 2.3 - - 0.3 V IO = 12 mA 2.7 - - 0.4 V IO = 24 mA 3.0 - - 0.55 V IO = 32 mA 4.5 - - 0.55 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 1.65 to 5.5 - - 5 A IOZ output leakage current VI = VIH; VO = 5.5 V or GND 1.65 to 5.5 - - 10 A Ioff power-off leakage current VI or VO = 5.5 V 0.0 - - 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 - - 10 A ICC additional quiescent supply VI = VCC - 0.6 V; current per input pin IO = 0 2.3 to 5.5 - - 500 A Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2003 Nov 11 7 Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A AC CHARACTERISTICS GND = 0 V; tr = tf 2 ns for VCC 2.7 V and tr = tf 2.5 ns for VCC 2.7 V. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = -40 to +85 C; note 1 tPLZ/tPZL propagation delay nA to nY see Figs 6 and 7 1.65 to 1.95 - 2.5 - ns 2.3 to 2.7 0.5 1.6 2.8 ns 2.7 0.5 2.4 3.3 ns 3.0 to 3.6 0.5 2.2 3.6 ns 4.5 to 5.5 0.5 1.6 2.6 ns 1.65 to 1.95 - - - ns 2.3 to 2.7 0.5 - 3.5 ns 2.7 0.5 - 4.5 ns 3.0 to 3.6 0.5 - 4.5 ns 4.5 to 5.5 0.5 - 3.5 ns Tamb = -40 to +125 C tPLZ/tPZL propagation delay nA to nY see Figs 6 and 7 Note 1. All typical values are measured at Tamb = 25 C and at VCC = 1.8, 2.5, 2.7, 3.3 and 5.0 V, respectively. 2003 Nov 11 8 Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A AC WAVEFORMS VI handbook, full pagewidth VM nA input GND t PLZ t PZL VCC nY output VM VX VOL MNA528 VCC VM VX <2.7 V 0.5 x VCC VOL + 0.15 V 2.7 to 3.6 V 1.5 V VOL + 0.3 V 4.5 to 5.5 V 0.5 x VCC VOL + 0.3 V Fig.6 The input nA to output nY propagation delays. Vext handbook, full pagewidth VCC PULSE GENERATOR VI RL VO D.U.T. CL RT MNA530 VCC Vext VI CL RL 1.65 to 1.95 V 2 x VCC VCC 30 pF 1 k 2.3 to 2.7 V 2 x VCC VCC 30 pF 500 2.7 V 6V 2.7 V 50 pF 500 3.0 to 3.6 V 6V 2.7 V 50 pF 500 4.5 to 5.5 V 2 x VCC VCC 50 pF 500 Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2003 Nov 11 9 RL Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 2003 Nov 11 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 10 o 8 0o Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 2003 Nov 11 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 11 o Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- 2003 Nov 11 12 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Hex buffer with open-drain outputs 74LVC07A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Nov 11 13 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA75 (c) Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/03/pp14 Date of release: 2003 Nov 11 Document order number: 9397 750 11931