MX25U51245G
MX25U51245G
1.8V, 512M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Support DTR (Double Transfer Rate) Mode
• 8/16/32/64 byte Wrap-Around Read Mode
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MX25U51245G
Rev. 1.1, June 29, 2017P/N: PM2244
Contents
1. FEATURES ..............................................................................................................................................................5
2. GENERAL DESCRIPTION ..................................................................................................................................... 7
Table 1. Read performance Comparison ....................................................................................................7
3. PIN CONFIGURATIONS ......................................................................................................................................... 8
Table 2. PIN DESCRIPTION .......................................................................................................................8
4. BLOCK DIAGRAM ................................................................................................................................................... 9
5. MEMORY ORGANIZATION ................................................................................................................................... 10
6. DATA PROTECTION .............................................................................................................................................. 11
6-1. Block lock protection ................................................................................................................................ 12
Table 3. Protected Area Sizes ...................................................................................................................12
6-2. Additional 8K-bit secured OTP ................................................................................................................ 13
Table 4. 8K-bit Secured OTP Denition ....................................................................................................13
7. DEVICE OPERATION ............................................................................................................................................ 14
7-1. 256Mb Address Protocol .......................................................................................................................... 16
7-2. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 19
8. COMMAND SET .................................................................................................................................................... 20
Table 5. Read/Write Array Commands ...................................................................................................... 20
Table 6. Read/Write Array Commands (4 Byte Address Command Set) ..................................................21
Table 7. Register/Setting Commands ........................................................................................................22
Table 8. ID/Security Commands ................................................................................................................23
Table 9. Reset Commands ........................................................................................................................ 24
9. REGISTER DESCRIPTION .................................................................................................................................... 25
9-1. Status Register ........................................................................................................................................ 25
9-2. Conguration Register ............................................................................................................................. 26
9-3. Security Register ..................................................................................................................................... 28
Table 10. Security Register Denition .......................................................................................................28
10. COMMAND DESCRIPTION ................................................................................................................................. 29
10-1. Write Enable (WREN) .............................................................................................................................. 29
10-2. Write Disable (WRDI) ............................................................................................................................... 30
10-3. Read Identication (RDID) ....................................................................................................................... 31
10-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 32
10-5. Read Electronic Manufacturer ID & Device ID (REMS) ........................................................................... 34
10-6. QPI ID Read (QPIID) ............................................................................................................................... 35
Table 11. ID Denitions ............................................................................................................................35
10-7. Read Status Register (RDSR) ................................................................................................................. 36
10-8. Read Conguration Register (RDCR) ...................................................................................................... 37
10-9. Write Status Register (WRSR) ................................................................................................................. 40
Table 12. Protection Modes .......................................................................................................................41
10-10. Enter 4-byte mode (EN4B) ...................................................................................................................... 44
10-11. Exit 4-byte mode (EX4B) ......................................................................................................................... 44
10-12. Read Data Bytes (READ) ........................................................................................................................ 45
10-13. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 46
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10-14. Dual Output Read Mode (DREAD) .......................................................................................................... 47
10-15. 2 x I/O Read Mode (2READ) ................................................................................................................... 48
10-16. Quad Read Mode (QREAD) .................................................................................................................... 49
10-17. 4 x I/O Read Mode (4READ) ................................................................................................................... 50
10-18. 4 x I/O Double Transfer Rate Read Mode (4DTRD) ................................................................................ 52
10-19. Preamble Bit ........................................................................................................................................... 54
10-20. 4 Byte Address Command Set ................................................................................................................. 58
10-21. Performance Enhance Mode ................................................................................................................... 63
10-22. Burst Read ............................................................................................................................................... 68
10-23. Fast Boot ................................................................................................................................................. 69
10-24. Sector Erase (SE) .................................................................................................................................... 72
10-25. Block Erase (BE32K) ............................................................................................................................... 73
10-26. Block Erase (BE) ..................................................................................................................................... 74
10-27. Chip Erase (CE) ....................................................................................................................................... 75
10-28. Page Program (PP) ................................................................................................................................. 76
10-29. 4 x I/O Page Program (4PP) .................................................................................................................... 78
10-30. Deep Power-down (DP) ........................................................................................................................... 79
10-31. Enter Secured OTP (ENSO) .................................................................................................................... 80
10-32. Exit Secured OTP (EXSO) ....................................................................................................................... 80
10-33. Read Security Register (RDSCUR) ......................................................................................................... 80
10-34. Write Security Register (WRSCUR) ......................................................................................................... 80
10-35. Write Protection Selection (WPSEL) ........................................................................................................ 81
10-36. Advanced Sector Protection .................................................................................................................... 83
10-37. Program Suspend and Erase Suspend ................................................................................................... 91
Table 13. Acceptable Commands During Suspend .................................................................................. 92
10-38. Program Resume and Erase Resume ..................................................................................................... 93
10-39. No Operation (NOP) ................................................................................................................................ 94
10-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 94
11. Serial Flash Discoverable Parameter (SFDP)................................................................................................... 96
11-1. Read SFDP Mode (RDSFDP) .................................................................................................................. 96
Table 14. Signature and Parameter Identication Data Values ................................................................ 97
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables ..............................................................99
Table 16. Parameter Table (1): 4-Byte Instruction Tables .......................................................................106
Table 17. Parameter Table (2): Macronix Flash Parameter Tables .........................................................108
12. RESET................................................................................................................................................................ 110
Table 18. Reset Timing-(Power On) ........................................................................................................ 110
Table 19. Reset Timing-(Other Operation) .............................................................................................. 110
13. POWER-ON STATE ........................................................................................................................................... 111
14. ELECTRICAL SPECIFICATIONS ...................................................................................................................... 112
Table 20. ABSOLUTE MAXIMUM RATINGS .......................................................................................... 112
Table 21. CAPACITANCE TA = 25°C, f = 1.0 MHz .................................................................................. 112
Table 22. DC CHARACTERISTICS ........................................................................................................ 114
Table 23. AC CHARACTERISTICS ......................................................................................................... 115
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15. OPERATING CONDITIONS ............................................................................................................................... 117
Table 24. Power-Up/Down Voltage and Timing ...................................................................................... 119
15-1. INITIAL DELIVERY STATE .....................................................................................................................119
16. ERASE AND PROGRAMMING PERFORMANCE ............................................................................................ 120
17. DATA RETENTION ............................................................................................................................................ 120
18. LATCH-UP CHARACTERISTICS ...................................................................................................................... 120
19. ORDERING INFORMATION .............................................................................................................................. 121
20. PART NAME DESCRIPTION ............................................................................................................................. 122
21. PACKAGE INFORMATION ................................................................................................................................ 123
22. REVISION HISTORY ......................................................................................................................................... 126
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MX25U51245G
Rev. 1.1, June 29, 2017P/N: PM2244
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
• 512Mb: 536,870,912 x 1 bit structure or 268,435,456 x 2 bits (two I/O mode) structure or 134,217,728 x 4 bits (four
I/O mode) structure
• Protocol Support
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Fast read for SPI mode
- Support fast clock frequency up to 166MHz
- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions
- Support DTR (Double Transfer Rate) Mode
- Congurable dummy cycle number for fast read operation
• Quad Peripheral Interface (QPI) available
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits dene the size of the area to be protected against program and erase
instructions
- Advanced sector protection function
• Additional 8K bit security OTP
- Features unique identier
- Factory locked identiable, and customer lockable
• Command Reset
• Program/Erase Suspend and Resume operation
• Electronic Identication
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
1.8V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)
FLASH MEMORY
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HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• RESET#
- Hardware Reset pin
• RESET#/SIO3 * or NC/SIO3 *
- Hardware Reset pin or Serial input & Output for 4 x I/O read mode
or
- No Connection or Serial input & Output for 4 x I/O read mode
* Depends on part number options
• PACKAGE
- 16-pin SOP (300mil)
- 24-Ball BGA (5x5 ball array)
- 8-land WSON (8x6mm 3.4 x 4.3EP)
- All devices are RoHS Compliant and Halogen-free
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2. GENERAL DESCRIPTION
MX25U51245G is 512Mb bits Serial NOR Flash memory, which is congured as 67,108,864 x 8 internally. When
it is in two or four I/O mode, the structure becomes 268,435,456 bits x 2 or 134,217,728 bits x 4. MX25U51245G
feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in
single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO).
Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0
pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U51245G
MXSMIO (Serial Multi I/O)
provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25U51245G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Read performance Comparison
Numbers of
Dummy Cycles
Fast Read
(MHz)
Dual Output
Fast Read
(MHz)
Quad Output
Fast Read
(MHz)
Dual IO
Fast Read
(MHz)
Quad IO
Fast Read
(MHz)
Quad I/O DT
Read
(MHz)
4 - - - 84* 70 42
6 133 133 104 104 84* 52*
8133* 133* 133* 133 104 66
10 166 166 166 166 133 100
Note: * mean default status
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3. PIN CONFIGURATIONS
16-PIN SOP (300mil)
1
2
3
4
5
6
7
8
NC/SIO3
VCC
RESET#
NC
DNU
DNU
CS#
SO/SIO1
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
DNU
DNU
GND
WP#/SIO2
Table 2. PIN DESCRIPTION
SYMBOL DESCRIPTION
CS# Chip Select
SCLK Clock Input
RESET# Hardware Reset Pin Active low (Note1)
SI/SIO0
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SO/SIO1
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
WP#/SIO2
Write Protection Active Low or Serial
Data Input & Output (for 4xI/O read
mode)
NC/SIO3 * No Connection or Serial Data Input &
Output (for 4xI/O read mode)
RESET#/SIO3 *
Hardware Reset Pin Active low or
Serial Data Input & Output (for 4xI/O
read mode)
VCC Power Supply
GND Ground
NC No Connection
DNU Do Not Use (It may connect to
internal signal inside)
24-Ball BGA (5x5 ball array)
RESET#
VCC
WP#/SIO2
NC/SIO3
NC
NC
GND
SI/SIO0
NC
NC
SCLK
SO/SIO1
NC
DNU
NC
NC
NC
NC
NC
NC NC
NC
NC
CS#
A
B
C
D
E
1 2 3 4 5
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
VCC
RESET#/SIO3
SCLK
SI/SIO0
* Depends on part number options.
Note:
1. The pin of RESET#, RESET#/SIO3 or WP#/SIO2
will remain internal pull up function while this pin is
not physically connected in system conguration.
However, the internal pull up function will be
disabled if the system has physical connection to
RESET#, RESET#/SIO3 or WP#/SIO2 pin.
8-WSON (8x6mm 3.4 x 4.3EP)
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4. BLOCK DIAGRAM
Address
Generator
Memory Array
Y-Decoder
X-Decoder
Data
Register
SRAM
Buffer
SI/SIO0
SO/SIO1
SIO2 *
SIO3 *
WP# *
HOLD# *
RESET# *
CS#
SCLK Clock Generator
State
Machine
Mode
Logic
Sense
Amplifier
HV
Generator
Output
Buffer
* Depends on part number options.
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5. MEMORY ORGANIZATION
Block(32K-byte) Sector
16383 3FFF000h 3FFFFFFh
…
16376 3FF8000h 3FF8FFFh
16375 3FF7000h 3FF7FFFh
…
16368 3FF0000h 3FF0FFFh
16367 3FEF000h 3FEFFFFh
…
16360 3FE8000h 3FE8FFFh
16359 3FE7000h 3FE7FFFh
…
16352 3FE0000h 3FE0FFFh
16351 3FDF000h 3FDFFFFh
…
16344 3FD8000h 3FD8FFFh
16343 3FD7000h 3FD7FFFh
…
…
……………
…
……………
16336 3FD0000h 3FD0FFFh
47 002F000h 002FFFFh
…
40 0028000h 0028FFFh
39 027000h 0027FFFh
…
32 0020000h 0020FFFh
31 001F000h 001FFFFh
…
24 0018000h 0018FFFh
23 0017000h 0017FFFh
…
16 0010000h 0010FFFh
15 000F000h 000FFFFh
…
80008000h 0008FFFh
70007000h 0007FFFh
…
………………
………………
00000000h 0000FFFh
2044
2043
2042
Address Range
2047
2046
2045
individual block
lock/unlock unit:64K-byte
individual 16 sectors
lock/unlock unit:4K-byte
individual block
lock/unlock unit:64K-byte
individual block
lock/unlock unit:64K-byte
Block(64K-byte)
1021
2
1
0
1023
1022
0
5
4
3
2
1
individual 16 sectors
lock/unlock unit:4K-byte
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6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specic command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the ash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic
Signature command (RES), Erase/Program suspend command, Erase/Program resume command and softreset
command.
• Advanced Security Features: there are some protection and security features which protect content from
inadvertent write and hostile access.
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6-1. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area denition is shown as "Table 3. Protected Area Sizes", the protected
areas are more exible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status
Register Write Protect bit.
- In four I/O and QPI mode, the feature of HPM will be disabled.
Table 3. Protected Area Sizes
Protected Area Sizes (T/B bit = 1)
Protected Area Sizes (T/B bit = 0)
Status bit Protect Level
BP3 BP2 BP1 BP0 512Mb
0 0 0 0 0 (none)
0 0 0 1 1 (1 block, protected block 1023rd)
0 0 1 0 2 (2 blocks, protected block 1022nd~1023rd)
0 0 1 1 3 (4 blocks, protected block 1020th~1023rd)
0 1 0 0 4 (8 blocks, protected block 1016th~1023rd)
0 1 0 1 5 (16 blocks, protected block 1008th~1023rd)
0 1 1 0 6 (32 blocks, protected block 992nd~1023rd)
0 1 1 1 7 (64 blocks, protected block 960th~1023rd)
1 0 0 0 8 (128 blocks, protected block 896th~1023rd)
1 0 0 1 9 (256 blocks, protected block 768th~1023rd)
1 0 1 0 10 (512 blocks, protected block 512nd~1023rd)
1 0 1 1 11 (1024 blocks, protected all)
1 1 0 0 12 (1024 blocks, protected all)
1 1 0 1 13 (1024 blocks, protected all)
1 1 1 0 14 (1024 blocks, protected all)
1 1 1 1 15 (1024 blocks, protected all)
Status bit Protect Level
BP3 BP2 BP1 BP0 512Mb
0 0 0 0 0 (none)
0 0 0 1 1 (1 block, protected block 0th)
0 0 1 0 2 (2 blocks, protected block 0th~1st)
0 0 1 1 3 (4 blocks, protected block 0th~3rd)
0 1 0 0 4 (8 blocks, protected block 0th~7th)
0 1 0 1 5 (16 blocks, protected block 0th~15th)
0 1 1 0 6 (32 blocks, protected block 0th~31st)
0 1 1 1 7 (64 blocks, protected block 0th~63rd)
1 0 0 0 8 (128 blocks, protected block 0th~127th)
1 0 0 1 9 (256 blocks, protected block 0th~255th)
1 0 1 0 10 (512 blocks, protected block 0th~511th)
1 0 1 1 11 (1024 blocks, protected all)
1 1 0 0 12 (1024 blocks, protected all)
1 1 0 1 13 (1024 blocks, protected all)
1 1 1 0 14 (1024 blocks, protected all)
1 1 1 1 15 (1024 blocks, protected all)
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Rev. 1.1, June 29, 2017P/N: PM2244
6-2. Additional 8K-bit secured OTP
The secured OTP for unique identier: to provide 8K-bit one-time program area for setting device unique serial
number. Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 8K-bit secured OTP by entering secured OTP mode (with Enter Security OTP command), and
going through normal program procedure, and then exiting secured OTP mode by writing Exit Security OTP
command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 10. Security Register Denition" for
security register bit denition and "Table 4. 8K-bit Secured OTP Denition" for address range denition.
- Note: Once lock-down by factory or customer, the corresponding range cannot be changed any more. While in
secured OTP mode, array access is not allowed.
Table 4. 8K-bit Secured OTP Denition
Address range Size Lock-down
xxx000~xxx1FF 4096-bit Determined by Customer
xxx200~xxx3FF 4096-bit Determined by Factory
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7. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.
3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode
until next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ/READ4B, FAST_READ/FAST_READ4B,
2READ/2READ4B, DREAD/DREAD4B, 4READ/4READ4B, QREAD/QREAD4B, RDSFDP, RES, REMS,
QPIID, RDDPB, RDSPB, RDLR, RDEAR, RDFBR, RDCR, the shifted-in instruction sequence is followed by a
data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions:
WREN, WRDI, WRSR, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, PP/PP4B, 4PP/4PP4B, DP, ENSO, EXSO,
WRSCUR, EN4B, EX4B, WPSEL, GBLK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO
the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is
neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
SCLK
MSB
CPHA shift in shift out
SI
0
1
CPOL
0(Serial mode 0)
(Serial mode 3) 1
SO
SCLK
MSB
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Figure 2. Serial Input Timing
Figure 3. Output Timing (STR mode)
SCLK
SI
CS#
MSB
SO
tDVCH
High-Z
LSB
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
LSB
ADDR.LSB IN
tSHQZ
tCH
tCL
tCLQX
tCLQV
tCLQX
tCLQV
SCLK
SO
CS#
SI
Figure 4. Output Timing (DTR mode)
ADDR.LSB IN
tSHQZ
tCH
tCL
tCLQX
tCLQV
LSB
tCLQX
tCLQV
SCLK
SO
CS#
SI
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7-1. 256Mb Address Protocol
The original 24 bit address protocol of Serial NOR Flash can only access density size below 128Mb. For the
memory device of 256Mb and above, the 32bit address is requested for access higher memory size. The
MX25U51245G provides three different methods to access the whole density:
(1) Command entry 4-byte address mode:
Issue Enter 4-Byte mode command to set up the 4BYTE bit in Conguration Register bit. After 4BYTE bit has
been set, the number of address cycle become 32-bit.
(2) Extended Address Register (EAR):
congure the memory device into four 128Mb segments to select which one is active through the EAR<0-1>.
(3) 4-byte Address Command Set:
When issuing 4-byte address command set, 4-byte address (A31-A0) is requested after the instruction code.
Please note that it is not necessary to issue EN4B command before issuing any of 4-byte command set.
Extended Address Register
The device provides an 8-bit volatile register for extended Address Register: it identies the extended address (A31~A24)
above 128Mb density by using original 3-byte address.
Extended Address Register (EAR)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A31 A30 A29 A28 A27 A26 A25 A24
For the MX25U51245G the A31 to A26 are Don't Care. During EAR, reading these bits will read as 0. The bit 0 is
default as "0".
Enter 4-Byte Address Mode
In 4-byte Address mode, all instructions are 32-bits address clock cycles. By using EN4B and EX4B to enable and
disable the 4-byte address mode.
When 4-byte address mode is enabled, the EAR<0-1> becomes "don't care" for all instructions requiring 4-byte
address. The EAR function will be disabled when 4-byte mode is enabled.
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When under EAR mode, Read, Program, Erase operates in the selected segment by using 3-byte address mode.
For the read operation, the whole array data can be continually read out with one command. Data output starts from
the selected top or bottom 128Mb, but it can cross the boundary. When the last byte of the segment is reached,
the next byte (in a continuous reading) is the rst byte of the next segment. However, the EAR (Extended Address
Register) value does not change. The random access reading can only be operated in the selected segment.
The Chip erase command will erase the whole chip and is not limited by EAR selected segment. However, the
sector erase ,block erase , program operation are limited in selected segment and will not cross the boundary.
Figure 5. Write EAR Register (WREAR) Sequence (SPI Mode)
Figure 6. Write EAR Register (WREAR) Sequence (QPI Mode)
21 3456789 10 11 12 13 14 15
EAR In
0
MSB
SCLK
SI
CS#
SO
C5h
High-Z
command
Mode 3
Mode 0
765 4321 0
SCLK
SIO[3:0]
CS#
2 310
H0 L0
Command EAR in
Mode 3 Mode 3
Mode 0 Mode 0
C5h
03FFFFFFh
02FFFFFFh
02000000h
03000000h
EAR<1-0>= 11
EAR<1-0>= 10
01FFFFFFh
00FFFFFFh
00000000h
01000000h
EAR<1-0>= 01
EAR<1-0>= 00
Figure 7. EAR Operation Segments
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Figure 8. Read EAR (RDEAR) Sequence (SPI Mode)
Figure 9. Read EAR (RDEAR) Sequence (QPI Mode)
21 3456789 10 11 12 13 14 15
command
0
76543210
EAR Out EAR Out
High-Z
MSB
76543210
MSB
7
SCLK
SI
CS#
SO
C8h
Mode 3
Mode 0
0 1 3
SCLK
SIO[3:0]
CS#
C8h
2
H0 L0
MSB LSB
4 5 7
H0 L0
6
H0 L0 H0 L0
EAR Out EAR Out EAR Out EAR Out
Mode 3
Mode 0
N
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7-2. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial NOR Flash by providing the Quad I/O interface
in command cycles, address cycles and as well as data output cycles.
Enable QPI mode
By issuing command EQIO(35h), the QPI mode is enabled.
Figure 10. Enable QPI Sequence
MODE 3
SCLK
SIO0
CS#
MODE 0
234567
35h
SIO[3:1]
0 1
Reset QPI (RSTQIO)
To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device
returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).
Note:
For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.
Figure 11. Reset QPI Mode
SCLK
SIO[3:0]
CS#
F5h
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8. COMMAND SET
Table 5. Read/Write Array Commands
Command
(byte)
READ
(normal read)
FAST READ
(fast read data)
2READ
(2 x I/O read
command)
DREAD
(1I 2O read)
4READ
(4 I/O read start
from bottom
128Mb)
QREAD
(1I 4O read)
4DTRD (Quad
I/O DT Read)
Mode SPI SPI SPI SPI SPI/QPI SPI SPI/QPI
Address Bytes 3/4 3/4 3/4 3/4 3/4 3/4 3/4
1st byte 03 (hex) 0B (hex) BB (hex) 3B (hex) EB (hex) 6B (hex) ED (hex)
2nd byte ADD1 ADD1 ADD1 ADD1 ADD1 ADD1 ADD1
3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 ADD2 ADD2
4th byte ADD3 ADD3 ADD3 ADD3 ADD3 ADD3 ADD3
5th byte Dummy* Dummy* Dummy* Dummy* Dummy* Dummy*
Data Cycles
Action
n bytes read
out until CS#
goes high
n bytes read
out until CS#
goes high
n bytes read
out by 2 x I/O
until CS# goes
high
n bytes read
out by Dual
output until
CS# goes high
Quad I/O read
for bottom
128Mb with 6
dummy cycles
n bytes read
out by Quad
output until
CS# goes high
n bytes read
out (Double
Transfer Rate)
by 4xI/O until
CS# goes high
Command
(byte)
PP
(page program)
4PP
(quad page
program)
SE
(sector erase)
BE 32K
(block erase
32KB)
BE
(block erase
64KB)
CE
(chip erase)
Mode SPI/QPI SPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI
Address Bytes 3/4 3/4 3/4 3/4 3/4 0
1st byte 02 (hex) 38 (hex) 20 (hex) 52 (hex) D8 (hex) 60 or C7 (hex)
2nd byte ADD1 ADD1 ADD1 ADD1
3rd byte ADD2 ADD2 ADD2 ADD2
4th byte ADD3 ADD3 ADD3 ADD3
5th byte
Data Cycles 1-256 1-256
Action
to program the
selected page
quad input to
program the
selected page
to erase the
selected sector
to erase the
selected 32K
block
to erase the
selected block
to erase whole
chip
* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in conguration register.
Notes 2: Please note the address cycles above are based on 3-byte address mode. After enter 4-byte address
mode by EN4B command, the address cycles will be increased to 4byte.
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Table 6. Read/Write Array Commands (4 Byte Address Command Set)
Command
(byte) PP4B 4PP4B
BE4B
(block erase
64KB)
BE32K4B
(block erase
32KB)
SE4B
(Sector erase
4KB)
Mode SPI/QPI SPI SPI/QPI SPI/QPI SPI/QPI
Address Bytes 4 4 4 4 4
1st byte 12 (hex) 3E (hex) DC (hex) 5C (hex) 21 (hex)
2nd byte ADD1 ADD1 ADD1 ADD1 ADD1
3rd byte ADD2 ADD2 ADD2 ADD2 ADD2
4th byte ADD3 ADD3 ADD3 ADD3 ADD3
5th byte ADD4 ADD4 ADD4 ADD4 ADD4
6th byte
Data Cycles 1-256 1-256
Action
to program the
selected page
with 4byte
address
Quad input to
program the
selected page
with 4byte
address
to erase the
selected (64KB)
block with
4byte address
to erase the
selected (32KB)
block with
4byte address
to erase the
selected (4KB)
sector with
4byte address
Command
(byte) READ4B FAST
READ4B 2READ4B DREAD4B 4READ4B QREAD4B
4DTRD4B
(Quad I/O DT
Read)
Mode SPI SPI SPI SPI SPI/QPI SPI SPI/QPI
Address Bytes 4 4 4 4 4 4 4
1st byte 13 (hex) 0C (hex) BC (hex) 3C (hex) EC (hex) 6C (hex) EE (hex)
2nd byte ADD1 ADD1 ADD1 ADD1 ADD1 ADD1 ADD1
3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 ADD2 ADD2
4th byte ADD3 ADD3 ADD3 ADD3 ADD3 ADD3 ADD3
5th byte ADD4 ADD4 ADD4 ADD4 ADD4 ADD4 ADD4
6th byte Dummy* Dummy* Dummy* Dummy* Dummy* Dummy*
Data Cycles
Action
read data byte
by
4 byte address
read data byte
by
4 byte address
read data byte
by 2 x I/O with
4 byte address
Read data byte
by Dual Output
with 4 byte
address
read data byte
by 4 x I/O with
4 byte address
Read data
byte by Quad
Output with 4
byte address
n bytes read
out (Double
Transfer Rate)
by 4xI/O until
CS# goes high
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Table 7. Register/Setting Commands
Command
(byte)
WREN
(write enable)
WRDI
(write disable)
RDSR
(read status
register)
RDCR
(read
conguration
register)
WRSR
(write status/
conguration
register)
RDEAR
(read extended
address
register)
WREAR
(write extended
address
register)
Mode SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI
1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) C8 (hex) C5 (hex)
2nd byte Values
3rd byte Values
4th byte
5th byte
Data Cycles 1-2 1
Action
sets the (WEL)
write enable
latch bit
resets the
(WEL) write
enable latch bit
to read out the
values of the
status register
to read out the
values of the
conguration
register
to write new
values of the
status/
conguration
register
read extended
address
register
write extended
address
register
Command
(byte)
WPSEL
(Write Protect
Selection)
EQIO
(Enable QPI)
RSTQIO
(Reset QPI)
EN4B
(enter 4-byte
mode)
EX4B
(exit 4-byte
mode)
PGM/ERS
Suspend
(Suspends
Program/
Erase)
PGM/ERS
Resume
(Resumes
Program/
Erase)
Mode SPI SPI QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI
1st byte 68 (hex) 35 (hex) F5 (hex) B7 (hex) E9 (hex) B0 (hex) 30 (hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
to enter and
enable individal
block protect
mode
Entering the
QPI mode
Exiting the QPI
mode
to enter 4-byte
mode and set
4BYTE bit as
"1"
to exit 4-byte
mode and clear
4BYTE bit to
be "0"
Command
(byte)
DP
(Deep power
down)
RDP (Release
from deep
power down)
SBL
(Set Burst
Length)
RDFBR
(read fast boot
register)
WRFBR
(write fast boot
register)
ESFBR
(erase fast
boot register)
Mode SPI/QPI SPI/QPI SPI/QPI SPI SPI SPI
1st byte B9 (hex) AB (hex) C0 (hex) 16(hex) 17(hex) 18(hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles 1-4 4
Action
enters deep
power down
mode
release from
deep power
down mode
to set Burst
length