The ARG81800 includes all the control and protection circuitry
to produce a PWM regulator with ±1.5% output voltage
accuracy, with ultralow quiescent current to enable “keepalive”
supply operation with minimal current draw from the supply
during very light load regulation. There are two versions of
the ARG81800 available, 500 mA and 1 A, so the physical size
of the power components can be optimized for lower current
systems, thus reducing PCB area and saving cost. PWM
switching frequency can be programmed over a wide range to
balance efficiency, component sizing, and EMC performance.
If VIN decays and the duty cycle reaches its maximum, the
ARG81800 will automatically fold back its PWM frequency
to extend the duty cycle and maintain VOUT.
The ARG81800 employs Low-Power (LP) mode to maintain
the output voltage at no load or very light load conditions while
drawing only micro-amps from VIN. The ARG81800 includes a
PWM/AUTO control pin so the system can dynamically force
either PWM or AUTO mode by setting this pin high or low,
respectively.
If the SYNCIN pin is driven by an external clock, the ARG81800
will be forced into PWM mode and synchronize to the incoming
clock. The ARG81800 adds frequency dithering to the SYNCIN
clock to reduce EMI/EMC. The ARG81800 provides a CLKOUT
pin so “downstream” regulators can be easily interleaved and
dithered via their synchronization inputs.
ARG81800-DS
MCO-0000676
• Automotive AEC-Q100 qualified
• Input operating voltage range: 3.5 to 36 V
□Withstands surge voltages to 40 V for load dump
• Low-Power (LP) mode—draws just 8 µA from VIN while
maintaining 3.3 or 5.0 VOUT
• AUTO mode allows automatic transition between PWM
and LP mode based on load current
• Programmable PWM frequency (fSW): 250 kHz to 2.4 MHz
• PWM frequency dithering and controlled switch node
slew rate reduce EMI/EMC signature
• CLKOUT allows interleaving and dithering of “downstream”
regulators using their synchronization inputs
• Interleaving minimizes input filter capacitor requirement
and improves EMI/EMC performance
• Synchronization of PWM frequency to external clock on
SYNCIN pin
• Adjustable output voltage: ±1.5% accuracy over
operating temperature range (‒40°C to 150°C)
• Maximized duty cycle at low VIN improves dropout
• Soft recovery from dropout condition
• Adjustable soft-start time controls inrush current to
accommodate a wide range of output capacitances
• External compensation provides flexibility to tune the
system for maximum stability or fast transient response
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
PACKAGE:
Typical Application Diagram
ARG81800
BOOT
COMP
PWM/AUTO
SYNC
IN
EN
GND
VIN
PGND
FB
BIAS
CLK
OUT
PGOOD
SW
FSET
SS VREG
3.5 to 36 V
1 µF
14.3 kΩ
22 nF 4.7 µF
2.2 nF 68 pF
40.2 kΩ
3.3 V, 1 A
0.1 µF
95.3 kΩ
3.3 µH
301 kΩ
4.7 pF 10 kΩ
20 µF
f
SW
= 2.15 MHz
Continued on next page...
FEATURES AND BENEFITS DESCRIPTION
Not to scale
Continued on next page...
June 11, 2019
20-pin, 4 mm × 4 mm,
QFN (ES) with wettable flank
APPLICATIONS
• Infotainment
• Navigation Systems
• Instrument Clusters
• Audio Systems
• ADAS Applications
• Battery Powered Systems
• Industrial Systems
• Network and Telecom
• Home Audio
• HVAC Systems
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
SELECTION GUIDE
Part Number DC Current Package Packing Lead Frame
ARG81800KESJSR 1 A 20-pin wettable flank QFN
package with thermal pad 6000 pieces per 13-inch reel 100% matte tin
ARG81800KESJSR-1 0.5 A
*Contact Allegro for additional packing options
The ARG81800 has external compensation, so it can be tuned to
satisfy a wide range of system goals with many different external
components over a wide range of PWM frequencies. The ARG81800
includes adjustable soft start to minimize inrush current. The
ARG81800 monitors the feedback voltage to provide an open-drain
power good signal. The Enable input can command an ultra-low
current shutdown mode with VOUT = 0 V.
Extensive protection features of the ARG81800 include pulse-by-
pulse current limit, hiccup mode short circuit protection, BOOT
open/short voltage protection, VIN undervoltage lockout, VOUT
overvoltage protection, and thermal shutdown. The ARG81800 is
supplied in a low profile 20-pin wettable flank QFN package (suffix
“ES”) with exposed power pad.
• Enable input can command ultralow 1 µA shutdown current
• Open-drain PGOOD output with rising delay
• Pre-bias startup allows quick restart and avoids reset
• Overvoltage, pulse-by-pulse current limit, hiccup mode short
circuit, and thermal protections
• Robust FMEA: pin open/short and component faults
FEATURES AND BENEFITS DESCRIPTION
Table of Contents
Features and Benefits ........................................................... 1
Description .......................................................................... 1
Package ............................................................................. 1
Typical Application Diagram ................................................... 1
Selection Guide ................................................................... 2
Absolute Maximum Ratings ................................................... 3
Thermal Characteristics ........................................................ 3
Functional Block Diagram ..................................................... 4
Pinout Diagram and Terminal List ........................................... 5
Electrical Characteristics ....................................................... 6
Typical Performance Characteristics ......................................11
Functional Description ........................................................ 16
Overview ....................................................................... 16
Reference Voltage .......................................................... 16
Internal VREG Regulator ................................................. 16
Oscillator/Switching Frequency ......................................... 16
Synchronization (SYNCIN) and Clock Output (CLKOUT) ........ 16
Frequency Dither ............................................................ 16
Transconductance Error Amplifier ..................................... 17
Compensation Components ............................................. 18
Power MOSFETs ............................................................ 18
BOOT Regulator ............................................................. 18
Soft Start (Startup) and Inrush Current Control ................... 18
Slope Compensation ....................................................... 18
Pre-Biased Startup .......................................................... 19
Dropout ......................................................................... 19
PGOOD Output .............................................................. 19
Current Sense Amplifier ................................................... 19
Pulse-Width Modulation (PWM) ........................................ 19
Low-Power (LP) Mode ..................................................... 20
Protection Features ......................................................... 21
Undervoltage Lockout (UVLO) ...................................... 21
Pulse-by-Pulse Peak Current Protection (PCP) ............... 21
Overcurrent Protection (OCP) and Hiccup Mode ............. 21
BOOT Capacitor Protection .......................................... 22
Asynchronous Diode Protection .................................... 22
Overvoltage Protection (OVP) ....................................... 22
SW Pin Protection ....................................................... 22
Pin-to-Ground and Pin-to-Short Protections .................... 22
Thermal Shutdown (TSD) ............................................. 23
Application Information ....................................................... 25
Design and Component Selection ..................................... 25
PWM Switching Frequency (RFSET) ............................... 25
Output Voltage Setting ................................................. 25
Output Inductor (LO) .................................................... 26
Output Capacitors (CO) ................................................ 27
Output Voltage Ripple – Ultralow-IQ LP Mode ................. 28
Input Capacitors .......................................................... 29
Bootstrap Capacitor ..................................................... 29
Soft Start and Hiccup Mode Timing (CSS) ....................... 29
Compensation Components (RZ, CZ, and CP) ................. 30
Power Stage ............................................................... 30
Error Amplifier ............................................................. 31
A Generalized Tuning Procedure ................................... 32
Power Dissipation and Thermal Calculations ......................... 34
EMI/EMC Aware PCB Design .............................................. 36
Typical Reference Designs .................................................. 39
Package Outline Drawing .................................................... 41
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ABSOLUTE MAXIMUM RATINGS [1]
Characteristic Symbol Notes Rating Unit
VIN, EN, SS, BIAS Pin Voltage –0.3 to 40 V
SW Pin Voltage VSW
Continuous –0.3 [2] to VIN + 0.3 V
VIN ≤ 36 V, t < 50 ns –1.0 to VIN + 2 V
BOOT Pin Voltage VBOOT
Continuous VSW – 0.3 to VSW + 5.5 V
t < 1 ms VSW – 0.3 to VSW + 7.0 V
All Other Pin Voltages –0.3 to 5.5 V
Operating Junction Temperature TJ(max) –40 to 150 °C
Storage Temperature Tstg –55 to 150 °C
[1] Stresses beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated
conditions for extended periods may aect device reliability.
[2] This voltage is a function of temperature.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions [3] Value Unit
Package Thermal Resistance RqJA On 4-layer PCB based on JEDEC standard 37 °C/W
[3] Additional thermal information available on the Allegro website.
SPECIFICATIONS
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
BG
VIN
BOOT
VIN
Protection & Fault
PWM/LP
Control
Logic
HD
3.55 V UVLO
3.3V
LDO
Bias
0.8V
VREG
REGOK
EN t
DIS
2.5V
BIAS Bias
Bias >3.15V
REGOK
EN
LD
BOOT REG
BOOT FAULT
LD
Current
Sense Amp
G
cs
EN
d
REGOK
UVLO
EN
d
OOV
OOV
TSD
VREG
SW
PGND
FBUV
Slope
Compensation
Ramp
Offset
FSET PLL+
Dither
Div 2 or 4
Start up or Hiccup
or Drop out
FB
t
off
CLK
FAULT
SYNC
IN
PWM
COMP
MODE
FB
0.8 V
LXGND
SC
FBOV
VINLX
SC
0.88 V
0.74 V
FBUV
FBOV
Error Amp
COMP
Overcurrent
Clamp
OCL
OCL
LP
Clamp
MODE
0.804 V
SLEEP
LP Comparator
MODE
GND
PGOOD
SS
Hiccup, Dropout,
Stop-Start Recovery,
Fault, Startup
Delay
SLEEP
500mΩ
210mΩ
SS
Offset
SS
FB
PWM/
AUTO
OSC
CLK
OUT
T/2
MODE
VREG
5.4V
21.6 V
Functional Block Diagram
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Terminal List Table
Number Name Function
1 BOOT
This pin supplies the drive for the high-side N-channel MOSFET. Connect a 100 nF
ceramic capacitor from BOOT to SW. Do not add any external resistor in series with the
boot capacitor.
2, 3 SW Regulator switch node output pins. Connect these pins to power inductor with a short
and wide PCB trace.
4 SS Soft start pin. Connect a capacitor, CSS, from this pin to GND to set the start-up time.
This capacitor also determines the hiccup period during overcurrent.
5 EN
This pin must be set high to enable the ARG81800. If this pin is low, the ARG81800 will
enter a very low current shutdown or “SLEEP” state where VOUT = 0 V. If the application
does not require a logic level controlled enable, then this pin can be tied directly to VIN.
Also, if this pin is floated, it will be pulled low by an internal pull-down resistor, disabling
the ARG81800.
6 CLKOUT
Dual function pin: Clock output pin for “Master” operation. Frequency dithering is added
to this pin when the ARG81800 is operating as a Master. For “Follower” operation, this
pin must be connected to VREG so dithering will not be internally added to SYNCIN; see
Figure 1. The exact functionality of this pin is dependent on the status of the SYNCIN
pin; see Table 1 and the description for SYNCIN for additional details.
7 SYNCIN
Triple function pin: High/Low/ExtClock. Setting this pin high sets CLKOUT to the internal
oscillator frequency (fSW) but with 180 degree phase shift. Setting this pin low disables
the CLKOUT pin. Applying an external clock (at fSYNC) forces PWM mode, synchronizes
the PWM switching frequency to the external clock plus dithering, and sets CLKOUT to
the same dithered frequency but with 180 degree phase shift. See Table 1 for details.
8 GND Analog ground pin.
9 FSET Frequency setting pin. A resistor, RFSET, from this pin to GND sets the oscillator
frequency, fSW.
10 PWM/
AUTO
Mode selection pin. High/Low. Setting this pin high forces PWM mode. Setting this pin
low allows AUTO changeover between PWM and LP mode based on the load current.
11 COMP Output of the error amplifier and compensation node for the current mode control loop.
Connect a series RC network from this pin to GND for loop compensation.
12 PGOOD
Power good output signal. PGOOD is an open-drain output that remains low until
the output has achieved regulation for tdPG(SU). The PGOOD pull-up resistor can be
connected to VREG, VOUT, or any external supply voltage less than 5.5 V. PGOOD will
pull low if the output voltage (VOUT) is out of range.
13 BIAS Connect this pin to the output of the regulator. This pin supplies the internal circuitry
when the voltage level is high enough.
14 FB Feedback (negative) input to the error amplifier. Connect a resistor divider from the
regulators output, VOUT, to this pin to program the output voltage.
15 VREG Internal voltage regulator bypass capacitor pin. Connect a 4.7 µF capacitor from this pin
to PGND and place it very close to the ARG81800.
16, 17 PGND Power ground pins for the lower MOSFET, gate driver, and BOOT charge circuit.
18 NC No connection.
19, 20 VIN
Power input for the control circuits and the drain of the internal high-side N-channel
MOSFET. Bypass VIN to PGND with an X7R or X8R ceramic capacitor. Place the
capacitor as close to the VIN and PGND pins as possible. Additional capacitors
may be required depending on the application to comply with EMC requirements.
‒PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be
connected to the ground plane of the PCB with at least 6 vias directly in the pad.
Package ES, 20-Pin QFN
Pinout Diagram
PINOUT DIAGRAM AND TERMINAL LIST
1
2
3
4
511
12
13
14
15
6
7
8
9
10 16
17
18
19
20
BOOT
SW
SW
SS
EN
CLKOUT
SYNCIN
GND
FSET
PWM/AUTO
COMP
PGOOD
BIAS
FB
VREG
PGND
PGND
NC
VIN
VIN
PAD
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
INPUT VOLTAGE
Input Voltage Range VIN VIN must first rise above VINUV(ON) (max) 3.5 – 36 V
VIN UVLO Start VINUV(ON) VIN rising 3.35 3.55 3.8 V
VIN UVLO Stop VINUV(OFF) VIN falling 3.1 3.3 3.5 V
VIN UVLO Hysteresis VINUV(HYS) −250 −mV
INPUT SUPPLY CURRENT
Input Shutdown Current [2] IIN(SD) VIN = 12 V, VEN = 0, VSW = VIN, TJ = 25°C −1 2 µA
Input Current, PWM Mode [2] IIN(PWM) VIN = 12 V, VEN = 2 V, no load, no switching −5 6.5 mA
3.3 VOUT LP Input Current [3][4] ILP(3.3V)
VIN = 12 V, IOUT = 0 µA, TJ = 25°C −8−µA
VIN = 12 V, IOUT = 50 µA, TJ = 25°C −33 −µA
5.0 VOUT LP Input Current [3][4] ILP(5.0V)
VIN = 12 V, IOUT = 0 µA, TJ = 25°C −8−µA
VIN = 12 V, IOUT = 50 µA, TJ = 25°C −44 −µA
REGULATION ACCURACY (FB PIN)
Feedback Voltage Accuracy VFB –40°C < TJ < 150°C, VIN ≥ 3.5 V, VFB = VCOMP 788 800 812 mV
SWITCHING FREQUENCY AND DITHERING (FSET PIN)
PWM Switching Frequency fSW
RFSET = 14.3 kΩ 1.93 2.15 2.37 MHz
RFSET = 34 kΩ 0.90 1.00 1.10 MHz
RFSET = 71.5 kΩ 450 500 550 kHz
RFSET = 86.6 kΩ 360 410 460 kHz
Dropout Switching Frequency fDROP −fSW/4 − −
PWM Frequency Dither Range fDITH(RNG)
CLKOUT left open −±5 ±6.5 % of fSW
CLKOUT connected to VREG −0−% of fSW
PWM Dither Modulation Frequency fDITH(MAG) −±0.5 −% of fSW
PULSE WIDTH MODULATION (PWM) TIMING AND CONTROL
Minimum Controllable SW On-Time tON(MIN) VIN = 12 V, IOUT = 0.7 A, VBOOT – VSW = 4.5 V −60 85 ns
Minimum SW Off-Time tOFF(MIN) VIN =12 V, IOUT = 0.7 A −85 110 ns
COMP to SW Current Gain gmPOWER1 ARG81800 −2.0 −A/V
gmPOWER2 ARG81800-1 −1.0 −A/V
Slope Compensation
SE1 fSW = 2.15 MHz, ARG81800 650 900 1100 mA/µs
SE2 fSW = 2.15 MHz, ARG81800-1 325 450 550 mA/µs
SE3 fSW = 252 kHz, ARG81800 75 100 125 mA/µs
SE4 fSW = 252 kHz, ARG81800-1 35 50 65 mA/µs
PWM Ramp Offset VPWM(OFFS) −650 −mV
ELECTRICAL CHARACTERISTICS: Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specied
Continued on next page...
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
LOW-POWER (LP) MODE
LP Output Voltage Ripple [3][4] ΔVOUT(LP) LP Mode, 8 V < VIN < 12 V − 65 −mV
Low IQ Peak Current Threshold IPEAK(LP1) ARG81800, No Load, VIN = 12 V 320 400 500 mA
IPEAK(LP2) ARG81800-1, No Load, VIN = 12 V 160 212 270 mA
INTERNAL POWER SWITCHES
High-Side MOSFET On-Resistance RDS(on)HS
TJ =25°C [3], VBOOT – VSW = 4.5 V, IDS = 800 mA −500 600 mΩ
TJ = 150°C, VBOOT – VSW = 4.5 V, IDS = 800 mA − − 1075 mΩ
Low-Side MOSFET On-Resistance RDS(on)LS
TJ =25°C [3], VIN ≥ 4.5 V, IDS = 1 A −210 250 mΩ
TJ =150°C, VIN ≥ 4.5 V, IDS = 1 A − − 450 mΩ
High-Side Leakage Current [5] ILKG(HS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 0 V −1.5 − 1.5 µA
Low-Side Leakage Current ILKG(HS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 12 V −1.5 − 1.5 µA
Gate Drive Non-Overlap Time [3] tNO −10 25 ns
Switch Node Rising Slew Rate SRHS 12 V < VIN < 16 V [3] −5−V/ns
MOSFET CURRENT PROTECTION THRESHOLDS
High-Side Current Limit ILIMHS1 tON = tON(MIN), ARG81800 1.7 2.0 2.3 A
ILIMHS2 tON = tON(MIN), ARG81800-1 0.85 1.0 1.15 A
Low-Side Current Limit ILIMLSx −50 −% of
ILIMHSx
SYNCHRONIZATION INPUT (SYNCIN PIN)
Synchronization Frequency Range fSW(SYNC) 0.25 −2.5 MHz
SYNCIN Duty Cycle DCSYNC 20 50 70 %
SYNCIN Pulse Width tPWSYNC 80 − − ns
SYNCIN Voltage Thresholds VSYNC(HI) VSYNC(IN) rising −1.35 1.5 V
VSYNC(LO) VSYNC(IN) falling 0.8 1.2 −V
SYNCIN Hysteresis VSYNC(HYS) VSYNC(HI) ‒ VSYNC(LO)−150 −mV
SYNCIN Pin Current ISYNC VSYNC(IN) = 5 V −±1 −µA
CLOCK OUTPUT (CLKOUT PIN)
SYNCIN to CLKOUT Delay ФSYNC(CLK)
RFSET = 14.3 kΩ, VSYNC(HI) = 3.3 V,
Dither disabled −1/(2×fSW)
± 70 −ns
SWMASTER to SWFOLLOWER Delay [3] ФSWM(SWF) RFSET = 14.3 kΩ, VSYNC(HI) = 3.3 V −1/(2×fSW)
± 30 −ns
CLKOUT Output Voltages VCLK(OUT)H VVREG = 4.8 V 2.2 − − V
VCLK(OUT)L VVREG = 4.8 V − − 0.6 V
ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specied
Continued on next page...
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
ERROR AMPLIFIER
Feedback Input Bias Current [2] IFB VFB = 800 mV –40 – –15 nA
Open-Loop Voltage Gain AVOL −65 −dB
Transconductance gm VFB > 400 mV 550 750 950 μA/V
0 V < VFB < 400 mV 275 375 550 μA/V
Output Current IEA −±75 − μA
COMP Pull-Down Resistance RCOMP FAULT = 1 or HICCUP = 1 −1− kΩ
SOFT START
Startup (Source) Current ISS HICCUP = FAULT = 0 −30 −20 −10 µA
Hiccup/Dropout (Sink) Current IHIC HICCUP = 1 or Dropout Mode 1 2.2 5 µA
Soft Start Delay Time [3] tdSS CSS = 22 nF −440 −µs
Soft Start Ramp Time [3] tSS CSS = 22 nF −880 −µs
FAULT/HICCUP Reset Voltage VSSRST VSS falling due to HICCUP or FAULT −200 275 mV
Hiccup OCP (and LP) Counter Enable
Threshold VHIC/LP(EN) VSS rising −2.3 −V
Soft Start Frequency Foldback fSW(SS)
0 V < VFB < 200 mV – fSW / 4 – –
200 mV < VFB < 400 mV – fSW / 2 – –
400 mV < VFB – fSW – –
Maximum Voltage VSS(MAX) VEN = 0 V or FAULT without HICCUP −VVREG − −
Pull-Down Resistance RSS(FLT) 2kΩ
HICCUP MODE COUNTS
High-Side Overcurrent Count HICOC After VSS > VHIC/LP(EN) −120 −fSW
counts
SW Short-to-Ground Count HICSW(GND) −2−fSW
counts
BOOT Short Circuit Count HICBOOT(SC) −120 −fSW
counts
BOOT Open Circuit Count [3] HICBOOT(OC) −7−fSW
counts
ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specied
Continued on next page...
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
OUTPUT VOLTAGE PROTECTION THRESHOLDS (VFB, OV, UV)
VFB OV PWM Threshold VFB(OV) VFB rising 850 880 900 mV
VFB OV PWM Hysteresis VFB(OV,HYS) VFB falling, relative to VFB(OV) –−15 – mV
VFB UV PWM Threshold VFB(UV) VFB falling 716 740 764 mV
VFB UV PWM Hysteresis VFB(UV,HYS) VFB rising, relative to VFB(UV) – +15 – mV
VFB UV LP Mode Threshold [3] VFB(UV,LP) VFB falling 665 700 735 mV
POWER GOOD OUTPUT (PGOOD PIN)
PGOOD Startup (SU) Delay tdPG(SU) Increasing VFB due to startup −30 −µs
PGOOD Undervoltage (UV) Delay tdPG(UV) Decreasing VFB −30 −µs
PGOOD Overvoltage (OV) Delay tdPG(OV) After an overvoltage event −240 −fSW
cycles
PGOOD Low Voltage VPG(L) IPGOOD = 5 mA −200 400 mV
PGOOD Leakage [1] IPG(LKG) VPGOOD = 5.5 V − − 2 µA
PWM/AUTO INPUT
PWM/AUTO High Threshold VHI(PWM) VPWM/AUTO rising 1.8 2.0 2.5 V
PWM/AUTO Float Voltage VFLOAT(PWM) VPWM/AUTO floating 1.1 1.4 1.7 V
PWM/AUTO Low Threshold VLO(PWM) VPWM/AUTO falling 0.6 0.8 1.0 V
PWM to LP Transition Delay [3] tdPWM(LP)
VPWM/AUTO = 0 V, VSS > VHIC/LP(EN),
PGOOD high −7.5 −ms
ENABLE INPUT (EN PIN)
Enable High Threshold VENHI VEN rising −1.6 2.0 V
Enable Low Threshold VENLO VEN falling 0.8 1.4 −V
Enable Input Hysteresis VENHYS VENHI ‒ VENLO −200 −mV
Disable Delay tDISDLY
VEN transitions low to when SW stops
switching −120 −fSW
cycles
Enable Pin Input Current IEN VEN = VPWM/AUTO = 5 V −12 −µA
ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specied
Continued on next page...
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
BOOT REGULATOR (BOOT PIN)
BOOT Charging Frequency fBOOT −fSW − −
BOOT Voltage VBOOT VIN = 12 V, VBOOT – VSW −4.8 5.3 V
INTERNAL REGULATOR (VREG PIN)
BIAS Disconnected VVREG1 6 V < VVIN < 36 V, VBIAS = 0 V 4.5 4.8 5.1 V
BIAS Connected VVREG2
VBIAS = 3.3V 2.85 3.2 3.29 V
6 V < VBIAS < 20 V 4.5 4.8 5.1 V
BIAS Input Voltage Range VBIAS 3.3 −36 V
THERMAL SHUTDOWN PROTECTION (TSD)
TSD Rising Threshold [3] TTSD
TJ rising, PWM stops immediately and COMP
and SS are pulled low 155 170 −°C
TSD Hysteresis [3] TSDHYS TJ falling, relative to TTSD −20 −°C
ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specied
[1] Negative current is dened as coming out of the node or pin, positive current is dened as going into the node or pin.
[2] Thermally limited depending on input voltage, duty cycle, regulator load currents, PCB layout, and airow.
[3] Ensured by design and characterization, not production tested.
[4] Using recommended external components specied in Table 3.
[5] At VIN = 36 V, IOUT = 0 A, and TJ = 150°C, VOUT rises to overvoltage threshold due to leakage.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C.
ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values.
ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values.
UVLO Start and Stop Thresholds
vs. Temperature
No-Load Input Current (PWM Mode)
vs. Input Voltage
No-Load Input Current (PWM Mode)
vs. Temperature
Input Shutdown Current
vs. Temperature
EN High and Low Thresholds
vs. Temperature
Bias Pin Current vs. Output Voltage Feedback Voltage vs. Temperature
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
-40 -20 0 20 40 60 80 100 120 140 160
Voltage (V)
Temperature (°C)
UVLO Stop UVLO Start
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
3.5 8.5 1 3.5 1 8. 5 23. 5 28. 5 33. 5 3 8.5
Current (mA)
Input Voltage (V)
No Load Input Current, PWM Mode
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
-40 -20 0 20 40 60 80 100 120 140 160
Current (mA)
Temperature (°C)
No Load Input Current, PWM Mode
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-40 -20 0 20 40 60 80 100 120 140 160
Current (µA)
Temperature (°C)
Input Shutdown Current
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-40 -20 0 20 40 60 80 100 1 20 1 40 1 60
Voltage (V)
Temperature (°C)
EN High Threshold EN Low T hre shold
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
3.5 6.5 9.5 12. 5 1 5. 5 1 8. 5 21. 5
Current (mA)
Bias Voltage (V)
Bias Pin Current, PWM Mode
798
799
800
801
802
803
804
805
-40 -20 0 20 40 60 80 100 120 140 160
Voltage (mV)
Temperature (°C)
Feedback Voltage
Input Current
vs. Input Voltage
0
1
2
3
4
5
6
7
8
9
10
3.5 8.5 1 3.5 1 8. 5 23. 5 28. 5 3 3. 5
Current (µA)
Input Voltage (V)
Input Shutdown Current No Load Input Current, HLP Mode
On Resistance (High-Side and Low-Side)
vs. Temperature
100
200
300
400
500
600
700
800
-40 -20 0 20 40 60 80 100 120 140 160
Resistance (mΩ)
Temperature (°C)
High-Side On Resistance Low-Side On Resistance
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C.
ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values.
ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values.
Minimum On and O Time
vs. Temperature
High-Side Current Limit vs. Temperature
– ARG81800
High-Side Current Limit vs. Temperature –
ARG81800-1
Feedback Input Bias Current
vs. Temperature
PGOOD Delay (UV and SU)
vs. Temperature
PGOOD Leakage Current
vs. Temperature
PGOOD Low Voltage
vs. Temperature
Feedback OV and UV Threshold
vs. Temperature
35
40
45
50
55
60
65
70
-40 -20 0 20 40 60 80 100 120 140 160
Time (ns)
Temperature (°C)
Minimum On Time Minimum Off Time
1.9
1.95
2
2.05
2.1
-40 -20 0 20 40 60 80 1 00 1 20 140 160
Current (A)
Temperature (°C)
High-Side Current Limit - ARG81800
0.9
0.95
1
1.05
1.1
-40 -20 020 40 60 80 100 120 1 40 1 60
Current (A)
Temperature (°C)
High-Side Current Limit - ARG81800-1
-30
-29
-28
-27
-26
-25
-24
-23
-22
-21
-20
-40 -20 0 20 40 60 80 1 00 1 20 140 160
Current (nA)
Temperature (°C)
Feedback Input Bias Current
5
10
15
20
25
30
35
40
-40 -20 0 20 40 60 80 1 00 1 20 140 160
Time (µs )
Temperature (°C)
PGOOD UV/SU Delay
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
-40 -20 0 20 40 60 80 1 00 1 20 140 160
Current (nA)
Temperature (°C)
PGOOD Leakage Current
40
60
80
100
120
140
160
180
200
-40 -20 0 20 40 60 80 100 120 140 160
Voltage (mV)
Temperature (°C)
PGOOD Low Voltage
700
720
740
760
780
800
820
840
860
880
900
-40 -20 0 20 40 60 80 100 120 140 160
Voltage (mV)
Temperature (°C)
FB OV Threshold, PWM Mode FB UV Threshold, PWM Mode
Switching Frequency
vs. Temperature
2.08
2.09
2.1
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
-40 -20 0 20 40 60 80 100 1 20 1 40 1 60
Switching Frequency (MHz)
Temperature (°C)
RFSET = 14.3 kΩ
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
13
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C.
ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values.
ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values.
Ecency vs. Load Current
VOUT = 3.3 V, fSW = 2.15 MHz
Ecency vs. Load Current
VOUT = 5.0 V, fSW = 400 kHz
Load Regulation
VOUT = 3.3 V, fSW = 2.15 MHz, LP Mode
Load Regulation
VOUT = 5.0 V, fSW = 400 kHz, PWM Mode
Line Regulation
VOUT = 5.0 V, fSW = 400 kHz, PWM Mode
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0.05 0.1 0.15 0.2 0.25 0.3
Regulation (%)
Load Current (A)
VIN = 8 V VIN = 12 V VIN = 16 V
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Regulation (%)
Load Current (A)
VIN = 8 V VIN = 12 V VIN = 16 V
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
712 17 22 27 32
Regulation (%)
Input Voltage (V)
IOUT = 0 A IOUT = 0.25 A IOUT = 0.5 A
36
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
5.5 1 0. 5 1 5. 5 2 0. 5 25. 5 30. 5 35. 5
Regulation (%)
Input Voltage (V)
IOUT = 0 A IOUT = 0.15 A
Line Regulation
VOUT = 3.3 V, fSW = 2.15 MHz, LP Mode
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Efficiency (%)
Load Current (A)
VIN = 8 V, HLP Mode VIN = 12 V, HLP Mode VIN = 16 V, HLP Mode
VIN = 8 V, PWM Mode VIN = 12 V, PWM Mode VIN = 16 V, PWM Mode
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1
Efficiency (%)
Load Current (A)
VIN = 8 V, HLP Mode VIN = 12 V, HLP Mode VIN = 16 V, HLP Mode
VIN = 8 V, PWM Mode VIN = 12 V, PWM Mode VIN = 16 V, PWM Mode
0.5
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
14
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C.
ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values.
ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values.
Start-up with EN rising
VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode
Shut-down with EN falling
VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode
Pre-bias Start-up with EN rising
VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode
Pre-bias Shut-down with EN falling
VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode
Steady-State Performance
VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode
Steady-State Performance
VOUT = 3.3 V, IOUT = 10 mA, LP Mode
Steady-State Performance
VOUT = 3.3 V, IOUT =100 mA, LP Mode
Load Transient Performance
VOUT = 3.3 V, PWM Mode
Load Transient Performance
VOUT = 3.3 V, LP Mode
VOUT: 1 V/DIV
VSS: 2 V/DIV
VPGOOD: 5 V/DIV
VOUT: 1 V/DIV
VSS: 2 V/DIV
VPGOOD: 5 V/DIV
VOUT: 2 V/DIV
VSS: 2 V/DIV
ILO: 1 A/DIV
VPGOOD: 5 V/DIV
VSS: 2 V/DIV
VOUT: 2 V/DIV
VPGOOD: 2 V/DIV
IL: 500 mA/DIV
VOUT (AC): 20 mV/DIV
VOUT (AC): 100 mV/DIV IL: 500 mA/DIV
VPGOOD: 2 V/DIV
VPGOOD: 2 V/DIV
IL: 500 mA/DIV
VOUT (AC): 50 mV/DIV
VOUT (AC): 100 mV/DIV
IOUT: 500 mA/DIV
VPGOOD: 2 V/DIV VPGOOD: 2 V/DIV
IOUT: 500 mA/DIV
VOUT (AC): 200 mV/DIV
1 ms/DIV 100 µs/DIV 1 ms/DIV
200 µs/DIV 500 ns/DIV 10 µs/DIV
5 µs/DIV 200 µs/DIV 200 µs/DIV
VEN: 5 V/DIV
VEN: 5 V/DIV VEN: 5 V/DIV
VEN: 5 V/DIV
VSW: 10 V/DIV
VSW: 10 V/DIV
VSW: 10 V/DIV
40 mA/µs40 mA/µs
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
15
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VEN = 12 V, CBOOT = 0.1 µF, CSS = 22 nF, unless otherwise noted −40°C ≤ TJ ≤ 150°C. Typical Values are at TA = 25°C.
ARG81800, VOUT = 3.3 V, fSW = 2.15 MHz. See Table 3 for External Component Values.
ARG81800-1, VOUT = 5.0V, fSW = 0.4 MHz. See Table 3 for External Component Values.
ISO 16750-2: Level 1 Starting Profile
VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode
ISO 16750-2: Reset Voltage Profile
VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode
Load Transient Performance
VOUT = 5.0 V, LP Mode
Load Transient Performance
VOUT = 5.0 V, PWM Mode
External Clock Synchronization
VOUT = 3.3 V, fSW = 2.15 MHz, fEXT= 1 MHz
Interleaved Clock Generation
VOUT = 5.0 V, fSW = 500 kHz, PWM Mode
Output Short Protection
VOUT = 3.3 V, PWM Mode
ISO 16750-2: Load Dump Pulse
VOUT = 3.3 V, IOUT = 1.0A, PWM Mode
V
IN
Slow Ramp Up and Ramp Down
VOUT = 3.3 V, IOUT = 1.0 A, PWM Mode
VPGOOD: 5 V/DIV
VOUT (AC): 100 mV/DIV
IOUT: 500 mA/DIV
200 µs/DIV
VOUT (AC): 100 mV/DIV
IOUT: 500 mA/DIV
VPGOOD: 5 V/DIV
200 µs/DIV
VOUT (AC): 100 mV/DIV
VSYNCIN: 5 V/DIV 5 µs/DIV
5 ms/DIV
VSS: 2 V/DIV
VOUT: 2 V/DIV
VPGOOD: 5 V/DIV 500 ns/DIV
VSW (follower): 5 V/DIV
VOUT: 2 V/DIV
100 ms/DIVIOUT: 1 A/DIV
VPGOOD: 2 V/DIV
10 s/DIV
200 ms/DIV
50 s/DIV
VOUT: 2 V/DIV
VPGOOD: 2 V/DIV
IOUT: 1 A/DIV
VOUT: 2 V/DIV
VPGOOD: 2 V/DIV
IOUT: 1 A/DIV
VPGOOD: 2 V/DIV
VOUT: 2 V/DIV
VSW: 10 V/DIV
VSW: 10 V/DIV
VSW (MASTER): 5 V/DIV
VIN: 10 V/DIV
VIN: 5 V/DIV VIN: 5 V/DIV VIN: 5 V/DIV
20 mA/µs 20 mA/µs
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
16
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION
Overview
The ARG81800 is a wide input voltage (3.5 to 36 V) synchronous
PWM buck regulator that integrates low RDS(on) high-side and
low-side N-channel MOSFETs. The ARG81800 employs peak
current mode control to provide superior line and load regulation,
cycle-by-cycle current limit, fast transient response, and simple
compensation. The features of the ARG81800 include ultralow
IQ LP mode, extremely low minimum on-time, maximized duty
cycle for low dropout operation, soft recovery from dropout con-
dition, and pre-bias startup capability.
Protection features of the ARG81800 include VIN undervoltage
lockout, cycle-by-cycle overcurrent protection, BOOT over-
voltage and undervoltage protection, hiccup mode short circuit
protection, overvoltage protection, and thermal shutdown. In
addition, the ARG81800 provides open circuit, adjacent pin short
circuit, and pin-to-ground short circuit protection.
Reference Voltage
The ARG81800 incorporates an internal precision reference
that allows output voltages as low as 0.8 V. The accuracy of the
internal reference is ±1.5% across –40°C to 150°C. The output
voltage of the regulator is programmed with a resistor divider
between VOUT and the FB pin of the ARG81800.
Internal VREG Regulator
VREG is used as the power supply for internal control circuitry
and a low-side MOSFET driver. The ARG81800 consists of two
internal low dropout regulators, VIN LDO and Bias LDO, to
generate VREG voltage. VIN LDO is powered from input voltage
to generate 4.8 V for VREG supply. Bias LDO uses the BIAS pin
as a supply to generate VREG voltage. When voltage at the BIAS
pin exceeds 3.0 V, VIN LDO is deactivated and Bias LDO gener-
ates the VREG voltage. Bias LDO can be made more efficient
than VIN LDO by providing an external voltage at the BIAS pin
that is less than the input voltage. If the output voltage of the
ARG81800 is programmed to be greater than 3.1 V, it is recom-
mended to supply the output voltage to the BIAS pin to improve
the efficiency of the regulator.
Oscillator/Switching Frequency
The PWM switching frequency of the ARG81800 is adjustable
from 250 kHz to 2.4 MHz by programming the internal clock fre-
quency of the oscillator by connecting an FSET resistor from the
FSET pin to GND. The internal clock has an accuracy of about
±10% over the operating temperature range. Usually, an FSET
resistor with ±1% tolerance is recommended. A graph of switch-
ing frequency versus FSET resistor value is shown in the Design
and Component Selection section. The ARG81800 will suspend
operation if the FSET pin is shorted to GND or left open.
Synchronization (SYNCIN) and Clock Output
(CLKOUT)
The Phase-Locked Loop (PLL) in the ARG81800 allows its inter-
nal oscillator to be synchronized to an external clock applied on the
SYNCIN pin. If the SYNCIN pin is driven by an external clock, the
ARG81800 will be forced to operate in PWM mode, with synchro-
nized switching frequency, overriding the mode selection on the
PWM/AUTO pin. The external clock must also satisfy the pulse
width, duty cycle, and rise/fall time requirements shown in the
Electrical Characteristics table. If the SYNCIN pin is continuously
pulled high, the ARG81800 outputs a 180-degree phase-shifted
internal oscillator clock on the CLKOUT pin, so “downstream”
ARG81800 devices can be easily interleaved via their synchro-
nization inputs. Figure 1 shows the usage of multiple ARG81800
devices in master-follower configuration. If the SYNCIN pin is
continuously pulled low, the device disables the CLKOUT pin.
Frequency Dither
In addition to EMI-aware PCB layout, extensive filtering,
controlled switch node transitions, and shielding, switching
frequency dithering is an effective way to mitigate EMI concerns
in switching power supplies. Frequency dither helps to minimize
peak emissions by spreading the emissions across a wide range of
frequencies. The ARG81800 provides frequency dither by spread-
ing the switching frequency ±5% using a triangular modulated
wave of 0.5% switching frequency.
The ARG81800 is capable of adding dither to the external clock
applied on the SYNCIN pin. This unique feature allows the
minimizing of electromagnetic emissions even when the device
is using external clock. Frequency dither scheme can be disabled
by connecting the CLKOUT pin to VREG pin. In master-follower
configuration, the CLKOUT pin of the follower device should be
connected to VREG to avoid double-dithering.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
17
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ARG81800
Master
SW1
SYNC
IN
CLK
OUT
f
SYNC
f
SYNC
± f
DITHER
f
SYNC
± f
DITHER
+ 180°
V
O1
f
SYNC
± f
DITHER
+ 180°
V
O2
V
O3
f
SYNC
± f
DITHER
+ 180°
ARG81800
Follower
SW2
SYNC
IN
CLK
OUT
VREG
ARG81800
Follower
SW3
SYNC
IN
CLK
OUT
VREG
Figure 1: Master-Follower Conguration
Table 1: PWM Frequency, CLKOUT, and Dithering Settings
Device SYNCIN
PWM Frequency and Dithering CLKOUT Frequency and Dithering
SW
Frequency
Magnitude of
Dithering
Dither Modulation
Frequency Frequency Magnitude of
Dithering
Dither Modulation
Frequency
ARG81800/
ARG81800-1
Low fSW ±0.05 × fSW 0.005 × fSW
Disabled/Off None None
High fSW fSW + 180° ±0.05 × fSW 0.005 × fSW
fSYNC fSYNC ±0.05 × fSW 0.005 × fSW fSYNC + 180° ±0.05 × fSYNC 0.005 × fSYNC
Transconductance Error Amplifier
The transconductance error amplifier’s primary function is to
control the regulator’s output voltage. The error amplifier is a
three-terminal input device with two positive inputs and one
negative input, as shown in Figure 2. The negative input is simply
connected to the FB pin and is used to sense the feedback volt-
age for regulation. The error amplifier performs an “analog OR”
selection between its positive inputs and operates according to
the positive input with the lowest potential. The two positive
inputs are used for soft-start and steady-state regulation. The error
amplifier regulates to the soft-start pin voltage minus 400 mV
during startup and to the internal reference (VREF) during normal
operation.
FB Pin
VREF
800 mv
SS Pin
400 mV
Error Amplifier
COMP
Pin
Figure 2: ARG81800 Error Amplier
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
18
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Compensation Components
To stabilize the regulator, a series RC compensation network (RZ
and CZ) must be connected from the output of the error amplifier
(COMP pin) to GND as shown in the applications schematic. In
most instances, an additional low-value capacitor (CP) should
be connected in parallel with the RZ-CZ compensation network
to reduce the loop gain at very high frequencies. However, if
the CP capacitor is too large, the phase margin of the converter
may be reduced. Calculation of RZ, CZ, and CP is covered in the
Component Selection section of this datasheet. If a fault occurs
or the regulator is disabled, the COMP pin is pulled to GND via
the approximately 1 kΩ internal resistor and PWM switching is
inhibited.
Power MOSFETs
The ARG81800 includes a 500 mΩ, high-side N-channel MOS-
FET and a 210 mΩ, low-side N-channel MOSFET to provide
synchronous rectification. When the ARG81800 is disabled via
the EN input being low or a fault condition, its output stage is tri-
stated by turning off both the upper and lower MOSFETs.
BOOT Regulator
The ARG81800 includes a BOOT regulator to supply the power
for a high-side MOSFET gate driver. The voltage across the
BOOT capacitor is typically 4.8 V. If the BOOT capacitor is
missing, the device will detect a BOOT overvoltage. Similarly,
if the BOOT capacitor is shorted, the ARG81800 will detect a
BOOT undervoltage. Also, the BOOT regulator has a current
limit to protect itself during a short-circuit condition.
Soft Start (Startup) and Inrush Current Control
The soft start function controls the inrush current at startup. The
soft start pin (SS) is connected to GND via a capacitor. When the
ARG81800 is enabled and all faults are cleared, the SS pin sources
the charging current ISS and the voltage on the soft start capacitor
CSS starts ramping upward from 0 V. When the voltage at the soft
start pin exceeds the soft start offset voltage (SS Offset), typically
400 mV, the error amplifier will ramp up its output voltage above
the PWM Ramp Offset. At this instant, the top and bottom MOS-
FETs will begin switching. There is a small delay (tdSS) from the
moment EN pin transitioning high to the moment soft start voltage
reaching 400 mV to initiate PWM switching.
Immediately after the start of PWM switching, the error amplifier
will regulate the voltage at the FB pin to the soft start pin voltage
minus approximately 400 mV. During the active portion of soft
start, the voltage at the SS pin will rise from 400 mV to 1.2 V (a
difference of 800 mV), the voltage at the FB pin will rise from
0 V to 800 mV, and the regulator output voltage will rise from
0 V to the set voltage determined by the feedback resistor divider.
During startup, PWM switching frequency is reduced to 25% of
fSW while FB is below 200 mV. If FB voltage is above 200 mV
but below 400 mV, the switching frequency is 50% of fSW. At
the same time, the transconductance of the error amplifier, gm,
is reduced to half of nominal value when FB is below 400 mV.
When FB is above 400 mV, the switching frequency will be
fSW and the error amplifier gain will be the nominal value. The
reduced switching frequency and error amplifier gain are neces-
sary to help improve output regulation and stability when VOUT is
very low. During low VOUT, the PWM control loop requires on-
time near the minimum controllable on-time and very low duty
cycles that are not possible at the nominal switching frequency.
When the voltage at the soft start pin reaches approximately
1.2 V, the error amplifier will switch over and begin regulating
the voltage at the FB pin to the fixed internal bandgap reference
voltage of 800 mV. The voltage at the soft start pin will con-
tinue to rise to the internal LDO regulator output voltage. If the
ARG81800 is disabled or a fault occurs, the internal fault latch is
set and the capacitor at the SS pin is discharged to ground very
quickly through a 2 kΩ pull-down resistor. The device will clear
the internal fault latch when the voltage at the SS pin decays to
approximately 200 mV. However, if the device enters hiccup
mode, the capacitor at the SS pin is slowly discharged through
a current sink, IHIC. Therefore, the soft start capacitor CSS not
only controls the startup time but also the time between soft start
attempts in hiccup mode.
Slope Compensation
The ARG81800 incorporates internal slope compensation that
ensures stable operation at PWM duty cycles above 50% for a wide
range of input/output voltages, switching frequencies, and induc-
tor values. As shown in the functional block diagram, the slope
compensation signal is added to the sum of the current sense and
PWM Ramp Offset. The relationship between slope compensation
and adjustable switching frequency is given by
Equation 1:
SE = 12.84 / (37.037 / fSW – 3)
where fSW is switching frequency in MHz and SE is slope compen-
sation in A/µs. Internal slope compensation in ARG81800-1 is half
of that (Equation 1) in ARG81800.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
19
Allegro MicroSystems
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Pre-Biased Startup
If the output of the buck regulator is pre-biased at a certain output
voltage level, the ARG81800 will modify the normal startup
routine to prevent discharging the output capacitors. As described
in the Soft Start (Startup) and Inrush Current Control section,
the error amplifier usually becomes active when the voltage at
the soft start pin exceeds 400 mV. If the output is pre-biased,
the voltage at the FB pin will be non-zero. The device will not
start switching until the voltage at SS pin rises to approximately
VFB + 400 mV. From then on, the error amplifier becomes active,
the voltage at the COMP pin rises, PWM switching starts, and
VOUT will ramp upward from the pre-bias level.
Dropout
The ARG81800 is designed to operate at extremely wide duty
cycles to minimize any reduction in output voltage during drop-
out conditions (difference between input and output voltage drops
to a minimum value) such as cold crank. During dropout, if the
minimum off-time (85 ns typical) is reached for more than 5 con-
secutive switching cycles, the programmed switching frequency
fSW is reduced by a factor of 4 and the off-time is extended to
115 ns (typical). While operating with reduced frequency, if the
device further reaches minimum off-time (115 ns typical) for
more than 35 consecutive switching cycles, it continues to oper-
ate with reduced frequency. Otherwise, the device toggles back
to the programmed switching frequency fSW. In addition, during
dropout operation, the soft start capacitor CSS will discharge so
that if the input voltage increases, the output voltage recovers
with a slew rate set by the soft start ramp.
PGOOD Output
The ARG81800 provides a Power Good (PGOOD) status signal
to indicate if the output voltage is within the regulation limits.
Since the PGOOD output is an open-drain output, an external
pull-up resistor must be used as shown in the applications sche-
matic. PGOOD transitions high when the output voltage, sensed
at the FB pin, is within regulation.
During start-up, PGOOD signal exhibits an additional delay of
tdPG(SU) after FB pin voltage reaches the regulation voltage. This
delay helps to filter out any glitches on the FB pin voltage.
The PGOOD output is pulled low if either an undervoltage or over-
voltage condition occurs or the ARG81800 junction temperature
exceeds thermal shutdown threshold (TSD). The PGOOD overvolt-
age and undervoltage comparators incorporate a small amount of
hysteresis (VFB(OV,HYS), VFB(UV,HYS)) to prevent chattering and
deglitch filtering (tdPG(UV), tdPG(OV)) to eliminate false triggering.
For other faults, PGOOD depends on the output voltage.
It is important that the correct status of PGOOD is reported
during either the input supply ramp up or ramp down. During a
supply ramp up, the PGOOD is designed to operate in the correct
state from a very low input voltage. Also, during supply ramp
down, the PGOOD is designed to operate in the correct state
down to a very low input voltage.
Current Sense Amplifier
The ARG81800 incorporates a high-bandwidth current sense
amplifier to monitor the current through the top MOSFET. This
current signal is used to regulate the peak current when the top
MOSFET is turned on. The current signal is also used by the pro-
tection circuitry for the cycle-by-cycle current limit and hiccup
mode short circuit protection
Pulse-Width Modulation (PWM)
The ARG81800 employs fixed-frequency, peak current mode
control to provide excellent load and line regulation, fast transient
response, and simple compensation. A high-speed comparator and
control logic is included in the ARG81800. The inverting input
of the PWM comparator is connected to the output of the error
amplifier. The non-inverting input is connected to the sum of the
current sense signal, the slope compensation signal, and a DC
PWM Ramp offset voltage (Ramp Offset).
At the beginning of each PWM cycle, the CLK signal sets the PWM
flip flop, the bottom MOSFET is turned off, the top MOSFET is
turned on, and the inductor current increases. When the voltage at
the non-inverting of PWM comparator rises above the error ampli-
fier output COMP, the PWM flip flop is reset, the top MOSFET is
turned off, the bottom MOSFET is turned on, and the inductor cur-
rent decreases. Since the PWM flip flop is reset, the dominant error
amplifier may override the CLK signal in certain situations.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
20
Allegro MicroSystems
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Low-Power (LP) Mode
The ARG81800 operates in ultralow IQ LP mode when PWM/
AUTO pin is pulled to logic low. If the PWM/AUTO pin transi-
tions from logic high to logic low while output is in regulation,
the device waits for 7 clock cycles before entering the LP mode.
This delay provides adequate filtering to ensure no noise tran-
sients forces the device to erroneously enter LP mode.
When LP mode is selected, the ARG81800 operates in continu-
ous conduction PWM Mode until peak inductor current decreases
to IPEAK(LP). When peak inductor current falls below IPEAK(LP),
the LP comparator monitors FB node and regulates the output
voltage in hysteretic manner. The reference for the LP compara-
tor is calibrated approximately 0.5% above the PWM regulation
point. The transition point from PWM to LP mode is defined by
the input voltage, output voltage, and inductor value. The exact
operation of the ARG81800 in LP mode is described below.
When voltage on the COMP pin falls to the voltage correspond-
ing to the ultralow IQ peak current threshold value, an internal
clamp prevents the COMP voltage from falling further. This
results in a momentary rise in the FB voltage beyond LP com-
parator upper threshold which causes the LP comparator to trip.
Once the LP comparator trips, the device enters coast period
during which MOSFET switching is terminated and the associ-
ated control circuitry is also shut down. This ensures a very low
quiescent current is drawn from the input.
The coast period terminates once the FB voltage falls below the
LP comparator lower threshold. The device will fully power-up
approximately after a 2.5 μs delay and the high-side MOSFET is
repeatedly turned on, operating at the PWM switching frequency
until the voltage at the FB pin rises again above the LP compara-
tor threshold. The rate of rise of output voltage is determined by
the input voltage, output voltage, inductor value, output capaci-
tance, and load.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
21
Allegro MicroSystems
955 Perimeter Road
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Protection Features
The ARG81800 was designed to satisfy the most demanding
automotive and non-automotive applications. In this section, a
description of each protection feature is described and Table 2
summarizes the protections and their operation.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout (UVLO) comparator in the ARG81800
monitors the voltage at the VIN pin and keeps the regulator dis-
abled if the voltage is below the start threshold (VINUV(ON), VIN
rising) or the stop threshold (VINUV(OFF), VIN falling). The UVLO
comparator incorporates some hysteresis (VINUV(HYS)) to help
prevent on-off cycling of the regulator due to resistive or inductive
drops in the VIN path during heavy loading or during startup.
PULSE-BY-PULSE PEAK CURRENT PROTECTION (PCP)
The ARG81800 monitors the current in the high-side MOSFET,
and if the peak MOSFET current exceeds the pulse-by-pulse
overcurrent limit ILIMHSx, the upper MOSFET is turned off and
the bottom MOSFET is turned on until the start of the next clock
pulse from the oscillator. The device includes leading edge blank-
ing to prevent false triggering of pulse-by-pulse current protec-
tion when the upper MOSFET is turned on.
Because of the addition of the slope compensation ramp to the
sensed inductor current, the ARG81800 can deliver more current
at minimum duty cycle and less current at maximum duty cycle.
Figure 3 illustrates the relationship between the high-side MOS-
FET peak current limit and duty cycle. As shown, the peak cur-
rent limit at minimum and maximum duty cycle remains fixed,
but the relationship versus duty cycle is skewed with frequency
due to the fixed minimum off-time. Given the relationship, it is
best to use the IHSPKMIND and IHSPKMAXD current limits to calcu-
late the current limit at any given duty cycle.
During synchronization, slope compensation scales in a similar
fashion as with RFSET although with slightly less accuracy. The
exact current the buck regulators can support is heavily depen-
dent on duty cycle (VIN, VOUT), ambient temperature, thermal
resistance of the PCB, airflow, component selection, and nearby
heat sources.
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
0 10 20 30 40 50 60 70 80 90
Peak Current Limit (A)
Duty Cycle (%)
ARG81800 Max ARG81800-1 Max
ARG81800 Min ARG81800-1 Min
Figure 3: Peak Current Limit vs. Duty Cycle
OVERCURRENT PROTECTION (OCP) AND HICCUP MODE
An OCP counter and hiccup mode circuit protect the buck regula-
tor when the output of the regulator is shorted to ground or when
the load is too high. When the soft-start ramp is active (t < tss),
the OCP hiccup counter is disabled. The following two condi-
tions must be met for the OCP counter to be enabled and begin
counting:
• SS pin voltage, VSS > VHIC/LP(EN) (2.3 V), and
• Comp pin voltage, VCOMP clamped at its maximum
voltage (OCP = 1)
As long as these two conditions are met, the OCP counter
remains enabled and will count pulses from the overcurrent
comparator. If the COMP voltage decreases (OCP = 0), the OCP
counter is cleared. Otherwise, if the OCP counter reaches HICOCP
clock counts (120), PWM switching ceases, a hiccup latch is set,
and the COMP pin is quickly pulled down by a relatively low
resistance (1 kΩ). The hiccup latch also enables a small current
sink connected to the SS pin (IHIC). This causes the voltage at
the soft start pin to slowly ramp downward. When the voltage at
the soft start pin decays to a low enough level (VSSRST, 200 mV),
the hiccup latch is cleared, and the current sink is turned off. At
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
22
Allegro MicroSystems
955 Perimeter Road
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this instant, the SS pin will begin to source current (ISS) and the
voltage at the SS pin will ramp upward. This marks the begin-
ning of a new, normal soft start cycle as described earlier. When
the voltage at the soft start pin exceeds the error amp voltage by
approximately 400 mV, the error amplifier will force the voltage
at the COMP pin to quickly slew upward and PWM switching
will resume.
If the short circuit/overload at the regulator output persists,
another hiccup cycle will occur. Hiccups will repeat until the
short circuit/overload is removed or the converter is disabled. If
the short circuit/overload is removed, the device will soft start
normally and the output voltage will automatically recover to the
desired level. Thus, hiccup mode is a very effective protection for
the short-circuit/overload condition. It avoids false trigger during
short duration short-circuit/overload. On the other hand, for the
extended short-circuit/overload duration, the reduced average
power dissipation with hiccup mode of operation helps in lower-
ing the temperature rise of the device and enhancing the system
reliability.
Note that OCP is the only fault that results in hiccup mode being
ignored while VSS < 2.3 V.
BOOT CAPACITOR PROTECTION
The ARG81800 monitors the voltage across the BOOT capaci-
tor to detect if the BOOT capacitor is missing or short-circuited.
If the BOOT capacitor is missing, the regulator enters hiccup
mode after 7 clock counts. If the BOOT capacitor is shorted, the
device enters hiccup mode after 120 clock counts. Also, the boot
regulator has a current limit to protect itself during a short-circuit
condition.
For a boot fault, hiccup mode operates virtually the same as
described previously for overcurrent protection (OCP), with soft
start ramping up and down for repeated hiccups. Boot faults are
non-latched faults, so the device will automatically recover when
the fault is removed.
OVERVOLTAGE PROTECTION (OVP)
The ARG8100 consists of an always-on overvoltage protection
circuit that monitors output overvoltage on the BIAS pin, perhaps
caused by the FB pin pulled to ground, high-side MOSFET leak-
age current, or line/load transients. During an overvoltage fault
caused by any of the above events, the controller tries to reduce
the output overvoltage by terminating the high-side MOSFET
switching and pulsing the low side MOSFET with minimum
off-time (tOFFmin) until FB returns to regulation. The ARG81800
waits for tdPG(OV) (120) clock counts before pulling the PGOOD
low. If the overvoltage fault is not cleared even beyond tdPG(OV),
PGOOD is pulled low and the device continuously attempts to
reduce the output overvoltage. The output overvoltage protec-
tion threshold, at any given time, varies with the voltage on the
feedback node as shown in Figure 4. If the BIAS pin is connected
to VOUT, the maximum settable output voltage is limited to 20 V.
0
5
10
15
20
25
0 100 200 300 400 500 600 700 800 900
Output Overvoltage Threshold (V)
FB Voltage (mV)
Figure 4: Output Overvoltage Threshold Variation with
Increasing Feedback Voltage
SW PIN PROTECTION
Unlike most regulators, the ARG81800 protects itself when the
SW pin is shorted to ground. If the SW pin is shorted to ground,
there will be a very high current in the high-side MOSFET when
it is turned on. The ARG81800 incorporates an internal secondary
current protection to detect this unusually high current and turns
off the high-side MOSFET if the high current persists for more
than two consecutive switching cycles. After turning off the high-
side MOSFET, the device enables the hiccup latch and attempts
to restart after hiccup latch is cleared. If the short to ground is
removed, the regulator will automatically recover; otherwise, the
device continues hiccupping. Unlike other hiccup mode protec-
tions, the SW pin protection is not delayed until soft start is
completed, i.e., VSS > 2.3 V.
PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTECTIONS
The ARG81800 is designed to satisfy the most demanding
automotive applications. For example, the device has been care-
fully designed to withstand a short circuit to ground at each pin
without causing any damage to the IC.
In addition, care was taken when defining the device pinouts to
optimize protection against pin-to-pin adjacent short circuits. For
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
23
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
example, logic pins and high-voltage pins are separated as much as
possible. Inevitably, some low-voltage pins are located adjacent to
high voltage pins, but in these instances, the low voltage pins are
designed to withstand increased voltages, with clamps and/or series
input resistance, to prevent damage to the device.
THERMAL SHUTDOWN (TSD)
The ARG81800 monitors internal junction temperature and shuts
down the IC by disabling the switching pulses of high- and low-
side MOSFETs if the junction temperature exceeds the Thermal
Shutdown Threshold TTSD. Also, to prepare for a restart, the
internal soft-start voltage (VSS) and the voltage at the COMP pin
are pulled low until VSS < VSSRST. TSD is a non-latched fault,
so the device automatically recovers if the junction temperature
decreases by approximately 20°C.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
24
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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Table 2: Summary of ARG81800 Fault Modes and Operation
Fault Mode Internal
Soft Start
During Fault Counting, before Hiccup Mode BOOT
Charging
PGOOD
State
Latched
Fault
Reset
Condition
VCOMP
High-Side
MOFSET
Low-Side
MOFSET
VIN
undervoltage
Pulled low via
2 kΩ resistor,
No Hiccup
Pulled low via
1 kΩ resistor,
No Hiccup
Forced
Turn-off
Forced
Turn-off Disabled Depends on
VREG
NO
Automatic,
VIN above UVLO
start threshold
Output
shorted to
ground
Hiccup, after
120 OCP
clock counts
Clamped to
ILIMHS, then
pulled low for
Hiccup
fSW / 4 due to
VOUT < 25%,
responds to
VCOMP
Turned on if
BOOT voltage
is too low
Not affected Depends on
VOUT
NO Automatic,
Short removed
Output
overcurrent,
VOUT > 50%
Hiccup, after
120 OCP
clock counts
Clamped to
ILIMHS, then
pulled low for
Hiccup
fSW responds to
VCOMP
Turned on if
BOOT voltage
is too low
Not affected Depends on
VOUT
NO
Automatic,
Load current
decreased
High-side
MOSFET
overcurrent
(SW short to
GND)
Hiccup, after
2 clock count
Pulled low via
1 kΩ resistor
for hiccup
Forced
Turn-off
Forced
Turn-off Not affected Depends on
VOUT
NO Automatic,
Short removed
Boot capacitor
open/missing
Hiccup, after
7 clock counts
Pulled low via
1 kΩ resistor
for hiccup
Forced
Turn-off
Turned off when
fault occurs
Disabled when
fault occurs
Depends on
VOUT
NO
Automatic,
Boot capacitor
replaced
Boot capacitor
shorted
(BOOTUV)
Hiccup, after
120 clock
counts
Pulled low via
1 kΩ resistor
for hiccup
Forced
Turn-off
Turned off
only during
hiccup
Disabled only
during hiccup
Depends on
VOUT
NO Automatic,
Short removed
Output
overvoltage Not affected
Transitions
low via loop
response
Turned-off by
low VCOMP
Pulsed with
Minimum
off-time
Disabled when
VFB
is too high
Pulled low
when VFB is
too high
NO
Automatic,
After VFB returns
to normal range
Output
undervoltage Not affected
Transitions
high via loop
response
Active,
Responds to
VCOMP
Turned on if
BOOT voltage
is too low
Not affected
Pulled low
when VFB is
too low
NO
Automatic,
After VFB returns
to normal range
FSET shorted
to GND or
above 1.0 V
Pulled Low Pulled Low Forced
Turn-off
Forced
Turn-off Disabled Depends on
VOUT
NO Automatic
FB open Not affected
Transitions
low via loop
response
Turned-off by
low VCOMP
Pulsed with
Minimum
off-time
Disabled when
VFB
is too high
Pulled low
when VFB is
too high
NO
Automatic,
After VFB returns
to normal range
Thermal
shutdown
(TSD)
Pulled low
until
VSS < VSSRST
and TSD = 0
Pulled low
until
VSS < VSSRST
and TSD = 0
Forced
Turn-off
Forced
Turn-off Disabled Pulled low NO Automatic,
Part cools down
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
25
Allegro MicroSystems
955 Perimeter Road
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APPLICATION INFORMATION
Design and Component Selection
PWM SWITCHING FREQUENCY (RFSET)
The PWM switching frequency is set by connecting a resistor
from the FSET pin to signal ground. Figure 5 shows the relation-
ship between the typical switching frequency (y-axis) and the
FSET resistor (x-axis). For a required switching frequency (fSW),
the FSET resistor value can be calculated as follows:
Equation 2:
=37037 −2.96
where fSW is in kHz and RFSET is in kΩ.
0
500
1000
1500
2000
2500
3000
0 10 20 30 40 50 60 70 80 90 100110120130140
Switching Frequency, fSW (kHz)
FSET Resistor, R
FSET
(kΩ)
Figure 5: PWM Switching Frequency vs. RFSET
While choosing the PWM switching frequency, the designer should
be aware of the minimum controllable on-time, tON(MIN), of the
ARG81800. If the required on-time of the system is less than the
minimum controllable on-time, pulse skipping will occur and the
output voltage will have increased ripple. The PWM switching
frequency should be calculated using Equation 3, where VOUT is
the output voltage, tON(MIN) is the minimum controllable on-time of
the device (see EC table), and VIN(MAX) is the maximum required
operational input voltage (not the peak surge voltage).
Equation 3:
<×
V
IN(MAX)
t
ON(MIN)
V
OUT
f
SW
If an external clock fSYNC is used for synchronization, the base
switching frequency should be chosen such that pulse skipping will
not occur at the maximum synchronized switching frequency (i.e.,
1.5 × fSYNC should be less than the frequency fSW in Equation 3).
OUTPUT VOLTAGE SETTING
The output voltage of the ARG81800 is determined by connect-
ing a resistive feedback divider (RFB1, RFB2) from the output
node (VOUT) to the FB pin as shown in Figure 6. The feedback
resistors must satisfy the ratio shown in Equation 4 below to
produce the desired output voltage (VOUT).
Equation 4:
1
2
=0.8 −1.0
1% resistors are recommended to maintain the output voltage
accuracy. There are tradeoffs while choosing the value of the
feedback resistors. If the series combination (RFB1 + RFB2) is too
low, the light load efficiency of the regulator will be reduced. So to
maximize the efficiency, it is best to choose large values for feed-
back resistors. On the other hand, large values of feedback resistors
increases the parallel combination (RFB1//RFB2) and makes the
regulator more susceptible to noise coupling onto the FB pin.
RFB1
RFB2
CFF
VOUT
FB IFB
Figure 6: Feedback Divider
with Feedforward Capacitor
Large values of RFB1 also impact the output voltage accuracy of
the regulator. A small amount of leakage current IFB flowing into
the FB pin increases the output voltage beyond the set regulation
voltage. The output voltage of the regulator considering the FB
pin leakage current is given by:
Equation 5:
= 0.8 ×
(
1 + 1
2
)
+1
×
FB pin leakage current increases the output voltage beyond the
set regulation voltage by an amount of IFBRFB1. The larger the
value of RFB1, the larger is the inaccuracy in the output voltage.
A feedforward capacitor (CFF) can be connected in parallel with
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
26
Allegro MicroSystems
955 Perimeter Road
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RFB1 to increase phase margin and loop crossover frequency
for improving transient response of the regulator. Addition of
CFF results in an additional zero and pole in the compensation
network and boosts the loop phase at the crossover frequency. In
general, CFF should be less than 25 pF. While large value of CFF
increases the loop crossover frequency and reduces the phase
margin, very small value of CFF will not have any effect. Optimal
value of CFF can be calculated from the below equation.
Equation 6:
=1
21
× × ×
OUTPUT INDUCTOR (LO)
The ARG81800 incorporates a peak current mode control
technique for closed-loop regulation of the output voltage. It is
common knowledge that, without adequate slope compensation,
a peak current mode controlled regulator will become unstable
when duty cycle is near or above 50%. Hence, to stabilize the
regulator over the complete range of its operating duty cycle,
the ARG81800 employs a fixed internal slope compensation
(SE). Many factors determine the selection of output inductor,
such as switching frequency, output/input voltage ratio, transient
response, and ripple current. A larger value inductor will result in
less ripple current, which also results in lower output ripple volt-
age. However, the larger value inductor will have a larger physi-
cal size, higher series resistance, and/or lower saturation current.
A good rule of thumb for determining the output inductor is to
allow the peak-to-peak ripple current in the inductor to be approxi-
mately 30% of the maximum output current (IOUT(MAX)). The
inductance value can be calculated from the following equation:
Equation 7:
=×∆×
(
1−
)
where ∆ILO is the peak-to-peak inductor ripple current, which
is 0.3 × IOUT(MAX).
A second constraint on inductor value arises from the loop stabil-
ity at duty cycles greater than 50%. Although slope compensa-
tion is primarily required to avoid subharmonic oscillations, the
inductor value calculated from the formula derived by Dr. Ridley,
given below in Equation 8, can critically damp the pole pair at
half the switching frequency.
Equation 8:
≥×
(
1−0.18 ×
( )
)
where LO is output inductance in µH and SE is external slope
compensation provided in the Electrical Characteristics table.
To avoid dropout, VIN(MIN) must be approximately 1 to 1.5 V
above VOUT. Choose output inductor such that its inductance
is greater than the maximum of inductance values calculated in
Equation 7 and Equation 8. However, absolute maximum induc-
tance should not exceed 1.1 × VOUT / SE(min).
The saturation current of the inductor should be higher than the
peak current capability of the ARG81800. Ideally, for output
short-circuit conditions, inductor should not saturate, given the
highest peak current limit (ILIMHSx) at minimum duty cycle. At
the very least, the output inductor should not saturate with the
peak operating current according to the following equation:
Equation 9:
ILIMHSx(MAX)
−
(
×
1.15 × × ( )
)
>
ISAT_Lo
where tON(MIN) is the minimum on-time provided in the Electri-
cal Characteristics table.
The typical DC output current capability of the regulator at any
given duty cycle (D) is:
Equation 10:
=−×−×(1−)
2 × ×
I
OUT(TYP)
I
LIMHSx(TYP)
After an inductor is chosen, it should be tested during output
short-circuit conditions. The inductor current should be moni-
tored using a current probe. A good design should ensure neither
the inductor nor the regulator are damaged when the output is
shorted to ground at maximum input voltage and the highest
expected ambient temperature.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
27
Allegro MicroSystems
955 Perimeter Road
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OUTPUT CAPACITORS (CO)
The output capacitor of switching regulators filter the output volt-
age to provide an acceptable level of ripple on the output voltage,
and they also store energy to help maintain voltage regulation
during a load transient. The voltage rating of the output capacitors
must support the output voltage with sufficient design margin.
The output voltage ripple (ΔVOUT ) is a function of the output
capacitor parameters: CO, ESRCO, and ESLCO:
Equation 11:
∆=∆× + −×
+∆
8 × ×
The type of output capacitors determine which terms of Equa-
tion 11 are dominant. For ceramic output capacitors, ESRCO and
ESLCO are virtually zero, so the output voltage ripple will be
dominated by the third term of Equation 11. The value of CO can
be calculated as:
Equation 12:
≥∆
8 × × ∆
Voltage ripple of a regulator using ceramic output capacitors
can be reduced by increasing the total capacitance, reducing the
inductor current ripple, or increasing the switching frequency.
For electrolytic output capacitors, the value of capacitance will
be relatively high, so the third term in Equation 11 will be very
small and the output voltage ripple will be determined primarily
by the first two terms:
Equation 13:
∆=∆× + −×
Voltage ripple of a regulator using electrolytic output capacitors
can be reduced by: decreasing the equivalent ESRCO and ESLCO
by using a high quality capacitor, adding more capacitors in par-
allel, or reducing the inductor current ripple.
As the ESR of some electrolytic capacitors can be quite high,
Allegro recommends choosing a quality capacitor for which
the ESR or the total impedance is clearly documented in the
capacitor datasheet. Also, ESR of electrolytic capacitors usually
increases significantly at cold ambient temperatures, as much as
10 times, which increases the output voltage ripple and in most
cases reduces the stability of the system.
The transient response of the regulator depends on the quantity
and type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors in
parallel or by using higher quality capacitors. At the instant of a
fast load transient (high diO/dt), the change in the output voltage,
using electrolytic output capacitors, is:
Equation 14:
∆=∆× + ×
When ceramic capacitors are used in the output, the output
voltage deviation during load transients depends on the bulk
output capacitance along with various other factors. To calculate
the bulk ceramic capacitance required, the entire load transient
duration can be divided into two stages: large signal and small
signal. During large signal load transients, immediately after the
transient event, the output voltage deviates from the nominal
value due to large mismatch in the load current requirement and
the inductor current. The output voltage deviation during this
interval is maximum and depends on output inductor, bulk output
capacitance, and closed-loop crossover frequency. For designs
with higher crossover frequency, the controller typically saturates
the duty cycle, i.e., either minimum or maximum. For a chosen
output inductor and crossover frequency values, the output volt-
age deviation can be minimized by increasing the output bulk
capacitance. In the case of a buck converter, operating with a low
duty cycle, the step-down load transient is more severe and hence
the output capacitance should be determined for this scenario.
The bulk ceramic output capacitance required is given by:
Equation 15:
,=∆2×
2 × × ∆,
where ∆IO is the magnitude of the change in the load current,
∆VOUT,spec is the maximum allowed output voltage deviation
during load transient event. Gradually, as the mismatch between
the load current and the inductor current becomes small, the
output voltage deviation also reduces, resembling a small signal
transient event. Eventually, during small signal transient interval,
the error amplifier brings the output voltage back to its nominal
value. The speed with which the error amplifier brings the output
voltage back into regulation depends mainly on the loop cross-
over frequency. A higher crossover frequency usually results in a
shorter time to return to the nominal set voltage.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
28
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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OUTPUT VOLTAGE RIPPLE – ULTRALOW-IQ
LP MODE
After choosing output inductor and output capacitor(s), it is
important to calculate the output voltage ripple (VPP(LP)) during
ultralow-IQ LP mode. With ceramic output capacitors, the output
voltage ripple in PWM mode is usually negligible, but this is not
the case during LP mode.
In LP mode, the peak inductor current during on-time of the high-
side switch is limited to IPEAK(LP). Also, in LP mode, the low-side
switch is constantly turned off thereby forcing the regulator to
operate in Discontinuous Conduction Mode (DCM) in order to
reduce switching losses. A LP comparator monitors the output
voltage on the FB pin and allows the regulator to switch until the
FB pin voltage is greater than 0.5% of its nominal value (0.8 V).
When FB voltage is greater than 0.804 V, the ARG81800 coasts
by terminating the switching pulses.
During coasting, the device shuts down most of its internal con-
trol circuitry to ensure very low quiescent current is drawn from
the input. The number of switching pulses, in LP mode, required
to coast the device depend on various factors including: input
voltage, output voltage, load current, output inductor, and output
capacitor. If ARG81800 starts coasting after a single switching
pulse, then the output voltage ripple would be dictated by this
single pulse. The peak inductor current without slope compensa-
tion (IPEAK_LO) is given by:
Equation 16:
=
1 + ×
−
IPEAK(LP)
I
PEAK_LO
where IPEAK(LP) is the peak inductor current, specified in the
Electrical Characteristics table, at which device enters into LP
mode. Referring to Figure 7, on-time and off-time calculations
are given as:
Equation 17:
=_×
− − ×
(
( ) +( )
)
Equation 18:
=_×
VOUT
ILo
VPP(LP)
IOUT
IPEAK_Lo
t
ON
t
OFF
t
1
t
2
Figure 7: Output Voltage Ripple in LP Mode
During on-time interval, the length of time for the inductor cur-
rent to rise from 0 A to IOUT is:
Equation 19:
1=×
− − _×
(
( ) +( )
)
During off-time interval, the length of time for the inductor cur-
rent to fall from IOUT to 0 A is:
Equation 20:
2=×
Given the peak inductor current (IPEAK_L) and the rise and fall
times (tON and tOFF) for the inductor current, the output voltage
ripple for a single switching pulse can be calculated as follows:
Equation 21:
( ) =_−
2 × × ( + −1−2)
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
29
Allegro MicroSystems
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INPUT CAPACITORS
Three factors should be considered when choosing the input
capacitors. First, the capacitors must be chosen to support the
maximum expected input surge voltage with adequate design
margin. Second, the capacitor RMS current rating must be higher
than the expected RMS input current to the regulator. Third, the
capacitors must have enough capacitance and a low enough ESR
to limit the input voltage dV/dt to much less than the hysteresis
of the UVLO circuitry (250 mV nominal) at maximum loading
and minimum input voltage. The input capacitors must deliver an
RMS current (IRMS) given by:
Equation 22:
= ×
√
× (1 −)
where the duty cycle (D) is defined as:
Equation 23:
≈
Figure 8 shows the normalized input capacitor RMS current
versus duty cycle. To use this graph, simply find the operational
duty cycle (D) on the x-axis and determine the input/output cur-
rent multiplier on the y-axis. For example, at a 20% duty cycle,
the input/output current multiplier is 0.40. Therefore, if the
regulator is delivering 1.0 A of steady-state load current, the input
capacitor(s) must support 0.40 × 1.0 A or 0.4 A RMS.
The input capacitor(s) must limit the voltage deviations at the
VIN pin to significantly less than the device UVLO hysteresis
during maximum load and minimum input voltage condition.
The following equation allows to calculate the minimum input
capacitance required:
Equation 24:
≥× × (1 −)
0.85 × ×∆( )
where ΔVIN(MIN) is chosen to be much less than the hysteresis
of the VIN UVLO comparator (ΔVIN(MIN) ≤ 150 mV is recom-
mended), and fSW is the nominal PWM frequency. The D × (1–D)
term in Equation 22 has an absolute maximum value of 0.25 at
50% duty cycle. So, for example, a very conservative design
based on IOUT = 1.0 A, fSW = 0.5 MHz, D × (1–D) = 0.25, and
ΔVIN =150 mV yields:
≥1.0 × 0.25
0.85 × 0.5 × 106× 150 × 10−3= 1.95 µ
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0 10 20 30 40 50 60 70 80 90 100
IRMS/IOUT
Duty Cycle, D(%)
Figure 8: Normalized Input Capacitor Ripple
versus Duty Cycle
A good design should consider the DC bias effect on a ceramic
capacitor: as the applied voltage approaches the rated value, the
capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much
as 90% reduction), so these types should be avoided. The X5R,
X7R, and X8R type capacitors should be the primary choices due
to their stability versus both DC bias and temperature.
For all ceramic capacitors, the DC bias effect is even more pro-
nounced on smaller sizes of device case, so a good design uses
the largest affordable case size (such as 1206 or 1210). Also, it is
advisable to select input capacitors with plenty of design margin
in the voltage rating to accommodate the worst case transient
input voltage (such as a load dump as high as 40 V for automo-
tive applications).
BOOTSTRAP CAPACITOR
A bootstrap capacitor must be connected between the BOOT and
SW pins to provide floating gate drive to the high-side MOSFET.
Usually, 47 nF is an adequate value. This capacitor should be a
high-quality ceramic capacitor, such as an X5R or X7R, with a
voltage rating of at least 16 V.
SOFT START AND HICCUP MODE TIMING (CSS)
The soft start time of the ARG81800 is determined by the
value of the capacitance (CSS) at the soft start pin. When the
ARG81800 is enabled, the SS pin sources the charging current
ISS and the voltage across the soft start capacitor CSS starts ramp-
ing upward from 0 V. However, PWM switching will begin only
after the voltage across the CSS rises above 400 mV.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
30
Allegro MicroSystems
955 Perimeter Road
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The soft start delay (tdSS) can be calculated using the equation
below:
Equation 25:
= ×
(
0.4
)
d
If the device is starting with a very heavy load, a very fast soft
start time may cause the regulator to exceed the pulse-by-pulse
overcurrent threshold. This occurs because the sum of the full
load current, the inductor ripple current, and the additional cur-
rent required to charge the output capacitors
Equation 26:
= ×
is higher than the pulse-by-pulse current threshold. This phenom-
enon is more pronounced when using high value electrolytic type
output capacitors. To avoid prematurely triggering hiccup mode,
the soft start capacitor (CSS) should be calculated according to
equation below:
Equation 27:
≥× ×
0.8 ×
where VOUT is the output voltage, CO is the output capacitance,
ICO is the amount of current allowed to charge the output capaci-
tance during soft start (0.1 A < ICO < 0.3 A is recommended). The
soft start time (tSS) can be calculated as below:
Equation 28:
= 0.8 ×
( )
Higher values of ICO result in faster soft start times. However,
lower values of ICO ensure that hiccup mode is not falsely trig-
gered. Allegro recommends starting the design with an ICO of
0.1 A and increasing it only if the soft start time is too slow. If a
non-standard capacitor value for CSS is calculated, the next larger
value should be used.
When the device is in hiccup mode, the soft start capacitor is used
as a timing capacitor and sets the hiccup period. The soft start pin
charges the soft start capacitor with ISS during a startup attempt
and discharges the same capacitor with IHIC between startup
attempts. Because the ratio of ISS:IHIC is approximately 4:1, the
time between hiccups will be about four times as long as the
startup time. Therefore, the effective duty cycle will be very low
and the junction temperature will be kept low.
COMPENSATION COMPONENTS (RZ, CZ, AND CP)
The objective of the selection of the compensation components is
to ensure adequate stability margins to avoid instability issues, to
maintain a high loop gain at DC to achieve excellent output volt-
age regulation and to obtain a high loop bandwidth for superior
transient response. To a first order, the closed-loop model of a
peak current mode controlled regulator can be broken into two
blocks as shown below in Figure 9.
IOUT
CORL
VOUT
gmPOWER
A/V
RFB1
RFB2
gm=
750 µA/V
0.8 V
Reference
FB Pin
RO
RZ
CZ
CP
COMP
Pin
Error Amplifier
Power Stage
VC
VFB
Figure 9: Closed-Loop Model of Peak Current Mode
Controlled Regulator
POWER STAGE
The power stage includes the output filter capacitor, CO, the
equivalent load, RL, and the inner current loop which consists of
the PWM modulator and the output inductor, LO. The inner current
loop, with a first-order approximation, can be effectively modeled
as a transconductance amplifier that converts the control voltage
(VC) from the error amplifier to a peak output inductor current with
an equivalent gain gmPower. Although, the peak current through the
inductor is being controlled—neglecting the inductor ripple cur-
rent—it is acceptable to replace it with output current IOUT.
From a small-signal point of view, the current mode control loop
behaves like a current source and therefore the power inductor
can be ignored. The output capacitor integrates the ripple current
through the inductor, effectively forming a single pole with the
output load. A control-to-output transfer function between the
control voltage (VC), output of the error amplifier in the feed-
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
31
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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back loop, and the regulator output voltage (VOUT) describes the
dynamics of the power stage. The DC gain of the power stage,
i.e., control-to-output transfer function, is given by:
Equation 29:
( ) = ×
where gmPOWER is the equivalent gain of the inner current loop
(specified in the Electrical Characteristics table) and RL is the
load resistance.
The control-to-output transfer function has a pole fP(CO), formed by
the output capacitance (CO) and load resistance (RL), located at:
Equation 30:
( ) =1
2××
The control-to-output transfer function has a zero fZ(CO), formed
by the output capacitance (CO) and its associated ESR, located at:
Equation 31:
( ) =1
2× ×
For a design with very low-ESR type output capacitors (such as
ceramic or OSCON output capacitors), the ESR zero, fZ(CO), is
usually at a very high frequency so it can be ignored. On the other
hand, with high-ESR electrolytic output capacitors, the ESR zero
falls below or near the 0 dB crossover frequency of the closed-loop;
hence, it should be cancelled by the pole formed by the CP capacitor
and the RZ resistor discussed and identified later as fP2(EA).
ERROR AMPLIFIER
The error amplifier, as a part of the output voltage feedback loop,
comprises a transconductance amplifier with an external Type-II
compensation formed by RZ-CZ-CP network. A Type-II compen-
sated error amplifier introduces two poles and a zero. The place-
ment of these poles and zero should be such that the closed-loop
system has sufficient stability margins and high bandwidth (loop
crossover frequency) and provides optimal transient response.
The DC gain of the feedback loop, including the error amplifier
and the feedback resistor divider is given by:
Equation 32:
( ) = × 2
1
+
2
=×
where A
VOL is the open-loop DC gain of the error amplifier (spec-
ified in the Electrical Characteristics table).
The DC gain of the error amplifier is 65 dB (equivalent to 1778)
and with a gm value of 750 μA/V, the effective output impedance,
RO, of the amplifier is:
Equation 33:
=1778
750 × 10−6= 2.37 Ω
Typically, RO ≫ RZ and CZ ≫ CP, which simplifies the derivation
of the transfer function of the Type-II compensated error ampli-
fier. The transfer function has a (very) low frequency pole fP1(EA)
dominated by the error amplifier output impedance RO and the
compensation capacitor CZ:
Equation 34:
1( ) =1
2××
The transfer function of the Type-II compensated error amplifier
also has a zero at frequency fZ(EA) caused by the resistor RZ and
the capacitor CZ:
Equation 35:
( ) =1
2××
Lastly, the transfer function of the Type-II compensated error
amplifier has a (very) high frequency pole fP2(EA) dominated by
the resistor RZ resistor and the capacitor CP:
Equation 36:
2( ) =1
2××
Although there are many different approaches for designing the
feedback loop, a good design approach attempts to maximize the
closed-loop system stability, while providing a high bandwidth
and optimized transient response. A generalized tuning procedure
is presented below to systematically determine the values of com-
pensation components (RZ, CZ, and CP) in the feedback loop.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
32
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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A GENERALIZED TUNING PROCEDURE
1. Choose the system bandwidth (fC). This is the frequency at
which the magnitude of the gain crosses 0 dB. Recommended
values for fC, based on the PWM switching frequency, are
in the range fSW / 20 < fC < fSW / 10. A higher value of fC
generally provides a better transient response, while a lower
value of fC generally makes it easier to obtain higher gain and
phase margins.
2. Calculate the RZ resistor value. This sets the system band-
width (fC):
Equation 37:
= × × 2×
×
3. Calculate the range of values for the CZ capacitor. Use the
following:
Equation 38:
4
2××< < 1
2×× 1.5 × ( )
To maximize system stability, i.e., high gain and phase mar-
gins, use a higher value of CZ. To optimize transient recovery
time, although at the expense of low stability margins, use a
lower value of CZ.
4. Calculate the frequency of the ESR zero fZ(CO) formed by the
output capacitor(s) by using Equation 31 (repeated here):
( ) =1
2× ×
If fZ(CO) is at least one decade higher than the target crossover
frequency fC, then fZ(CO) can be ignored. This is usually the case
for a design using ceramic output capacitors. Use Equation 36
to calculate the value of CP by setting fP2(EA) to either 5 × fC or
fSW / 2, whichever is higher.
Alternatively, if fZ(CO) is near or below the target crossover
frequency fC, then use Equation 36 to calculate the value of CP by
setting fP2(EA) equal to fZ(CO). This is usually the case for a design
using high ESR electrolytic output capacitors.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
33
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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C
O
R
FB2
R
FB1
C
FF
L
O
R
Z
C
Z
C
P
V
OUT
BOOT
COMP
GND
VIN
PGND
FB
BIAS
SW
VREG
C
IN
4.7 μF
FSET
R
FSET
PGOOD
10 kΩ
0.1 μF
Figure 10: Applications Schematic Showing Component Locations
Table 3: Recommended External Components (for load transient slew rate < 50 mA/µs)
ARG81800
VOUT fSW RFSET LOCO
COMP Components
(BW ~75 kHz / 30 kHz, PM > 60 deg) FB Components
CIN(MIN)
RZCZCPRFB1 RFB2 CFF
5.0 V 2.15 MHz 14.3 kΩ 4.7 µH 20 µF 51.1 kΩ 1.2 nF 82 pF 732 kΩ 137 kΩ 4.7 pF 1.0 µF
3.3 V 2.15 MHz 14.3 kΩ 3.3 µH 20 µF 40.2 kΩ 2.2 nF 68 pF 301 kΩ 95.3 kΩ 4.7 pF 1.0 µF
5.0 V 400 kHz 90.9 kΩ 22 µH 33 µF 24.9 kΩ 2.2 nF 100 pF 732 kΩ 137 kΩ 4.7 pF 4.7 µF
3.3 V 400 kHz 90.9 kΩ 15 µH 47 µF 29.4 kΩ 2.2 nF 47 pF 301 kΩ 95.3 kΩ 4.7 pF 4.7 µF
ARG81800-1
VOUT fSW RFSET LOCO
COMP Components
(BW ~75 kHz / 30 kHz, PM > 60 deg) FB Components
CIN(MIN)
RZCZCPRFB1 RFB2 CFF
5.0 V 2.15 MHz 14.3 kΩ 9.1 µH 20 µF 150 kΩ 1.0 nF 47 pF 732 kΩ 137 kΩ 4.7 pF 1.0 µF
3.3 V 2.15 MHz 14.3 kΩ 7.5 µH 20 µF 60.4 kΩ 1.0 nF 33 pF 301 kΩ 95.3 kΩ 4.7 pF 1.0 µF
5.0 V 400 kHz 90.9 kΩ 43 µH 33 µF 51.1 kΩ 2.2 nF 47 pF 732 kΩ 137 kΩ 4.7 pF 4.7 µF
3.3 V 400 kHz 90.9 kΩ 33 µH 47 µF 49.9 kΩ 2.2 nF 47 pF 301 kΩ 95.3 kΩ 4.7 pF 4.7 µF
Note 1: Components were chosen to maintain LP ripple voltage and minimize voltage droop during LP to PWM changeover.
Note 2: CFF is chosen to offset 15 to 25 pF of stray capacitance at the FB pin.
Table 4: Recommended External Components (for load transient slew rate > 50 mA/µs)
ARG81800
VOUT fSW RFSET LOCO
COMP Components
(BW ~75 kHz / 30 kHz, PM > 60 deg) FB Components
CIN(MIN)
RZCZCPRFB1 RFB2 CFF
5.0 V 2.15 MHz 14.3 kΩ 4.7 µH 42 µF 10.0 kΩ 5.6 nF 10 pF 732 kΩ 137 kΩ 4.7 pF 1.0 µF
3.3 V 2.15 MHz 14.3 kΩ 3.3 µH 42 µF 8.06 kΩ 9.1 nF 10 pF 301 kΩ 95.3 kΩ 4.7 pF 1.0 µF
5.0 V 400 kHz 90.9 kΩ 22 µH 55 µF 5.11 kΩ 9.1 nF 10 pF 732 kΩ 137 kΩ 4.7 pF 4.7 µF
3.3 V 400 kHz 90.0 kΩ 15 µH 69 µF 5.23 kΩ 9.1 nF 10 pF 301 kΩ 95.3 kΩ 4.7 pF 4.7 µF
ARG81800-1
VOUT fSW RFSET LOCO
COMP Components
(BW ~75 kHz / 30 kHz, PM > 60 deg) FB Components
CIN(MIN)
RZCZCPRFB1 RFB2 CFF
5.0 V 2.15 MHz 14.3 kΩ 9.1 µH 42 µF 30.1 kΩ 5.6 nF 10 pF 732 kΩ 137 kΩ 4.7 pF 1.0 µF
3.3 V 2.15 MHz 14.3 kΩ 7.5 µH 42 µF 12.1 kΩ 5.6 nF 10 pF 301 kΩ 95.3 kΩ 4.7 pF 1.0 µF
5.0 V 400 kHz 90.9 kΩ 43 µH 55 µF 10.0 kΩ 9.1 nF 10 pF 732 kΩ 137 kΩ 4.7 pF 4.7 µF
3.3 V 400 kHz 90.9 kΩ 33 µH 69 µF 10.0 kΩ 9.1 nF 10 pF 301 kΩ 95.3 kΩ 4.7 pF 4.7 µF
Note 1: Components were chosen to maintain LP ripple voltage and minimize voltage droop during LP to PWM changeover.
Note 2: CFF is chosen to offset 15 to 25 pF of stray capacitance at the FB pin.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
34
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
The total power dissipated in the ARG81800 is the sum of the
power dissipated from the VIN supply current (PIN), the power
dissipated due to the switching of the high-side power MOS-
FET (PSWH), the power dissipated due to the conduction of rms
current in the high-side MOSFET (PCH) and low-side MOSFET
(PCL), power dissipated due to the low-side MOSFET body diode
conduction during the non-overlap time (PNO) and the power dis-
sipated by both high-side and low-side gate drivers (PDRIVER).
The power dissipated from the VIN supply current (with BIAS pin
open) can be calculated using Equation 39:
Equation 39:
= × ,
+(−)×(
H
+)×
L
where VIN is the input voltage, IIN,PWM is the input quiescent
current drawn by the ARG81800 in PWM mode (see EC table),
VGS is the MOSFET gate drive voltage (typically 4.8 V), QGH
and QGL are the internal high-side and low-side MOSFET gate
charges (approximately 0.3 nC and 0.6 nC, respectively), and
fSW is the PWM switching frequency.
The power dissipated by the high-side MOSFET during PWM
switching can be calculated using Equation 40:
Equation 40:
=× ×
(
+
)
×
2
where VIN is the input voltage, IOUT is the regulator output cur-
rent, fSW is the PWM switching frequency, tr and tf are the rise
and fall times measured at the switch node.
The exact rise and fall times at the SW node will depend on the
external components and PCB layout, so each design should be
measured at full load. Approximate values for both tr and tf range
from 10 to 20 ns.
The power dissipated in the high-side MOSFET while it is con-
ducting can be calculated using Equation 41:
Equation 41:
=,
2×( )
=
()
×
(
2+∆
2
12
)
×( )
Similarly, the conduction losses dissipated in the low-side MOSFET
while it is conducting can be calculated by the following equation:
Equation 42:
=,
2×( )
=
(
1−
)
×
(
2+∆
2
12
)
×( )
where IOUT is the regulator output current, ΔILO is the peak-
to-peak inductor ripple current, RDS(ON)H is the on-resistance
of the high-side MOSFET, RDS(ON)L is the on-resistance of the
low-side MOSFET.
The RDS(ON) of both MOSFETs have some initial tolerance plus an
increase from self-heating and elevated ambient temperatures. A
conservative design should accommodate an RDS(ON) with at least
15% initial tolerance plus 0.39%/°C increase due to temperature.
The power dissipated in the low-side MOSFET body diode dur-
ing the non-overlap time can be calculated as follows:
Equation 43:
= × × 2 × ×
where VSD is the source-to-drain voltage of the low-side MOS-
FET (typically 0.60 V), and tNO is the non-overlap time (15 ns
typical).
The power dissipated in the internal gate drivers can be calcu-
lated using Equation 44:
Equation 44:
=(+)××
where VGS is the gate drive voltage (typically 4.8 V).
Finally, the total power dissipated in the ARG81800 is given by:
Equation 45:
= + + + + +
The average junction temperature (TJ) can be calculated as follows:
Equation 46:
= × +
where PTOTAL is the total power dissipated from Equation 45,
RθJA is the junction-to-ambient thermal resistance (37°C/W on
a 4-layer PCB), and TA is the ambient temperature.
RθJA includes the thermal impedance from junction to case, RθJC
and the thermal impedance from case to ambient, RθCA. RθCA is
generally determined by the amount of copper that is used under-
neath and around the device on the printed circuit board.
POWER DISSIPATION AND THERMAL CALCULATIONS
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
35
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
The maximum allowed power dissipation depends on how effi-
ciently heat can be transferred from the junction to the ambient
air, i.e., minimizing the RθJA. As with any regulator, there are
limits to the amount of heat that can be dissipated before risking
thermal shutdown. There are tradeoffs between ambient operat-
ing temperature, input voltage, output voltage, output current,
switching frequency, PCB thermal resistance, airflow, and other
nearby heat sources. Even a small amount of airflow will reduce
the junction temperature considerably.
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
36
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
The ARG81800 is designed to minimize electromagnetic (EM)
emissions when proper PCB layout techniques are adopted. A good
PCB layout is also critical for the ARG81800 to provide clean and
stable output voltages. Design guidelines for EMI/EMC-aware
PCB layout are presented below. Figure 10 shows a typical appli-
cation schematic of a synchronous buck regulator IC with critical
power paths/loops.
1. Place the ceramic input capacitors as close as possible to the
VIN pin and PGND pins to make the loop area minimal, and
the traces of the input capacitors to VIN pin should be short
and wide to minimize the inductance. This critical loop is
shown as trace 1 in Figure 11. The bulk/electrolytic input ca-
pacitor can be located further away from VIN pin. The input
capacitors and ARG81800 IC should be on the same side of
the board with traces on the same layer.
2. The loop from the input supply and capacitors, through the high-
side MOSFET, into the load via the output inductor, and back to
ground should be minimized with relatively wide traces.
3. When the high-side MOSFET is o, free-wheeling cur-
rent ows from ground, through the synchronous low-side
MOSFET, into the load via the output inductor, and back to
ground. This loop should be minimized and have relatively
wide traces. This loop is shown as trace 2 in Figure 11.
4. Place the output capacitors relatively close to the output induc-
tor (LO) and the ARG81800. Ideally, the output capacitors, out-
put inductor and the ARG81800 should be on the same layer.
Connect the output inductor and the output capacitors with
a fairly wide trace. The output capacitors must use a ground
plane to make a very low-inductance connection to the GND.
These critical connections are shown as trace 3 in Figure 11.
5. Place the output inductor (LO) as close as possible to the SW
pin with short and wide traces. This critical trace is shown as
trace 4 in Figure 11. The voltage at SW node transitions from
0 V to VIN with a high dv/dt rate. This node is the root cause of
many noise issues. It is suggested to minimize the SW copper
area to minimize the coupling capacitance between SW node
and other noise-sensitive nodes; however, the SW node area
cannot be too small in order to conduct high current. A ground
copper area can be placed underneath the SW node to provide
additional shielding. Also, noise sensitive analog signals (like
FB, COMP) should not be routed near the SW polygon.
6. Place the feedback resistor divider (RFB1 and RFB2) very
close to the FB pin. Route the ground side of RFB2 as close as
possible to the ARG81800.
7. Place the compensation components (RZ, CZ, and CP) as
close as possible to the COMP pin. Also route the ground side
of CZ and CP as close as possible to the ARG81800.
8. Place the FSET resistor as close as possible to the FSET pin;
Place the soft start capacitor CSS as close as possible to the
SS pin.
9. The output voltage sense trace (from VOUT to RFB1) should
be routed as close as possible to the load to obtain the best
load regulation.
10. Place the bootstrap capacitor (CBOOT) near the BOOT pin
and keep the routing from this capacitor to the SW polygon
as short as possible. This critical trace is shown as trace 5 in
Figure 11.
11. A two-layer (TOP and BOT) PCB is sucient for better
thermal performance.
12. When connecting the input and output ceramic capacitors,
use multiple vias to GND planes and place the vias as close
as possible to the pads of the components. Do not use thermal
reliefs around the pads for the input and output ceramic
capacitors.
13. Place all the components on the TOP layer and limit the rout-
ing only to the top layer. Use BOT layer as GND plane.
14. To minimize thermal resistance, extend ground planes on
TOP layer as much as possible and use thermal vias to con-
nect them to GND plane in BOT layer.
15. To minimize PCB losses and improve system eciency, the
power traces should be as wide as possible.
16. EMI/EMC issues are always a concern. Allegro recommends
having placeholder for an RC snubber from SW to ground.
The resistor should be 0805 or 1206 size.
EMI/EMC AWARE PCB DESIGN
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
37
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 11: PCB Layout for Minimizing EM Emissions
VOUT
EN VIN
PGOOD
FB
BIAS
PGND
VREG
SYNC
IN
FSET
BOOT
SS
GND
SW
COMP
C
SS
R
Z
C
Z
C
P
C
IN
C
O
R
FB1
R
FB2
C
Boot
L
O
C
REG
R
FSET
4
1
13
Internal
Regulator
VREG
R
Pullup
Boot
Regulator
2
CLK
OUT
5
R
L
Figure 12: 3.3 V, 1 A Buck Regulator with Input EMI Filter
BOOT
PWM/AUTO
SYNCIN
EN
GND
VIN
PGND
BIAS
PGOOD
SW
FSET
SS
VREG
10 kΩ
14.3 kΩ
3.3 μH, 2.5 A
301 kΩ
VBAT: 3.5 V to 36 V
3.3 V / 1 A
CLKOUT
COMP
30.1 kΩ
FB
10 Ω
0.25 W
0.1 μF
16 V, X7R
2 × 10 μF
16 V, X7R
10 pF
50 V, COG
2.2 nF
50 V, COG
4.7 pF
50 V, COG
0.1 μF
16 V, X7R
22 nF
16 V, X7R
4.7 μF
16 V, X7R
0.1 μF
50 V, X7R
4.7 μF
50 V, X7R
10 μF
50 V, X7R
10 μF
50 V, X7R
4.7 μF
50 V, X7R
0.1 μF
50 V, X7R
6.8 μH, 2.5 A
680 pF
50 V, COG
95.3 kΩ
fSW = 2.15 MHz
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
38
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 14: Radiated EMI – Biconical Antenna
VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 2.15 MHz
Figure 13: Radiated EMI – Biconical Antenna
VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 2.15 MHz
0
5
10
15
20
25
30
35
40
45
30M 50 60 70 80 90 100M 200 330M
Level in dBµV/m
Frequency in Hz
EN 55025 (2008) Automotive Components PK
EN 55025 (2008) Automotive Components AV
Horizontal Polarization
0
5
10
15
20
25
30
35
40
45
30M 50 60 70 80 90 100M 200 330M
Level in dBµV/m
Frequency in Hz
EN 55025 (2008) Automotive Components PK
EN 55025 (2008) Automotive Components AV
Vertical Polarization
Figure 15: Radiated EMI – Monopole Antenna
VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 2.15 MHz
-5
0
5
10
15
20
25
30
35
40
45
50
150k 300 400 500 800 1M 2M 3M 4M 5M 6 8 10M 20M 30M
Level in dBµV/m
Frequency in Hz
EN 55025 (2008) Automotive Radiated Class 5 PK
EN 55025 (2008) Automotive Radiated Class 5 AV
-10
0
10
20
30
40
50
60
70
80
150k 300 400500 8001M 2M 3M 4M5M 6 8 10M 20M 30M 40 50 60 80 108M
Level in dBµV
Frequency in Hz
EN 55025 (2008) Automotive Voltage PK
EN 55025 (2008) Automotive Voltage AV
Figure 16: Conducted EMI
VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 2.15 MHz
EMI test results are obtained using standard evaluation board with Input EMI filter and Snubber (see Figure 12 above).
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
39
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
TYPICAL REFERENCE DESIGNS
Figure 17: Reference Design 1 – AUTO Mode with CLKOUT enabled
VIN = 3.5 to 36 V, VOUT = 3.3 V, IOUT = 0 to 1.0 A, fSW = 2.15 MHz
BOOT
COMP
PWM/AUTO
SYNCIN
EN
GND
VIN
PGND
FB
BIAS
CLKOUT
PGOOD
SW
FSET
SS
R6
C8
R4
L1
R2
R3
C7
R5
C10 C11
C9
C5
C4
VBAT: 3.5 V to 36 V
C1
C2 C3
C6
R1
VREG
VOUT
ARG81800
U1
Table 5: Reference Design 1 – Recommended Bill of Materials
Designator Description Value Footprint Manufacturer Manufacturer P/N
C1 Capacitor, X7R 0.1 µF, 50 V 0603 Murata GCM188R71H104KA57D
C2 Capacitor, X7R 4.7 µF, 50 V 1206 Murata GRJ31CR71H475KE11L
C3 Capacitor, X7R 0.1 µF, 50 V 0603 Murata GCM188R71H104KA57D
C4 Capacitor, X7R 0.1 µF, 50 V 1206 Murata GCM319R71H104KA37J
C5 Capacitor, X7R 10 µF, 16 V 1210 Murata GRM32DR71C106KA01L
C6 Capacitor, X7R 10 µF, 16 V 1210 Murata GRM32DR71C106KA01L
C7 Capacitor, C0G (NP0) 4.7 pF, 50 V 0603 Murata GCM1885C1H4R7BA16D
C8 Capacitor, X7R 4.7 µF, 16 V 0805 Murata GCJ21BR71C475KA01L
C9 Capacitor, X7R 22 nF, 50 V 0603 Murata GRM188R71H223KA01D
C10 Capacitor, X7R 2.2 nF, 50 V 0603 Murata GCM188R71H222KA37D
C11 Capacitor, C0G (NP0) 10 pF, 50 V 0603 Kemet C0603C100J5GACTU
L1 Inductor 3.3 µH, 2 A 5.2 mm × 5.2 mm Wurth Electronics 74437334033
R1 Resistor, 1%, 1/10 W 10 kΩ 0603 Panasonic ERJ-3EKF1002V
R2 Resistor, 1%, 1/10 W 301 kΩ 0603 Panasonic ERJ-3EKF3013V
R3 Resistor, 1%, 1/10 W 95.3 kΩ 0603 Panasonic ERJ-3EKF9532V
R4 Resistor, 1%, 1/10 W 14.3 kΩ 0603 Panasonic ERJ-3EKF1432V
R5 Resistor, 1%, 1/10 W 30.1 kΩ 0603 Panasonic ERJ-3EKF3012V
R6 Resistor, 1%, 1/10 W 10 kΩ 0603 Panasonic ERJ-3EKF1002V
U1 Allegro IC ARG81800 QFN20_4x4 Allegro ARG81800KESJSR
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
40
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 18: Reference Design 2 – Forced PWM Mode with CLKOUT disabled
VIN = 3.5 to 36 V, VOUT = 5.0 V, IOUT = 0 to 0.5 A, fSW = 400 kHz
Table 6: Reference Design 2 – Recommended Bill of Materials
Designator Description Value Footprint Manufacturer Manufacturer P/N
C1 Capacitor, X7R 0.1 µF, 50 V 0603 Murata GCM188R71H104KA57D
C2 Capacitor, X7R 4.7 µF, 50 V 1206 Murata GRJ31CR71H475KE11L
C3 Capacitor, X7R 0.1 µF, 50 V 0603 Murata GCM188R71H104KA57D
C4 Capacitor, X7R 0.1 µF, 50 V 1206 Murata GCM319R71H104KA37J
C5 Capacitor, X7R 22 µF, 16 V 1210 Murata GRM32ER71C226MEA8L
C6 Capacitor, X7R 10 µF, 16 V 1210 Murata GRM32DR71C106KA01L
C7 Capacitor, C0G (NP0) 4.7 pF, 50 V 0603 Murata GCM1885C1H4R7BA16D
C8 Capacitor, X7R 4.7 µF, 16 V 0805 Murata GCJ21BR71C475KA01L
C9 Capacitor, X7R 22 nF, 50 V 0603 Murata GRM188R71H223KA01D
C10 Capacitor, X7R 2.2 nF, 50 V 0603 Murata GCM188R71H222KA37D
C11 Capacitor, C0G (NP0) 10 pF, 50 V 0603 Kemet C0603C100J5GACTU
L1 Inductor 47 µH, 2.2A 10 mm × 10 mm Wurth Electronics 7447714470
R1 Resistor, 1%, 1/10 W 10 kΩ 0603 Panasonic ERJ-3EKF1002V
R2 Resistor, 1%, 1/10 W 732 kΩ 0603 Panasonic ERJ-3EKF7323V
R3 Resistor, 1%, 1/10 W 140 kΩ 0603 Panasonic ERJ-3EKF1403V
R4 Resistor, 1%, 1/10 W 90.9 kΩ 0603 Panasonic ERJ-3EKF7152V
R5 Resistor, 1%, 1/10 W 34 kΩ 0603 Panasonic ERJ-3EKF3402V
R6 Resistor, 1%, 1/10 W 10 kΩ 0603 Panasonic ERJ-3EKF1002V
U1 Allegro IC ARG81800-1 QFN20_4x4 Allegro ARG81800KESJSR-1
BOOT
COMP
PWM/AUTO
SYNCIN
EN
GND
VIN
PGND
FB
BIAS
CLKOUT
PGOOD
SW
FSET
SS
R6
C8
R4
L1
R2
R3
C7
R5
C10 C11
C9
C5
C4
VBAT: 3.5 V to 36 V
C1
C2 C3
C6
R1
VREG
VOUT
ARG81800-1
U1
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
41
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
PACKAGE OUTLINE DRAWING
Figure 19: Package ES, 20-pin wettable ank QFN with exposed thermal pad
For Reference Only –Not for Tooling Use
(Reference JEDEC MO-220WGGD)
Dimensions in millimeters
NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.95
C
SEATING
PLANE
C
0.08
21X
20
20
2
1
1
2
20
2
1
A
A
B
C
D
D
C
4.00 ±0.10
2.45 ±0.10
4.00 ±0.10
2.45 ±0.10
4.10
0.30
0.50
4.10
0.75 ±0.05
0.50 BSC
0.40 ±0.10
0.22 ±0.05
2.60
2.60
B
PCB Layout Reference View
Terminal #1 mark area
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier
discretion)
Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to
meet application process requirements and PCB layout tolerances; when mounting
on a multilayer PCB, thermal vias at the exposed thermal pad land can improve
thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Coplanarity includes exposed thermal pad and terminals
0.05 REF
0.08 REF
0.40 ±0.10
0.05 REF
0.08 REF 0.203 REF
Detail A
DETAIL A
0.20
0.25 0.10
40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
42
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Revision History
Number Date Description
– June 11, 2019 Initial release
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
