40 V, 500 mA / 1.0 A Synchronous Buck Regulators
with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
ARG81800
18
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Compensation Components
To stabilize the regulator, a series RC compensation network (RZ
and CZ) must be connected from the output of the error amplifier
(COMP pin) to GND as shown in the applications schematic. In
most instances, an additional low-value capacitor (CP) should
be connected in parallel with the RZ-CZ compensation network
to reduce the loop gain at very high frequencies. However, if
the CP capacitor is too large, the phase margin of the converter
may be reduced. Calculation of RZ, CZ, and CP is covered in the
Component Selection section of this datasheet. If a fault occurs
or the regulator is disabled, the COMP pin is pulled to GND via
the approximately 1 kΩ internal resistor and PWM switching is
inhibited.
Power MOSFETs
The ARG81800 includes a 500 mΩ, high-side N-channel MOS-
FET and a 210 mΩ, low-side N-channel MOSFET to provide
synchronous rectification. When the ARG81800 is disabled via
the EN input being low or a fault condition, its output stage is tri-
stated by turning off both the upper and lower MOSFETs.
BOOT Regulator
The ARG81800 includes a BOOT regulator to supply the power
for a high-side MOSFET gate driver. The voltage across the
BOOT capacitor is typically 4.8 V. If the BOOT capacitor is
missing, the device will detect a BOOT overvoltage. Similarly,
if the BOOT capacitor is shorted, the ARG81800 will detect a
BOOT undervoltage. Also, the BOOT regulator has a current
limit to protect itself during a short-circuit condition.
Soft Start (Startup) and Inrush Current Control
The soft start function controls the inrush current at startup. The
soft start pin (SS) is connected to GND via a capacitor. When the
ARG81800 is enabled and all faults are cleared, the SS pin sources
the charging current ISS and the voltage on the soft start capacitor
CSS starts ramping upward from 0 V. When the voltage at the soft
start pin exceeds the soft start offset voltage (SS Offset), typically
400 mV, the error amplifier will ramp up its output voltage above
the PWM Ramp Offset. At this instant, the top and bottom MOS-
FETs will begin switching. There is a small delay (tdSS) from the
moment EN pin transitioning high to the moment soft start voltage
reaching 400 mV to initiate PWM switching.
Immediately after the start of PWM switching, the error amplifier
will regulate the voltage at the FB pin to the soft start pin voltage
minus approximately 400 mV. During the active portion of soft
start, the voltage at the SS pin will rise from 400 mV to 1.2 V (a
difference of 800 mV), the voltage at the FB pin will rise from
0 V to 800 mV, and the regulator output voltage will rise from
0 V to the set voltage determined by the feedback resistor divider.
During startup, PWM switching frequency is reduced to 25% of
fSW while FB is below 200 mV. If FB voltage is above 200 mV
but below 400 mV, the switching frequency is 50% of fSW. At
the same time, the transconductance of the error amplifier, gm,
is reduced to half of nominal value when FB is below 400 mV.
When FB is above 400 mV, the switching frequency will be
fSW and the error amplifier gain will be the nominal value. The
reduced switching frequency and error amplifier gain are neces-
sary to help improve output regulation and stability when VOUT is
very low. During low VOUT, the PWM control loop requires on-
time near the minimum controllable on-time and very low duty
cycles that are not possible at the nominal switching frequency.
When the voltage at the soft start pin reaches approximately
1.2 V, the error amplifier will switch over and begin regulating
the voltage at the FB pin to the fixed internal bandgap reference
voltage of 800 mV. The voltage at the soft start pin will con-
tinue to rise to the internal LDO regulator output voltage. If the
ARG81800 is disabled or a fault occurs, the internal fault latch is
set and the capacitor at the SS pin is discharged to ground very
quickly through a 2 kΩ pull-down resistor. The device will clear
the internal fault latch when the voltage at the SS pin decays to
approximately 200 mV. However, if the device enters hiccup
mode, the capacitor at the SS pin is slowly discharged through
a current sink, IHIC. Therefore, the soft start capacitor CSS not
only controls the startup time but also the time between soft start
attempts in hiccup mode.
Slope Compensation
The ARG81800 incorporates internal slope compensation that
ensures stable operation at PWM duty cycles above 50% for a wide
range of input/output voltages, switching frequencies, and induc-
tor values. As shown in the functional block diagram, the slope
compensation signal is added to the sum of the current sense and
PWM Ramp Offset. The relationship between slope compensation
and adjustable switching frequency is given by
Equation 1:
SE = 12.84 / (37.037 / fSW – 3)
where fSW is switching frequency in MHz and SE is slope compen-
sation in A/µs. Internal slope compensation in ARG81800-1 is half
of that (Equation 1) in ARG81800.