SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14015B dual 4-bit static shift register is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4-state serial-input/parallel-output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master-slave flip-flops. Data is shifted from one stage to the next during the positive-going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial-to-parallel conversion where low power dissipation and/or noise immunity is desired. * Diode Protection on All Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Logic Edge-Clocked Flip-Flop Design -- Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse. * Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range. IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = - 55 to 125C for all packages. MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit - 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin 10 mA PD Power Dissipation, per Package 500 mW Tstg Storage Temperature - 65 to + 150 _C 260 _C TL Lead Temperature (8-Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C BLOCK DIAGRAM 7 9 Q0 5 Q1 4 Q2 3 D C R Q3 10 Q0 13 Q1 12 Q2 11 6 15 1 D C R Q3 TRUTH TABLE C X 2 14 D R Q0 Qn 0 0 0 Qn-1 1 0 1 Qn-1 X 0 No Change No Change X 1 0 0 VDD = PIN 16 VSS = PIN 8 X = Don't Care Qn = Q0, Q1, Q2, or Q3, as applicable. Qn-1 = Output of prior stage. REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14015B 57 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIII IIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIII IIIIIIIIII IIII III III IIII III IIII III IIII III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIII IIIIIIIIIIIIIIIIIIII IIII III IIII III IIII III III IIIIII IIIIIIII IIIIII IIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit Output Voltage Vin = VDD or 0 "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc Vin = 0 or VDD "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc 5.0 10 15 -- -- -- 1.5 3.0 4.0 -- -- -- 2.25 4.50 6.75 1.5 3.0 4.0 -- -- -- 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 0.88 2.25 8.8 -- -- -- 0.36 0.9 2.4 -- -- -- mAdc Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 5.0 10 20 -- -- -- 0.005 0.010 0.015 5.0 10 20 -- -- -- 150 300 600 Adc IT 5.0 10 15 Input Voltage "0" Level (VO = 4.5 or .05 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL (VO = 0.5 or 4.5 Vdc) "1" Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIH Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (1.2 A/kHz)f + IDD IT = (2.4 A/kHz)f + IDD IT = (3.6 A/kHz)f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.002. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MC14015B 58 PIN ASSIGNMENT CB 1 16 VDD Q3B 2 15 DB Q2A 3 14 RB Q1A 4 13 Q0B Q0A 5 12 Q1B RA 6 11 Q2B DA 7 10 Q3A VSS 8 9 CA MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIII IIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIII IIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock, Data to Q tPLH, tPHL = (1.7 ns/pF) CL + 225 ns tPLH, tPHL = (0.66 ns/pF) CL + 92 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns Reset to Q tPLH, tPHL = (1.7 ns/pF) CL + 375 ns tPLH, tPHL = (0.66 ns/pF) CL + 147 ns tPLH, tPHL = (0.5 ns/pF) CL + 95 ns tPLH, tPHL Clock Pulse Width Min Typ # Max 5.0 10 15 -- -- -- 100 50 40 200 100 80 Unit ns ns 5.0 10 15 -- -- -- 310 125 90 750 250 170 5.0 10 15 -- -- -- 460 180 120 750 250 170 tWH 5.0 10 15 400 175 135 185 85 55 -- -- -- ns fcl 5.0 10 15 -- -- -- 2.0 6.0 7.5 1.5 3.0 3.75 MHz tTLH, tTHL 5.0 10 15 -- -- -- -- -- -- 15 5 4 s tWH 5.0 10 15 400 160 120 200 80 60 -- -- -- ns tsu 5.0 10 15 350 100 75 100 50 40 -- -- -- ns Clock Pulse Frequency Clock Pulse Rise and Fall Times VDD Reset Pulse Width Setup Time * The formulas given are for typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD PULSE GENERATOR 2 500 F D PULSE GENERATOR 1 0.01 F CERAMIC ID C R VDD Q0 Q1 Q2 Q3 CL CL CL CL VSS 1 f CLOCK 50% DATA Figure 1. Power Dissipation Test Circuit and Waveform MOTOROLA CMOS LOGIC DATA MC14015B 59 tTLH DATA INPUT tTHL VDD 90% 50% 10% 0V tsu PULSE GENERATOR 2 VDD D Q0 PULSE GENERATOR 1 CL Q2 C R CLOCK INPUT CL Q1 SYNC t- tTLH tWH tPLH CL Q3 CL tTHL 90% 50% 10% tWL Q0 tWL = tWH = 50% Duty Cycle tTLH = tTHL 20 ns 0V tPHL 90% VSS VDD tTLH 50% 10% tTHL Figure 2. Switching Test Circuit and Waveforms PULSE GENERATOR 2 VDD D CL Q1 SYNC PULSE GENERATOR 1 Q0 0V tsu CL Q3 CL VSS VDD 50% CL Q2 C R CLOCK INPUT th DATA INPUT 50% VDD 0V Figure 3. Setup and Hold Time Test Circuit and Waveforms MC14015B 60 MOTOROLA CMOS LOGIC DATA MOTOROLA CMOS LOGIC DATA DATA IN VSS VDD DATA INPUT BUFFER DATA IN CLOCK RESET DATA TO FIRST BIT RESET IN VSS VDD RESET INPUT BUFFER VSS VDD SINGLE BIT RESET TO 4 BITS CLOCK IN TO D OF NEXT BIT VSS VDD CLOCK TO 4 BITS CLOCK INPUT BUFFER Q CIRCUIT SCHEMATICS MC14015B 61 LOGIC DIAGRAMS SINGLE BIT Q C C TO D OF NEXT BIT DATA C C C C C C RESET C C C COMPLETE DEVICE 5 4 Q0 3 Q1 10 Q2 Q3 DATA INPUT BUFFER D D 7 C CLOCK INPUT BUFFER C R Q D Q C R Q D Q C R Q D Q C Q R Q 9 R 6 13 RESET INPUT BUFFER 12 Q0 11 Q1 2 Q2 Q3 DATA INPUT BUFFER D D 15 CLOCK INPUT BUFFER C C R Q D Q C R Q D Q C R Q D Q C Q R Q 1 VDD = PIN 16 VSS = PIN 8 R 14 RESET INPUT BUFFER MC14015B 62 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B- C L DIM A B C D E F G H K L M N -T- K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14015B 63 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C -T- SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14015B 64 *MC14015B/D* MOTOROLA CMOS LOGIC DATA MC14015B/D