MC14015BCL - Motorola / Freescale Semiconductor

MOTOROLA CMOS LOGIC DATA 57

MC14015B

    

The MC14015B dual 4–bit static shift register is constructed with MOS

P–channel and N–channel enhancement mode devices in a single

monolithic structure. It consists of two identical, independent 4–state

serial–input/parallel–output registers. Each register has independent Clock

and Reset inputs with a single serial Data input. The register states are type

D master–slave flip–flops. Data is shifted from one stage to the next during

the positive–going clock transition. Each register can be cleared when a high

level is applied on the Reset line. These complementary MOS shift registers

find primary use in buffer storage and serial–to–parallel conversion where

low power dissipation and/or noise immunity is desired.

•Diode Protection on All Inputs

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Logic Edge–Clocked Flip–Flop Design —

Logic state is retained indefinitely with clock level either high or low;

information is transferred to the output only on the positive going edge

of the clock pulse.

•Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VDD

ÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎÎ

– 0.5 to + 18.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Voltage (DC or Transient)

ÎÎÎÎÎÎ

– 0.5 to VDD + 0.5

ÎÎÎ

ÎÎÎÎ

lin, lout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Current (DC or Transient),

per Pin

ÎÎÎÎÎÎ

± 10

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation, per Package†

ÎÎÎÎÎÎ

500

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature (8–Second Soldering)

ÎÎÎÎÎÎ

260

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages: – 12 mW/

C From 100

C To 125

TRUTH TABLE

C D R Q0 Qn

0 0 0 Qn–1

1 0 1 Qn–1

X 0 No Change No Change

X X 1 0 0

X = Don’t Care

Qn = Q0, Q1, Q2, or Q3, as applicable.

Qn–1 = Output of prior stage.



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

BLOCK DIAGRAM

VDD = PIN 16

VSS = PIN 8

MOTOROLA CMOS LOGIC DATAMC14015B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎÎ

– 55

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage

“0” Level

Vin = VDD or 0

Vin = 0 or VDD “1” Level

ÎÎÎÎ

VOL

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

0.05

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

0.05

ÎÎÎÎ

—

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Vin = 0 or VDD

“1” Level

ÎÎÎÎ

VOH

ÎÎÎ

5.0

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

—

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or .05 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

—

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

—

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIH

ÎÎÎ

5.0

ÎÎÎ

3.5

7.0

ÎÎÎÎ

—

ÎÎÎ

3.5

7.0

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

—

ÎÎÎÎ

3.5

7.0

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎÎ

—

ÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎ

—

ÎÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOL

ÎÎÎ

5.0

ÎÎÎ

0.64

1.6

4.2

ÎÎÎÎ

—

ÎÎÎ

0.51

1.3

3.4

ÎÎÎÎ

0.88

2.25

8.8

ÎÎÎ

—

ÎÎÎÎ

0.36

0.9

2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

—

ÎÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎÎ

±0.00001

ÎÎÎ

± 0.1

ÎÎÎÎ

—

ÎÎÎ

± 1.0

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

0.005

0.010

0.015

ÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎ

150

300

600

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

ÎÎÎÎ

ÎÎÎ

5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (1.2 µA/kHz)f + IDD

IT = (2.4 µA/kHz)f + IDD

IT = (3.6 µA/kHz)f + IDD

ÎÎÎ

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

**The formulas given are for the typical characteristics only at 25

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However , precautions must

be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, Vin and

Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either VSS or VDD). Unused outputs must be left open.

PIN ASSIGNMENT

125

Q1B

Q0B

VDD

Q3A

Q2B

Q1A

Q2A

Q3B

VSS

Q0A

MOTOROLA CMOS LOGIC DATA 59

MC14015B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎÎ

VDD

ÎÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

100

ÎÎÎÎ

200

100

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

Clock, Data to Q

tPLH, tPHL = (1.7 ns/pF) CL + 225 ns

tPLH, tPHL = (0.66 ns/pF) CL + 92 ns

tPLH, tPHL = (0.5 ns/pF) CL + 65 ns

Reset to Q

tPLH, tPHL = (1.7 ns/pF) CL + 375 ns

tPLH, tPHL = (0.66 ns/pF) CL + 147 ns

tPLH, tPHL = (0.5 ns/pF) CL + 95 ns

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

310

125

460

180

120

ÎÎÎÎ

750

250

170

750

250

170

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Width

ÎÎÎÎ

tWH

ÎÎÎÎÎ

5.0

ÎÎÎÎ

400

175

135

ÎÎÎÎ

185

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Frequency

ÎÎÎÎ

fcl

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

2.0

6.0

7.5

ÎÎÎÎ

1.5

3.0

3.75

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Rise and Fall Times

ÎÎÎÎ

tTLH, tTHL

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset Pulse Width

ÎÎÎÎ

tWH

ÎÎÎÎÎ

5.0

ÎÎÎÎ

400

160

120

ÎÎÎÎ

200

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Setup Time

ÎÎÎÎ

tsu

ÎÎÎÎÎ

5.0

ÎÎÎÎ

350

100

ÎÎÎÎ

100

ÎÎÎÎ

—

ÎÎÎ

*The formulas given are for typical characteristics only at 25

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit and Waveform

PULSE

GENERATOR

CLOCK

DATA

50%

PULSE

GENERATOR

500

VDD

ID0.01

CERAMIC

VSS

CLCLCL

VDD

MOTOROLA CMOS LOGIC DATAMC14015B

Figure 2. Switching Test Circuit and Waveforms

VDD

VSS

PULSE

GENERATOR

PULSE

GENERATOR

RCL

CLCL

DATA

INPUT

CLOCK

INPUT

tTLH tTHL

VDD

0 V

VDD

0 V

tsu

tTLH tTHL

tWH tWL

tTLH tTHL

tPLH tPHL

90%

50%

10%

90%

50%

10%

90% 50%

10%

tWL = tWH = 50% Duty Cycle

tTLH = tTHL ≤ 20 ns

SYNC

t–

Figure 3. Setup and Hold Time Test Circuit and Waveforms

VDD

VSS

PULSE

GENERATOR

PULSE

GENERATOR

RCL

CLCL

SYNC

CLOCK

INPUT

DATA

INPUT

50% VDD

0 V

VDD

0 V

tsu

50%

MOTOROLA CMOS LOGIC DATA 61

MC14015B

CIRCUIT SCHEMATICS

DATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFER

SINGLE BIT

VDD

VSS

TO D OF

NEXT BIT

DATA

CLOCK

RESET

VDD

VSS

VDD

VSS

VDD

VSS

DATA

IN RESET

IN CLOCK

TO 4 BITS

RESET

TO 4 BITS

DATA TO

FIRST BIT

MOTOROLA CMOS LOGIC DATAMC14015B

LOGIC DIAGRAMS

SINGLE BIT

DATA

RESET

TO D OF

NEXT BIT

COMPLETE DEVICE

DATA INPUT BUFFER

CLOCK INPUT BUFFER

RESET INPUT BUFFER

DATA INPUT BUFFER

CLOCK INPUT BUFFER

RESET INPUT BUFFER

5 4 3 10

Q0 Q1 Q2 Q3

11 21213Q0 Q1 Q2 Q3

VDD = PIN 16

VSS = PIN 8

MOTOROLA CMOS LOGIC DATA 63

MC14015B

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

HGD

16 PL

SEATING

1 8

916

PLANE

–T–

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–A–

–B–

–T–

SEATING

PLANE

16 PLD

0.25 (0.010) T

16 PLJ

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.750 0.785 19.05 19.93

B0.240 0.295 6.10 7.49

C––– 0.200 ––– 5.08

D0.015 0.020 0.39 0.50

E0.050 BSC 1.27 BSC

F0.055 0.065 1.40 1.65

G0.100 BSC 2.54 BSC

H0.008 0.015 0.21 0.38

K0.125 0.170 3.18 4.31

L0.300 BSC 7.62 BSC

M0 15 0 15

N0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATAMC14015B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

RX 45

8 PLP

–B–

–A–

0.25 (0.010) B S

–T–

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided

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MC14015B/D

*MC14015B/D*

◊