© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 0
1Publication Order Number:
NB7L1008M/D
NB7L1008M
2.5V / 3.3V 1:8 CML Fanout
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L1008M is a high performance differential 1:8 Clock/Data
fanout buffer. The NB7L1008M produces eight identical output copies
of Clock or Data operating up to 6 GHz or 10.7 Gb/s, respectively. As
such, the NB7L1008M is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the VT pin. This feature allows the NB7L1008M
to accept various logic standards, such as LVPECL, CML, LVDS,
LVCMOS or LVTTL logic levels. The VREFAC reference output can
be used to rebias capacitor−coupled differential or single−ended input
signals. The 1:8 fanout design was optimized for low output skew
applications. The NB7L1008M is a member of the GigaComm™
family of high performance clock products.
Features
•Input Data Rate > 12 Gb/s Typical
•Data Dependent Jitter < 20 ps
•Maximum Input Clock Frequency > 8 GHz Typical
•Random Clock Jitter < 0.8 ps RMS
•Low Skew 1:8 CML Outputs, < 25 ps max
•Multi−Level Inputs, accepts LVPECL, CML, LVDS
•160 ps Typical Propagation Delay
•45 ps Typical Rise and Fall Times
•Differential CML Outputs, 400 mV Peak−to−Peak, Typical
•Operating Range: VCC = 2.375 V to 3.6 V, GND = 0 V
•Internal Input Termination Resistors, 50 W
•VREFAC Reference Output
•QFN−32 Package, 5 mm x 5 mm
•−40°C to +85°C Ambient Operating Temperature
•These are Pb−Free Devices
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 9 of
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
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32
1NB7L
1008M
AWLYYWWG
G
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
SIMPLIFIED LOGIC DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
VREFAC
IN
VT
IN
Q6
Q6
Q7
Q7
32
(Note: Microdot may be in either location)
50W
50W
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VCC
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
VCC
VREFAC
VCC
GND
VCC
Q4
Q4
Q3
Q3
GND
VCC
IN
VT
IN
GND
GND
Figure 1. 32−Lead QFN Pinout (Top View)
NB7L1008M
Exposed Pad
(EP)
Q7
Q7
Q6
Q6
Q5
Q5
VCC
VCC
Q0
Q0
Q1
Q1
Q2
Q2
VCC
Table 1. PIN DESCRIPTION
Pin Name I/O Description
3, 6 IN, IN LVPECL, CML,
LVDS Input
Non−inverted / Inverted Differential Clock/Data Input. Note 1
4 VT Internal 50 W Termination Pin for IN and IN
2, 7 17,24 GND Negative Supply Voltage, Note 2
1, 8, 9, 16, 18,
23, 25, 32
VCC Positive Supply Voltage, Note 2
31, 30, 29, 28,
27, 26, 22, 21,
20, 19, 15, 14,
13, 12, 11, 10
Q0, Q0, Q1,
Q1, Q2, Q2,
Q3, Q3, Q4,
Q4, Q5, Q5,
Q6, Q6, Q7, Q7
CML Non−inverted / Inverted Differential Output. Note 1
5 VREFAC Output Voltage Reference for Capacitor−Coupled Inputs, only
−EP −The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heat−sinking conduit. The pad is electrically connected to GND and is
recommended to be electrically connected to GND on the PC board.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN, then the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50 W source termination resistors.
2. All VCC and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation.
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Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity (Note 3) Indefinite Time of the Drypack
QFN−32 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 263
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, refer to Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply GND = 0 V 4.0 V
VIN Input Voltage GND = 0 V −0.5 to VCC V
VINPP Differential Input Voltage |IN − IN| 1.89 V
IIN Input Current Through RT (50 W Resistor) $40 mA
Iout Output Current Continuous
Surge
34
40
mA
IVFREFAC VREFAC Sink/Source Current $1.5 mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) (Note 4)
TGSD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard
Board
QFN−32 12 °C/W
Tsol Wave Solder Pb−Free 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 4. DC CHARACTERISTICS − CML OUTPUT VCC = 2.375 V to 3.6 V; GND = 0V TA = −40°C to 85°C (Note 6)
Symbol Characteristic Min Typ Max Unit
POWER SUPPLY
VCC Power Supply Voltage VCC = 3.3 V
VCC = 2.5 V
3.0
2.375
3.3
2.5
3.6
2.625
V
POWER SUPPLY CURRENT
ICC Power Supply Current, Inputs and Outputs Open 265 315 mA
CML OUTPUTS (Note 5, Figures 10 and 11)
VOH Output HIGH Voltage
VCC = 3.3V
VCC = 2.5V
VCC – 30
3270
2470
VCC – 10
3290
2490
VCC
3300
2500
mV
VOL Output LOW Voltage
VCC = 3.3V
VCC = 2.5V
VCC – 600
2700
1900
VCC – 400
2900
2100
VCC – 350
2950
2150
mV
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Notes 7 and 8) (Figures 6 and 8)
VIH Single−Ended Input HIGH Voltage Vth + 100 VCC mV
VIL Single−Ended Input LOW Voltage GND Vth – 100 mV
Vth Input Threshold Reference Voltage Range 1100 VCC – 100 mV
VISE Single−Ended Input Voltage (VIH – VIL) 200 1200 mV
VREFAC
VREFAC Output Reference Voltage @ 100 mA for Capacitor − Coupled
Inputs, Only VCC = 3.3 V
VCC = 2.5 V
VCC – 1375
VCC – 1325
VCC – 1200
VCC – 1200
VCC – 1100
VCC – 1075
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (IN, IN) (Note 9) (Figures 4 and 7)
VIHD Differential Input HIGH Voltage 1100 VCC mV
VILD Differential Input LOW Voltage GND VIHD − 100 mV
VID Differential Input Voltage (VIHD − VILD) 100 1200 mV
IIH Input HIGH Current −150 40 +150 mA
IIL Input LOW Current −150 5 +150 mA
TERMINATION RESISTORS
RTIN Internal Input Termination Resistor 45 50 55 W
RTOUT Internal Output Termination Resistor 45 50 55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. CML outputs loaded with 50 W to VCC for proper operation.
6. Input and output parameters vary 1:1 with VCC.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
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Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0V TA = −40°C to 85°C (Note 10)
Symbol Characteristic Min Typ Max Unit
fDATA Maximum Operating Input Data Rate 10 12 Gb/s
fINCLK Maximum Input Clock Frequency, VOUTPP w 200 mV 6 8 GHz
VOUTPP Output Voltage Amplitude (see Figures 2 and 5, Note 11)
fin v 4 GHz
fin v 6 GHz
200
200
400
350
mV
VCMR Input Common Mode Range (Differential Configuration,
Note 12, Figure 9)
1050 VCC − 50 mV
tPLH, tPHL Propagation Delay to Output Differential, IN/IN to Qn/Qn 100 160 250 ps
tPLH TC Propagation Delay Temperature Coefficient −40°C to +85°C 35 fs/°C
tDC Output Clock Duty Cycle fin v 6 GHz 45 49/51 55 %
tSKEW Duty Cycle Skew (Note 13)
Within Device Skew (Note 14)
Device to Device Skew (Note 15)
0.15
7
25
1
25
70
ps
tJITTER Clock Jitter RMS, 1000 Cycles (Note 16) fin v 6 GHz
Data Dependent Jitter (DDJ) (Note 17) v10 Gb/s
0.2
3
0.8
20
ps
VINPP Input Voltage Swing (Differential Configuration) (Note 18)
(Figure 5)
100 1200 mV
tr, tfOutput Rise/Fall Times (20% − 80%) Qn, Qn 20 45 70 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured using a 400 mV source, 50% duty cycle 1 GHz clock source. All outputs must be loaded with external 50 W to VCC. Input
edge rates 40 ps (20% − 80%).
11. Output voltage swing is a single−ended measurement operating in differential mode.
12.VCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the
differential input signal.
13.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.
14.Within device skew compares coincident edges.
15.Device to device skew is measured between outputs under identical transition
16.Additive CLOCK jitter with 50% duty cycle clock signal.
17.Additive Peak−to−Peak jitter with input NRZ data at PRBS23.
18.Input voltage swing is a single−ended measurement operating in differential mode.
Figure 2. Output Voltage Amplitude (VOUTPP)
vs. Input Frequency (fin) at Ambient
Temperature (Typical)
500
450
400
350
300
250
200
0 1.0 2.0 3.0 8.07.06.05.04.0
.
fout, CLOCK OUTPUT FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE
(mV)
Q Output Amplitude (mV)
Figure 3. Input Structure
50 W
50 W
VT
VCC
IN
IN
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IN
IN
Q
Q
tPLH
tPHL
VOUTPP = VOH(Q) − VOL(Q)
VINPP = VIH(IN) − VIL(IN)
Figure 4. Differential Inputs Driven Differentially Figure 5. AC Reference Measurement
VIHD
VILD
VID = |VIHD(IN) − VILD(IN)|
IN
IN
Figure 6. Differential Input Driven Single−Ended Figure 7. Differential Inputs Driven Differentially
Figure 8. Vth Diagram Figure 9. VCMR Diagram
IN
VCC
GND
VIH
VIHmin
VIHmax
Vthmax
Vth
Vth
Vthmin VCMmin
VCMmax
IN
VCMR
VCC
GND
IN
IN
Vth
Vth
IN
IN
VILmax
VIL
VILmin
IN
VILDmax
VIHDmax
VID = VIHD − VILD
VILDtyp
VIHDtyp
VILDmin
VIHDmin
VIH
VIL
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Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8173/D)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VCC
Figure 11. Typical CML Output Structure and Termination
VCCO
50 W50 W
16 mA
50 W50 W
VCC (Receiver)
GND
Q
Q
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LVPECL
Driver
VCC
GND
ZO = 50 W
VT = VCC − 2 V
ZO = 50 W
NB7L1008M
IN
50 W
50 W
IN
GND
Figure 12. LVPECL Interface
LVDS
Driver
VCC
GND
ZO = 50 W
VT = Open
ZO = 50 W
NB7L1008M
IN
50 W
50 W
IN
GND
Figure 13. LVDS Interface
VCC
VCC
CML
Driver
VCC
GND
ZO = 50 W
VT = VCC
ZO = 50 W
NB7L1008M
IN
50 W
50 W
IN
GND
VCC
Figure 14. Standard 50 W Load CML Interface
Differential
Driver
VCC
GND
ZO = 50 W
VT = VREFAC*
ZO = 50 W
NB7L1008M
IN
50 W
50 W
IN
GND
VCC
Figure 15. Capacitor−Coupled
Differential Interface
(VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor
Differential
Driver
VCC
GND
ZO = 50 W
VT = VREFAC*
NB7L1008M
IN
50 W
50 W
IN
GND
VCC
Figure 16. Capacitor−Coupled
Single−Ended Interface
(VT Connected to VREFAC)
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ORDERING INFORMATION
Device Package Shipping
NB7L1008MMNG QFN32
(Pb−Free)
74 Units / Rail
NB7L1008MMNR4G QFN32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
SEATING
32 X
K
0.15 C
(A3)
A
A1
D2
b
1
916 17
32
2 X
2 X
E2
32 X
8
24
32 X
L
32 X
BOTTOM VIEW
EXPOSED PAD
TOP VIEW
SIDE VIEW
D
A
B
E
0.15 C
ÉÉ
ÉÉ
PIN ONE
LOCATION
0.10 C
0.08 C
C
25
e
A0.10 B
C
0.05 C
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
DIM MIN NOM MAX
MILLIMETERS
A0.800 0.900 1.000
A1 0.000 0.025 0.050
A3 0.200 REF
b0.180 0.250 0.300
D5.00 BSC
D2 2.950 3.100 3.250
E5.00 BSC
E2
e0.500 BSC
K0.200 −−− −−−
L0.300 0.400 0.500
2.950 3.100 3.250
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50 PITCH
3.20
0.28
3.20
32 X
28 X
0.63
32 X
5.30
5.30
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NB7L1008M/D
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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