April 2003 1
© 20 01 Actel Corporation
v4.0
SX-A Family FPGAs
e
u
Leading-Edge Performance
• 250 MHz System Performance
• 350 MH z Internal Performanc e
• 3.8 ns Clock-to-Out (Pad-to-Pad)
Specifications
• 12,000 to 108,000 Available System Gates
• Up to 360 User-Programmable I/O Pins
• Up to 2,012 D edicated Flip-Flops
•0.22
µ/0.25µ CMOS Pr oce ss Te c hno l ogy
Features
• Hot-S wap Compliant I/Os
• Power-up/down Friendly (No Sequencing Required for
Supp ly Vo lta g e s)
• 66 MHz PCI Co mp li an t
• S i ng le-Chip So lu tio n
• Nonvolatile
• Confi gu r a bl e I /O S up po r t f o r 3. 3 V / 5 V P C I , 5 V TT L ,
3.3V LVTTL, 2.5V LVCMOS2
• 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input
Tolerance and 5V Drive Strength
• Devices Support Multiple Temperature Grades
• Confi gu rable We a k-Res is to r Pull- up or P u ll -d ow n f or
Outputs at Power-up
• Individual Output Slew Rate Control
• Up to 100% Resource Utilization and 100% Pin Locking
• Deterministic, User-Controllable Timing
• Unique I n- Sy stem Di ag n os t ic an d Ve r if ic a t io n Ca pa b ility
wi t h S i l i con E x p lor e r I I
• Bound ar y Scan Testi ng in Compli anc e with IEEE
St andard 1149.1 (JTAG)
• A ctel ’s S ecu re Pro gr ammi ng Tec hno log y w it h Fu se Lock ™
Prevents Reverse Engineer ing and Design Theft
SX-A Product Profile
Device A54SX08A A54SX16A A54SX32A A54SX72A
Capacity
Typical Gates
System Gates 8,000
12,000 16,000
24,000 32,000
48,000 72,000
108,000
Logic Mod ules
Combinatorial Cells 768
512 1,452
924 2,880
1,800 6,036
4,024
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops 256
512 528
990 1,080
1,980 2,012
4,024
Maximum User I/Os 130 180 249 360
Global Clocks 3333
Quadrant Clocks 0004
Boundary Scan Testing Yes Yes Yes Yes
3.3V/5V PCI Yes Yes Yes Yes
Clock-to-Out 4.2 ns 4.6 ns 4.7 ns 5.8 ns
Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns
Speed Grades –F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3
Temperature Grades C, I, A C, I, M, A C, I, M, A C, I, M, A
Package (by pin count)
PQFP
TQFP
PBGA
FBGA
CQFP*
208
100, 144
—
144
208
100, 144
—
144, 256
208
100, 144, 176
329
144, 256, 484
208, 256
208
—
—
256, 484
208, 256
Note: For more informat ion about the CQFP package optio ns, refer to the HiRel SX-A datasheet at: www.actel.com/documents/HRSXADS.pdf
SX-A Family FPGAs
2v4.0
Ordering Information
Plastic Device Resources
User I/Os (including clock buffers)
Device PQFP
208-Pin TQFP
100-Pin TQFP
144-Pin TQFP
176-Pin PBGA
329-Pin FBGA
144-Pin FBGA
256-Pin FBGA
484-Pin
A54SX08A 130 81 113 — — 111 ——
A54SX16A 175 81 113 ——111 180 —
A54SX32A 174 81 113 147 249 111 203 249
A54SX72A 171 —————203 360
Contact your Actel sales representative for product availability.
Package De fin iti ons
PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = 1.27mm Plastic Ball Grid Array, FBGA = 1.0mm Fine Pitch Ball
Grid Array
Applic ation (Tem pera ture Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
A = Automotive (–40 to +125°C)
Package Type
BG = 1.27mm Plastic Ball Grid Array
FG = 1.0mm Fine Pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4mm) Quad Flat Pack
CQ = Ceramic Quad Flat Pack*
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
A54SX08A = 12,000 System Gates
A54SX16A = 24,000 System Gates
A54SX32A = 48,000 System Gates
A54S X72A = 108,000 System Gates
Package Lead Count
A54SX16 PQ 2082
A = 0.22µ /0.25µ CMOS Technology
A
*For more information about the CQFP packa ge option s, refer to the HiRel SX-A datasheet at: www.actel.com/documents/HRSXADS.pdf
v4.0 3
SX-A Family FPGAs
Product Plan
Speed Grade** Application
–FStd–1–2–3 C I
†M•A
A54SX08A Device
100-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔✔✔
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔✔✔
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔✔ ✔✔✔✔
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔✔✔
A54SX16A Device
100-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔✔✔
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔✔✔
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔✔ ✔✔✔✔
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔✔✔
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔✔✔
A54SX32A Device
100-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔✔✔
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔✔✔
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔✔–
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔✔ ✔✔✔✔
208-Pin Ceramic Quad Flat Pack (CQFP)* ✔✔✔✔✔ ✔✔✔–
256-Pin Ceramic Quad Flat Pack (CQFP)* ✔✔✔✔✔ ✔✔✔–
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔✔✔
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔✔✔
329-Pin P lastic Ball Grid Array (PBGA) ✔✔✔✔✔ ✔✔✔–
484-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔✔–
A54SX72A Device
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔✔ ✔✔✔✔
208-Pin Ceramic Quad Flat Pack (CQFP)* ✔✔✔✔✔ ✔✔✔–
256-Pin Ceramic Quad Flat Pack (CQFP)* ✔✔✔✔✔ ✔✔✔–
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔✔✔
484-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔✔✔
Contact your Actel sales representative for product availability.
*For more information about the CQFP package options, refer to the HiRel SX-A datasheet at: www.actel.com/documents/HRSXADS.pdf
Applications: C = Commercial Availability: ✔= Available **Speed Grade: –1 = Approx. 15% faster than Standard
I = Industri al –2 = Approx. 25% faster than Standard
M = Military –3 = Approx. 35% faste r th an Standard
A = Automotive –F = Approx. 40% slower than Standard
† Only Std, –1, –2 Speed Grade
• Only Std, –1 Speed Grade
SX-A Family FPGAs
4v4.0
General Description
Actel’s SX-A family of FPGAs features a sea-of-modules
architecture that delivers high device performance. SX-A
devices simplify design time, enable dramatic reductions in
design costs and power consumption, and further decrease
time-to-market for performance-intensive applications.
Actel’s SX-A architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient mapping
of synthesized logic functions. The routing and interconnect
resources are in the metal layers above the logic modules,
providing optimal use of silicon. This enables the entire
floor of the device to be spanned with an uninterrupted grid
of fine-grained, synthesis-friendly logic modules (or
“sea-of-modules”), which reduces the distance signals have
to travel between logic modules. To minimize signal
propagation delay, SX-A devices employ both local and
general routing resources. The high-speed local routing
resources (DirectConnect and FastConnect) enable very
fast local signal propagation that is optimal for fast
counters, state machines, and datapath logic. The general
system of segmented routing tracks allows any logic module
in the array to be connected to any other logic or I/O
module. Within this syst em, propagation delay is minimized
by limiting the number of antifuse interconnect elements to
five (90 percent of connections typically use only three or
fewer antifuses). The unique local and general routing
structure featured in SX-A devices gives fast and predictable
performance, allows 100% pin-locking with full logic
utilization, enables concurrent PCB development, reduces
design time, and allows designers to achieve performance
goals with minimum effort.
Further complementing SX-A’s flexible routing structure is a
hardwired, constantly loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal
logic has eliminated the n eed to embed latches or flip-f lops
in the I/O cells to achieve fast clock-to-out or fast input
set-up times. SX-A devices have easy-to-use I/O cells t hat do
not require HDL instantiation, facilitating design re-use and
reducing design and verification time.
SX-A Family Architecture
The SX-A family architecture was designed to satisfy
performance and integration requirements for
production-volume designs in a broad range of applications.
Programmable Interconnect Element
The SX-A family pr ovides efficient use of silicon by locating
the routing interconnect resources between the top two
metal layers (Figure 1). This completely eliminates the
channels of routing and interconnect resources between
logic modules (as implemented on SRAM FPGAs and
previous generations of antifuse FPGAs), and enables the
entire floor of the device to be spanned with an
uninterrupted grid of logic modules.
Note: A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. A54SX08A, A54SX16A, and
A54SX32A have three layers of metal with antifuse between Metal 2 and Metal 3.
Figure 1 • SX-A Family Interconnect Elements
Silicon Substrate
Metal 4
Metal 3
Metal 2
Metal 1
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
Tungsten Plug Contact
Routing Tracks
v4.0 5
SX-A Family FPGAs
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SX-A family abundant routing resources and
provides excellent protection against design pirating.
Reverse engineering is virtually impossible because it is
extremely diffi cul t to distinguish between programmed and
unprogrammed antifuses, and since SX-A is a nonvolatile,
single-chip solution, there is no configuration bitstream to
intercept.
Additionally, the interconnect (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
Logic Module Design
The SX-A family architecture is described as a
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX-A family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell) .
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (Figure 2). The R-cell registers
feature programmable clock polarity selectable on a
register-by-register basis. This provides additional flexibility
while allowing mapping of synthesized functions into the
SX-A FPGA. The clock source for the R-cell can be chosen
from either the hardwired clock, the routed clocks, or
internal logic.
The C-cell implements a range of combinatorial functions of
up to five inputs (Figure 3 on page 6). Inclusion of the DB
input and its associated inverter function increases the
number of combinatorial functions that can be implemented
in a single module from 800 options (as in previous
architectures) to more than 4,000 in the SX-A architecture.
An example of the improved flexibility enabled by the
inversion capability is the ability to integrate a 3-input
exclusive-OR function into a single C-cell. This facilitates
construction of 9-bit parity-tree functions with 1.9 ns
propagation delays. At the same time, the C-cell structure is
extremely synthesis friendly, simplifying the overall design
and reducing synthesis time.
Figure 2 •R-Cell
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS CKP
CLR
PRE
Y
Routed
Data Input
S0 S1
DQ
SX-A Family FPGAs
6v4.0
Chip Architecture
The SX-A family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of new
and emerging applications.
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(Figure 4 on page7). SuperCluster 1 is a two-wide grouping
of Type 1 Clusters. SuperCluster 2 is a two-wide group
containing one Type 1 Cluster and one Type 2 Cluster. SX-A
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
significantly more combinatorial logic than flip-flops.
Routing Resources
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 5 and Figure 6 on
page8). This routing architecture also dramatically reduces
the number of antifuses required to complete a circuit,
ensuring the highest p ossible performance.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hardwired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering a maximum pin-to-pin propagation time of
0.3 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen b y the 100% automatic
place-and-route software to minimize signal propagation
delays.
Clock Resources
Actel’s high-drive routing structure provides three clock
netwo rks (Table 1). The first clock, called HCLK, is hardwired
from t he H CLK bu ffer to the clo ck sel ect M U X in ea ch R-ce ll.
HCLK cannot be connected to combinatorial logic. This
provides a fast propagation path for the clock signal, enabling
the 3.8 ns clo ck-to-out (pad- to -p ad) perfor mance of the SX-A
devices. The hardwired clock is tuned to provide clock skew
less than 0.3 ns worst case. If not used, this pin must be set as
LOW or HIGH on the board. It must not be left floating.
Figure 7 describes the cloc k circu it used fo r the constant load
HCLK. Upon power-up of the SX-A device, four clock pulses
must be detected on HCLK before the clock signal will be
propagated to registers in the design.
Two additional clocks (CLKA, CLKB) are global clocks that
can be sourced from external pins or from internal logic
signals within the SX-A device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
Figure 3 •C-Cell
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
v4.0 7
SX-A Family FPGAs
Figure 4 •Cluster Organization
Figure 5 •DirectConnect and FastConnect for Type 1 SuperClusters
Type 1 SuperCluster Type 2 SuperCluster
Cluster 1 Cluster 1 Cluster 2 Cluster 1
R-Cell C-Cell
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS CKP
CLR
PRE
YDQ
Routed
Data Input
S0 S1
Type 1 SuperClusters
DirectConnect
• No antifuses
• 0.1 ns maximum routing delay
FastConnect
• One antifuse
• 0.3 ns maximum routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
SX-A Family FPGAs
8v4.0
CLKA or CLKB pins are not used or sourced from signals, then
these pins must be set as LOW or HIGH on the board. They
mus t n ot be lef t fl oati ng (exc ept in t he A5 4S X72 A wher e thes e
clocks can be configured as regular I/Os and can float).
Figure 8 describes the CLKA and CLKB circuit used in SX-A
devices with the exception of A54SX72A.
In addition, the A54SX72A device provides four quadrant
clocks (QCLKA, QCLKB, QCLKC, QCLKD – co rresponding to
bottom-left, bottom-right, top-left, and top-right locations on
the die, respectively), which can be sourced from external
pins or from inte rnal logic signals within the d evice. Each of
these c locks can individ ually drive up to a quarter of the chip,
or they can be grouped together to drive multiple quadrants.
If QCLKs are not used as quadr a nt clocks, they w ill beh ave as
regular I/Os. Bidirectional c loc k buffers are also available on
the A54SX72A. The CLKA, CLKB, and QCLK circuits for
A54SX72A are shown in Figure 9 on page 9. Note that
bidirectional clock buffers are only available in A54SX72A.
For more information, refer to the “Pin Description” section
on page 53.
For more information on how to use quadrant clocks in the
A54SX72A device, refer to the Global Clock Networks in
Actel’s Antifuse Devices and Using A54SX72A and
RT54SX72S Quadrant Clocks application notes.
Figure 6 •DirectConnect and FastConnect for Type 2 SuperClusters
Type 2 SuperClusters
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
FastConnect
• One antifuse
• 0.3 ns maximum routing delay
DirectConnect
• No antifuses
• 0.1 ns maximum routing delay
Table 1 •SX-A Clock Resources
A54SX08A A54SX16A A54SX32A A54SX72A
Routed Clocks (CLKA, CLKB) 2222
Hardwired Clocks (HCLK) 1111
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD) 0004
Figure 7 •SX-A HCLK Clock Pad
Constant Load
Clock Network
HCLKBUF
Note: This does n ot include the clock pad for HiRel A54SX72A.
Figure 8 •SX-A Routed Clock Structure
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
v4.0 9
SX-A Family FPGAs
Other Architectural Features
Technology
Actel’s SX-A family is implemented on a high-voltage,
twin-well CMOS process using 0.22µ/0.25µ desi gn rul es. T he
metal-to-metal antifuse is comprised of a combination of
amorphous silicon and dielectric material with barrier
metals and has a programmed (“on” state) resistance of
25Ω with capacitance of 1.0 fF for low signal impedance.
Performance
The combination of architectural features described above
enables SX-A devices to operate with internal clock
frequencie s of 350 MHz , enabling very f ast execut ion of even
complex logic functions. Thus, the SX-A family is an optimal
platform upon which to integrate the functionality
previously contained in multiple CPLDs. In addition,
designs that previously would have required a gate array to
meet performance goals can be integrated into an SX-A
device with dramatic improvements in cost and
time-to-market. Using timing-driven place-and-route tools,
designers can achieve highly deterministic device
performance.
User Security
The Actel FuseLock advantage ensures that unauthorized
users will not be able t o read back the contents of an Actel
antif use FPGA. In addition to the inherent strengths o f the
architecture, special security fuses that prevent internal
probing and overwriting are hidden throughout the fabric of
the device. They are located such that they cannot be
accessed or bypassed without destroying the rest of the
device, making both invasive and more-subtle noninvasive
attacks ineffective against Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure.
For more information, refer to Actel’s Implementation of
Security in Actel Antifuse FPGAs applic ation note.
I/O Modules
Each user I/O on an SX-A device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Mixed I/O standards can be set for individual pins, though
this is only allowed with the same voltage as the input. These
I/Os, combined with array registers, can achieve
clock-to-output- pad timing as fast as 3.8 ns even without the
dedicated I/O registers. In most FPGAs, I/O cells that have
embed de d la tches an d f lip- flop s requi re in stant iat io n in HDL
code; this is a design complication not encountered in SX-A
FPGAs. Fast pin-to-pin timing ensures that the device is able
to interface with any other device in the system, which in
turn enables parallel design of system components and
re du c es ove r a ll de s i gn time. A ll unused I/Os ar e co nf ig ured a s
tristate outputs by Actel’s Designer software, for maximum
flexibility when designing new boards or migrating existing
designs.
SX-A inputs should be driven by high-speed push-pull devices
with a low-resistance pull-up device. If the input voltage is
greater than VCCI an d a fa s t pu s h-p u ll d ev i c e is N OT us e d, the
high-resistance pull-up of the driver and the internal circuitry
of the SX-A I/O may create a voltage divider. This voltage
divider could pull the input voltage below specification for
some devices con ne cted to the driver. A logic '1' may not be
correctly presented in this case. For example, if an open
Figure 9 •A54SX72A Routed Clock and QClock Structure
Clock Network
From Internal Logic
From Internal Logic
OE
QCLKBUF
QCLKBUFI
QCLKINT
QCLKINTI
QCLKBIBUF
CLKBUF
CLKBUFI
CLKINT
CLKINTI
CLKBIBUF
e
u
SX-A Family FPGAs
10 v4.0
drain driver is used with a pull-up resistor to 5V to provide the
logic ’1’ input, an d VCCI is set to 3.3V o n the S X-A de vice, the
input signal may be pulled down by the SX-A input.
Each I/O module has an available power-up resistor of
approximately 50kΩ that can configure the I/O in a known
state during power-up. Just slightly before VCCA reaches 2.5V,
the resistors are disabled, so the I/Os will be controlled by
user logic. See Table 2 and Table3 for more information
concerning available I/O features.
Hot Swapping
SX-A I/Os can be configured to be hot-swappable in
compliance with the Compact PCI (5.0V) Specification.
However, note that 3.3V PCI device is not hot swappable.
During power-up/down (or partial up/down), all I/Os are
tristated. VCCA and VCCI do not have to be stable during
power-up/down. After the SX-A device is plugged into an
electrically active system, the device will not degrade the
reliability of or cause damage to the host system. The
device’s output pins are driven to a high impedance state
until normal chip operating conditions are reached. Table 4
summarizes the VCCA voltage at which the I/Os behave
according to the user’s design for an SX-A device at room
temperature for various ramp-up rates. The data reported
assumes a linear ramp-up profile to 2.5V. For more
information on power-up and hot-swapping, refer to the
application note, Actel SX-A and RT54SX-S Devices in
Hot-Swap and Cold-Sparing Applications.
Table 2 •I/O Features
Function Description
Input Buffer Threshold Selections •5V PCI, TTL
•3.3V PCI, LVTTL
•2.5V LVCMOS2
Flexible Output Driver •5V: PCI, TTL
•3.3V: PCI, LVTTL
•2.5V: LVCMOS2
Output Buffer “Hot-Swap” Capability (3.3V PCI is not hot swappable)
•I/O on an unpowered device does not sink current
•Can be used for “cold-sparing”
Selectable on an individual I/O basis
Individually selectable slew rate, high slew or low slew (The default is high slew
rate). The slew is only affected on the falling edge of an output. Rising edges of
outputs a re not af fected.
Power-Up Individually selectable pull-ups and pull-downs during power-up (default is to
power-up i n tristate )
Enables deterministic power-up of device
VCCA and VCCI can be powered in any order
Table 3 •I/O Characteristics for All I/O Configur ations
Hot Swappable Slew Rate Control Power-up Resistor
TTL, LVTTL, LVCMOS2 Yes Yes. Only affects falling edges of outputs pull-up or pull-down
3.3V PCI No No. High slew rate only pull-up or pull-down
5V PCI Yes No. High slew rate only pull-up or pull-down
Table 4 •Power-up Time at which I/Os Become Active
Supply R amp Rate 0.25V/ µs 0.025V/µs 5V/ms 2.5V/ms 0.5V/ms 0.25V/ms 0.1V/ms 0.025V/ms
Units µsµsmsmsmsmsmsms
A54SX08A 10 96 0.34 0.65 2.7 5.4 12.9 50.8
A54SX16A 10 100 0.36 0.62 2.5 4.7 11.0 41.6
A54SX32A 10 100 0.46 0.74 2.8 5.2 12.1 47.2
A54SX72A 10 100 0.41 0.67 2.6 5.0 12.1 47.2
v4.0 11
SX-A Family FPGAs
Boundary-Scan Testing (BST)
All S X-A devices are IEEE 1149.1 c ompliant and offer sup erior
diagnostic and testing capabilities by providing Boundary
Scan Testing (BST) and probing capabilities. The BST
function is controlled through the special JTAG pins (TMS,
TDI, TCK, TDO, and TRST). The functionality of the JTAG
pins is defined by two available modes: Dedicated and
Flexible. TMS cannot be employed as user I/O in either mode.
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS and
TDI pins, and the TMS pin will function as defined in the
IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, users need to reserve the JTAG
pins in Actel’s Designer software. To reserve the JTAG pins,
users can ch eck the "R eserve JTAG " box in "Devi ce Sele ct io n
Wizard" (Figure 10).
Flexible Mode
In Flexible mode, TDI, TCK, and TDO may be employed as
either use r I /Os or as JTA G i nput pi ns. The int ernal re sist ors
on the TMS and TDI pins are not present in flexible JTAG
mode.
To select the Flexible mode, users need to uncheck the
"Reserve JTAG" box in "Device Selection Wizard" in Actel’s
Desi gn er s oft wa re . I n Fl exi bl e m od e, TDI , TCK a nd TDO pi ns
may function as user I/Os or BST pins. The functionality is
controlled by the BST TAP controller. The TAP controller
receives two control inputs, TMS and TCK. Upon power-up,
the TAP controller enters the Test-Logic-Reset state. In this
state, TDI, TCK and TDO function as user I/ Os. The TDI, TCK,
and TDO are tran sforme d from user I/ Os into BST pins whe n
a rising edge on TCK is detect ed wh ile TMS is at logic low. To
return to Test-Logic Reset state, TMS must be high for at
least five TC K cycles. An extern al 10K pull-up resistor to VCCI
sho uld be placed on the TM S pin to pull it HIGH by de fault.
Table 5 describes the different co nfigur ation requirements of
BST pins and their functionality in different modes.
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan Reset
pin when the "R eserve JT AG Test Reset" option is selected as
shown in Figure 10. An internal pull-up resistor is
permanently enabled on the TRST pin in this mode. Actel
recommends connecting this pin to ground in normal
operation to keep the JTAG state controller in the
Test-Logic-Reset state. When JTAG is being used, it can be
left floating or be driven high.
When the "Reserve JTAG Test Reset" option is not selected,
this pin will func tion as a regular I/O. If unused as an I/O i n
the desig n, it wil l be conf igur ed as a tristate d outp ut.
Probing Capabilities
SX-A devi ces also p rovid e a n inte rna l prob ing ca pa bility th at
is accessed with the JTAG pins. The Silicon Explorer II
Diagnostic Hardware is used to control the TDI, TCK, TMS
and TDO pins to select the desired nets for debugging. The
user assigns the selected internal nets in Actel’s Silicon
Explorer II software to the PRA/PRB output pins for
observation. Silicon Explorer II automatically places the
device into JTAG mode. However, probing functionality is
only activated when the TRST pin is driven high or left
floating, allowing the internal pull-up resistor to pull TRST
HIGH. If the TRST pin is held LOW, the TAP controller
remains in the Test-Logic-Reset state so no probing can be
performed. However, the user must drive the TRST pin HIGH
or allow t he internal pu ll- up r esi s to r to pul l TRS T H IG H.
When selecting the "Reserve Probe Pin" box as shown in
Figure10, direct the layout tool to reserve the PRA and PRB
pins as dedicated outputs for probing. This "reserve" option is
merely a guideline. If the designer assigns user I/Os to the
PRA and PRB pins and selects the "Reserve Probe Pin"
option, Designer Layout will override the "Reserve Probe Pin"
option and place the user I/Os on those pins.
To allow probing capabilities, the security fuse must not be
programmed. Programming the security fuse disables the
probe circuitry. Table6 summarizes the possible device
configurations for probing once the device leaves the
"Test-Logic-Reset" JTAG state.
Figure 10 •Device Selection Wizar d
Table 5 •Boundary-Scan Pin Configurations and Functions
Mode Designer "Reserve JTAG" Selection TAP Controller State
Dedicated (JTAG) Checked Any
Flexible (User I/O) Unchecked Test-Logic-Reset
Flexible (JTAG) Unchecked Any EXCEPT Test-Logic-Reset
SX-A Family FPGAs
12 v4.0
SX-A Probe Circuit Control Pins
SX-A d evices contai n interna l pro bing circu itry that provid es
built-in access to every node in a design, enabling 100%
real-t ime observ ation and anal ysis of a devi ce’s inte rn al lo gi c
nodes without design iteration. The probe circuitry is
accessed by Silicon Explorer II, an easy to use integrated
verification and logic analysis tool that can sample data at
100 MHz (asynchronous) or 66MHz (synchronous).
Silicon Explorer II attaches to a PC’s standard COM port,
turning the PC into a fully functional 18 channel logic
analy zer. S il icon Exp lore r II al lo ws desi gn ers to c om pl ete t he
design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
The Silicon Explorer II tool uses the boundary-scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 11 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification.
Design Considerations
Avoid using the TDI, TCK , TDO, PRA , and PRB pins as i nput
or bidirectional ports. Since these pins are active during
probing, critical input signals through these pins are not
available. In addition, do not program the Security Fuse.
Programming the Security Fuse disables the Probe Circuit.
Actel recommends that you use a 70Ω series termination
resistor on every probe connector (TDI, TCK, TMS, TDO,
PRA, PRB). The 70Ω series termination is used to prevent
data transmission corruption during probing and reading
back the checksum.
Table 6 •Device Configuration Options for Probe Capability ( TRST pin reserved)
JTAG Mode TRST1Security Fuse Programmed PRA, PRB2TDI, TCK, TDO2
Dedicated LOW No User I/O3Probing Unavailable
Flexible LOW No User I/O3User I/O3
Dedicated HIGH No Probe Circuit Outputs Probe Ci rcuit Inputs
Flexible HIGH No Probe Circuit Outputs Probe Circuit Inputs
–– Yes Probe Circuit Secured Probe Circuit Secured
Notes:
1. If the TRST pin is not reserved, the device behaves according to TRST=HIGH as described in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. I f no user sig nal is assign ed to these pins, they will beh ave as unused I/Os in this mode. Unused pins are automat ically trist ated b y the
Designer software.
Figur e 11 •Probe Setup
Silicon Explorer IISer ial Conne ct ion
16
Additional
Channels
SX-A FPGA
70 Ω
70 Ω
70 Ω
70 Ω
70 Ω
70 Ω
TDI
TCK
TMS
TDO
PRA
PRB
v4.0 13
SX-A Family FPGAs
Development Tool Support
The SX-A family of FPGAs is fully supported by both the
Actel Libero™ Integrated Design Environment and the
Actel Designer FPGA Development Software. Actel's
Designer software provides a comprehensive suite of
back-end development tools for FPGA development. The
Designer software includes timing-driven place and rout e, a
world-class integrated static timing analyzer and
constraints editor, and a design netlist schematic viewer.
Libero IDE provides an integrated design manager that
seamlessly integrates design tools while guiding the user
through the design flow, managing all design and log files,
and passing necessary design data among tools. Libero IDE
includes Synplic ity ® Synplify for Actel, Mentor Graphics™
ViewDraw for Actel, Actel's own Designer software, Model
Technology™ ModelSim HDL Simulator, and
SynaptiCAD™ WaveFor mer Lit e ( Figure 12).
Figur e 12 •Design F low
Synthesis
Timing Simulation
Functional Simulation
Stimulus Generation
Simulator
Schematic Entry
Synthesis
Libraries
Fuse or Bitstream
Layout
Compile
Back-Annotate
NetlistViewer
SmartPower
ChipEdit and
ChipViewer
PinEdit
Timer
Static Timing Analyzer
and Constraints Editor
I/O Assignments
Design Synthesis and Optimization
Power Analysis
Schematic Viewer
Placement Editor
Silicon Sculptor
(Antifuse and Flash Families) Silicon Explorer II
(Antifuse and Flash Families)
FlashPro
(Flash Families)
FlashPro Lite
(ProASICPLUS Family)
BP Microsystems
Programmers
Cross-Probing
User
Testbench
Actel
Device
Design Implementation Design Implementation
ProgrammingProgramming System VerificationSystem Verification
Design Creation/VerificationDesign Creation/Verification
HDL Editor
ACTgen
Macro Builder
Optimization and DRC
Timing Driven Place-and-Route
Libero TM IDE Project Manager
SX-A Family FPGAs
14 v4.0
2.5V/3.3V/5V Operating Conditions
3.3V LVTTL and 5V TTL Electrical Specifications
Absolute Maximum Ratings1
Symbol Parameter Limits Units
VCCI DC Supply Vol tage –0.3 to +6.0 V
VCCA DC Supply Vol tage –0.3 to +3.0 V
VIInput Voltage –0.5 to +5.75 V
VOOutput Voltage –0.5 to +VCCI V
TSTG Storage Temperature –65 to +150 °C
Note:
1. Stresses beyond those listed under “Absol ute Maxim um Ratings”
may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Devices should not be operated outside
the Recommended Operating Conditions.
Recommended Operating Conditions
Parameter Commercial Industrial Military Units
Temperature Range10 to +70 –40 to +85 –55 to +125 °C
2.5V Power Supply Range 2.25 to 2.75 2.25 to 2.75 2.25 to 2.75 V
3.3V Power Supply Range 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V
5V Power Supply Range 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 V
Note:
1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used
for military.
Symbol
Commercial Industrial
Parameter Min. Max. Min. Max. Units
VOH
VCCI = MIN
VI = VIH or VIL
(IOH = -1mA) 0.9 VCCI 0.9 VCCI V
VCCI = MIN, VCCI
VI = VIH or VIL
(IOH = -8mA) 2.4 2.4 V
VOL
VCCI = MIN, VCCI
VI = VIH or VIL
(IOL= 1mA) 0.4 0.4 V
VCCI = MIN, VCCI
VI = VIH or VIL
(IOL= 12mA) 0.4 0.4 V
VIL Input Low Voltage 0.8 0.8 V
VIH Input High Voltage 2.0 VCCI + 0.5 2.0 VCCI + 0.5 V
IIL/ IIH Input Leakage Current, VIN = VCCI or GND –10 10 –10 10 µA
IOZ 3-State Output Leakage Current –10 10 –10 10 µA
tR, tFInput Transition Time tR, tF10 10 ns
CIO I/O Capacitance 10 10 pF
ICC Standby Current 10 20 mA
IV Curve*Can be derived from the IBIS model on the web.
Note: *The IBIS model can be found at www.actel.com/support/support/support_ibis.html.
v4.0 15
SX-A Family FPGAs
PCI Compliance for the SX-A Family
The SX-A family supports 3.3V and 5V PCI and is compliant
with the PCI Local Bus S pecification Rev. 2.1.
2.5V LVCMOS2 Electrical Specifications
Symbol
Commercial Industrial
Parameter Min. Max. Min. Max. Units
VOH
VDD = MIN,
VI = VIH or VIL
(IOH = -100µA) 2.1 2.1 V
VDD = MIN,
VI = VIH or VIL
(IOH = -1 mA) 2 .0 2.0 V
VDD = MIN,
VI = VIH or VIL
(IOH = -2 mA) 1 .7 1.7 V
VOL
VDD = MIN,
VI = VIH or VIL
(IOL= 100µA) 0.2 0.2 V
VDD = MIN,
VI = VIH or VIL
(IOL= 1mA) 0.4 0.4 V
VDD = MIN,
VI = VIH or VIL
(IOL= 2 mA) 0.7 0.7 V
VIL Input Low Voltage, VOUT ≤ VVOL(max) -0.3 0.7 -0.3 0.7 V
VIH Input High Voltage, VOUT ≥ VVOH(min) 1.7 VDD + 0.3 1.7 VDD + 0.3 V
IOZ 3-State Output Leakage Current, VOUT = VCCI or GND –10 10 –10 10 µA
tR, tFInput Transition Time tR, tF10 10 ns
CIO I/O Capacitance 10 10 pF
ICC Standby Current 10 20 mA
IV Curve1Can be derived from the IBIS model on the web.
Note:
1. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.
SX-A Family FPGAs
16 v4.0
DC Specifications (5V PCI Operation)
Symbol Parameter Condition Min. Max. Units
VCCA Supply Voltage for Array 2.3 2.7 V
VCCI Supply Voltage for I/Os 4.75 5 .25 V
VIH Input High Voltage 2.0 VCCI + 0.5 V
VIL Input Low Voltage –0.5 0.8 V
IIH Input High Leakage Current1VIN = 2.7 70 µA
IIL Input Low Leakage Current1VIN = 0.5 –70 µA
VOH Output High Voltage IOUT = –2 mA 2.4 V
VOL Output Low Voltage2IOUT = 3 mA, 6 mA 0.55 V
CIN Input Pin Capacitance310 pF
CCLK CLK Pin Cap acitance 5 12 pF
Notes:
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter includes
FRA ME#, IRD Y#, TR DY #, DE VS EL#, STOP #, SERR #, PERR# , LOC K#, an d , when used AD[63: :3 2], C /BE[7::4 ]#, PA R64 , REQ6 4# , and ACK6 4#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
v4.0 17
SX-A Family FPGAs
AC Specifications (5V PCI Operation)
Symbol Parameter Condition Min. Max. Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 1.4 1–44 mA
1.4 ≤ VOUT < 2.4 1, 2 (–44 + (VOUT – 1.4)/0.024) mA
3.1 < VOUT < VCCI 1, 3 Equat ion A
on page 18
(Test Point) VOUT = 3.1 3–142 mA
IOL(AC)
Switching Current Low VOUT ≥ 2.2 195 mA
2.2 > VOUT > 0.55 1(VOUT/0.023) mA
0.71 > VOUT > 0 1, 3 Equati on B
on page 18
(Test Point) VOUT = 0.71 3206 mA
ICL Low Clamp Current –5 < VIN ≤ –1–25 + (VIN + 1)/0.015 mA
slewROutput Rise Slew Rate 0.4V to 2.4V load 415V/ns
slewFOutput Fall Slew Rate 2.4V to 0.4V load 415V/ns
Notes:
1. Refer to the V/I curves in Figu re 13 on page 1 8. Swi tchin g cur rent c hara cte ristic s for REQ # and G NT# are p er mitted t o be one hal f of that
specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are
system outputs. “Switching Current High” spe cific atio ns are not rel evan t to SERR #, INT A#, I NTB#, IN TC# , a nd INT D#, whi ch are op en dr ain
outputs.
2. Note that this s egm ent of the minimum curren t curve is drawn f rom t he A C dri ve poin t directl y to the DC d rive poin t ra ther th an toward the
voltage rail (as is done in the pull-down curve). Thi s difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)
are provided with the respective diagrams in Figure13 on page18. The equation defined maxima should be met by design. In order to
facilitate component te sting, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpret ed as the cumulativ e edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter wit h a n
unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is
now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to
revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard
designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity
modeling accounts for this. Rise slew rate does not apply to open drain ou tputs.
output
buffer
1/2 in. max.
50 pF
pin
SX-A Family FPGAs
18 v4.0
Figure 13 shows the 5V PCI V/I curve and t he minimum and maximum PCI drive characteristics of the SX-A family.
Equation A
IOH = 11.9 * (VOUT – 5.25) * (VOUT + 2.45)
for VCCI > VOUT > 3.1V
Equation B IOL = 78.5 * VOUT * (4.4 – VOUT)
for 0V < VOUT < 0.71V
DC Specifications (3.3V PCI Operation)
Figur e 13 •5V PCI V/I Curve for SX-A Fami ly
–200.0
–150.0
–100.0
–50.0
0.0
50.0
100.0
150.0
200.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Voltage Out (V)
Current (mA)
IOH
IOL
IOH MIN Spec IOH MAX Spec
IOL MIN Spec
IOL MAX Spec
Symbol Parameter Condition Min. Max. Units
VCCA Supply Voltage for Array 2.3 2.7 V
VCCI Supply Voltage for I/Os 3.0 3.6 V
VIH Input High Voltage 0.5VCCI VCCI + 0.5 V
VIL Input Low Voltage –0.5 0.3VCCI V
IIPU Input Pull-up Voltage10.7VCCI V
IIL Input Leakage Current20 < VIN < VCCI –10 +10 µA
VOH Output High Voltage IOUT = –500 µA 0.9VCCI V
VOL Output Low Voltage IOUT = 1500 µA 0.1VCCI V
CIN Input Pin Capacitance310 pF
CCLK CLK Pin Cap acitance 5 12 pF
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. Designers should ensure that the input buffer is conducting minimum current at thi s input voltage in applications sensitive to
static power utilization.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
v4.0 19
SX-A Family FPGAs
AC Specifications (3.3V PCI Operation)
Symbol Parameter Condition Min. Max. Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 0.3V CCI 1–12VCCI mA
0.3VCCI ≤ VOUT < 0.9VCCI 1(–17.1(VCCI – VOUT)) mA
0.7VCCI < VOUT < VCCI 1, 2 Equation C
on page 20
(Test Point) VOUT = 0.7VCC 2–32VCCI mA
IOL(AC)
Switching Current Low
VCCI > VOUT ≥ 0.6VCCI 116VCCI mA
0.6VCCI > VOUT > 0.1VCCI 1(26.7VOUT)mA
0.18VCCI > VOUT > 0 1, 2 Equa tion D
on page 20
(Test Point) VOUT = 0.18VCC 2 38VCCI mA
ICL Low Clamp Current –3 < VIN ≤ –1–25 + (VIN + 1)/0.015 mA
ICH High Clamp Current VCCI + 4 > VIN ≥ VCCI + 1 25 + (VIN – VCCI – 1)/0.015 mA
slewROutput Rise Slew Rate 0.2VCCI - 0.6VCCI load 314V/ns
slewFOutput Fall Slew Rate 0.6VCCI - 0.2VCCI load 314V/ns
Notes:
1. Refer to the V/I curves in Figure14 on page20. Switching current characteristics for REQ# and GNT# are permitted to be one half of that
specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are
system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain
outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D)
are provided with the respective diagrams in Figure14 on page20. The equati on de fine d ma ximum sho uld be m et by desi gn. I n o rder to
facilitate component te sting, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
output
buffer
1/2 in. max.
10 pF
1k/25Ω
pin
1k/25Ω
pin
buffer
output
10 pF