v4.0 53
SX-A Family FPGAs
Pin Description
CLKA/B Clock A and B
These pins are clock inputs for clock distribution networks.
Input levels are compatible with standard TTL, LVTTL , 3.3V
PCI or 5V PCI specifications. The clock input is buffered
prior to clocking the R-cells. If not used, this pin must be set
LOW or HIGH on the board except A54SX72A. In A54SX72A
these cl ocks can be configured as user I/O.
QCLKA/B/C/D, Quadrant Clock A, B, C, and D
I/O
These four pins are the quadrant clock inputs and are only
for A54SX72A with A, B, C, and D corresponding to
bottom-left, bottom-right, top-left, and top-right quadrants,
respectively. They are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL,
LVTTL, 3.3V PCI or 5V PCI specifications. Each of these
clock inputs can drive up to a quarter of the chip, or they
can be grouped together to drive multiple quadrants. The
clock input is buffered prior to clocking the R-cells. If not
used as a clock it will behave as a regular I/O.
GND Ground
LOW supply voltage.
HCLK Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL, LVTTL, 3.3V PCI
or 5V PCI specific ations. This input is directly wired to each
R-cell and offers clock speeds independent of the number of
R-cells being driven. If not used, this pin must be set LOW
or HIGH on the board. It must not be left floating.
I/O Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain con figurations, input
and output levels are compatible with standard TTL, LVTTL,
3.3V PCI or 5V PCI specifications. Unused I/O pins are
automatically tristated by the Desig n er Series software .
NC No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device. The
only exception is for the A54SX32A FG-484, where the NC
pins must be left floating.
PRA, I/O Probe A/B
PRB, I/O
The Probe pin is used to output data from any user-defined
design node within the d evice. This independent diagnos tic
pin can be used in conjunction with the other probe pin to
allow real-time diagnostic output of any signal path within
the device. The Probe pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
TCK, I/O Test Clock
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to Table 5 on page 11). Th is
pin functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDI, I/O Test Data Input
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to Table 5 on page 11). This pin functions as an I/O
when the boundary scan state machine reaches the “logic
reset” state.
TDO, I/O Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer t o Table 5
on page 11). This pin functions as an I/O when the boundary
scan state machine reaches the "logic reset" state. When
Silicon Explorer II is being used, TDO will act as an output
when the "checksum" command is run. It will r e turn to user
IO when "checksum" is complete.
TMS Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO, TRST). In flexible mode when
the TMS pin is set LOW, the TCK, TDI, and TDO pins are
boundary scan pins (refer to Table 5 on page 11). Once the
boundary scan pins are in test mode, they will remain in
that mode until the internal boundary scan state machine
reaches the “logic reset” state. At this point, the boundary
scan pins will be released and will function as regular I/O
pins. The “logic reset” state is reached 5 TCK cycles after
the TMS pin is set HIGH. In dedicated test mode, TMS
functions as specified in the IEEE 1149.1 specifications.
TRST, I/O Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
function s as an act ive-low input to asynchr onously initi alize
or reset the boundary scan circuit. The TRST pin is
equipped with an internal pull-up resistor. This pin
functions as an I/O when the “Reserve JTAG Reset Pin” is
not selected in Designer.
VCCI Supply Voltage
Supply voltage for I/Os. See “Recommended Operating
Conditions” table on page 14. All VCCI power pins in the
device should be connected.
VCCA Supply Voltage
Supply voltage for Array. See “Recommended Operating
Conditions” table on page 14. All VCCA power pins in the
device should be connected.