This is information on a product in full production.
November 2012 Doc ID 023683 Rev 1 1/97
1
STM32F050x4 STM32F050x6
Low- and medium-density advanced ARM™-based 32-bit MCU with
up to 32 Kbytes Flash, timers, ADC and comm. interfaces
Datasheet − production data
Features
■Core: ARM 32-bit Cortex™-M0 CPU,
frequency up to 48 MHz
■Memories
– 16 to 32 Kbytes of Flash memory
– 4 Kbytes of SRAM with HW parity checking
■CRC calculation unit
■Reset and supply management
– Voltage range: 2.0 V to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop and
Standby
–V
BAT supply for RTC and backup registers
■Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
■Up to 39 fast I/Os
– All mappable on external interrupt vectors
– Up to 25 I/Os with 5 V tolerant capability
■5-channel DMA controller
■1 × 12-bit, 1.0 µs ADC (up to 10 channels)
– Conversion range: 0 to 3.6V
– Separate analog supply from 2.4 up to
3.6 V
■Up to 9 timers
– 1 x 16-bit 7-channel advanced-control timer
for 6 channels PWM output, with deadtime
generation and emergency stop
– 1 x 32-bit and 1 x 16-bit timer, with up to 4
IC/OC, usable for IR control decoding
– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,
deadtime generation and emergency stop
– 1 x 16-bit timer, with IC/OC and OCN,
deadtime generation, emergency stop and
modulator gate for IR control
– 1 x 16-bit timer with 1 IC/OC
– Independent and system watchdog timers
– SysTick timer: 24-bit downcounter
■Calendar RTC with alarm and periodic wakeup
from Stop/Standby
■Communication interfaces
– 1 x I2C interface; supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus, and wakeup from STOP
– 1 x USART supporting master synchronous
SPI and modem control; one with ISO7816
interface, LIN, IrDA capability auto baud
rate detection and wakeup feature
– 1 x SPI (18 Mbit/s) with 4 to 16
programmable bit frames, with I2S interface
multiplexed
■Serial wire debug (SWD)
■96-bit unique ID
■Extended temperature range: -40 to +105°C
Table 1. Device summary
Reference Part number
STM32F050x4 STM32F050F4, STM32F050G4, STM32F050K4,
STM32F050C4
STM32F050x6 STM32F050F6, STM32F050G6, STM32F050K6,
STM32F050C6
LQFP48 7x7 UFQFPN32 5x5
TSSOP20
UFQFPN28 4x4
www.st.com
Contents STM32F050xx
2/97 Doc ID 023683 Rev 1
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2 General-purpose timers (TIM2..3, TIM14..17) . . . . . . . . . . . . . . . . . . . . 18
3.11.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Universal synchronous/asynchronous receiver transmitter (USART) . . . 21
3.15 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 22
STM32F050xx Contents
Doc ID 023683 Rev 1 3/97
3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 40
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 40
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.17 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Contents STM32F050xx
4/97 Doc ID 023683 Rev 1
7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
STM32F050xx List of tables
Doc ID 023683 Rev 1 5/97
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F050xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 30
Table 10. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 31
Table 11. STM32F050x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Typical and maximum current consumption from VDD supply at VDD = 3.6 . . . . . . . . . . . 43
Table 21. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 44
Table 22. Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 45
Table 23. Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 45
Table 24. Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 48
Table 27. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 34. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 37. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 40. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 41. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 42. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 43. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 44. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 45. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 46. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 47. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
List of tables STM32F050xx
6/97 Doc ID 023683 Rev 1
Table 48. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 49. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 50. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 51. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 52. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 53. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 54. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 55. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 56. WWDG min-max timeout value @48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 57. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 58. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 59. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 60. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 61. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 85
Table 62. UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 63. UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 64. TSSOP20 – 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 91
Table 65. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 66. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
STM32F050xx List of figures
Doc ID 023683 Rev 1 7/97
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. UFQFPN28 28-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. STM32F050xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 13. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 15. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 16. HSI oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 17. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 18. TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 19. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 68
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . 68
Figure 22. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 24. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 26. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 27. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 28. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 29. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 30. I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 31. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 32. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 85
Figure 33. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 34. UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline . . . 87
Figure 35. UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 36. UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline . . . 89
Figure 37. UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 38. TSSOP20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 39. TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Introduction STM32F050xx
8/97 Doc ID 023683 Rev 1
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F050x4 and STM32F050x6 microcontrollers, hereafter referred to as
STM32F050xx.
This datasheet should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM Cortex™-M0 core, please refer to the Cortex™-M0 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html.
STM32F050xx Description
Doc ID 023683 Rev 1 9/97
2 Description
The STM32F050xx family incorporates the high-performance ARM Cortex™-M0 32-bit
RISC core operating at a 48 MHz maximum frequency, high-speed embedded memories
(Flash memory up to 32 Kbytes and SRAM up to 4 Kbytes), and an extensive range of
enhanced peripherals and I/Os. All devices offer standard communication interfaces (one
I2C, one SPI, one I2S, and one USART), one 12-bit ADC, up to five general-purpose 16-bit
timers, a 32-bit timer and an advanced-control PWM timer.
The STM32F050xx family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes
allows the design of low-power applications.
The STM32F050xx family includes devices in five different packages ranging from 20 pins to
48 pins. Depending on the device chosen, different sets of peripherals are included. An
overview of the complete range of peripherals proposed in this family is provided.
These features make the STM32F050xx microcontroller family suitable for a wide range of
applications such as control application and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Description STM32F050xx
10/97 Doc ID 023683 Rev 1
Table 2. STM32F050xx family device features and peripheral counts
Peripheral STM32F050Fx STM32F050Gx STM32F050Kx STM32F050Cx
Flash (Kbytes) 16 32 16 32 16 32 16 32
SRAM (Kbytes) 4 4 4 4
Timers
Advanced
control 1 (16-bit)
General
purpose
4 (16-bit)
1 (32-bit)
Comm.
interfaces
SPI (I2S)(1) 1
I2C1
USART 1
12-bit synchronized
ADC
(number of channels)
1
(9 ext. + 3 int.)
1
(10 ext. + 3 int.)
GPIOs 15232739
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: -40°C to 105°C / -40 °C to 125 °C
Packages TSSOP20 UFQFPN28 UFQFPN32 LQFP48
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
STM32F050xx Description
Doc ID 023683 Rev 1 11/97
Figure 1. Block diagram
0!; =
%84)4
.6)#
37#,+
37$!4
.234
6$$ TO 6
!&
!("
32!-
7+50
633
'0$-!
CHANNELS
84!, /3#
-(Z
84!, K(Z
/3#). 0&
/3#/54 0&
/3#?/54
/3#?).
!("0#,+
(#,+
!0"0#,+
&,!3(
6/,4 2%'
64/ 6
6$$ 0/7%2
24# INTERFACE
AS!&
"US-ATRIX
BITS
)NTERFACE
+"
24#
#/24%8-#05
F(#,+-(Z
OBL
FLASH
"ACKUP
REG
3#,3$!3-"AL
)#
AS !&
CHANNELS
COMPL CHANNELS
"2+%42 INPUT AS !&
CH%42AS!&
&#,+
0OWER
)7$'
6$$
637
0/2 0$2
3500,9
6$$!
6$$!
6"!4 6 TO 6
2848 #43 243
#+ AS !&
.6)#
30))3
#ONTROLLER
6$$!
350%26)3)/.
06$
2ESET
)NT
6$$
!0"
0/2
4!-0%224#
2%3%4
#,/#+
#/.42/,
!$##,+
0,,
!,!2- /54
3ERIAL7IRE
$EBUG
#%##,+
-)3/-#+
0";=
0#;=
0&;=
CH%42AS!&
CHANNELAS!&
6$$
+"
2#(3-(Z
53!24#,+
CHANNEL
COMPL"2+AS!&
CHANNEL
COMPL"2+AS!&
CONTROLLER
32!-
393#&' )&
M! FOR &-
)2?/54AS!&
$"'-#5
!(" DECODER
-36
4)-%2
4)-%2
4)-%2
4)-%2
4)-%2
4)-%2
53!24
'0)/PORT!
'0)/PORT"
'0)/PORT#
'0)/PORT&
BIT!$#
!$#?).
6$$!
4EMP SENSOR
633! 6$$!
)&
2#(3-(Z
2#,3
3#+#+
-/3)3$
.3373AS!&
77$'
#2#
Functional overview STM32F050xx
12/97 Doc ID 023683 Rev 1
3 Functional overview
3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM
The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F050xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2 Memories
The device has the following features:
●4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
●The non-volatile memory is divided into two arrays:
– 16 to 32 Kbytes of embedded Flash memory for programs and data
–Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
3.3 Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
●Boot from User Flash
●Boot from System Memory
●Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
STM32F050xx Functional overview
Doc ID 023683 Rev 1 13/97
3.4 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Power management
3.5.1 Power supply schemes
●VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●VDDA = 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL
(minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). The VDDA
voltage level must be always greater or equal to the VDD voltage level and must be
provided first.
●VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
3.5.2 Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
●The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
●The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
Functional overview STM32F050xx
14/97 Doc ID 023683 Rev 1
3.5.3 Voltage regulator
The regulator has three operating modes: main (MR), low power (LPR) and power down.
●MR is used in normal operating mode (Run)
●LPR can be used in Stop mode where the power demand is reduced
●Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
3.5.4 Low-power modes
The STM32F050xx family supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
●Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC alarm, I2C1 or
USART1.
The I2C1 and the USART1 can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used, the voltage regulator should not be put in the
low-power mode but kept in normal mode.
●Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pins, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
STM32F050xx Functional overview
Doc ID 023683 Rev 1 15/97
3.6 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Figure 2. Clock tree
-(Z
(3%/3#
/3#?).
/3#?/54
/3#?).
/3#?/54
-(Z
(3)2#
TO)7$'
0,,
XX
X
0,,-5,
-#/
-AINCLOCK
OUTPUT
!("
0,,#,+
(3)
(3%
!0"
PRESCALER
!$#
0RESCALER
(#,+
0,,#,+
TO!("BUSCORE
MEMORYAND$-!
TO!$#
-(ZMAX
,3%
,3)
(3)
(3)
(3%
TO24#
0,,32# 37
-#/
393#,+
24##,+
24#3%,;=
)7$'#,+
393#,+
TO4)-
)F!0"PRESCALER
XELSEX
&,)4&#,+
TO&LASHPROGRAMMINGINTERFACE
(3)
-(Z
(3)2#
(3)
TO)#
TO53!24
,3%
(3)
393#,+
0#,+
393#,+
(3)
0#,+
-36
TO)3
TOCORTEX3YSTEMTIMER
&(#,+#ORTEXFREERUNNINGCLOCK
TO!0"PERIPHERALS
!("
PRESCALER
#33
,3%/3#
K(Z
,3)2#
K(Z
,3)
,3%
Functional overview STM32F050xx
16/97 Doc ID 023683 Rev 1
3.7 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.
3.8 Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14) and ADC.
3.9 Interrupts and events
3.9.1 Nested vectored interrupt controller (NVIC)
The STM32F050xx family embeds a nested vectored interrupt controller able to handle up
to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4
priority levels.
●Closely coupled NVIC gives low latency interrupt processing
●Interrupt entry vector table address passed directly to the core
●Closely coupled NVIC core interface
●Allows early processing of interrupts
●Processing of late arriving higher priority interrupts
●Support for tail-chaining
●Processor state automatically saved
●Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2 Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 39
GPIOs can be connected to the 16 external interrupt lines.
STM32F050xx Functional overview
Doc ID 023683 Rev 1 17/97
3.10 Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1 Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.10.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area. It is accessible in read-only mode.
Table 3. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C
VDDA= 3.3 V
0x1FFF F7C2 - 0x1FFF F7C3
Table 4. Temperature sensor calibration values
Calibration value name Description Memory address
VREFINT_CAL
Raw data acquired at
temperature of 30 °C
VDDA= 3.3 V
0x1FFF F7BA - 0x1FFF F7BB
Functional overview STM32F050xx
18/97 Doc ID 023683 Rev 1
3.11 Timers and watchdogs
The STM32F050xx family devices include up to six general-purpose timers, one basic timer
and an advanced control timer.
Ta bl e 5 compares the features of the advanced-control, general-purpose and basic timers.
3.11.1 Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
●Input capture
●Output compare
●PWM generation (edge or center-aligned modes)
●One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.11.2 General-purpose timers (TIM2..3, TIM14..17)
There are six synchronizable general-purpose timers embedded in the STM32F050xx
devices (see Ta b l e 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
Table 5. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Capture/compare
channels
Complementary
outputs
Advanced
control TIM1 16-bit Up, down,
up/down
Any integer
between 1
and 65536
Ye s 4 Ye s
General
purpose
TIM2 32-bit Up, down,
up/down
Any integer
between 1
and 65536
Ye s 4 N o
TIM3 16-bit Up, down,
up/down
Any integer
between 1
and 65536
Ye s 4 N o
TIM14 16-bit Up
Any integer
between 1
and 65536
No 1 No
TIM16,
TIM17 16-bit Up
Any integer
between 1
and 65536
Ye s 1 Ye s
STM32F050xx Functional overview
Doc ID 023683 Rev 1 19/97
TIM2, TIM3
STM32F050xx devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or
one-pulse mode output.
TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
3.11.3 Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-
defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.11.4 System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
Functional overview STM32F050xx
20/97 Doc ID 023683 Rev 1
3.11.5 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
●A 24-bit down counter
●Autoreload capability
●Maskable system interrupt generation when the counter reaches 0.
●Programmable clock source (HCLK or HCLK/8)
3.12 Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
●Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
●Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.
●Programmable alarm with wake up from Stop and Standby mode capability.
●On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
●Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
●2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
●Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
●A 32.768 kHz external crystal
●A resonator or oscillator
●The internal low-power RC oscillator (typical frequency of 40 kHz)
●The high-speed external clock divided by 32.
STM32F050xx Functional overview
Doc ID 023683 Rev 1 21/97
3.13 Inter-integrated circuit interface (I2C)
The I2C interface (I2C1) can operate in multimaster or slave mode. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,
1 with configurable mask). It also includes programmable analog and digital noise filters.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interface can be served by the DMA controller.
3.14 Universal synchronous/asynchronous receiver transmitter
(USART)
The device embeds an universal synchronous/asynchronous receiver transmitters
(USART1), which communicates at speeds of up to 6 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. It also supports SmartCard communication (ISO 7816), IrDA SIR
ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain
independent from the CPU clock, allowing it to wake up the MCU from Stop mode.
The USART interface can be served by the DMA controller.
Table 6. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of
suppressed spikes ≥ 50 ns Programmable length from 1 to 15
I2C peripheral clocks
Benefits Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Functional overview STM32F050xx
22/97 Doc ID 023683 Rev 1
3.15 Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
The SPI (SPI1) is able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I2S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit
programmable linear prescaler. When operating in master mode it can output a clock for an
external audio component at 256 times the sampling frequency.
3.16 Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
STM32F050xx Pinouts and pin description
Doc ID 023683 Rev 1 23/97
4 Pinouts and pin description
Figure 3. LQFP48 48-pin package pinout
Figure 4. UFQFPN32 32-pin package pinout
,1&0
0!
0!
0!
0!
0!
0"
0"
0"
0"
0"
633
6$$
0&
0&
0!
0!
0!
0!
0!
0!
0"
0"
0"
0"
6"!4
.234
633!
6$$!
0!
0!
0!
6$$
633
0"
0"
"//4
0"
0"
0"
0"
0"
0!
0!
-36
0#
0#/3#?).
0&/3#?).
0&/3#?/54
0#/3#?/54
0!
6$$
.234
0!
0!
0!
0!
0!
0"
0!
6$$
0!
0!
0!
0!
0!
0!
0"
"//4
0"
0"
0"
-36
6$$!
0"
0"
0!
0"
0"
0!
0&/3#?).
0&/3#?/54
0!
633
633!
Pinouts and pin description STM32F050xx
24/97 Doc ID 023683 Rev 1
Figure 5. UFQFPN28 28-pin package pinout
Figure 6. TSSOP20 20-pin package pinout
0!
0!
0!
0"
0!
0!
0!
6$$!
0&/3#?).
.234
"//4
6$$
633
0"
0!
0!
0!
0"
0"
0!
0!
0"
0"
0"
0&/3#?/54
-36
0!
0!
0!
-36
0&/3#?).
"//4
0&/3#?/54
.234
6$$!
0!
0!
6$$
0!
0!
0!
0"
633
0!
0!
0!
0! 0!
0!
0!
STM32F050xx Pinouts and pin description
Doc ID 023683 Rev 1 25/97
Table 7. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
TTa 3.3 V tolerant I/O directly connected to ADC
TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Pin
functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Pinouts and pin description STM32F050xx
26/97 Doc ID 023683 Rev 1
Table 8. Pin definitions
Pin number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP48
UFQFPN32
UFQFPN28
TSSOP20
Alternate functions Additional
functions
1 - - - VBAT S Backup power supply
2- - - PC13 I/OTC
(1)(2)
RTC_TAMP1,
RTC_TS,
RTC_OUT,
WKUP2
3- - - PC14/OSC32_IN
(PC14) I/O TC (1)(2) OSC32_IN
4- - -PC15/OSC32_OUT
(PC15) I/O TC (1)(2) OSC32_OUT
52 2 2 PF0/OSC_IN
(PF0) I/O FT OSC_IN
63 3 3 PF1/OSC_OUT
(PF1) I/O FT OSC_OUT
7 4 4 4 NRST I/O RST Device reset input / internal reset output
(active low)
8 0 - - VSSA S Analog ground
9 5 5 5 VDDA S Analog power supply
10 6 6 6 PA0 I/O TTa TIM2_CH1_ETR,
USART1_CTS(3)
ADC_IN0,
RTC_TAMP2,
WKUP1
11 7 7 7 PA1 I/O TTa
TIM2_CH2,
EVENTOUT,
USART1_RTS(3)
ADC_IN1
12 8 8 8 PA2 I/O TTa TIM2_CH3,
USART1_TX(3) ADC_IN2
13 9 9 9 PA3 I/O TTa TIM2_CH4,
USART1_RX(3) ADC_IN3
14 10 10 10 PA4 I/O TTa
SPI1_NSS,
I2S1_WS,
TIM14_CH1,
USART1_CK(3)
ADC_IN4
15 11 11 11 PA5 I/O TTa
SPI1_SCK,
I2S1_CK,
TIM2_CH1_ETR
ADC_IN5
STM32F050xx Pinouts and pin description
Doc ID 023683 Rev 1 27/97
16 12 12 12 PA6 I/O TTa
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
TIM1_BKIN,
TIM16_CH1,
EVENTOUT
ADC_IN6
17 13 13 13 PA7 I/O TTa
SPI1_MOSI,
I2S1_SD,
TIM3_CH2,
TIM14_CH1,
TIM1_CH1N,
TIM17_CH1,
EVENTOUT
ADC_IN7
18 14 14 - PB0 I/O TTa
TIM3_CH3,
TIM1_CH2N,
EVENTOUT
ADC_IN8
19 15 15 14 PB1 I/O TTa
TIM3_CH4,
TIM14_CH1,
TIM1_CH3N
ADC_IN9
20 16 - - PB2 I/O FT
21 - - - PB10 I/O FTf TIM2_CH3,
I2C1_SCL(3)
22 - - - PB11 I/O FTf
TIM2_CH4,
EVENTOUT,
I2C1_SDA(3)
23 0 16 15 VSS S Ground
24 17 17 16 VDD S Digital power supply
25 - - - PB12 I/O FT
TIM1_BKIN,
EVENTOUT,
SPI1_NSS(3)
26 - - - PB13 I/O FT TIM1_CH1N,
SPI1_SCK(3)
27 - - - PB14 I/O FT TIM1_CH2N,
SPI1_MISO(3)
28 - - - PB15 I/O FT TIM1_CH3N,
SPI1_MOSI(3) RTC_REFIN
Table 8. Pin definitions (continued)
Pin number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP48
UFQFPN32
UFQFPN28
TSSOP20
Alternate functions Additional
functions
Pinouts and pin description STM32F050xx
28/97 Doc ID 023683 Rev 1
29 18 18 - PA8 I/O FT
USART1_CK,
TIM1_CH1,
EVENTOUT,
MCO
30 19 19 17 PA9 I/O FTf
USART1_TX,
TIM1_CH2,
I2C1_SCL(3)
31 20 20 18 PA10 I/O FTf
USART1_RX,
TIM1_CH3,
TIM17_BKIN,
I2C1_SDA(3)
32 21 - - PA11 I/O FT
USART1_CTS,
TIM1_CH4,
EVENTOUT
33 22 - - PA12 I/O FT
USART1_RTS,
TIM1_ETR,
EVENTOUT
34 23 21 19 PA 1 3
(SWDAT) I/O FT (4) IR_OUT,
SWDAT
35 - - - PF6 I/O FTf I2C1_SCL(3)
36 - - - PF7 I/O FTf I2C1_SDA(3)
37 24 22 20 PA 1 4
(SWCLK) I/O FT (4) SWCLK,
USART1_TX(3)
38 25 23 - PA15 I/O FT
SPI1_NSS,
I2S1_WS,
TIM2_CH_ETR,
EVENTOUT,
USART1_RX(3)
39 26 24 - PB3 I/O FT
SPI1_SCK,
I2S1_CK,
TIM2_CH2,
EVENTOUT
40 27 25 - PB4 I/O FT
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
EVENTOUT
Table 8. Pin definitions (continued)
Pin number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP48
UFQFPN32
UFQFPN28
TSSOP20
Alternate functions Additional
functions
STM32F050xx Pinouts and pin description
Doc ID 023683 Rev 1 29/97
41 28 26 - PB5 I/O FT
SPI1_MOSI,
I2S1_SD,
I2C1_SMBA,
TIM16_BKIN,
TIM3_CH2
42 29 27 - PB6 I/O FTf
I2C1_SCL,
USART1_TX,
TIM16_CH1N
43 30 28 - PB7 I/O FTf
I2C1_SDA,
USART1_RX,
TIM17_CH1N
44 31 1 1 BOOT0 I B Boot memory selection
45 32 - - PB8 I/O FTf I2C1_SCL,
TIM16_CH1
46 - - - PB9 I/O FTf
I2C1_SDA,
IR_OUT,
TIM17_CH1,
EVENTOUT
47 0 - - VSS S Ground
48 1 - - VDD S Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as a current sources (e.g. to drive an LED).
2. After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the
Battery backup domain and BKP register description sections in the STM32F05xx reference manual.
3. This alternate feature is available on standard dies only.
4. After reset, these pins are configured as SWDAT and SWCLK alternate functions, and the internal pull-up on SWDAT pin
and internal pull-down on SWCLK pin are activated.
Table 8. Pin definitions (continued)
Pin number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP48
UFQFPN32
UFQFPN28
TSSOP20
Alternate functions Additional
functions
Pinouts and pin description STM32F050xx
30/97 Doc ID 023683 Rev 1
Table 9. Alternate functions selected through GPIOA_AFR registers for port A
Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PA0 USART1_CKS(1) TIM2_CH1_
ETR
PA1 EVENTOUT USART1_TX(1) TIM2_CH2
PA2 USART1_RX(1) TIM2_CH3
PA3 USART1_CTS(1) TIM2_CH4
PA 4 SPI1_NSS,
I2S1_WS USART1_RTS(1) TIM14_CH1
PA 5 SPI1_SCK,
I2S1_CK
TIM2_CH1_
ETR
PA 6 SPI1_MISO,
I2S1_MCK TIM3_CH1 TIM1_BKIN TIM16_CH1 EVENTOUT
PA 7 SPI1_MOSI,
I2S1_SD TIM3_CH2 TIM1_CH1N TIM14_CH1 TIM17_CH1 EVENTOUT
PA8 MCO USART1_CK TIM1_CH1 EVENTOUT
PA9 USART1_TX TIM1_CH2 I2C1_SCL(1)
PA10 TIM17_BKIN USART1_RX TIM1_CH3 I2C1_SDA(1)
PA11 EVENTOUT USART1_CTS TIM1_CH4
PA12 EVENTOUT USART1_RTS TIM1_ETR
PA 1 3 S W DAT I R _ O U T
PA14 SWCLK USART1_TX(1)
PA 1 5 SPI1_NSS,
I2S1_WS USART1_RX(1) TIM2_CH1_
ETR EVENTOUT
1. This alternate feature is available on standard dies only.
STM32F050xx Pinouts and pin description
Doc ID 023683 Rev 1 31/97
Table 10. Alternate functions selected through GPIOB_AFR registers for port B
Pin name AF0 AF1 AF2 AF3
PB0 EVENTOUT TIM3_CH3 TIM1_CH2N
PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N
PB2
PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2
PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT
PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA
PB6 USART1_TX I2C1_SCL TIM16_CH1N
PB7 USART1_RX I2C1_SDA TIM17_CH1N
PB8 I2C1_SCL TIM16_CH1
PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT
PB10 I2C1_SCL(1) TIM2_CH3
PB11 EVENTOUT I2C1_SDA(1) TIM2_CH4
PB12 SPI1_NSS(1) EVENTOUT TIM1_BKIN
PB13 SPI1_SCK(1) TIM1_CH1N
PB14 SPI1_MISO(1) TIM1_CH2N
PB15 SPI1_MOSI(1) TIM1_CH3N
1. This alternate feature is available on standard dies only.
Memory mapping STM32F050xx
32/97 Doc ID 023683 Rev 1
5 Memory mapping
Figure 7. STM32F050xx memory map
2ESERVED
!("
X&&&&&&&&
0ERIPHERALS
32!-
&LASHMEMORY
RESERVED
RESERVED
3YSTEMMEMORY
/PTION
BYTES
X%
-36
&LASHSYSTEMMEMORY
OR32!-DEPENDINGON
"//4CONFIGURATION
X
X%
X#
X!
X
X
X
X
X
X
X
X&&&%#
X&&&&
X&&&&#
X&&&&&&&
X
RESERVED
#/$%
!0"
!0"
RESERVED
X
X
X
X
RESERVED
X
!("
X
RESERVED
X&&
X&&
X
X
#ORTEX-INTERNAL
PERIPHERALS
STM32F050xx Memory mapping
Doc ID 023683 Rev 1 33/97
Table 11. STM32F050x peripheral register boundary addresses
Bus Boundary address Size Peripheral
0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved
AHB2
0x4800 1400 - 0x4800 17FF 1KB GPIOF
0x4800 1000 - 0x4800 13FF 1KB Reserved
0x4800 0C00 - 0x4800 0FFF 1KB Reserved
0x4800 0800 - 0x4800 0BFF 1KB GPIOC
0x4800 0400 - 0x4800 07FF 1KB GPIOB
0x4800 0000 - 0x4800 03FF 1KB GPIOA
0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
AHB1
0x4002 4000 - 0x4002 43FF 1KB Reserved
0x4002 3400 - 0x4002 3FFF 3KB Reserved
0x4002 3000 - 0x4002 33FF 1KB CRC
0x4002 2400 - 0x4002 2FFF 3KB Reserved
0x4002 2000 - 0x4002 23FF 1KB FLASH Interface
0x4002 1400 - 0x4002 1FFF 3KB Reserved
0x4002 1000 - 0x4002 13FF 1KB RCC
0x4002 0400 - 0x4002 0FFF 3KB Reserved
0x4002 0000 - 0x4002 03FF 1KB DMA
0x4001 8000 - 0x4001 FFFF 32KB Reserved
APB
0x4001 5C00 - 0x4001 7FFF 9KB Reserved
0x4001 5800 - 0x4001 5BFF 1KB DBGMCU
0x4001 4C00 - 0x4001 57FF 3KB Reserved
0x4001 4800 - 0x4001 4BFF 1KB TIM17
0x4001 4400 - 0x4001 47FF 1KB TIM16
0x4001 4000 - 0x4001 43FF 1KB Reserved
0x4001 3C00 - 0x4001 3FFF 1KB Reserved
0x4001 3800 - 0x4001 3BFF 1KB USART1
0x4001 3400 - 0x4001 37FF 1KB Reserved
0x4001 3000 - 0x4001 33FF 1KB SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF 1KB TIM1
0x4001 2800 - 0x4001 2BFF 1KB Reserved
0x4001 2400 - 0x4001 27FF 1KB ADC
0x4001 0800 - 0x4001 23FF 7KB Reserved
0x4001 0400 - 0x4001 07FF 1KB EXTI
0x4001 0000 - 0x4001 03FF 1KB SYSCFG
0x4000 8000 - 0x4000 FFFF 32KB Reserved
Memory mapping STM32F050xx
34/97 Doc ID 023683 Rev 1
APB
0x4000 7C00 - 0x4000 7FFF 1KB Reserved
0x4000 7800 - 0x4000 7BFF 1KB Reserved
0x4000 7400 - 0x4000 77FF 1KB Reserved
0x4000 7000 - 0x4000 73FF 1KB PWR
0x4000 5C00 - 0x4000 6FFF 5KB Reserved
0x4000 5800 - 0x4000 5BFF 1KB Reserved
0x4000 5400 - 0x4000 57FF 1KB I2C1
0x4000 4800 - 0x4000 53FF 3 KB Reserved
0x4000 4400 - 0x4000 47FF 1KB Reserved
0x4000 3C00 - 0x4000 43FF 2KB Reserved
0x4000 3800 - 0x4000 3BFF 1KB Reserved
0x4000 3400 - 0x4000 37FF 1KB Reserved
0x4000 3000 - 0x4000 33FF 1KB IWDG
0x4000 2C00 - 0x4000 2FFF 1KB WWDG
0x4000 2800 - 0x4000 2BFF 1KB RTC
0x4000 2400 - 0x4000 27FF 1KB Reserved
0x4000 2000 - 0x4000 23FF 1KB TIM14
0x4000 1400 - 0x4000 1FFF 3KB Reserved
0x4000 1000 - 0x4000 13FF 1KB Reserved
0x4000 0800 - 0x4000 0FFF 2KB Reserved
0x4000 0400 - 0x4000 07FF 1KB TIM3
0x4000 0000 - 0x4000 03FF 1KB TIM2
Table 11. STM32F050x peripheral register boundary addresses (continued)
Bus Boundary address Size Peripheral
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 35/97
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8. Pin loading conditions Figure 9. Pin input voltage
-36
C = 50 pF
-#5PIN
-36
-#5PIN
6).
Electrical characteristics STM32F050xx
36/97 Doc ID 023683 Rev 1
6.1.6 Power supply scheme
Figure 10. Power supply scheme
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
6.1.7 Current consumption measurement
Figure 11. Current consumption measurement scheme
-36
!NALOG
2#S0,,
0O WERSWITCH
6"!4
'0 )/ S
/54
). +ERNELLOGIC
#05
$IGITAL
-EMORIES
"ACKUPCIRCUITRY
,3%24#
"ACKUPREGISTERS
7AKEUPLOGIC
§N&
§&
6
2EGULATOR
6$$!
633!
!$#
$!#
,EVELSHIFTER
)/
,OGIC
6$$
N&
&
6$$!
62%&
62%&
6$$
633
§
§
-36
6"!4
6$$
6$$!
)$$
)$$!
*%%@7#"5
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 37/97
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics,
Table 13: Current characteristics, and Table 14: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 12. Voltage characteristics(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
Symbol Ratings Min Max Unit
VDD–VDDA Allowed voltage difference for VDD >V
DDA -0.4V
VIN(2)
2. VIN maximum must always be respected. Refer to Table 13: Current characteristics for the maximum
allowed injected current values.
Input voltage on FT and FTf pins VSS − 0.3 VDD + 4.0 V
Input voltage on TTa pins VSS − 0.3 4.0 V
Input voltage on any other pin VSS − 0.3 4.0 V
|ΔVDDx| Variations between different VDD power pins - 50 mV
|VSSX − VSS|Variations between all the different ground
pins -50mV
VESD(HBM)
Electrostatic discharge voltage (human
body model)
see Section 6.3.11: Electrical
sensitivity characteristics
Table 13. Current characteristics
Symbol Ratings Max. Unit
IVDD(Σ)
Total current into sum of all VDD_x and VDDSDx power lines
(source)(1) 120
mA
IVSS(Σ)
Total current out of sum of all VSS_x and VSSSD ground lines
(sink)(1) -120
IVDD(PIN) Maximum current into each VDD_x or VDDSDx power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS_x or VSSSD ground pin (sink)(1) -100
IIO(PIN)
Output current sunk by any I/O and control pin 25
Output current source by any I/O and control pin - 25
ΣIIO(PIN)
Total output current sunk by sum of all IOs and control pins(2) 80
Total output current sourced by sum of all IOs and control pins(2) -80
IINJ(PIN)
Injected current on FT, FTf and B pins(3) -5/+0
Injected current on TC and RST pin(4) ± 5
Injected current on TTa pins(5) ± 5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
Electrical characteristics STM32F050xx
38/97 Doc ID 023683 Rev 1
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 12: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 12: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note (2) below Table 51: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 14. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 39/97
6.3 Operating conditions
6.3.1 General operating conditions
Table 15. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 48 MHz
fPCLK Internal APB clock frequency 0 48
VDD Standard operating voltage 2 3.6 V
VDDA(1)
Analog operating voltage
(ADC not used) Must have a potential equal to or
higher than VDD
23.6
V
Analog operating voltage
(ADC used) 2.4 3.6
VBAT Backup operating voltage 1.65 3.6 V
VIN I/O input voltage
TC I/O –0.3 VDD+0.3
V
TTa I/O –0.3 VDDA+0.3
FT and FTf I/O(2) –0.3 5.5
BOOT0 0 5.5
PD
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(3)
LQFP48 - 364
mW
UFQFPN32 - 526
UFQFPN28 - 169
TSSOP20 - 182
TA
Ambient temperature for 6
suffix version
Maximum power dissipation –40 85 °C
Low power dissipation(4) –40 105
Ambient temperature for 7
suffix version
Maximum power dissipation –40 105 °C
Low power dissipation(4) –40 125
TJ Junction temperature range 6 suffix version –40 105 °C
7 suffix version –40 125
1. When the ADC is used, refer to Table 49: ADC characteristics.
2. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 14: Thermal characteristics).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 14:
Thermal characteristics).
Electrical characteristics STM32F050xx
40/97 Doc ID 023683 Rev 1
6.3.2 Operating conditions at power-up / power-down
The parameters given in Ta b l e 1 6 are derived from tests performed under the ambient
temperature condition summarized in Ta bl e 1 5 .
6.3.3 Embedded reset and power control block characteristics
The parameter given in Ta b l e 1 7 is derived from tests performed under ambient temperature
and VDD supply voltage conditions summarized in Table 15: General operating conditions.
Table 16. Operating conditions at power-up / power-down
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate 0 ∞
µs/V
VDD fall time rate 20 ∞
tVDDA
VDDA rise time rate 0 ∞
VDDA fall time rate 20 ∞
Table 17. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPOR/PDR(1)
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
Power on/power down
reset threshold
Falling edge 1.8(2)
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
1.88 1.96 V
Rising edge 1.84 1.92 2.0 V
VPDRhyst(1) PDR hysteresis - 40 - mV
tRSTTEMPO(3)
3. Guaranteed by design, not tested in production.
Reset temporization 1.5 2.5 4.5 ms
Table 18. Programmable voltage detector characteristics
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
VPVD0 PVD threshold 0 Rising edge 2.1 2.18 2.26 V
Falling edge 2 2.08 2.16 V
VPVD1 PVD threshold 1 Rising edge 2.19 2.28 2.37 V
Falling edge 2.09 2.18 2.27 V
VPVD2 PVD threshold 2 Rising edge 2.28 2.38 2.48 V
Falling edge 2.18 2.28 2.38 V
VPVD3 PVD threshold 3 Rising edge 2.38 2.48 2.58 V
Falling edge 2.28 2.38 2.48 V
VPVD4 PVD threshold 4 Rising edge 2.47 2.58 2.69 V
Falling edge 2.37 2.48 2.59 V
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 41/97
6.3.4 Embedded reference voltage
The parameters given in Ta b l e 1 9 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 15: General operating
conditions.
VPVD5 PVD threshold 5 Rising edge 2.57 2.68 2.79 V
Falling edge 2.47 2.58 2.69 V
VPVD6 PVD threshold 6 Rising edge 2.66 2.78 2.9 V
Falling edge 2.56 2.68 2.8 V
VPVD7 PVD threshold 7 Rising edge 2.76 2.88 3 V
Falling edge 2.66 2.78 2.9 V
VPVDhyst(2) PVD hysteresis - 100 - mV
IDD(PVD) PVD current consumption - 0.15 0.26 µA
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
Table 18. Programmable voltage detector characteristics (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Table 19. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.16 1.2 1.25 V
–40 °C < TA < +85 °C 1.16 1.2 1.24(1)
1. Data based on characterization results, not tested in production.
V
TS_vrefint (2)
2. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when
reading the internal
reference voltage
- 5.1 17.1(3)
3. Guaranteed by design, not tested in production.
µs
ΔVREFINT
Internal reference voltage
spread over the
temperature range
VDDA = 3 V ±10 mV - - 10(3) mV
TCoeff Temperature coefficient - - 100(3) ppm/°C
Electrical characteristics STM32F050xx
42/97 Doc ID 023683 Rev 1
6.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
The data provided apply to standard dies only.
Typical and maximum current consumption
The MCU is placed under the following conditions:
●All I/O pins are in input mode with a static value at VDD or VSS (no load)
●All peripherals are disabled except when explicitly mentioned
●The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz and 1 wait state above 24 MHz)
●Prefetch is ON when the peripherals are enabled, otherwise it is OFF (to enable
prefetch the PRFTBE bit in the FLASH_ACR register must be set before clock setting
and bus prescaling)
●When the peripherals are enabled fPCLK = fHCLK
The parameters given in Ta b l e 2 0 to Ta b l e 2 6 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 15: General
operating conditions.
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 43/97
Table 20. Typical and maximum current consumption from VDD supply at VDD = 3.6
Symbol
Parameter
Conditions fHCLK
All peripherals enabled All peripherals disabled
Unit
Typ
Max @ TA(1)
Typ
Max @ TA(1)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
IDD
Supply
current in
Run mode,
executing
from Flash
External
clock (HSE
bypass)
48 MHz 18.4 20.0 20.1 20.4 11.4 12.5 12.5 12.6
mA
32 MHz 12.4 13.2 13.2 13.8 7.9 8.3 8.5 8.6
24 MHz 9.9 10.7 10.7 11.0 6.2 6.8 7.0 7.0
8 MHz 3.3 3.6 3.8 3.9 2.2 2.6 2.6 2.6
1 MHz 0.8 1.1 1.1 1.1 0.7 0.9 0.9 0.9
Internal
clock (HSI)
48 MHz 18.9 20.9 21.1 21.5 11.7 12.3 12.9 13.1
32 MHz 12.8 13.7 14.2 14.8 8.0 8.7 9.1 9.1
24 MHz 9.7 10.4 11.2 11.3 6.1 6.5 6.7 6.9
8 MHz 3.5 4.0 4.0 4.1 2.4 2.6 2.7 2.7
Supply
current in
Run mode,
executing
from RAM
External
clock (HSE
bypass)
48 MHz 17.3 19.7 19.8 20.0 10.3 11.2 11.3 11.7
32 MHz 11.2 12.5 12.7 12.7 6.7 7.3 7.6 7.6
24 MHz 8.9 10.0 10.1 10.2 5.1 5.5 5.8 5.9
8 MHz 2.8 3.1 3.3 3.4 1.7 2.0 2.1 2.1
1 MHz 0.3 0.6 0.6 1.3 0.2 0.5 0.8 0.8
Internal
clock (HSI)
48 MHz 17.4 19.7 20.0 20.2 10.4 11.2 11.3 11.8
32 MHz 11.8 12.8 13.1 13.3 6.8 7.4 7.7 7.9
24 MHz 9.0 10.0 10.1 10.2 5.2 5.7 6.0 6.0
8 MHz 3.0 3.2 3.5 3.6 1.8 2.0 2.2 2.2
Supply
current in
Sleep
mode,
executing
from Flash
or RAM
External
clock (HSE
bypass)
48 MHz 10.7 11.7 11.9 12.5 2.4 2.6 2.7 2.9
32 MHz 7.1 7.8 8.1 8.2 1.6 1.7 1.9 1.9
24 MHz 5.5 6.3 6.4 6.4 1.3 1.4 1.5 1.5
8 MHz 1.8 2.0 2.0 2.1 0.4 0.4 0.5 0.5
1 MHz 0.2 0.5 0.5 0.5 0.1 0.1 0.1 0.1
Internal
clock (HSI)
48 MHz 10.8 11.9 12.1 12.6 2.4 2.7 2.7 2.9
32 MHz 7.3 8.0 8.4 8.5 1.7 1.9 1.9 2.0
24 MHz 5.5 6.2 6.5 6.5 1.3 1.5 1.5 1.6
8 MHz 1.9 2.2 2.3 2.4 0.5 0.5 0.5 0.6
Electrical characteristics STM32F050xx
44/97 Doc ID 023683 Rev 1
Table 21. Typical and maximum current consumption from the VDDA supply
Symbol Parameter Conditions
(1) fHCLK
VDDA = 2.4 V VDDA = 3.6 V
Unit
Typ
Max @ TA(2)
Typ
Max @ TA(2)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
IDDA
Supply
current in
Run mode,
code
executing
from Flash
or RAM
HSE
bypass,
PLL on
48 MHz 150 170 178 182 164 183 195 198
µA
32 MHz 104 121 126 128 113 129 135 138
24 MHz 82 96 100 103 88 102 106 108
HSE
bypass,
PLL off
8 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
1 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
HSI clock,
PLL on
48 MHz 220 240 248 252 244 263 275 278
32 MHz 174 191 196 198 193 209 215 218
24 MHz 152 167 173 174 168 183 190 192
HSI clock,
PLL off 8 MHz 72 79 82 83 83.5 91 94 95
Supply
current in
Sleep
mode,
code
executing
from Flash
or RAM
HSE
bypass,
PLL on
48 MHz 150 170 178 182 164 183 195 198
32 MHz 104 121 126 128 113 129 135 138
24 MHz 82 96 100 103 88 102 106 108
HSE
bypass,
PLL off
8 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
1 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
HSI clock,
PLL on
48 MHz 220 240 248 252 244 263 275 278
32 MHz 174 191 196 198 193 209 215 218
24 MHz 152 167 173 174 168 183 190 192
HSI clock,
PLL off 8 MHz 72 79 82 83 83.5 91 94 95
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 45/97
upply current
Table 22. Typical and maximum VDD consumption in Stop and Standby modes
Symbol Parameter Conditions
Typ @VDD (VDD = VDDA)Max
(1)
Unit
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply
current in
Stop mode
Regulator in run mode,
all oscillators OFF 15 15.1 15.25 15.45 15.7 16 18(2) 38 55(2)
µA
Regulator in low-power
mode, all oscillators
OFF
3.15 3.25 3.35 3.45 3.7 4 5.5(2) 22 41(2)
Supply
current in
Standby
mode
LSI ON and IWDG ON 0.8 0.95 1.05 1.2 1.35 1.5 - - -
LSI OFF and IWDG
OFF 0.65 0.75 0.85 0.95 1.1 1.3 2(2) 2.5 3(2)
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production.
Table 23. Typical and maximum VDDA consumption in Stop and Standby modes
Symbol Parameter Conditions
Typ @VDD (VDD = VDDA)Max
(1)
Unit
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA =
25 °C
TA =
85 °C
TA =
105 °C
IDDA
Supply
current in
Stop mode
VDDA monitoring ON
Regulator in run mode,
all oscillators OFF 1.85 2 2.15 2.3 2.45 2.6 3.5 3.5 4.5
µA
Regulator in low-power
mode, all oscillators
OFF
1.85 2 2.15 2.3 2.45 2.6 3.5 3.5 4.5
Supply
current in
Standby
mode
LSI ON and IWDG ON 2.25 2.5 2.65 2.85 3.05 3.3 - - -
LSI OFF and IWDG
OFF 1.75 1.9 2 2.15 2.3 2.5 3.5 3.5 4.5
Supply
current in
Stop mode
VDDA monitoring OFF
Regulator in run mode,
all oscillators OFF 1.11 1.15 1.18 1.22 1.27 1.35 - - -
Regulator in low-power
mode, all oscillators
OFF
1.11 1.15 1.18 1.22 1.27 1.35 - - -
Supply
current in
Standby
mode
LSI ON and IWDG ON 1.5 1.58 1.65 1.78 1.91 2.04 - - -
LSI OFF and IWDG
OFF 1 1.02 1.05 1.05 1.15 1.22 - - -
1. Data based on characterization results, not tested in production.
Electrical characteristics STM32F050xx
46/97 Doc ID 023683 Rev 1
Typical current consumption
The MCU is placed under the following conditions:
●VDD=VDDA=3.3 V
●All I/O pins are in analog input configuration
●The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state above)
●Prefetch is ON when the peripherals are enabled, otherwise it is OFF
●When the peripherals are enabled, fPCLK = fHCLK
●PLL is used for frequencies greater than 8 MHz
●AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
●A development tool is connected to the board and the parasitic pull-up current is around
30 µA
Table 24. Typical and maximum current consumption from VBAT supply
Symbol Parameter Conditions
Typ @ VBAT Max(1)
Unit
= 1.65 V
= 1.8 V
= 2.4 V
= 2.7 V
= 3.3 V
= 3.6 V
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD_VBAT
Backup
domain
supply
current
LSE & RTC ON; “Xtal
mode”: lower driving
capability;
LSEDRV[1:0] = '00'
0.41 0.43 0.53 0.58 0.71 0.80 0.85 1.1 1.5
µA
LSE & RTC ON; “Xtal
mode” higher driving
capability;
LSEDRV[1:0] = '11'
0.71 0.75 0.85 0.91 1.06 1.16 1.25 1.55 2
1. Data based on characterization results, not tested in production.
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 47/97
Table 25. Typical current consumption in Run mode, code with data processing
running from Flash
Symbol Parameter Conditions fHCLK
Typ
Unit
Peripherals
enabled
Peripherals
disabled
IDD
Supply current in Run
mode from VDD
supply
Running from
HSE crystal
clock 8 MHz,
code
executing
from Flash
48 MHz 18.4 11.4
mA
36 MHz 13.9 8.9
32 MHz 12.4 7.9
24 MHz 9.9 6.2
16 MHz 6.6 4.3
8 MHz 3.3 2.2
4 MHz 1.7 1.6
2 MHz 1.3 1.2
1 MHz 0.8 0.7
500 kHz 0.6 0.6
IDDA
Supply current in Run
mode from VDDA
supply
48 MHz 140 140
µA
36 MHz 109 109
32 MHz 96 96
24 MHz 76 76
16 MHz 51 51
8 MHz 1.7 1.7
4 MHz 1.6 1.6
2 MHz 1.5 1.5
1 MHz 1.1 1.1
500 kHz 1.1 1.1
Electrical characteristics STM32F050xx
48/97 Doc ID 023683 Rev 1
Table 26. Typical current consumption in Sleep mode, code running from Flash or
RAM
Symbol Parameter Conditions fHCLK
Typ
Unit
Peripherals
enabled
Peripherals
disabled
IDD
Supply current in
Sleep mode from VDD
supply
Running from
HSE crystal
clock 8 MHz,
code executing
from Flash or
RAM
48 MHz 10.7 2.4
mA
36 MHz 8.1 1.8
32 MHz 7.1 1.6
24 MHz 5.5 1.3
16 MHz 3.7 0.9
8 MHz 1.9 0.5
4 MHz 1.5 0.4
2 MHz 1.1 0.3
1 MHz 0.8 0.3
500 kHz 0.6 0.3
125 kHz 0.5 0.3
IDDA
Supply current in
Sleep mode from
VDDA supply
48 MHz 140 140
µA
36 MHz 109 109
32 MHz 96 96
24 MHz 76 76
16 MHz 51 51
8 MHz 1.7 1.7
4 MHz 1.6 1.6
2 MHz 1.5 1.5
1 MHz 1.1 1.1
500 kHz 1.1 1.1
125 kHz 1.1 1.1
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 49/97
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 45: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 28: Peripheral current consumption), the I/Os used by an application also contribute to
the current consumption. When an I/O pin switches, it uses the current from the MCU supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or
external) connected to the pin:
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
ISW VDD fSW C××=
Electrical characteristics STM32F050xx
50/97 Doc ID 023683 Rev 1
Table 27. Switching output I/O current consumption
Symbol Parameter Conditions(1)
1. CS = 7 pF (estimated value).
I/O toggling
frequency (fSW)Typ Unit
ISW
I/O current
consumption
VDD = 3.3 V
C =CINT
4 MHz 0.07
mA
8 MHz 0.15
16 MHz 0.31
24 MHz 0.53
48 MHz 0.92
VDD = 3.3 V
CEXT = 0 pF
C = CINT + CEXT+ CS
4 MHz 0.18
8 MHz 0.37
16 MHz 0.76
24 MHz 1.39
48 MHz 2.188
VDD = 3.3 V
CEXT = 10 pF
C = CINT + CEXT+ CS
4 MHz 0.32
8 MHz 0.64
16 MHz 1.25
24 MHz 2.23
48 MHz 4.442
VDD = 3.3 V
CEXT = 22 pF
C = CINT + CEXT+ CS
4 MHz 0.49
8 MHz 0.94
16 MHz 2.38
24 MHz 3.99
VDD = 3.3 V
CEXT = 33 pF
C = CINT + CEXT+ CS
4 MHz 0.64
8 MHz 1.25
16 MHz 3.24
24 MHz 5.02
VDD = 3.3 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
4 MHz 0.81
8 MHz 1.7
16 MHz 3.67
VDD = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
4 MHz 0.66
8 MHz 1.43
16 MHz 2.45
24 MHz 4.97
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 51/97
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Ta b l e 2 8 . The MCU is placed
under the following conditions:
●all I/O pins are in input mode with a static value at VDD or VSS (no load)
●all peripherals are disabled unless otherwise mentioned
●the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
●ambient operating temperature and VDD supply voltage conditions summarized in
Table 12: Voltage characteristics
Table 28. Peripheral current consumption
Peripheral
Typical consumption at 25 °C
Unit
IDD IDDA
ADC(1)
1. ADC is in ready state after setting the ADEN bit in the ADC_CR register (ADRDY bit in ADC_ISR is high).
0.53 0.964
mA
CRC 0.10 -
DBGMCU 0.18 -
DMA 0.35 -
GPIOA 0.48 -
GPIOB 0.58 -
GPIOC 0.12 -
GPIOF 0.06 -
I2C1 0.43 -
PWR 0.22 -
SPI1/I2S1 0.63 -
SYSCFG 0.28
TIM1 1.01 -
TIM2 1.00 -
TIM3 0.78 -
TIM6 0.32 -
TIM14 0.45 -
TIM16 0.57 -
TIM17 0.59 -
USART1 1.07 -
WWDG 0.22 -
Electrical characteristics STM32F050xx
52/97 Doc ID 023683 Rev 1
6.3.6 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 12: High-speed external clock
source AC timing diagram.
Figure 12. High-speed external clock source AC timing diagram
Table 29. High-speed external user clock characteristics
Symbol Parameter(1)
1. Guaranteed by design, not tested in production.
Conditions Min Typ Max Unit
fHSE_ext
User external clock source
frequency 1832MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD -V
DD V
VHSEL OSC_IN input pin low level voltage VSS -0.3V
DD
tw(HSEH)
tw(HSEL)
OSC_IN high or low time 15 - -
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time - - 20
-36
6(3%(
TF(3%
4(3%
T
TR(3%
6(3%,
T7(3%(
T7(3%,
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 53/97
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 13.
Figure 13. Low-speed external clock source AC timing diagram
Table 30. Low-speed external user clock characteristics
Symbol Parameter(1)
1. Guaranteed by design, not tested in production.
Conditions Min Typ Max Unit
fLSE_ext
User External clock source
frequency - 32.768 1000 kHz
VLSEH
OSC32_IN input pin high level
voltage 0.7VDD -V
DD
V
VLSEL
OSC32_IN input pin low level
voltage VSS -0.3V
DD
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time 450 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time - - 50
-36
6,3%(
TF,3%
4,3%
T
TR,3%
6,3%,
T7,3%(
T7,3%,
Electrical characteristics STM32F050xx
54/97 Doc ID 023683 Rev 1
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Ta b l e 3 1 . In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 14). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Table 31. HSE oscillator characteristics
Symbol Parameter Conditions(1)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
Min(2) Typ Max(2)
2. Guaranteed by design, not tested in production.
Unit
fOSC_IN Oscillator frequency 4 8 32 MHz
RFFeedback resistor - 200 - kΩ
IDD HSE current consumption
During startup(3)
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
-8.5
mA
VDD=3.3 V, Rm= 30Ω,
CL=10 pF@8 MHz -0.4-
VDD=3.3 V, Rm= 45Ω,
CL=10 pF@8 MHz -0.5-
VDD=3.3 V, Rm= 30Ω,
CL=5 pF@32 MHz -0.8-
VDD=3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz -1-
VDD=3.3 V, Rm= 30Ω,
CL=20 pF@32 MHz -1.5-
gm Oscillator transconductance Startup 10 - - mA/V
tSU(HSE)(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time VDD is stabilized - 2 - ms
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 55/97
Figure 14. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Ta bl e 3 2 . In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
-36
/3#?/54
/3#?). F(3%
#,
2&
-(Z
RESONATOR
2%84
#,
2ESONATORWITH
INTEGRATEDCAPACITORS
"IAS
CONTROLLED
GAIN
Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
IDD LSE current consumption
LSEDRV[1:0]=00
lower driving capability -0.50.9
µA
LSEDRV[1:0]= 01
medium low driving capability --1
LSEDRV[1:0] = 10
medium high driving capability --1.3
LSEDRV[1:0]=11
higher driving capability --1.6
gm
Oscillator
transconductance
LSEDRV[1:0]=00
lower driving capability 5- -
µA/V
LSEDRV[1:0]= 01
medium low driving capability 8- -
LSEDRV[1:0] = 10
medium high driving capability 15 - -
LSEDRV[1:0]=11
higher driving capability 25 - -
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Electrical characteristics STM32F050xx
56/97 Doc ID 023683 Rev 1
Figure 15. Typical application with a 32.768 kHz crystal
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
-36
/3#?/5 4
/3#?). F,3%
#,
K(Z
RESONATOR
#,
2ESONATORWITH
INTEGRATEDCAPACITORS
$RIVE
PROGRAMMABLE
AMPLIFIER
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 57/97
6.3.7 Internal clock source characteristics
The parameters given in Ta b l e 3 3 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 15: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI) RC oscillator
Figure 16. HSI oscillator accuracy characterization results
Table 33. HSI oscillator characteristics(1)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - 8 MHz
TRIM HSI user trimming step - - 1(2)
2. Guaranteed by design, not tested in production.
%
DuCy(HSI) Duty cycle 45(2) -55
(2) %
ACCHSI
Accuracy of the HSI
oscillator (factory
calibrated)
TA = –40 to 105 °C –3.8(3)
3. Data based on characterization results, not tested in production.
-4.6
(3) %
TA = –10 to 85 °C –2.9(3) -2.9
(3) %
TA = 0 to 70 °C –2.3(3) -2.2
(3) %
TA = 25 °C –1 - 1 %
tsu(HSI)
HSI oscillator startup
time 1(2) -2
(2) µs
IDDA(HSI)
HSI oscillator power
consumption - 80 100(2) µA
-36
-!8
-).
4!;#=
Electrical characteristics STM32F050xx
58/97 Doc ID 023683 Rev 1
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
Figure 17. HSI14 oscillator accuracy characterization results
Table 34. HSI14 oscillator characteristics(1)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI14 Frequency - 14 MHz
TRIM HSI14 user-trimming step - - 1(2)
2. Guaranteed by design, not tested in production.
%
DuCy(HSI14) Duty cycle 45(2) -55
(2) %
ACCHSI14
Accuracy of the HSI14
oscillator (factory calibrated)
TA = –40 to 105 °C –4.2(3)
3. Data based on characterization results, not tested in production.
-5.1
(3) %
TA = –10 to 85 °C –3.2(3) -3.1
(3) %
TA = 0 to 70 °C –2.5(3) -2.3
(3) %
TA = 25 °C –1 - 1 %
tsu(HSI14) HSI14 oscillator startup time 1(2) -2
(2) µs
IDDA(HSI14)
HSI14 oscillator power
consumption -100150
(2) µA
-36
-!8
-).
4!;#=
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 59/97
Low-speed internal (LSI) RC oscillator
Wakeup time from low-power mode
The wakeup times given in Ta ble 3 6 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The event used to wake up the device depends from the current operating mode:
●Stop or sleep mode: the wakeup event is WFE.
●The wakeup pin used in sleep, stop and standby modes is PA0.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 15: General operating conditions.
Table 35. LSI oscillator characteristics(1)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
fLSI Frequency 30 40 50 kHz
tsu(LSI)(2)
2. Guaranteed by design, not tested in production.
LSI oscillator startup time - - 85 µs
IDDA(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA
Table 36. Low-power mode wakeup timings
Symbol Parameter Conditions
Typ @VDD
Max Unit
= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V
tWUSTOP
Wakeup from Stop
mode
Regulator in run
mode 4.24.24.24.24.25
µs
Regulator in low
power mode 8.05 7.05 6.6 6.27 6.05 9
tWUSTANDBY Wakeup from
Standby mode 60.35 55.6 53.5 52.02 50.96
tWUSLEEP
Wakeup from Sleep
mode 1.11.11.11.11.1
Electrical characteristics STM32F050xx
60/97 Doc ID 023683 Rev 1
6.3.8 PLL characteristics
The parameters given in Ta b l e 3 7 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 15: General operating
conditions.
Table 37. PLL characteristics
Symbol Parameter
Value
Unit
Min Typ Max
fPLL_IN
PLL input clock(1)
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
1(2) 8.0 24(2) MHz
PLL input clock duty cycle 40(2) -60
(2) %
fPLL_OUT PLL multiplier output clock 16(2) -48MHz
tLOCK PLL lock time - - 200(2)
2. Guaranteed by design, not tested in production.
µs
JitterPLL Cycle-to-cycle jitter - - 300(2) ps
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 61/97
6.3.9 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
6.3.10 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Ta b l e 4 0 . They are based on the EMS levels and classes
defined in application note AN1709.
Table 38. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max(1)
1. Guaranteed by design, not tested in production.
Unit
tprog 16-bit programming time TA = –40 to +105 °C 40 53.5 60 µs
tERASE Page (1 KB) erase time TA = –40 to +105 °C 20 - 40 ms
tME Mass erase time TA = –40 to +105 °C 20 - 40 ms
IDD Supply current Write mode - - 10 mA
Erase mode - - 12 mA
Table 39. Flash memory endurance and data retention
Symbol Parameter Conditions
Value
Unit
Min(1)
1. Data based on characterization results, not tested in production.
NEND Endurance TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions) 10 kcycles
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Ye a r s1 kcycle(2) at TA = 105 °C 10
10 kcycles(2) at TA = 55 °C 20
Electrical characteristics STM32F050xx
62/97 Doc ID 023683 Rev 1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●Corrupted program counter
●Unexpected reset
●Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 40. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, LQFP64, TA = +25 °C,
fHCLK = 48 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP64, TA = +25 °C,
fHCLK = 48 MHz
conforms to IEC 61000-4-4
3B
Table 41. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz
SEMI Peak level
VDD = 3.6 V, TA = 25 °C,
LQFP64 package
compliant with IEC
61967-2
0.1 to 30 MHz -3
dBµV30 to 130 MHz 28
130 MHz to 1GHz 23
SAE EMI Level 4 -
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 63/97
6.3.11 Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●A supply overvoltage is applied to each power supply pin
●A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
6.3.12 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (more
than 5 LSB TUE), out of conventional limits of current injection on adjacent pins (more than
–5 µA) or other functional failure (reset occurrence or oscillator frequency deviation, for
example).
Table 42. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum value(1)
1. Data based on characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C, conforming
to JESD22-A114 22000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device model)
TA = +25 °C, conforming
to JESD22-C101 II 500
Table 43. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
Electrical characteristics STM32F050xx
64/97 Doc ID 023683 Rev 1
The characterization results are given in Ta b l e 4 4 .
Table 44. I/O current injection susceptibility
Symbol Description
Functional
susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on BOOT0 –0 NA
mA
Injected current on all FT and FTf pins with induced
leakage current on adjacent pins less than –5 µA –5 NA
Injected current on all TTa pins with induced leakage
current on adjacent pins less than –5 µA –5 +5
Injected current on all TC & RESET pins with induced
leakage current on adjacent pins less than –5 µA –5 +5
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 65/97
6.3.13 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Ta b l e 4 5 are derived from tests
performed under the conditions summarized in Table 15: General operating conditions. All
I/Os are CMOS and TTL compliant.
Table 45. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL
Low level input
voltage
TC and TTa I/O - - 0.3 VDD+0.07(1)
V
FT and FTf I/O - - 0.475 VDD–0.2(1)
BOOT0 - - 0.3 VDD–0.3(1)
All I/Os except BOOT0 pin - - 0.3 VDD
VIH
High level input
voltage
TC and TTa I/O 0.445 VDD+0.398(1) --
V
FT and FTf I/O 0.5 VDD+0.2(1) --
BOOT0 0.2 VDD+0.95(1) --
All I/Os except BOOT0 pin 0.7 VDD --
Vhys Schmitt trigger
hysteresis
TC and TTa I/O - 200(1) -
mVFT and FTf I/O - 100(1) -
BOOT0 - 300(1) -
Ilkg
Input leakage
current (2)
VSS ≤VIN ≤VDD
I/O TC, FT and FTf --±0 . 1
µA
VSS ≤VIN ≤VDD
2 V≤VDD ≤VDDA ≤3.6 V
I/O TTa used in digital
mode
--±0 . 1
VIN= 5 V
I/O FT and FTf --10
VIN= 3.6 V,
2 V≤VDD ≤VIN
VDDA = 3.6 V
I/O TTa used in digital
mode
--1
VSS ≤VIN ≤VDDA
2 V≤VDD ≤VDDA ≤3.6 V
I/O TTa used in analog
mode
--±0 . 2
RPU
Weak pull-up
equivalent
resistor(3)
VIN = VSS 25 40 55 kΩ
Electrical characteristics STM32F050xx
66/97 Doc ID 023683 Rev 1
RPD
Weak pull-down
equivalent
resistor(3)
VIN = VDD 25 40 55 kΩ
CIO
I/O pin
capacitance -5-pF
1. Data based on design simulation only. Not tested in production.
2. Leakage could be higher than maximum value, if negative current is injected on adjacent pins.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
Table 45. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 67/97
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os, and
in Figure 20 and Figure 21 for 5 V tolerant I/Os. The following curves are design simulation
results, not tested in production.
Figure 18. TC and TTa I/O input characteristics - CMOS port
Figure 19. TC and TTa I/O input characteristics - TTL port
MS30255V1
VDD (V)
VIHmin 2.0
VILmax 0.7
VIL/VIH (V)
1.3
2.0 3.6
CMOS standard requirements V
IHmin
= 0.7V
DD
V
ILmax
= 0.3V
DD
+0.07
0.6
2.7 3.0 3.3
CMOS standard requirements VILmax = 0.3VDD
V
IHmin
= 0.445V
DD
+0.398
Input range not
guaranteed
MS30256V1
VDD (V)
VIHmin 2.0
VILmax 0.8
VIL/VIH (V)
1.3
2.0 3.6
TTL standard requirements VIHmin = 2 V
V
ILmax
= 0.3V
DD
+0.07
0.7
2.7 3.0 3.3
TTL standard requirements VILmax = 0.8 V
V
IHmin
= 0.445V
DD
+0.398
Input range not
guaranteed
Electrical characteristics STM32F050xx
68/97 Doc ID 023683 Rev 1
Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port
MS30257V1
VDD (V)
2.0
VIL/VIH (V)
1.0
2.0 3.6
CMOS standard requirements VIH min= 0.7VDD
V
ILmax
= 0.475V
DD
-0.2
0.5
CMOS standard requirements VILmax = 0.3VDD
V
IHmin
= 0.5V
DD
+0.2
Input range not
guaranteed
MS30258V1
VDD (V)
2.0
VIL/VIH (V)
1.0
2.0 3.6
V
ILmin
= 0.475V
DD
-0.2
0.5
V
IHmin
= 0.5V
DD
+0.2
Input range not
guaranteed
2.7
TTL standard requirements VIHmin = 2 V
TTL standard requirements VILmax = 0.8 V
0.8
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 69/97
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
●The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 13: Current characteristics).
●The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 13: Current characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in Ta b l e 4 6 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15: General operating conditions. All I/Os are CMOS and TTL compliant (FT, TTa or
TC unless otherwise specified).
Table 46. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 13:
Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output low level voltage for an I/O pin CMOS port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
-0.4
V
VOH(3)
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 13: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output high level voltage for an I/O pin VDD–0.4 -
VOL (1) Output low level voltage for an I/O pin TTL port(2)
IIO =+ 8mA
2.7 V < VDD < 3.6 V
-0.4
V
VOH (3) Output high level voltage for an I/O pin 2.4 -
VOL(1)(4)
4. Data based on design simulation only. Not tested in production.
Output low level voltage for an I/O pin IIO = +20 mA
2.7 V < VDD < 3.6 V
-1.3
V
VOH(3)(4) Output high level voltage for an I/O pin VDD–1.3 -
VOL(1)(4) Output low level voltage for an I/O pin IIO = +6 mA
2 V < VDD < 2.7 V
-0.4
V
VOH(3)(4) Output high level voltage for an I/O pin VDD–0.4 -
VOLFM+(1) Output low level voltage for an FTf I/O
pin in FM+ mode
IIO = +20 mA
2.7 V < VDD < 3.6 V -0.4V
Electrical characteristics STM32F050xx
70/97 Doc ID 023683 Rev 1
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and
Ta bl e 4 7 , respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 15: General
operating conditions.
Table 47. I/O AC characteristics(1)
OSPEEDRy
[1:0] value(1) Symbol Parameter Conditions Min Max Unit
x0
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 2 MHz
tf(IO)out
Output high to low level
fall time CL = 50 pF, VDD = 2 V to 3.6 V
-125
(3)
ns
tr(IO)out
Output low to high level
rise time -125
(3)
01
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 10 MHz
tf(IO)out
Output high to low level
fall time CL = 50 pF, VDD = 2 V to 3.6 V
-25
(3)
ns
tr(IO)out
Output low to high level
rise time -25
(3)
11
fmax(IO)out Maximum frequency(2)
CL = 30 pF, VDD = 2.7 V to 3.6 V - 50
MHzCL = 50 pF, VDD = 2.7 V to 3.6 V - 30
CL = 50 pF, VDD = 2 V to 2.7 V - 20
tf(IO)out
Output high to low level
fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
ns
CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V - 12(3)
tr(IO)out
Output low to high level
rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V - 12(3)
FM+
configuration
(4)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 2(3) MHz
tf(IO)out
Output high to low level
fall time CL = 50 pF, VDD = 2 V to 3.6 V - 12(3)
ns
tr(IO)out
Output low to high level
rise time CL = 50 pF, VDD = 2 V to 3.6 V - 34(3)
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
10 - ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 22.
3. Guaranteed by design, not tested in production.
4. When FM+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F05xxx reference manual RM0091
for a detailed description of FM+ I/O configuration.
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 71/97
Figure 22. I/O AC characteristics definition
6.3.14 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 45: I/O static characteristics).
Unless otherwise specified, the parameters given in Ta b l e 4 8 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15: General operating conditions.
Figure 23. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 48. Otherwise the reset will not be taken into account by the device.
ai14131
10%
90%
50%
tr(IO)out
OUTPUT
EXT ERNAL
ON 50pF
Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)
10 %
50%
90%
when loaded by 50pF
T
tr(IO)out
Table 48. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1)
1. Guaranteed by design, not tested in production.
NRST input low level voltage –0.3 - 0.8 V
VIH(NRST)(1) NRST input high level voltage 2 - VDD+0.3
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis - 200 - mV
RPU Weak pull-up equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
VIN = VSS 25 40 55 kΩ
VF(NRST)(1) NRST input filtered pulse - - 100 ns
VNF(NRST)(1) NRST input not filtered pulse 300 - - ns
-36
205
.234
6$$
&ILTER
)NTERNAL2ESET
&
%XTERNAL
RESETCIRCUIT
Electrical characteristics STM32F050xx
72/97 Doc ID 023683 Rev 1
6.3.15 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Ta bl e 4 9 are preliminary values derived
from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 15: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 49. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply voltage for
ADC ON 2.4 - 3.6 V
fADC ADC clock frequency 0.6 - 14 MHz
fS(1) Sampling rate 0.05 - 1 MHz
fTRIG(1) External trigger frequency fADC = 14 MHz - - 823 kHz
--171/f
ADC
VAIN Conversion voltage range 0 - VDDA V
RAIN(1) External input impedance See Equation 1 and
Ta bl e 5 0 for details --50kΩ
RADC(1) Sampling switch resistance - - 1 kΩ
CADC(1) Internal sample and hold
capacitor --8pF
tCAL(1) Calibration time fADC = 14 MHz 5.9 µs
83 1/fADC
tlatr(1) Trigger conversion latency
fADC = fPCLK/2 = 14 MHz 0.196 µs
fADC = fPCLK/2 5.5 1/fPCLK
fADC = fPCLK/4 = 12 MHz 0.219 µs
fADC = fPCLK/4 10.5 1/fPCLK
fADC = fHSI14 = 14 MHz 0.188 - 0.259 µs
JitterADC ADC jitter on trigger
conversion fADC = fHSI14 -1-1/f
HSI14
tS(1) Sampling time fADC = 14 MHz 0.107 - 17.1 µs
1.5 - 239.5 1/fADC
tSTAB(1) Power-up time 0 0 1 µs
tCONV(1) Total conversion time
(including sampling time)
fADC = 14 MHz 1 18 µs
14 to 252 (tS for sampling +12.5 for
successive approximation) 1/fADC
1. Guaranteed by design, not tested in production.
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 73/97
Equation 1: RAIN max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 50. RAIN max for fADC = 14 MHz(1)
1. Guaranteed by design, not tested in production.
Ts (cycles) tS (µs) RAIN max (kΩ)
1.5 0.11 0.4
7.5 0.54 5.9
13.5 0.96 11.4
28.5 2.04 25.2
41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
Table 51. ADC accuracy(1)(2) (3)
1. ADC DC accuracy values are measured after internal calibration.
Symbol Parameter Test conditions Typ Max(4) Unit
ET Total unadjusted error
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
±1.3 ±2
LSB
EO Offset error ±1 ±1.5
EG Gain error ±0.5 ±1.5
ED Differential linearity error ±0.7 ±1
EL Integral linearity error ±0.8 ±1.5
ET Total unadjusted error
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.7 V to 3.6 V
TA = −40 to 105 °C
±3.3 ±4
LSB
EO Offset error ±1.9 ±2.8
EG Gain error ±2.8 ±3
ED Differential linearity error ±0.7 ±1.3
EL Integral linearity error ±1.2 ±1.7
ET Total unadjusted error
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
TA = 25 °C
±3.3 ±4
LSB
EO Offset error ±1.9 ±2.8
EG Gain error ±2.8 ±3
ED Differential linearity error ±0.7 ±1.3
EL Integral linearity error ±1.2 ±1.7
RAIN
TS
fADC CADC 2N2+
()ln××
----------------------------------------------------------------RADC
–<
Electrical characteristics STM32F050xx
74/97 Doc ID 023683 Rev 1
Figure 24. ADC accuracy characteristics
Figure 25. Typical connection diagram using the ADC
1. Refer to Table 49: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not
affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
EO
EG
1LSB
IDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1234567 4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
-36
1LSB
IDEAL
VDDA
-36
6$$!
AINx
IL±1 μA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC 12-bit
converter
CADC
Sample and hold ADC
converter
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 75/97
6.3.16 Temperature sensor characteristics
6.3.17 VBAT monitoring characteristics
6.3.18 Timer characteristics
The parameters given in Ta b l e 5 4 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 52. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Guaranteed by design, not tested in production.
VSENSE linearity with temperature - ±1±2°C
Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C
V25 Voltage at 25 °C 1.34 1.43 1.52 V
tSTART(1) Startup time 4 - 10 µs
TS_temp(1)(2)
2. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the
temperature 17.1 - - µs
Table 53. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -50-KΩ
QRatio on VBAT measurement - 2 -
Er(1)
1. Guaranteed by design, not tested in production.
Error on Q –1 - +1 %
TS_vbat(1)(2)
2. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the VBAT
1mV accuracy 5--µs
Table 54. TIMx(1) characteristics
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time 1-
tTIMxCLK
fTIMxCLK = 48 MHz 20.8 - ns
fEXT Timer external clock
frequency on CH1 to CH4
0
fTIMxCLK/2 MHz
fTIMxCLK = 48 MHz 0 24 MHz
ResTIM Timer resolution TIMx (except TIM2) - 16 bit
TIM2 - 32
Electrical characteristics STM32F050xx
76/97 Doc ID 023683 Rev 1
tCOUNTER 16-bit counter clock period 1 65536 tTIMxCLK
fTIMxCLK = 48 MHz 0.0208 1365 µs
tMAX_COUNT Maximum possible count
with 32-bit counter
- 65536 × 65536 tTIMxCLK
fTIMxCLK = 48 MHz - 89.48 s
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17
timers.
Table 55. IWDG min/max timeout period at 40 kHz (LSI) (1)
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from
30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the
phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of
uncertainty.
Prescaler divider PR[2:0] bits Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF Unit
/4 0 0.1 409.6
ms
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
Table 56. WWDG min-max timeout value @48 MHz (PCLK)
Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0853 5.4613
ms
2 1 0.1706 10.9226
4 2 0.3413 21.8453
8 3 0.6826 43.6906
Table 54. TIMx(1) characteristics (continued)
Symbol Parameter Conditions Min Max Unit
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 77/97
6.3.19 Communication interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Ta b l e 5 7 are derived from tests
performed under ambient temperature, fPCLK frequency and VDD supply voltage conditions
summarized in Table 15: General operating conditions.
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Ta b l e 5 7 . Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 57. I2C characteristics(1)
Symbol Parameter
Standard mode Fast mode Fast Mode Plus
Unit
Min Max Min Max Min Max
tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.5 - µs
tw(SCLH) SCL clock high time 4.0 - 0.6 - 0.26 -
tsu(SDA) SDA setup time 250 - 100 - 50 -
ns
th(SDA) SDA data hold time 0(3) 3450(2) 0(3) 900(2) 0(4) 450(2)
tr(SDA)
tr(SCL)
SDA and SCL rise time - 1000 - 300 - 120
tf(SDA)
tf(SCL)
SDA and SCL fall time - 300 - 300 - 120
th(STA) Start condition hold time 4.0 - 0.6 - 0.26 -
µs
tsu(STA)
Repeated Start condition
setup time 4.7 - 0.6 - 0.26 -
tsu(STO) Stop condition setup time 4.0 - 0.6 - 0.26 - μs
tw(STO:STA)
Stop to Start condition time
(bus free) 4.7 - 1.3 - 0.5 - μs
Cb
Capacitive load for each bus
line - 400 - 400 - 550 pF
1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in
production.
2. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
4. The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
Electrical characteristics STM32F050xx
78/97 Doc ID 023683 Rev 1
Figure 26. I2C bus AC waveforms and measurement circuit
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Ta b l e 5 9 for SPI or in Ta b l e 6 0 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 15: General operating conditions.
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 58. I2C analog filter characteristics(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Min Max Unit
tSP
Pulse width of spikes that are
suppressed by the analog filter 50 260 ns
-36
34!24
3$ !
Ω
)
#BUS
2
Ω
6$$
6$$
-#5
3$!
3#,
TF3$! TR3$!
3#,
TH34!
TW3#,(
TW3#,,
TSU3$!
TR3#, TF3#,
TH3$!
3 4!242%0%!4%$
34!24
TSU34!
TSU34/
34/0 TW34/34!
2
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 79/97
Table 59. SPI characteristics
Symbol Parameter Conditions Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency Master mode - 18 MHz
Slave mode - 18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time Capacitive load: C = 15 pF - 6 ns
tsu(NSS)(1) NSS setup time Slave mode 4Tpclk -
ns
th(NSS)(1) NSS hold time Slave mode 2Tpclk + 10 -
tw(SCKH)(1)
tw(SCKL)(1) SCK high and low time Master mode, fPCLK = 36 MHz,
presc = 4 Tpclk/2 -2 Tpclk/2 + 1
tsu(MI) (1)
tsu(SI)(1) Data input setup time Master mode 4 -
Slave mode 5 -
th(MI) (1)
Data input hold time Master mode 4 -
th(SI)(1) Slave mode 5 -
ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk
tdis(SO)(1)(3) Data output disable time Slave mode 0 18
tv(SO) (1) Data output valid time Slave mode (after enable edge) - 22.5
tv(MO)(1) Data output valid time Master mode (after enable edge) - 6
th(SO)(1)
Data output hold time Slave mode (after enable edge) 11.5 -
th(MO)(1) Master mode (after enable edge) 2 -
DuCy(SCK) SPI slave input clock duty
cycle Slave mode 25 75 %
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
Electrical characteristics STM32F050xx
80/97 Doc ID 023683 Rev 1
Figure 27. SPI timing diagram - slave mode and CPHA = 0
Figure 28. SPI timing diagram - slave mode and CPHA = 1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
ai14134c
SCK Input
CPHA= 0
MOSI
INPUT
MISO
OUT P UT
CPHA= 0
MS B O U T
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS)
tc(SCK)
th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI)
th(SI)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT P UT
CPHA=1
MS B O U T
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI) th(SI)
NSS input
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 81/97
Figure 29. SPI timing diagram - master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
ai14136
SCK Output
CPHA= 0
MOSI
OUTUT
MISO
INP UT
CPHA= 0
MS BIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B IT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
Electrical characteristics STM32F050xx
82/97 Doc ID 023683 Rev 1
Table 60. I2S characteristics
Symbol Parameter Conditions Min Max Unit
fCK
1/tc(CK)
I2S clock frequency
Master mode (data: 16 bits, Audio
frequency = 48 kHz) 1.597 1.601 MHz
Slave mode 0 6.5
tr(CK) I2S clock rise time Capacitive load CL=15pF -10
ns
tf(CK) I2S clock fall time - 12
tw(CKH) (1) I2S clock high time Master fPCLK= 16 MHz, audio
frequency = 48 kHz
306 -
tw(CKL) (1) I2S clock low time 312 -
tv(WS) (1) WS valid time Master mode 2 -
th(WS) (1) WS hold time Master mode 2 -
tsu(WS) (1) WS setup time Slave mode 7 -
th(WS) (1) WS hold time Slave mode 0 -
DuCy(SCK) I2S slave input clock duty
cycle Slave mode 25 75 %
tsu(SD_MR) (1) Data input setup time Master receiver 6 -
ns
tsu(SD_SR) (1) Data input setup time Slave receiver 2 -
th(SD_MR)(1)(2)
Data input hold time Master receiver 4 -
th(SD_SR) (1)(2) Slave receiver 0.5 -
tv(SD_ST) (1)(2) Data output valid time Slave transmitter (after enable
edge) -20
th(SD_ST) (1) Data output hold time Slave transmitter (after enable
edge) 13 -
tv(SD_MT) (1)(2) Data output valid time Master transmitter (after enable
edge) - 4
th(SD_MT) (1) Data output hold time Master transmitter (after enable
edge) 0-
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
STM32F050xx Electrical characteristics
Doc ID 023683 Rev 1 83/97
Figure 30. I2S slave timing diagram (Philips protocol)
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 31. I2S master timing diagram (Philips protocol)
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
CK Input
CPOL = 0
CPOL = 1
tc(CK)
WS input
SDtransmit
SDreceive
tw(CKH) tw(CKL)
tsu(WS)tv(SD_ST) th(SD_ST)
th(WS)
tsu(SD_SR) th(SD_SR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14881b
LSB receive(2)
LSB transmit(2)
CK output
CPOL = 0
CPOL = 1
tc(CK)
WS output
SDreceive
SDtransmit
tw(CKH)
tw(CKL)
tsu(SD_MR)
tv(SD_MT) th(SD_MT)
th(WS)
th(SD_MR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14884b
tf(CK) tr(CK)
tv(WS)
LSB receive
(2)
LSB transmit
(2)
Package characteristics STM32F050xx
84/97 Doc ID 023683 Rev 1
7 Package characteristics
7.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
STM32F050xx Package characteristics
Doc ID 023683 Rev 1 85/97
Figure 32. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline
1. Drawing is not to scale.
5B_ME
L
A1 K
L1
c
A
A2
ccc C
D
D1
D3
E3 E1 E
24
25
36
37
b
48
1
Pin 1
identification 12
13
Table 61. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.500 0.2165
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.500 0.2165
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0°3.5°7° 0°3.5°7°
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F050xx
86/97 Doc ID 023683 Rev 1
Figure 33. LQFP48 recommended footprint
1. Drawing is not to scale.
2. Dimensions are in millimeters.
9.70 5.80 7.30
12
24
0.20
7.30
1
37
36
1.20
5.80
9.70
0.30
25
1.20
0.50
ai14911b
1348
STM32F050xx Package characteristics
Doc ID 023683 Rev 1 87/97
Figure 34. UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must
be connected. It is referred to as pin 0 in Table 8: Pin definitions.
Seating plane
ddd C
C
A3
A1
A
D
e
916
17
24
32
Pin # 1 ID
R = 0.30
8
E
L
L
D2
1
b
E2
A0B8_ME
Bottom view
Table 62. UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data
Dim.
millimeters inches(1)
Min Typ Max Min Typ Max
A 0.5 0.55 0.6 0.0197 0.0217 0.0236
A1 0.00 0.02 0.05 0 0.0008 0.0020
A3 0.152 0.006
b 0.18 0.23 0.28 0.0071 0.0091 0.0110
D 4.90 5.00 5.10 0.1929 0.1969 0.2008
D2 3.50 0.1378
E 4.90 5.00 5.10 0.1929 0.1969 0.2008
E2 3.40 3.50 3.60 0.1339 0.1378 0.1417
e 0.500 0.0197
L 0.30 0.40 0.50 0.0118 0.0157 0.0197
ddd 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F050xx
88/97 Doc ID 023683 Rev 1
Figure 35. UFQFPN32 recommended footprint
1. Drawing is not to scale.
2. Dimensions are in millimeters.
STM32F050xx Package characteristics
Doc ID 023683 Rev 1 89/97
Figure 36. UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline
1. Drawing is not to scale.
2. Dimensions are in millimeters.
3. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
X
4E
B
3EATING
0LANE
! !
#OX
0INCORNER
,
,
2O4YP
$ETAIL:
$
$
%
%
0IN)$
3EATING
0LANE
"
!
$ETAIL:
!"?-%?6
Table 63. UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 0.5 0.55 0.6 0.0197 0.0217 0.0236
A1 -0.05 0 0.05 -0.002 0 0.002
D 3.9 4 4.1 0.1535 0.1575 0.1614
D1 2.9 3 3.1 0.1142 0.1181 0.122
E 3.9 4 4.1 0.1535 0.1575 0.1614
E1 2.9 3 3.1 0.1142 0.1181 0.122
L 0.3 0.4 0.5 0.0118 0.0157 0.0197
L1 0.25 0.35 0.45 0.0098 0.0138 0.0177
T 0.152 0.006
b 0.2 0.25 0.3 0.0079 0.0098 0.0118
e 0.5 0.0197
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F050xx
90/97 Doc ID 023683 Rev 1
Figure 37. UFQFPN28 recommended footprint
1. Dimensions are in millimeters
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
!"?-%?&0
STM32F050xx Package characteristics
Doc ID 023683 Rev 1 91/97
Figure 38. TSSOP20 - 20-pin thin shrink small outline
1. Drawing is not to scale.
9!?-%
#0
C
,
%%
$
!
!
K
EB
!
,
AAA
Table 64. TSSOP20 – 20-pin thin shrink small outline package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ
A 1.2 0.0472
A1 0.05 0.15 0.002 0.0059
A2 0.8 1 1.05 0.0315 0.0394 0.0413
b 0.19 0.3 0.0075 0.0118
c 0.09 0.2 0.0035 0.0079
D 6.4 6.5 6.6 0.252 0.2559 0.2598
E 6.2 6.4 6.6 0.2441 0.252 0.2598
E1 4.3 4.4 4.5 0.1693 0.1732 0.1772
e 0.65 0.0256
L 0.45 0.6 0.75 0.0177 0.0236 0.0295
L1 1 0.0394
k 0.0° 8.0° 0.0° 8.0°
aaa 0.1 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F050xx
92/97 Doc ID 023683 Rev 1
Figure 39. TSSOP20 recommended footprint
1. Dimensions are in millimeters
STM32F050xx Package characteristics
Doc ID 023683 Rev 1 93/97
7.2 Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 15: General operating conditions on page 39.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x Θ
JA)
Where:
●TA max is the maximum ambient temperature in °C,
●Θ
JA is the package junction-to-ambient thermal resistance, in °C/W,
●PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
●PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
7.2.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
7.2.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F05xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Table 65. Package thermal characteristics
Symbol Parameter Value Unit
Θ
JA
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm 55
°C/W
Thermal resistance junction-ambient
UFQFPN32 - 5 × 5 mm 38
Thermal resistance junction-ambient
UFQFPN28 - 4 × 4 mm 118
Thermal resistance junction-ambient
TSSOP20 110
Package characteristics STM32F050xx
94/97 Doc ID 023683 Rev 1
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 80 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Ta bl e 6 5 TJmax is calculated as follows:
– For LQFP48, 55 °C/W
TJmax = 80 °C + (55°C/W × 447 mW) = 80 °C + 24.585 °C = 104.585 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Ta bl e 1 5:
General operating conditions on page 39.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (55°C/W × 447 mW) = 105-24.585 = 80.415 °C
Suffix 7: TAmax = TJmax - (55°C/W × 447 mW) = 125-24.585 = 100.415 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Ta bl e 6 5 TJmax is calculated as follows:
– For LQFP48, 55 °C/W
TJmax = 100 °C + (55 °C/W × 134 mW) = 100 °C + 7.37 °C = 107.37 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation in order to be able to
use suffix 6 parts.
STM32F050xx Part numbering
Doc ID 023683 Rev 1 95/97
8 Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Example:STM32F050C6T6Ax
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
050 = STM32F050xx
Pin count
F = 20 pins
G = 28 pins
K = 32 pins
C = 48 pins
Code size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
Package
P = TSSOP
U = UFQFPN
T = LQFP
Temperature range
6 = –40 °C to +85 °C
7 = –40 °C to +105 °C
Internal code
A = non-optimized die
Blank = standard die
Options
xxx = programmed parts
TR = tape and real
STM32F050xx
Doc ID 023683 Rev 1 97/97
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2012 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
