1:8 Clock Fano ut Buffer
ComLink™ Series
CY2DP818
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-070 61 Rev. *A Revised July 9, 2002
Features
•Low-voltage operation VDD = 3.3V
•1:8 fanout
•Single-input-con figurable for LVDS, LVPECL , or LVTTL
•8 pair of LVPECL outputs
•Drives a 50-ohm load
•Low input capacitance
•Low output skew
•Low propagation delay Typical (tpd < 4 ns)
•Industrial versions availa ble
•Package availa ble inclu de: TSSO P
•Does not exceed Bellcore 802.3 standards
•Operation at ⇒ 350 MHz–700 Mbps
Description
This Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The C ypress CY2 DP818 fan out buf fe r fea tures a si ngle LVDS
or a single-ended LVTTL-compatible input and eight LVPECL
output pairs.
Designed for data-communications clock-management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVPECL-based clock s ignals.
The Cypress CY2DP818 has configurable input functions. The
input is us er co nfi gura ble via the Inc onf ig pin for sin gle end ed
or differential input.
Block Diagram Pin Configuration
INPUT
(LVPECL / LVDS / LVTTL)
OUTPUT
(LVPECL)
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
INPUT A
INPUT B
InConfig
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
38-pin TSSOP
GND
VDD
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
Q4A
GND
VDD
GND
GND
VDD
InConfig
INPUT A
INPUT B
GND
GND
CY2DP818
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ComLink™ Series
CY2DP818
Document #: 38-07061 Rev. *A Page 2 of 8
Maximum Ratings[1]
Storage Temperature: ................................–65°C to + 150°C
Ambient Temperature:...................................–40°C to +85°C
Supply Voltage to Ground Potential
(Inputs and VCC only) .......................................–0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only)........................................–0.3V to VDD + 0.3V
DC Input Voltage ...................................–0.3V to VDD + 0.3V
DC Output Voltage.................................–0.3V to VDD + 0.9V
Power Dissipation........................................................0.75W
Notes:
1. S tresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Pin Description
Pin Number Pin Name Pin Standard Interface Description
1, 9,12,18,19 ,20,38 GND POWER Ground
2,3,4,5,6,8, 13, 14,15,16,17,29 VDD POWE R Pow er Supply
10,11 Input A, Input B Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
Differential input pair or single line.
LVPECL/LVDS default. See InConfig,
below.
37, 36,35,34,
33,32, 31, 30,
28,27,26,25,
24,23,22,21
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
LVPECL Differential Outputs
7 InConfig LVTTL/LVCMOS Converts inpu ts from the default
LVPECL/LVDS (logic = 0)
To LVTTL/LVCMOS (logic = 1)
See Figure 4 and Figure 5 for additional
Information
Table 1. Power Supply Characteristics
Parameter Description Test Conditions Min. Typ. Max. Unit
ICCD Dynamic Power Supply Current VDD = Ma x.
Input toggling 50% Duty Cycle,
Output s Op en
1.5 2.0 mA/MHz
IC Total Power Supply Current VDD = Max.
Input toggling 50% Duty Cycle,
Outpu t s 50 ohm s
fL=100 MHz
350 mA
IC Core Core current when output loads are
disabled VDD = Max.
Input t oggling 5 0% Duty C ycle, Out put s
Disabled, not connected to VTT
fL=100 MHz
50 mA
Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS
INCONFIG
Pin 7
Binary Value Input Receiver Family Input Receiver Type
1 LVTTL in LVCMOS Single-ended, non-inverting, inverting, void of bias resistors
0 LVDS Low-voltage differential signaling
LVPECL Low-voltage pseudo (positive) emitter coupled logic
ComLink™ Series
CY2DP818
Document #: 38-07061 Rev. *A Page 3 of 8
Table 3. Function Control of the TTL Input Logic used to Accept or Invert the Input Signal
LVTTL/LVCMOS Input Logic
Input Condition Input Logic Output Logic Q Pins, Q1A or Q1
Ground Input B (–) Pin 11
Input A (+) Pin 10 Input True
VCC Input B (–) Pin 11
Input A (+) Pin 10 Input Invert
Ground Input A (+) Pin 10
Input B (–) Pin 11 Input Invert
VCC Input A (+) Pin 10
Input B (–) Pin 11 Input True
Table 4. DC Electrical C harac ter ist ics: 3.3V–LVDS Input
Parameter Description Conditions Min. Typ. Max. Unit
VID Magnitude of Differential Input Voltage 100 600 mV
VIC Common-mode of Differential Input
VoltageIVIDI (min. and max.) IVIDI/2 2.4–(IVIDI/2) V
VIH Input High Voltage Guaranteed Logic High Level 2 V
VIL Input Low Voltage Guaranteed Logic Low Level 0.8 V
IIH Input High Current VDD = Max. VIN = VDD ±10 ±20 µA
IIL Input Low Current VDD = Max. VIN = VSS ±10 ±20 µA
IIInput High Current VDD = Max., VIN = VDD(Max.) ±20 µA
Table 5. DC Electrical C harac ter ist ics: 3.3V–LVPECL Input
Parameter Description Conditions Min. Typ. Max. Unit
VID Differential Input Voltage p-p Guaranteed Logic High Level 400 2600 mV
VIH Input High Voltage Guaranteed Logic High Level 2.15 2.4 V
VIL Input Lo w Voltage Guaranteed Logic Low Level 1.5 1.8 V
IIH Input High Current VDD = Max. VIN = VDD ±10 ±20 µA
IIL Input Low Current VDD = Max. VIN = VSS ±10 ±20 µA
IIInput High Current VDD = Max., VIN = VDD(Max.) ±20 µA
VCM Common-mode Voltage 225 mV
Table 6. DC Electrical C harac ter ist ics: 3.3V–LVTTL/LVCMOS Input
Parameter Description Conditions Min. Typ. Max. Units
VIH Input High Voltage Guaranteed Logic High Level 2 V
VIL Input Lo w Voltage Gua rant eed Logic Low Level 0.8 V
IIH Input High Current VDD = Max VIN = 2.7V 1 µA
IIL Input Low Current VDD = Max VIN = 0.5V –1µA
IIInput High Current VDD = Max., VIN = VDD(Max) 20 µA
VIK Clamp Diod e Volt a ge VDD = Min., IIN = –18mA –0.7 –1.2 V
VHInput Hysteresis 80 mV
ComLink™ Series
CY2DP818
Document #: 38-07061 Rev. *A Page 4 of 8
Table 7. DC Electrical C harac ter ist ics: 3.3V–LVPECL Output
Parameter Description Conditions Min. Typ. Max. Unit
VOD Driver Differential Output
volt a ge p-p VDD = Min., VIN = VIH or VIL RL = 50 ohm 1000 3600 mV
VOC Driver common-mode p-p VDD = Min., VIN = VIH or VIL RL = 50 ohm 300 mV
Rise Time Diffe rential 20% to 80% CL–10 pF RL and CL to GND RL = 50 ohm 300 1200 ps
Fall Time
VOH Output High Voltage VDD = Min., VIN = VIH or VIL IOH = –12 mA 2.1 3.0 V
VOL Output Low Voltage VDD = Min., VIN = VIH or VIL
User defined by VTT RTT. 0.8 1.3 V
IOS Short Circuit Current VDD = Max, VOUT = GND –125 –150 mA
Table 8. AC Switching Characteristics @ 3.3 V (VDD = 3.3V ±5%, Temperature = –40°C to +85°C)
Parameter Description Conditions Min. Typ. Max. Unit
tPLH Propagation Delay – Low to High VOD = 100 mV 3 4 5 ns
tPHL Propagation Delay – High to Low 3 4 5 ns
TPE Enab le (EN) to functio na l opera tio n 6 ns
TPD Functional operation to Disable 5 ns
tSK(0) Output Ske w: Skew b etwee n outp uts of the same pa ckage (in ph ase) 0.2 ns
tSK(p) Pulse Skew: Skew between opposite transitions of the same output
(tPHL–tPLH)0.2 ns
tSK(t) Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type. Same
input signal level and output load.
VID = 100 mV 1 ns
Driver Design
Table 9. High-frequency Parame trics
Parameter Description Conditions Min. Typ. Max. Unit
Fmax Maximum frequen c y
VDD = 3.3V 45%–55% duty cycle
S tandard load circuit 350 MHz
ComLink™ Series
CY2DP818
Document #: 38-07061 Rev. *A Page 5 of 8
Notes:
2. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns .
3. RL = 50 ohm ± 1%; Zline = 50 ohm 6”.
4. CL includes instrumentation and fixture capacitance within 6 mm of the UT.
5. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD – 2.
80%
20%
0V Differential
V0Y -
V0Z
t
Rt
F
1.4 V
1.0 V
1.4 V
1.0 V
0V D ifferential
0V D ifferential
1.2 V CM
1.2 V C M
V1A
V1B
V0Y
V0Z
TPLH TPHL
TPA
TPC
TPB
50
50
GND
150
150
Sta nd a r d T ermina tion
Pulse
Generator
A
B10pF VDD-2V
Figure 1. Differential Receiver to Driver Propagation Delay and Driver Transition Time[2,3,4,5]
2.0V
1.6V
VI(A)
VI(B)
Next Device
VODVOC
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
Figure 2. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[2,3,4,5]
ComLink™ Series
CY2DP818
Document #: 38-07061 Rev. *A Page 6 of 8
Notes:
6. See Table 3.
7. LVPECL or LVDS differential input value.
0.0V
100%
80%
20%
0%
tRtF
1.4V
1.0V
VI(A)
VI(B)
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B10pF VDD-2V
Figure 3. Test Circuit and Voltage Definitions for the Differential Output Signal[2,3,4,5]
1
InConfig
LVCM OS / LVTTL
LVTTL/LVCMOS
IN P U T A
IN P U T B
GND
Figure 4. [6]
InConfig
LVPECL &
LVDS
LVDS/LVPECL0
Figure 5. [7]
ComLink™ Series
CY2DP818
Document #: 38-07061 Rev. *A Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
ComLink is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Ordering Information
Part Number Package Type Product Flow
CY2DP818ZI 38-pin TSSOP Industrial, –40° to 85 °C
CY2DP818ZIT 38-pin TSSOP–Tape and Reel Industrial, –40° to 85°C
CY2DP818ZC 38-pin TSSOP Commercial, 0°C to 70°C
CY2DP818ZCT 38-pin TSSOP–Tape and Reel Commercial, 0°C to 70°C
38-lead TSSOP (4.40 mm Body) Z38
51-85151-**
ComLink™ Series
CY2DP818
Document #: 38-07061 Rev. *A Page 8 of 8
Document Title: CY2DP818 1:8 Clock Fanout Buffer
Document Number: 38-07061
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 107086 06/07/01 IKA New Data Sheet
*A 115913 07/11/02 CTK IC, VCM, VOC, Rise/Fall Time Fmax (20)
