Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. D
04/28/08
IS61LV2568L
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
APRIL 2008
FEATURES
High-speed access time: 8, 10 ns
Operating Current: 50mA (typ.)
Standby Current: 700µA (typ.)
Multiple center power and ground pins for
greater noise immunity
Easy memory expansion with CE and OE
options
CE power-down
TTL compatible inputs and outputs
Single 3.3V power supply
Packages available:
– 36-pin 400-mil SOJ
– 44-pin TSOP (Type II)
Lead-free available
DESCRIPTION
The ISSI IS61LV2568L is a very high-speed, low power,
262,144-word by 8-bit CMOS static RAM. The IS61LV2568L
is fabricated using ISSI's high-performance CMOS tech-
nology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 36mW (max.) with CMOS input levels.
The IS61LV2568L operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV2568L is available in 36-pin 400-mil SOJ and
44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
CE
OE
WE
256K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
256K x 8 HIGH-SPEED CMOS STATIC RAM
IS61LV2568L
2
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. D
04/28/08
PIN DESCRIPTIONS
A0-A17 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
VDD Power
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
NC
NC
NC
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC
44
43
42
41
44-Pin TSOP (Type II)
PIN CONFIGURATION
36-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A4
A3
A2
A1
A0
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A9
A10
A11
A12
NC
NC
Integrated Silicon Solution, Inc. — www.issi.com —
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3
Rev. D
04/28/08
IS61LV2568L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VDD Supply voltage with Respect to GND –0.5 to +4.0 V
VTERM Terminal Voltage with Respect to GND –0.5 to VDD + 0.5 V
TSTG Storage Temperature –65 to +150 °C
PDPower Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation VDD Current
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage(1) 2.0 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND VIN
VDD –1 1 µA
ILO Output Leakage GND
VOUT
VDD, Outputs Disabled 1 1 µA
Note:
1. VIL(min) = –0.3V (DC); VIL(min) = –2.0V (pulse width - 2.0 ns).
VIH(max) = VDD + 0.3V (DC); VIH(max) = VDD + 2.0V (pulse width - 2.0 ns).
OPERATING RANGE
Range Ambient Temperature VDD (8ns) VDD (10 ns)
Commercial 0°C to +70°C 3.3V +10%,-5% 3.3V + 10%
Industrial –40°C to +85°C 3.3V + 10%
IS61LV2568L
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
04/28/08
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
CI/O Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC VDD Operating VDD = Max., CE = VIL Com. 65 60 mA
Supply Current IOUT = 0 mA, f = Max. Ind. 65
typ.
(2)
—50 —50
ISB1TTL Standby VDD = Max., Com. 30 25 mA
Current VIN = VIH or VIL Ind. 30
(TTL Inputs) CE VIH, f = max
ISB2CMOS Standby VDD = Max., Com. 3 3 mA
Current CE VDD – 0.2V, Ind. 4 mA
(CMOS Inputs) VIN VDD – 0.2V, or typ.
(2)
700 700 μA
VIN 0.2V
, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.3V, TA=250C. Not 100% tested.
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5
Rev. D
04/28/08
IS61LV2568L
AC TEST LOADS
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing and Reference Levels 1.5V
Output Load See Figures 1 and 2
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
Figure 1 Figure 2
Z
O
= 50Ω
1.5V
50Ω
OUTPUT
30 pF
Including
jig and
scope
IS61LV2568L
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
04/28/08
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
- 8 ns -10 ns
Symbol Parameter Min. Max Min. Max. Unit
tRC Read Cycle Time 8 10 ns
tAA Address Access Time 8 10 ns
tOHA Output Hold Time 2.5 2.5 ns
tACE CE Access Time 8 10 ns
tDOE OE Access Time 3.5 4 ns
tLZOE
(2)
OE to Low-Z Output 0 0 ns
tHZOE
(2)
OE to High-Z Output 0 3.5 0 4 ns
tLZCE
(2)
CE to Low-Z Output 3.5 3 ns
tHZCE
(2)
CE to High-Z Output 0 3.5 0 4 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. D
04/28/08
IS61LV2568L
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
IS61LV2568L
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
04/28/08
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
- 8 ns -10 ns
Symbol Parameter Min. Max Min. Max. Unit
tWC Write Cycle Time 8 10 ns
tSCE CE to Write End 7 8 ns
tAW Address Setup Time to Write End 7 8 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Setup Time 0 0 ns
tPWE1WE Pulse Width (OE = HIGH) 6 7 ns
tPWE2WE Pulse Width (OE = LOW) 6.5 8 ns
tSD Data Setup to Write End 4 5 ns
tHD Data Hold from Write End 0 0 ns
tHZWE(3) WE LOW to High-Z Output 3 4 ns
tLZWE(3) WE HIGH to Low-Z Output 0 0 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. D
04/28/08
IS61LV2568L
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a
Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or
falling edge of the signal that terminates the Write.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
IS61LV2568L
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
04/28/08
AC WAVEFORMS
WRITE CYCLE NO. 2(1)
(WE Controlled, OE = HIGH during Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
Integrated Silicon Solution, Inc. — www.issi.com —
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11
Rev. D
04/28/08
IS61LV2568L
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
8 IS61LV2568L-8K 400-mil SOJ
IS61LV2568L-8T TSOP (Type II)
IS61LV2568L-8TL TSOP (Type II), Lead-free
10 IS61LV2568L-10T TSOP (Type II)
IS61LV2568L-10TL TSOP (Type II), Lead-free
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
10 IS61LV2568L-10KI 400-mil SOJ
IS61LV2568L-10KLI 400-mil SOJ, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
PACKAGING INFORMATION
400-mil Plastic SOJ
Package Code: K
Notes:
1. Controlling dimension:
millimeters.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
SEATING PLANE
1
N
E1
D
E2
E
B
eA1
A
C
A2
b
N/2+1
N/2
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 28 32 36
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
PACKAGING INFORMATION
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 40 42 44
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
06/18/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
D
SEATING PLANE
b
eC
1N/2
N/2+1N
E1
A1
A
E
Lα
ZD
.
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
Plastic TSOP (T - Type II)
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 32 44 50
A 1.20 0.047 1.20 0.047 1.20 0.047
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008
D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830
E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471
e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC
L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024
ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF
α