3
INDUSTRIAL TEMPERATURE RANGE
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
NOTES:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (tU) which ranges
from 278ps to 625ps (see Programmable Skew Range and Resolution
Table). There are 16 skew configurations available for each output pair.
These configurations are chosen by the nF2:0 control pins. In order to
minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF2:0 control pins.
PROGRAMMABLE SKEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max Unit
VDDQ, VDD Supply Voltage Range –0.5 to +4.6 V
VI(2) Input Voltage Range –0.5 to 4.6 V
VO(2) Voltage range applied to any –0.5 to V
output in the high or low state VDDQ + 0.5
IIK (VI < 0) Input Clamp Current –50 mA
IO (VO = 0 to VDDQ) Continuous Output Current ±50 mA
VDDQ or GND Continuous Current ±100 mA
TSTG Storage Temperature Range –65 to +150 °C
NOTES:
1. Unused inputs must be held high or low to prevent them from floating.
2. Capacitance applies to all inputs except nF2:0. This value is characterized but not
production tested.
CAPACITANCE(1,2)(TA = +25°C, f = 1MHz, V IN = 0V)
Parameter Description Min Typ. Max. Unit
CIN Input Capacitance — 8 — pF
VI = VDDQ or GND
PIN DESCRIPTION
Pin Name Type Description
REF IN Reference Clock Input
SE IN Selectable positive or negative edge control. When LOW / HIGH, the outputs are synchronized with the negative/positive edge of the
reference clock. When outputs are synchronously stopped with the G pin, SE determines the level at which outputs stop. When SE is
LOW/HIGH, outputs synchronously stop HIGH/LOW.
FB IN Feedback Input
G IN Output gate for “true” nQ[1:0] outputs. When G is LOW, the “true” nQ[1:0] outputs are enabled. When G is HIGH, the “true” nQ[1:0] outputs
are in the state designated by SE (HIGH or LOW) (except 3Q0 and 3Q1) - 3Q0 and 3Q1 may be used as the feedback signal to maintain
phase lock.
TEST IN TEST = LOW means normal operation. TEST = HIGH means that the PLL is powered down and REF is routed to all the outputs. The
skews selected with the nF[2:0] pins are still in effect. (The TEST pin is a TTL input.)
nF[2:0] IN 3-level inputs for selecting 1 of 18 skew taps or frequency functions
nQ[1:0] OUT Clock Output Pairs
VDDQ PWR Power supply for output buffers
VDD PWR Power supply for phase locked loop and other internal circuitry
GND PWR Ground
LOCK OUT Lock Detect. Asserted (HIGH) when the PLL is locked. The REF input must be oscillating.