Publication Number S25FL004K-016K_00 Revision 02 Issue Date July 14, 2011
S25FL004K / S25FL008K / S25FL016K
S25FL004K / S25FL008K / S25FL016K Cover Sheet
4-Mbit / 8-Mbit / 16-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described he rein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
2 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizi ng their design. The following descriptions of Spansion data
sheet designations are pres ented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any desig n to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places th e following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. res erves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates tha t the produc t developmen t has pro gressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process th at occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preli minary status of this document i ndicates that product qu alification has been
completed, and that initial production h as begun. Due to the phases of the ma nufactu ring process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document dis tinguishes these products and their designations
wherever necessary, ty pically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as th e addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc . deems the products to have been in suffi cient production volu me such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
This document states th e current technic al specifica tions regardin g the Spansion produ ct(s) descr ibed herein. Spansion Inc. dee ms the produ cts to have been in suff icient pro-
duction volume such that subsequent versions of this document are not expected to change. Howe ver, typographical or specification corrections, or modifications to the valid com-
binations offered may occur.
Publication Number S25FL004K-016K_00 Revision 02 Issue Date July 14, 2011
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 to 3.6V read an d write operations
Memory architecture
– Uniform 4-kB sectors
– 256-byte page size
Program
– Page Program (up to 256 bytes) in 0.7 ms (typical)
– Program operations are on a page by page basis
– Quad Page Programming
Erase
– Bulk erase function
– Uniform sector erase (4 kB)
– Uniform block erase (32 kB and 64 kB)
– Erase/Program Suspend and Resume
Cycling endurance
– 100,000 erase/program cycles ty pical
Data retention
– 20-year data retention typical
Process technology
– Manufactured on 0.09 µm process technology
Package option
– Industry Standard Pinouts
– 8-pin SO package (208 mils)
– 8-pin SO package (150 mils)
Performance Characteristics
Speed
– Normal READ (Serial): 50 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– 104 MHz Dual SPI/Quad SPI clocks
– 208/416 MHz equivalent Dual/Quad SPI
– 50 MB/s continuous data transfer rate (S25FL004K/S25FL008K)
– 52 MB/s continuous data transfer rate (S25FL016K)
Low Power Consumption
– 4 mA active current
<1 µA in Deep Power-down mode (typical) (S25FL004K/
S25FL016K)
1 µA in Deep Power-down mode (typical) (S25FL008K)
– Industrial temperature range (–4 0°C to +85°C)
Efficient “Continuous Read Mode”
– Low I nstruction overhead
– Contin u ous Read with 8/16/32/64-byte Wrap
– As few as 8 clocks to address memory
– Allows true XIP (execute in place) operation
Memory Protection Features
Advanced security features
– Software and Hardware Write-Protect
– Top/Bottom, 4-kB complement array protection
– Power Supply Lock-Down and OTP protect i on
– 64-bit Unique ID for each device
– Discoverable Parameters (SFDP) Registers
– 3x 256-byte Security Regis ters with OTP locks
– Volatile and Non-volatile Status Register Bits
S25FL004K / S25FL008K / S25FL016K
4-Mbit / 8-Mbit / 16-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
4 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
General Description
The S25FL004K (4-Mbit), S25FL008K (8-Mbit), and S25FL016K (16-Mbit) Serial Flash memories provide an
ideal storage solution for systems with limited space, pins and power. The devices offer flexibility and
performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM,
executing code directly from Dua l/Quad S PI (XIP) an d storin g voice, te xt and data. The devices operate on a
single 2.7V to 3.6V power supply with current consumption as low as 4 mA active and 1 µA for deep power-
down. All devices are offered in space-saving pack ages.
The S25FL004K, S25FL008K, and S25FL016K support the standard Serial Peripheral Interface (SPI), and a
high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock (CLK), Chip Select (CS#),
Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). SPI c lo ck frequencies of up to 104 MHz are
supported allowing equivalent clock rates of 208 MHz (104 MHz x 2) for Dual I/O and 416 MHz (104 MHz x 4)
for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform
standard Asynchronous 8 and 16-bit Parallel Flash memories. The Con tinuous Read Mode allows for effic ient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP
(execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device
identification with a 64-bit Unique Serial Number.
S25FL004K
The S25FL004K array is organized into 2,048 programmable pages of 256 bytes each. Up to 256 bytes can
be programmed at a time. Pages can be erased in groups of 16 (4-kB sector erase), groups of 128 (32-kB
block erase), groups of 256 (64-kB block erase) or the entire chip (chip erase). The S25FL004K has 128
erasable sectors and 8 erasable blocks respectively. The small 4-kB sectors allow for greater flexibility in
applications that require data and parameter storage.
S25FL008K
The S25FL008K array is organized into 4,096 programmable pages of 256 bytes each. Up to 256 bytes can
be programmed at a time. Pages can be erased in groups of 16 (4-kB sector erase), groups of 128 (32-kB
block erase), groups of 256 (64-kB block erase) or the entire chip (chip erase). The S25FL008K has 256
erasable sectors and 16 erasable blocks respectively. The small 4-kB sectors allow for greater flexibility in
applications that require data and parameter storage.
S25FL016K
The S25FL016K array is organized into 8,192 programmable pages of 256 bytes each. Up to 256 bytes can
be programmed at a time. Pages can be erased in groups of 16 (4-kB sector erase), groups of 128 (32-kB
block erase), groups of 256 (64-kB block erase) or the entire chip (chip erase). The S25FL016K has 512
erasable sectors and 32 erasable blocks respectively. The small 4-kB sectors allow for greater flexibility in
applications that require data and parameter storage.
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 5
Data Sheet
Table of Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 S25FL004K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 S25FL008K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 S25FL016K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 SPI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 Write Enable (06h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2 Write Enable for Volatile Status Register (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3 Write Disable (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.4 Read Status Register-1 (05h) and Read Status Register-2 (35h) . . . . . . . . . . . . . . . . . . . . . 28
7.5 Write Status Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 Read Data (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.7 Fast Read (0Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.8 Fast Read Dual Output (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.9 Fast Read Quad Output (6Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.10 Fast Read Dual I/O (BBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.11 Fast Read Quad I/O (EBh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.12 Word Read Quad I/O (E7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.13 Octal Word Read Quad I/O (E3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.14 Set Burst with Wrap (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.15 Continuous Read Mode Bits (M7-0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.16 Continuous Read Mode Reset (FFh or FFFFh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.17 Page Program (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.18 Quad Page Program (32h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.19 Sector Erase (20h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.20 32 KB Block Erase (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.21 64 KB Block Erase (D8h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.22 Chip Erase (C7h / 60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.23 Erase / Program Suspend (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.24 Erase / Program Resume (7Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.25 Deep Power-down (B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.26 Release from Deep Power-down / Device ID (ABh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.27 Read Manufacturer / Device ID (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.28 Read Manufacturer / Device ID Dual I/O (92h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.29 Read Manufacturer / Device ID Quad I/O (94h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.30 Read Unique ID Number (4Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.31 Read JEDEC ID (9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.32 Read SFDP Register (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.33 Erase Security Registers (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.34 Program Security Registers (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.35 Read Security Registers (48h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
8.3 Power-Up Timing and Write Inhibit Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.5 AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.6 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.7 Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.8 Serial Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.9 Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.1 SOA008 narrow — 8-pin Plastic Small Outline Package (150-mils Body Width) . . . . . . . . . 67
9.2 SOC008 wide — 8-pin Plastic Small Outline Package (208-mils Body Width) . . . . . . . . . . . 68
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 7
Data Sheet
Figures Figure 2.1 8-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6.1 Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6.2 Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7.1 Write Enable Instruction Sequence Dia gram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7.2 Write Enable for Volatile Status Register Instruction Sequence Diagram . . . . . . . . . . . . . . . 27
Figure 7.3 Write Disable Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7.4 Read Status Register Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7.5 Write Status Register Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7.6 Read Data Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7.7 Fast Read Instruction Sequence Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 7.8 Fast Read Dual Output Instruction Sequence Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7.9 Fast Read Quad Output Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7.10 Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 10) . . . . . . 33
Figure 7.11 Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) . . . . . . . . . . 34
Figure 7.12 Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10) . . . . . . 35
Figure 7.13 Fast Read Quad I/O Instruction Sequence (Prev i ous instruction set M5-4 = 10) . . . . . . . . . 35
Figure 7.14 Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10) . . . . . 36
Figure 7.15 Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10). . . . . . . . . 37
Figure 7.16 Octal Word Read Quad I/O Instruction Sequence (Initia l instru ction or previous M5-4 10) 38
Figure 7.17 Octal Word Read Quad I/O Instruction Sequence (P revious instruction set M5-4 = 10). . . . 38
Figure 7.18 Set Burst with Wrap Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7.19 Continuous Read Mode Reset for Fast Read Dual/Quad I/O . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7.20 Page Program Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 7.21 Quad Page Program Instruction Sequence Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 7.22 Sector Erase Instruction Sequence Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 7.23 32 kB Block Erase Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 7.24 64 kB Block Erase Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 7.25 Chip Erase Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7.26 Erase/Program Suspend Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 7.27 Erase/Program Resume Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 7.28 Deep Power-down Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 7.29 Release from Deep Power-down Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 7.30 Release from Deep Power-down / Device ID Instruction Sequence Diagra m. . . . . . . . . . . . 50
Figure 7.31 Read Manufacturer / Device ID Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7.32 Read Manufacturer / Device ID Dual I/O Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 7.33 Read Manufacturer / Device ID Quad I/O Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 7.34 Read Unique ID Number Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 7.35 Read JEDEC ID Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 7.36 Read SFDP Register Instruction Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 7.37 Erase Security Registers Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 7.38 Program Security Registers Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 7.39 Read Security Registers Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 8.1 Power-Up Timing and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 8.2 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 8.3 Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 8.4 Serial Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 8.5 Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Tables Table 3.1 8-pin SOIC 150-mil / 208-mil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 4.1 S25FL004K, S25FL008K, and S25FL016K Valid Combinations . . . . . . . . . . . . . . . . . . . . . .13
Table 6.1 Status Register Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 6.2 S25FL004K Status Register Memory Protection (CMP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 6.3 S25FL008K Status Register Memory Protection (CMP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 6.4 S25FL016K Status Register Memory Protection (CMP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 6.5 S25FL004K Status Register Memory Protection (CMP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 6.6 S25FL008K Status Register Memory Protection (CMP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 6.7 S25FL016K Status Register Memory Protection (CMP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 7.1 Manufacturer Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7.2 Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7.3 Instruction Set (Erase, Program Instructions (1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7.4 Instruction Set (Read Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 7.5 Instruction Set (ID, Security Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.6 Serial Flash Discoverable Parameter Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 8.1 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 9
Data Sheet
1. Block Diagrams
1.1 S25FL004K Block Diag ram
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
Column Decode
And 256-byte Page Buffer
Beginning
Page Address Ending
Page Addre ss
S25FL0040K
SPI
Command &
Control Logic
Byte Address
Latch / Counter
Status
Register
Write Control
Logic
Page Address
Latch / Counter
SO (IO1)
SI (IO0)
CS#
CLK
HOLD# (IO3)
WP (IO2)
High Voltage
Generators
xx0F00h xx0FFFh
•Sector 0 (4 kB) •
xx0000h xx00FFh
xx1F00h xx1FFFh
•Sector 1 (4 kB) •
xx1000h xx10FFh
xx2F00h xx2FFFh
•Sector 2 (4 kB) •
xx2000h xx20FFh
•
•
•
xxDF00h xxDFFFh
•Sector 13 (4 kB) •
xxD000h xxD0FFh
xxEF00h xxEFFFh
•Sector 14 (4 kB) •
xxE000h xxE0FFh
xxFF00h xxFFFFh
•Sector 15 (4 kB) •
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 1 - 3
Write Protect Logic and Row Decode
000000h 0000FFh
SFDP Register
00FF00h 00FFFFh
• Block 0 (64 kB) •
000000h 0000FFh
01FF00h 01FFFFh
• Block 1 (64 kB) •
010000h 0100FFh
•
•
•
03FF00h 03FFFFh
• Block 3 (64 kB) •
030000h 0300FFh
04FF00h 04FFFFh
• Block 4 (64 kB) •
040000h 0400FFh
•
•
•
07FF00h 07FFFFh
• Block 7 (64 kB) •
070000h 0700FFh
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
xx0F00h xx0FFFh
xx0000h xx00FFh
xx1F00h xx1FFFh
xx1000h xx10FFh
xx2F00h xx2FFFh
xx2000h xx20FFh
•
•
•
xxDF00h xxDFFFh
xxD000h xxD0FFh
xxEF00h xxEFFFh
xxE000h xxE0FFh
xxFF00h xxFFFFh
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 1 - 3
Write Protect Logic and Row Decode
000000h 0000FFh
SFDP Register
00FF00h 00FFFFh
000000h 0000FFh
01FF00h 01FFFFh
010000h 0100FFh
•
•
•
03FF00h 03FFFFh
030000h 0300FFh
04FF00h 04FFFFh
040000h 0400FFh
•
•
•
07FF00h 07FFFFh
070000h 0700FFh
10 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
1.2 S25FL008K Block Diag ram
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
Column Decode
And 256-byte Page Buffer
Beginning
Page Address Ending
Page Address
S25FL008K
SPI
Command &
Control Logic
Byte Address
Latch / Counter
Status
Register
Write Control
Logic
Page Address
Latch / Counter
SO (IO1)
SI (IO0)
CS#
CLK
HOLD# (IO3)
WP# (IO2)
High Voltage
Generators
xx0F00h xx0FFFh
• Sector 0 (4 kB) •
xx0000h xx00FFh
xx1F00h xx1FFFh
• Sector 1 (4 kB) •
xx1000h xx10FFh
xx2F00h xx2FFFh
• Sector 2 (4 kB) •
xx2000h xx20FFh
•
•
•
xxDF00h xxDFFFh
• Sector 13 (4 kB) •
xxD000h xxD0FFh
xxEF00h xxEFFFh
• Sector 14 (4 kB) •
xxE000h xxE0FFh
xxFF00h xxFFFFh
• Sector 15 (4 kB) •
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 1 - 3
Write Protect Logic and Row Decode
000000h 0000FFh
SFDP Register
00FF00h 00FFFFh
• Block 0 (64 kB) •
000000h 0000FFh
•
•
•
03FF00h 03FFFFh
• Block 3 (64 kB) •
030000h 0300FFh
04FF00h 04FFFFh
• Block 4 (64 kB) •
040000h 0400FFh
•
•
•
07FF00h 07FFFFh
• Block 7 (64 kB) •
070000h 0700FFh
08FF00h 08FFFFh
• Block 8 (64 kB) •
080000h 0800FFh
•
•
•
0FFF00h 0FFFFFh
• Block 15 (64 kB) •
0F0000h 0F00FFh
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
Beginning
Page Address Ending
Page Address
CLK
xx0F00h xx0FFFh
xx0000h xx00FFh
xx1F00h xx1FFFh
xx1000h xx10FFh
xx2F00h xx2FFFh
xx2000h xx20FFh
•
•
•
xxDF00h xxDFFFh
xxD000h xxD0FFh
xxEF00h xxEFFFh
xxE000h xxE0FFh
xxFF00h xxFFFFh
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 1 - 3
Write Protect Logic and Row Decode
000000h 0000FFh
SFDP Register
00FF00h 00FFFFh
000000h 0000FFh
•
•
•
03FF00h 03FFFFh
030000h 0300FFh
04FF00h 04FFFFh
040000h 0400FFh
•
•
•
07FF00h 07FFFFh
070000h 0700FFh
08FF00h 08FFFFh
080000h 0800FFh
•
•
•
0FFF00h 0FFFFFh
0F0000h 0F00FFh
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 11
Data Sheet
1.3 S25FL016K Block Diag ram
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
Column Decode
And 256-byte Page Buffer
Beginning
Page Address Ending
Page Addre ss
S25FL016K
SPI
Command &
Control Logic
Byte Address
Latch / Counter
Status
Register
Write Control
Logic
Page Address
Latch / Counter
SO (IO1)
CS#
CLK
HOLD# (IO3)
WP# (IO2)
High Voltage
Generators
xx0F00h xx0FFFh
•Sector 0 (4 kB) •
xx0000h xx00FFh
xx1F00h xx1FFFh
•Sector 1 (4 kB) •
xx1000h xx10FFh
xx2F00h xx2FFFh
•Sector 2 (4 kB) •
xx2000h xx20FFh
•
•
•
xxDF00h xxDFFFh
•Sector 13 (4 kB) •
xxD000h xxD0FFh
xxEF00h xxEFFFh
•Sector 14 (4 kB) •
xxE000h xxE0FFh
xxFF00h xxFFFFh
•Sector 15 (4 kB) •
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 1 - 3
Write Protect Logic and Row Decode
00FF00h 00FFFFh
• Block 0 (64 kB) •
000000h 0000FFh
•
•
•
07FF00h 07FFFFh
• Block 7 (64 kB) •
070000h 0700FFh
08FF00h 08FFFFh
• Block 8 (64 kB) •
080000h 0800FFh
•
•
•
0FFF00h 0FFFFFh
• Block 15 (64 kB) •
0F0000h 0F00FFh
10FF00h 10FFFFh
• Block 16 (64 kB) •
100000h 1000FFh
•
•
•
1FFF00h 1FFFFFh
• Block 31 (64 kB) •
1F0000h 1F00FFh
000000h 0000FFh
SFDP Register
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
Beginning
Page Address Ending
Page Addre ss
Byte Address
Latch / Counter
SI (IO0)
CLK
xx0F00h xx0FFFh
xx0000h xx00FFh
xx1F00h xx1FFFh
xx1000h xx10FFh
xx2F00h xx2FFFh
xx2000h xx20FFh
•
•
•
xxDF00h xxDFFFh
xxD000h xxD0FFh
xxEF00h xxEFFFh
xxE000h xxE0FFh
xxFF00h xxFFFFh
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 1 - 3
Write Protect Logic and Row Decode
00FF00h 00FFFFh
000000h 0000FFh
•
•
•
07FF00h 07FFFFh
070000h 0700FFh
08FF00h 08FFFFh
080000h 0800FFh
•
•
•
0FFF00h 0FFFFFh
0F0000h 0F00FFh
10FF00h 10FFFFh
100000h 1000FFh
•
•
•
1FFF00h 1FFFFFh
1F0000h 1F00FFh
000000h 0000FFh
SFDP Register
12 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
2. Connection Diagrams
Figure 2.1 8-pin Plastic Small Outline Package (SO)
3. Input/Output Descriptions
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions.
2. IO0 – IO3 are used for Quad SPI instructions.
1
2
3
4
CS#
SO (IO1)
WP# (IO2)
GND SI (IO0)
CLK
HOLD# (IO3)
VCC
5
6
7
8
Table 3.1 8-pin SOIC 150-mil / 208-mil
Pin No. Pin Name I/O Function
1 CS# I Chip Select Input
2 SO (IO1) I/O Data Output (Data Input Output 1) (1)
3 WP# (IO2) I/O Write Protect Input (Data Input Output 2) (2)
4 GND Ground
5 SI (IO0) I/O Data Input (Data Input Output 0) (1)
6 CLK I Serial Clock Input
7 HOLD# (IO3) I/O Hold Input (Data Input Output 3) (2)
8 VCC Power Supply
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 13
Data Sheet
4. Ordering Information
The ordering part number is formed by a valid combination of the following:
4.1 Valid Combinations
Table 4.1 lists the valid combinations configurations planned to be supported in volume for this device.
S25FL 016 K 0X M F I 01 1 Pack ing Type
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
01 = 8-pin SO package (208 mil)
04 = 8-pin SO pac kage (150 mil)
Temperature Range
I = Industrial (–40°C to +85°C)
Package Materials
F = Lead (Pb)-free
Package Type
M = 8-pin SO package
Speed
0X = 104 MHz
Device Technology
K = 0.09 µm process technology
Density
004 = 4 Mbit
008 = 8 Mbit
016 = 16 Mbit
Device Family
S25FL
Spansion Memory 3.0 Volt-Only, Ser ial Peripheral Interface (SPI) Flash Memory
Table 4.1 S25FL004K, S25FL008K, and S25FL016K Valid Combinations
Valid Combinations
Pa ckage Marking
Base Ordering
Part Number Speed Option Package &
Temperature Model
Number Packing Type
S25FL004K 0X MFI 01, 04 0, 1, 3 FL004KIF
S25FL008K 0X MFI 01, 04 0, 1, 3 FL008KIF
S25FL016K 0X MFI 01, 04 0, 1, 3 FL016KIF
14 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
5. Functional Description
5.1 SPI Operations
5.1.1 Standard SPI Instructions
The S25FL004K/S25FL008K/S25FL016K is accessed through an SPI compatible bus consisting of four
signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Standard
SPI instructions use the SI input pin to s erially write instructions, addresses or data to the device on the rising
edge of CLK. The SO output pin is used to read data or status from the device on the falling edge CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode
3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being
transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of
CS#. For Mode 3, the CLK signal is normally high on the falling and rising edges of CS#.
5.1.2 Dual SPI Instructions
The S25FL004K/S25FL008K/S25FL016K supports Dual SPI operation when using the “Fast Read Dual
Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to
or from the device at two to three times the rate o f ordinary Serial Flash devices. The Dual SPI Read
instructions are ideal for quickly downloading c ode to RAM upon power-up (code-shado wing) or for executing
non-speed-critical code directly from the SPI bus (XIP). When usin g Dual SPI instructions, the SI and SO pins
become bidirectional I/O pins: IO0 and IO1.
5.1.3 Quad SPI Instructions
The S25FL004K/S25FL008K/S25FL016K supports Quad SPI operation when using the “Fast Read Quad
Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O
(E3h)” instructions. These instructions allow data to be transferred to or from the device four to six times the
rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and
random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus
(XIP). When using Quad SPI instructions the SI an d SO pins become bidire ctional IO0 and IO1, and the WP#
and HOLD# pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad
Enable bit (QE) in Status Register-2 to be set.
5.1.4 Hold Function
For Standard SPI and Dual SPI operations, the HOLD# signal allows the S25FL004K/S25FL008K/
S25FL016K operation to be paused while it is actively selected (when CS# is low). The HOLD# function may
be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider
if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case
the HOLD# function can save the state of the instruction and the data in the buffer so programming can
resume where it left off once the bus is available again . The HOLD# function is only available for standard S PI
and Dual SPI operation, not during Quad SPI.
To initiate a HOLD# condition, the device must be selecte d with CS# low. A HOLD# condition will ac tivate on
the falling edge of th e HOLD# s ignal if the CLK s ignal is already low. If the CLK is not already low the HOLD#
condition will activate after the next falling edge of CLK. The HOLD# condition will terminate on the rising
edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition
will terminate after the next falling edge of CLK. During a HOLD# condition, the Serial Data Output (SO) is
high impedance, and Serial Data Input (SI) and Serial Clock (CLK) are ign ored. The Chip Sele ct (CS#) signal
should be kept active (low) for the full duration of the HOLD# operation to avoid resetting the internal logic
state of the device.
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 15
Data Sheet
5.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the S25FL004 K/
S25FL008K/S25FL016K provides several means to protec t the data from inadvertent writes.
5.2.1 Write Protect Features
Device resets when VCC is belo w threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or prog ram
Software and Hardware (WP# pin) write protection using Status Register
Write Protection using Deep Power-down instruction
Lock Down write protection until next power-up
One Time Program (OTP) write protection
Upon power-up or at power-down, the S25FL004K/S25FL00 8K/S25FL016K will maintain a reset condition
while VCC is below the threshold value of VWI, (see Figure 8.1, Power-Up Timing and Voltage Levels
on page 62). While reset, all operations are disabled and no instructions are recognized. During power-up
and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a
time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase
and the Write Status Register instructions. Note that the chip select pin (CS#) must track th e VCC supply level
at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resistor on CS# can be
used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits. These
settings allow a portion as small as 4-kB sector or the entire memory array to be configured as read only.
Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be enabled or
disabled under hardware control. See Status Register on page 16. for further information. Additionally, the
Deep Power-down instruction offers an extra level of write prote ction as all instruction s are ignored except for
the Release from Deep Power-down instruction.
6. Control and Status Registers
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection,
Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write Status
Register instruction can be used to configure the device write protection features, Quad SPI setting and
Security Register OTP lock. Write access to the Status Regis ter is controlled by the state of the non-volatile
Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI
operations, the WP# pin.
16 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
6.1 Status Register
6.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 s tat e whe n the devic e is exe cuting a Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/
Program Security Register instruction. During this time the device will ignore further instructions except fo r the
Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in Section 8.6,
AC Electrical Characteristics on page 64). When the program, erase or write status/security register
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further
instructions.
6.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state
occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and
Program Security Register.
6.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0 ) are non-volatile re ad/write bits in the status register (S 4, S3, and S2)
that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register
Instruction (see tW in AC Electrica l Charac teristics on page 64). All, none or a portion of the memory array
can be protected from Program and Erase instructio ns (see Table 6.3 on page 20). The factory default setting
for the Block Protec tion Bits is 0 (none of the array is protected.)
6.1.4 Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in Table 6.1, Status Register Protection Bits on page 17.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruc tion depending
on the state of the SRP0, SRP1 and WEL bits.
6.1.5 Sector/Block Protect (SEC)
The non-volatile Sector/Block Protect bit (S EC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as
shown in Table 6.1. The default setting is SEC=0.
6.1.6 Complement Protect (CMP)
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protectio n set b y SEC, TB, BP2, BP1 and BP0 will be reve rsed. For instanc e,
when CMP=0, a top 4-kB sector can be protected while the rest of the array is not; when CMP=1, th e top 4-kB
sector will become unprotected while the res t of the array become read-only. Please refer to Table 6.1 for
details. The default setting is CMP=0.
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 17
Data Sheet
6.1.7 Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8
and S7). The SRP bits control the method of write protection: s oftware protection, hardware protection, power
supply lock-down or one time programmable (OTP) protection.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This fea ture is available upon special order. Please contact Spansion for details.
6.1.8 Erase/Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/
Program Suspend (75h) in struction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah)
instruction as well as a power-down, power-up cycle.
6.1.9 Security Register Lock Bits (LB3, LB2, LB1)
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and statu s to the Security Registers. The
default state of LB[3:1] is 0, Security Registers are unlocked. LB[3:1] can be set to 1 individually using the
Write Status Register instruction. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-byte Security Register will become read-only permanently.
6.1.10 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# are enabled. When
the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HO LD# functions are disabled.
Note: If the WP# or HOLD# pins are tied directly to the power supply or ground during standard SPI or Dual
SPI oper at ion, the QE bit should nev er be set to a 1.
Table 6.1 Status Register Protection Bits
SRP1 SRP0 WP# Status Register Description
0 0 X Software Protection WP# pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0 1 0 Hardware Protected When WP# pin is low the Status Register locked and can not be
written to.
0 1 1 Hardware Unprotected When WP# pin is high the Status register is unlock ed and can be
written to after a Write Enable instruction, WEL=1.
10X
Power Supply Lock-
Down Status Reg ister is protected and can not be written to again until
the next power-down, power-up cycle. (1)
1 1 X One Time Program (2) Status Register is permanently protected and can not be written
to.
18 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Figure 6.1 Status Register 1
Figure 6.2 Status Register 2
S7S6S5S4S3 S2S1S0
SRP0 SEC TB BP2 BP1 BP0 WEL BUSY
Status Register Protect 0
(non-volatile)
Sector Protect
(non-volatile)
Top/Bottom Protect
(non-volatile)
Block Protect Bits
(non-volatile)
Write Enable Latch
Erase/Write In Progress
S7S6S5S4S3 S2S1S0
SRP0 SEC TB BP2 BP1 BP0 WEL BUSY
S15 S14 S13 S12 S11 S10 S9S8
SUSCMP LB3LB2 LB1 (R) QE SRP1
Suspend Status
Complement Protect
(non-volatile)
Security Register Lock Bits
(non-volatile OTP)
Quad Enable
(non-volatile)
Status Register Protect 1
(
non-volatile
)
Reserved
S15 S14 S13 S12 S11 S10 S9S8
SUSCMP LB3LB2 LB1 (R) QE SRP1
(
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 19
Data Sheet
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
Table 6.2 S25FL004K Status Register Memory Protection (CMP = 0)
Status Register (1) S25FL004K (4 Mbit) Memory Protection (2)
SEC TB BP2 BP1 BP0 Block(s) Addresses Density Portion
X X 0 0 0 None None None None
0 0 0 0 1 7 070000h – 07FFFFh 64 kB Upper 1/8
0 0 0 1 0 6 and 7 060000h – 07FFFFh 128 kB Upper 1/4
0 0 0 1 1 4 thru 7 040000h – 07FFFFh 256 kB Upper 1/2
0 1 0 0 1 0 000000h – 00FFFFh 64 kB Lower 1/8
0 1 0 1 0 0 and 1 000000h – 01FFFFh 128 kB Lower 1/4
0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256 kB Lower 1/2
0 X 1 X X 0 thru 7 000000h – 07FFFFh 512 kB All
1 0 0 0 1 7 07F000h – 07FFFFh 4 kB Upper 1/128
1 0 0 1 0 7 07E000h – 07FFFFh 8 kB Upper 1/64
1 0 0 1 1 7 07C000h – 07FFFFh 16 kB Upper 1/32
1 0 1 0 X 7 078000h – 07FFFFh 32 kB Upper 1/16
1 0 1 1 0 7 078000h – 07FFFFh 32 kB Upper 1/16
1 1 0 0 1 0 000000h – 000FFFh 4 kB Lower 1/128
1 1 0 1 0 0 000000h – 001FFFh 8 kB Lower 1/64
1 1 0 1 1 0 000000h – 003FFFh 16 kB Lower 1/32
1 1 1 0 X 0 000000h – 007FFFh 32 kB Lower 1/16
1 1 1 1 0 0 000000h – 007FFFh 32 kB Lower 1/16
1 X 1 1 1 0 thru 7 000000h – 07FFFFh 512 kB All
20 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
Table 6.3 S25FL008K Status Register Memory Protection (CMP = 0)
Status Register (1) S25FL008K (8 Mbit) Memory Protection (2)
SEC TB BP2 BP1 BP0 Block(s) Addresses Density Portion
X X 0 0 0 None None None None
0 0 0 0 1 15 0F0000h – 0FFFFFh 64 kB Upper 1/16
0 0 0 1 0 14 and 15 0E0000h – 0FFFFFh 128 kB Upper 1/8
0 0 0 1 1 12 thru 15 0C0000h – 0FFFFFh 256 kB Upper 1/4
0 0 1 0 0 8 thru 15 080000h – 0FFFFFh 512 kB Upper 1/2
0 1 0 0 1 0 000000h – 00FFFFh 64 kB Lower 1/16
0 1 0 1 0 0 and 1 000000h – 01FFFFh 128 kB Lower 1/8
0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256 kB Lower 1/4
0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512 kB Lower 1/2
0 X 1 0 1 0 thru 15 000000h – 0FFFFFh 1 MB All
X X 1 1 X 0 thru 15 000000h – 0FFFFFh 1 MB All
1 0 0 0 1 15 0FF000h – 0FFFFFh 4 kB Upper 1/256
1 0 0 1 0 15 0FE000h – 0FFFFFh 8 kB Upper 1/128
1 0 0 1 1 15 0FC000h – 0FFFFFh 16 kB Upper 1/64
1 0 1 0 X 15 0F8000h – 0FFFFFh 32 kB Upper 1/32
1 1 0 0 1 0 000000h – 000FFFh 4 kB Lower 1/256
1 1 0 1 0 0 000000h – 001FFFh 8 kB Lower 1/128
1 1 0 1 1 0 000000h – 003FFFh 16 kB Lower 1/64
1 1 1 0 X 0 000000h – 007FFFh 32 kB Lower 1/32
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 21
Data Sheet
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
Table 6.4 S25FL016K Status Register Memory Protection (CMP = 0)
Status Register (1) S25FL016 K (16 Mbit) Memory Protection (2)
SEC TB BP2 BP1 BP0 Protected Block(s) Prot ect ed Addresses Protected
Density Protected Por tion (2)
X X 0 0 0 None None None None
0 0 0 0 1 31 1F0000h – 1FFFFFh 64 kB Upper 1/32
0 0 0 1 0 30 and 31 1E0000h – 1FFFFFh 128 kB Upper 1/16
0 0 0 1 1 28 thru 31 1C0000h – 1FFFFFh 256 kB Upper 1/8
0 0 1 0 0 24 thru 31 180000h – 1FFFFFh 512 kB Upper 1/4
0 0 1 0 1 16 thru 31 100000h – 1FFFFFh 1 MB Upper 1/2
0 1 0 0 1 0 000000h – 00FFFFh 64 kB Lower 1/32
0 1 0 1 0 0 and 1 000000h – 01FFFFh 128 kB Lower 1/16
0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256 kB Lower 1/8
0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512 kB Lower 1/4
0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1 MB Lower 1/2
X X 1 1 X 0 thru 31 000000h – 1FFFFFh 2 MB All
1 0 0 0 1 31 1FF000h – 1FFFFFh 4 kB Upper 1/512
1 0 0 1 0 31 1FE000h – 1FFFFFh 8 kB Upper 1/256
1 0 0 1 1 31 1FC000h – 1FFFFFh 16 kB Upper 1/128
1 0 1 0 X 31 1F8000h – 1FFFFFh 32 kB Upper 1/64
1 1 0 0 1 0 000000h – 000FFFh 4 kB Lower 1/512
1 1 0 1 0 0 000000h – 001FFFh 8 kB Lower 1/256
1 1 0 1 1 0 000000h – 003FFFh 16 kB Lower 1/128
1 1 1 0 X 0 000000h – 007FFFh 32 kB Lower 1/64
22 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
Table 6.5 S25FL004K Status Register Memory Protection (CMP = 1)
Status Register (1) S25FL004K (4 Mbit) Memory Protection (2)
SEC TB BP2 BP1 BP0 Block(s) Addresses Density Portion
X X 0 0 0 0 thru 7 000000h – 07FFFFh 512 kB All
0 0 0 0 1 0 thru 6 000000h – 06FFFFh 448 kB Lower 7/8
0 0 0 1 0 0 thru 5 000000h – 05FFFFh 384 kB Lower 3/4
0 0 0 1 1 0 thru 3 000000h – 03FFFFh 256 kB Lower 1/2
0 1 0 0 1 1 thru 7 010000h – 07FFFFh 448 kB Upper 7/8
0 1 0 1 0 2 thru 7 020000h – 07FFFFh 384 kB Upper 3/4
0 1 0 1 1 4 thru 7 040000h – 07FFFFh 256 kB Upper 1/2
1 0 0 0 1 0 thru 7 000000h – 07EFFFh 508 kB Low er 127/128
1 0 0 1 0 0 thru 7 000000h – 07DFFFh 504 kB Lower 63/64
1 0 0 1 1 0 thru 7 000000h – 07BFFFh 496 kB Lower 31/32
1 0 1 0 X 0 thru 7 000000h – 077FFFh 480 kB Low er 15/16
1 0 1 1 0 0 thru 7 000000h – 077FFFh 480 kB Lower 15/16
1 1 0 0 1 0 thru 7 001000h – 07FFFFh 508 kB Upper 127/128
1 1 0 1 0 0 thru 7 002000h – 07FFFFh 504 kB Upper 63/64
1 1 0 1 1 0 thru 7 004000h – 07FFFFh 496 kB Upper 31/32
1 1 1 0 X 0 thru 7 008000h – 07FFFFh 480 kB Upper 15/16
1 1 1 1 0 0 thru 7 008000h – 07FFFFh 480 kB Upper 15/16
X X 1 1 1 None None None None
Table 6.6 S25FL008K Status Register Memory Protection (CMP = 1)
Status Register (1) S25FL008K (8 Mbit) Memory Protection (2)
SEC TB BP2 BP1 BP0 Block(s) Addresses Density Portion
X X 0 0 0 0 thru 15 000000h – 0FFFFFh 1 MB All
0 0 0 0 1 0 thru 14 000000h – 0EFFFFh 960 kB Lower 15/16
0 0 0 1 0 0 thru 13 000000h – 0DFFFFh 896 kB Lower 7/8
0 0 0 1 1 0 thru 11 000000h – 0BFFFFh 768 kB Lower 3/4
0 0 1 0 0 0 thru 7 000000h – 07FFFFh 512 kB Lower 1/2
0 1 0 0 1 1 thru 15 010000h – 0FFFFFh 960 kB Upper 15/16
0 1 0 1 0 2 thru 15 020000h – 0FFFFFh 896 kB Upper 7/8
0 1 0 1 1 4 thru 15 040000h – 0FFFFFh 768 kB Upper 3/4
0 1 1 0 0 8 thru 15 080000h – 0FFFFFh 512 kB Upper 1/2
X X 1 1 1 None None None None
1 0 0 0 1 0 thru 15 000000h – 0FEFFFh 1,020 kB Lower 255/256
1 0 0 1 0 0 thru 15 000000h – 0FDFFFh 1,016 kB Lower 127/128
1 0 0 1 1 0 thru 15 000000h – 0FBFFFh 1,008 kB Lower 63/64
1 0 1 0 X 0 thru 15 000000h – 0F7FFFh 992 kB Lower 31/32
1 1 0 0 1 0 thru 15 001000h – 0FFFFFh 1,020 kB Upper 255/256
1 1 0 1 0 0 thru 15 002000h – 0FFFFFh 1,016 kB Upper 127/128
1 1 0 1 1 0 thru 15 004000h – 0FFFFFh 1,008 kB Upper 63/64
1 1 1 0 X 0 thru 15 008000h – 0FFFFFh 992 kB Upper 31/32
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 23
Data Sheet
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
7. Instructions
The instruction set of the S25FL004K, S25FL008K, and S25FL008K consist of thirty five basic instructions
that are fully controll ed through the SPI bus (see Table 7.3 to Table 7.5 on page 26). Instructions are initiated
with the falling edge of Chip Select (CS#). The first byte of data clocked into the SI input provides the
instruction code. Data on the SI input is sampled on the rising edge of clock with most significant bit (MSB)
first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge CS#. Clock relativ e timing diagrams for each instruction a re included in the fig ures belo w.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS# driven high after a full 8 bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Regis te r is being written, all instructions
except for Read Status Register will be ignored until the program or erase cycle has completed.
Table 6.7 S25FL016K Status Register Memory Protection (CMP = 1)
Status Register (1) S25FL016 K (16 Mbit) Memory Protection (2)
SEC TB BP2 BP1 BP0 Protected Block(s) Prot ect ed Addresses Protected
Density Protected Por tion (2)
X X 0 0 0 0 thru 31 000000h – 1FFFFFh All All
0 0 0 0 1 0 thru 30 000000h – 1EFFFFh 1,984 kB Lower 31/32
0 0 0 1 0 0 thru 29 000000h – 1DFFFFh 1,920 kB Lower 15/16
0 0 0 1 1 0 thru 27 000000h – 1BFFFFh 1,792 kB Lower 7/8
0 0 1 0 0 0 thru 23 000000h – 17FFFFh 1,536 kB Lower 3/4
0 0 1 0 1 0 thru 15 000000h – 0FFFFFh 1 MB Lower 1/2
0 1 0 0 1 1 thru 31 010000h – 1FFFFFh 1,984 kB Upper 31/32
0 1 0 1 0 2 and 31 020000h – 1FFFFFh 1,920 kB Upper 15/16
0 1 0 1 1 4 thru 31 040000h – 1FFFFFh 1,792 kB Upper 7/8
0 1 1 0 0 8 thru 31 080000h – 1FFFFFh 1,536 kB Upper 3/4
0 1 1 0 1 16 thru 31 100000h – 1FFFFFh 1 MB Upper 1/2
X X 1 1 X None None None None
1 0 0 0 1 0 thru 31 000000h – 1FEFFFh 2,044 kB Lower 511/512
1 0 0 1 0 0 thru 31 000000h – 1FDFFFh 2,040 kB Lower 255/256
1 0 0 1 1 0 thru 31 000000h – 1FBFFFh 2,032 kB Lower 127/128
1 0 1 0 X 0 thru 31 000000h – 1F7FFFh 2,016 kB Lower 63/64
1 1 0 0 1 0 thru 31 001000h – 1FFFFFh 2,044 kB Upper 511/512
1 1 0 1 0 0 thru 31 002000h – 1FFFFFh 2,040 kB Upper 255/256
1 1 0 1 1 0 thru 31 004000h – 1FFFFFh 2,032 kB Upper 127/128
1 1 1 0 X 0 thru 31 008000h – 1FFFFFh 2,016 kB Upper 63/64
24 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on
the SO pin.
2. The Status Register contents will repeat continuously until CS# terminates the instruction.
3. Quad Page Program Input Data: IO0 = (D4, D0, ……) IO1 = (D5, D1 , ……) IO2 = (D6, D2, ……) IO3 = (D7, D3, ……)
4. This instruction is recommended when using the Dual or Quad “Continuous Read Mode” feature. See Section 7.15 and Section 7.16
on page 40 for more information.
Table 7.1 Manufacturer Identification
Manufacturer ID Value
(MF7-MF0) EFh
Table 7.2 Device Identification
Device Density Device ID Instruction Value
S25FL004K (ID7-ID0) ABh, 90h, 92h, 94h 12h
(ID15-ID0) 9Fh 4013h
S25FL008K (ID7-ID0) ABh, 90h, 92h, 94h 13h
(ID15-ID0) 9Fh 4014h
S25FL016K (ID7-ID0) ABh, 90h 14h
(ID15-ID0) 9Fh 4015h
Table 7.3 Instruction Set (Erase, Program Instructions (1))
Instruction Name BYTE 1
(CODE) BYTE 2 BY TE 3 BYTE 4 BYTE 5 BYTE 6
Write Enable 06h
Write Enable for Volatile Status
Register 50h
Write Disable 04h
Read Status Register-1 05h (S7–S0) (2)
Read Status Register-2 35h (S15–S8) (2)
Write Status Register 01h (S7–S0) (S15–S8)
P age Program 02h A23–A16 A15–A8 A7–A0 (D7–D0)
Quad Page Program 32h A23–A16 A15–A8 A7–A0 (D7–D0, …) (3)
Sector Erase (4 kB) 20h A23–A16 A15–A8 A7–A0
Block Erase (32 kB) 52h A23–A16 A15–A8 A7–A0
Block Erase (64 kB) D8h A23–A16 A15–A8 A7–A0
Chip Erase C7h/60h
Erase / Progr am Sus pend 75h
Erase / Program Res ume 7Ah
Power-down
(S25FL004K/S25FL008K) B9h
Deep Power-down (S25FL016K) B9h
Continuous Read Mode Reset
(4) FFh FFh
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 25
Data Sheet
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address Set Burst with Wra p Input
IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x
IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x
IO2 = A22, A18, A14, A10, A6, A2 , M6, M2 IO2 = x, x, x, x, x, x, W6 x
IO3 = A23, A19, A15, A11, A7, A3 , M7, M3 IO3 = x, x, x, x, x, x, x, x
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0, …..)
IO1 = (x, x, x, x, D5, D1, …..)
IO2 = (x, x, x, x, D6, D2, …..)
IO3 = (x, x, x, x, D7, D3, …..)
6. Word Read Quad I/O Data
IO0 = (x, x, D4, D0, …..)
IO1 = (x, x, D5, D1, …..)
IO2 = (x, x, D6, D2, …..)
IO3 = (x, x, D7, D3, …..)
7. The lowest address bit must be 0. (A0 = 0)
8. The lowe st 4 address bits must be 0. (A0, A1, A2, A3 = 0)
Table 7.4 Instruction Set (Read Instructions)
Instruction Name BYTE 1
(CODE) BYTE 2 BY TE 3 BYTE 4 BYTE 5 BYTE 6
Read Data 03h A23–A16 A15–A8 A7–A0 (D7–D0)
Fast Read 0Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0)
Fast Read Dual Output 3Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0, …) (1)
Fast Read Quad Output 6Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0, …) (3)
Fast Read Dual I/O BBh A23–A8 (2) A7–A0, M7–M0
(2) (D7–D0, …) (1)
Fast Read Quad I/O EBh A23–A0,
M7–M0 (4) (x,x,x,x,
D7–D0, …) (5) (D7–D0, …) (3)
Word Read Quad I/O (7) E7h A23–A0,
M7–M0 (4) (x,x, D7–D0,
…) (6) (D7–D0, …) (3)
Octal Word Read Quad I/O (8) E3h A23–A0,
M7–M0 (4) (D7–D0, …) (3)
Set Burst with Wrap 77h xxxxxx,
W6–W4 (4)
26 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Notes:
1. The Device ID will repeat continuously until CS# terminates the instruction.
2. See Manufacturer and De vice Identification table for Device ID information.
3. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
7.1 Write Enable (06h)
The Write Enable instruction (Figure 7.1) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
The WEL bit must be set prior to every Page Program, Quad Page Program, Sec tor Erase, Block Erase, Chip
Erase, Write Status Register and Erase/Program Security Registers instruc tion. The Write Enable instru ction
is entered by driving CS# low, shiftin g the instruction code “06h” into the Data Input (SI) pin on the rising edge
of CLK, and then driving CS# high.
Figure 7.1 Write Enable Instruction Sequence Diagram
Table 7.5 Instruction Set (ID, Security Instructions)
Instruction Name BYTE 1
(CODE) BYTE 2 BY TE 3 BYTE 4 BYTE 5 BYTE 6
Release P o we r down / De vice ID
(S25FL004K/S25FL008K) ABh dummy dummy dummy (ID7-ID0) (1)
Release from Deep Power down
/ Device ID (S25FL016K) ABh dummy dummy dummy (ID7-ID0) (1)
Manufacturer/ Device ID (2) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0)
Manufacturer/Device ID by Dual
I/O 92h A23-A8 A7-A0, M[7:0]
(MF[7:0],
ID[7:0])
Manufacture/Device ID by Quad
I/O 94h A23-A0, M[7:0] xxxx, (MF[7:0],
ID[7:0]) (MF[7:0],
ID[7:0], …)
JEDEC ID 9Fh (MF7-MF0)
Manufacturer (ID15-ID8)
Memory Type (ID7-ID0)
Capacity
Read Unique ID 4Bh dummy dummy dummy dummy (ID63-ID0)
Read SFDP Register 48h, 5Ah 00h 00h A7-A0 dummy (D7-0)
Erase Security Registers (3) 44h A23-A16 A15-A8 A7-A0
Program Security Registers (3) 42h A23-A16 A15-A8 A7-A0 (D7-0) (D7-0)
Read Security Registers (3) 48h A23-A16 A15-A8 A7-A0 dummy (D7-0)
Instruction (06h)
CS#
CLK
SI
SOHigh Impedance
Mode 3
Mode 0
0 1 2 3 4 5 6 7
Mode 3
Mode 0
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 27
Data Sheet
7.2 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits describ ed in Section 6.1, Status Register on page 16 can also be written
to as volatile bits. This gives more flexibility to change th e system configuration and memory protection
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the
Status Register non-volatile bits. To write the volatile values into the Stat us Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction.
Write Enable for Volatile Status Register instruction (Figure 7.2) will not set the Write Enable Latch (WEL) bit,
it is only valid for the Write Status Register instruction to change the volatile Status Register bit values.
Figure 7.2 Write Enable for Volatile Status Register Instruction Sequence Diagram
7.3 Write Disable (04h)
The Write Disable instruction (Figure 6) resets the Write Ena ble Latch (WEL) bit in the Status Register to a 0.
The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the SI pin
and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion
of the Write Status Register, Erase/Program Se curity Registers, P age Progra m, Quad Page Program, Sector
Erase, Block Erase and Chip Erase instructions.
Figure 7.3 Write Disable Instruction Sequence Diagram
Instruction (50h)
CS#
CLK
SI
SOHigh Impedance
Mode 3
Mode 0
0 1 2 3 4 5 6 7
Mode 3
Mode 0
Instruction (04h)
CS#
CLK
SI
SOHigh Impedance
Mode 3
Mode 0
0 1 2 3 4 5 6 7
Mode 3
Mode 0
28 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.4 Read Status Register -1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving CS# low and shifting the instruction code “05h” for Status Register-1 or “35h” for Status Register-2
into the SI pin on the rising edge of CLK. The status register bits are then shifted out on the SO pin at the
falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.4. The Status Register bits are
shown in Figure 6.1 and Figure 6.2 and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1, QE,
LB3-1, CMP and SUS bits (see Section 6.1, Status Register on page 16).
The Read Status Register instruction may be used at any time, even while a Program, Era se or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is
complete and if the device can accept another instruction. The Status Register can be read continuously, as
shown in Figure 7.4. The instruction is completed by driving CS# high.
Figure 7.4 Read Statu s Register Instruction Sequence Diagram
7.5 Write Status Register (01h)
The Write Status Register instruction allows the Status Registe r to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2, LB1,
QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit locations are
read-only and will not be affected by the Write Status Register instruction. LB3-1 are non-volatile OTP bits;
once each is set to 1, it can not be cleared to 0. The Status Register bits are shown in Figure 6.1 and
Figure 6.2 on page 18, and described Section 6.1, Status Register on page 16.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must
equal 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code
“01h”, and then writing the status register data byte as illustrated in Figure 7.5.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have
been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,
SRP1 and LB3, LB2, LB1 can not be changed from 1 to 0 because o f the OTP prot ection for these bits. Upon
power off, the volatile Sta tus Register bit values will be lost, and the non-volatile Status Register bit values will
be restored when power on again.
To complete the Write Status Register instruction, the CS# pin must be driven high afte r the eighth or
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be
executed. If CS# is driven high after the eighth clock the CMP, QE and SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven high, the
self-timed Write Status Register cycle will commence fo r a time duration of tW (see Section 8.6, AC Electrical
Characteristics on page 64). While the Write Status Register cycle is in pro gress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write
Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After
the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.
Instruction (05h or 35h)
CS#
CLK
SI
SOHigh Impedance Status Register 1 or 2 Out
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
= MSB
Status Register 1 or 2 Out
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 29
Data Sheet
During volatile Status Register write operation (50h combined with 01h), after CS# is driven high, the Status
Register bits will be refreshed to the new values within the time period of tSHSL2 (see Section 8.6, AC
Electrical Characteristics on page 64). BUSY bit will remain 0 during the Status Register bit refresh period.
Refer to Section 6.1, Status Register on page 16 for detailed Status Register Bit de scriptions. Factory de fault
for all status Register bits are 0.
Figure 7.5 Write Status Register Instruction Sequence Diagram
7.6 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the SI pin. The code and address bits are latched on the rising edge of the CLK
pin. After the address is received, the data byte of the addressed memory loca tion will be shifted out on the
SO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allow ing for a continuous stre am
of data. This means that the entire memory can be accessed with a single instruction as long as the clock
continues. The instruction is completed by driving CS# high.
The Read Data instruction sequence is shown in Figure 7.6. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) th e instruc tion is ignored and will not hav e any effe cts
on the current cycle. The Read Data instruction allows clock rates from DC to a maximum of fR. (See AC
Electrical Characteristics on page 64.)
Figure 7.6 Read Data Instruction Sequence Diagram
CS#
CLK
SI
SO
= MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
Instruction (01h)
High Impedance
Status Register In
Mode 3
Mode 0
7 6 5 4 3 2 1 0 X 14 13 12 11 X 9 8
CS#
CLK
SI
SO
= MSB
Mode 3
Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction (03h)
High Impedance
24-Bit Address
Data Out 2Data Out 1
7 6 5 4 3 2 1 0 7
23 22 21 3 2 1 0
30 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.7 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR. (See AC Electrical Characteristics on page 64.) This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in Figure 7.7. The dummy clocks allow the devices
internal circuits additional time for setting up the initial address. During the dummy clocks the data value on
the SO pin is a “don’t care”.
Figure 7.7 Fast Read Instruction Sequence Diagram
= MSB
CS#
CLK
SI
SO
Mode 3
Mode 0
Instruction (0Bh) 24-Bit Address
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
23 22 21 3 2 1 0
CS#
CLK
SI
SO
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
Data Out 2Data Out 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 31
Data Sheet
7.8 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh ) instruction except that
data is output on two pins; IO0 and IO1. This allows data to be transferred from the S25FL004 K/S25FL008K/
S25FL016K at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for
quickly downloading code from Flash to RAM upon power-up or for app lications that cache code -segments to
RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR. (See AC Electrical Characteristics on page 64.) This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in Figure 7.8. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks is
“don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock.
Figure 7.8 Fast Read Dual Output Instruction Sequence Diagram
CS
CLK
IO0
IO1
Mode 3
Mode 0
Instruction (3Bh) 24-Bit Address
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
23 22 21 3 2 1 0
CS
CLK
IO0
IO1
= MSB
Data Out 2Data Out 1 Data Out 4Data Out 3
Dummy ClocksIO_0 Switches from Input to Output
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
6
32 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.9 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Out put (3Bh) instruction except
that data is output on four p ins, IO0, IO1, IO2, and IO3. A Quad enab le of Status Register-2 must be executed
before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1).
The Fast Read Quad Output Instruction allows data to be transferred from the S25FL0 04K/S25FL008K/
S25FL016K at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR. (See AC
Electrical Characteristics on page 64.) This is accomplished by adding eight “dummy” clocks after the 24-bit
address as shown in Figure 7.9. The dummy clocks allow the device's internal circuits additional time for
setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins
should be high-impedance prior to the falling edge of the first data out clock.
Figure 7.9 Fast Read Quad Output Instruction Sequence Diagram
CS
CLK
IO0
IO1
IO2
IO3
Instruction (6Bh) 24-Bit Address
23 22 21 3 2 1 0
CS
CLK
IO0
IO1
IO2
IO3
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy ClocksIO_0 Switches from Input to Output
4 0 4 0 4 0 4 0 4
5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6
7 3 7 3 7 3 7 3 7
Byte 1 Byte 2 Byte 3 Byte 4
Mode 3
Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 33
Data Sheet
7.10 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins,
IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the
Address bits (A23-0) two bits per c lock. This reduced instruction overhead may allow fo r code execution (XIP)
directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.10. The u pper nibble of the
(M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exc lusion of the
first byte instruction code. The lower nibble bits of the (M3-0) are don ’t care (“x”). However, the IO pins should
be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after CS# is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 7.11. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediat ely en tered after CS # is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instru ction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions. (See Continuous Read Mode Reset (FFh or FFFFh) on page 40.)
Figure 7.10 Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 10)
CS#
CLK
IO0
IO1
Instruction (BBh)
6 4 2 0 6 4 2 0 6 4 2 0 6 4
7 5 3 1 7 5 3 1 7 5 3 1
A23-16 A15-8A7-0 M7-0
7 5
CS#
CLK
IO0
IO1
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
IO Switches from Input to Output
Byte 1 Byte 2 Byte 3Byte 4
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0 Mode 3
Mode 0
34 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Figure 7.11 Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)
7.11 F ast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output throu gh four pins IO0, IO1, IO2 and IO3 and four Dummy clock are
required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status
Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.12, Fast Read Quad I/O
Instruction Sequence (Initial instruction or previous M5-4 ¹10) on page 35. The upper nibble of the (M7-4)
controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first
byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the EBh instruction code, as shown in Figure 7.13, Fast Read
Quad I/O Instruction Sequence (Previous instructio n set M5-4 = 10) on page 35 . This reduces the instruction
sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low.
If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is raised and
then lowered) requires the first byte ins truction code, thus re turning to norma l operation. A “Continuous Read
Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (see
Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page 40).
CS#
CLK
IO0
IO1
Mode 3
Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
6 4 2 0 6 4 2 0 6 4 2 0 6 4
7 5 3 1 7 5 3 1 7 5 3 1 7 5
A23-16 A15-8A7-0 M7-0
CS#
CLK
IO0
IO1
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
IO Switches from Input to Output
Byte 1 Byte 2 Byte 3Byte 4
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 35
Data Sheet
Figure 7.12 Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10)
Figure 7.13 Fast Read Quad I/O Instruction Sequence (Previous in struction set M5-4 = 10)
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a
“Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or
disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output
data starts at the initial address specified in the instruction, once it reaches the ending boundary of the
8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is
pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critica l address and then fill
the cache afterwards within a fixed length (8/1 6/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. See Section 7.14, Set Burst with Wrap (77h) on page 39.
CS#
CLK
IO0
IO1
IO2
IO3
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
IO Switches from
Input to Output
Instruction (EBh)
4 0 4 0 4 0 4 0 4 0 4 0 4
5 1 5 1 5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6 2 6 2 6
7 3 7 37 3 7 37 3 7 3 7
A23-16 A15-8A7-0 M7-0 Byte 1 Byte 2
Dummy Dummy
CS#
CLK
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
IO Switches from Input to Output
4 0 4 0 4 0 4 0 4 0 4 0 4
5 1 5 1 5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6 2 6 2 6
7 3 7 37 3 7 37 3 7 3 7
A23-16 A15-8A7-0 M7-0 Byte 1 Byte 2
Dummy Dummy
36 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.12 Word Read Quad I/O (E7h)
The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction ex cept that
the lowest Address bit (A0) must equal 0 and only two Dummy clock are re quired prior to the data output. The
Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP)
directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word
Read Quad I/O Instruction.
Word Read Quad I/O with “Continuous Read Mode”
The Word Read Quad I/O instruction can further redu ce instruction overhead through setting the “Contin uous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.14. The u pper nibble of the
(M7-4) controls the length of th e next Fast Read Quad I/O instruction through the inclusion or exclusion of the
first byte instruction code. The lower nibble bits of the (M3-0) are don ’t care (“x”). However, the IO pins should
be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the E7h instruction code, as shown in Figure 7.15. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediat ely en tered after CS # is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instru ction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page 40).
Figure 7.14 Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10)
CS#
CLK
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0 16 17 18 19 20 21 22 23
IO Switches from
Input to Output
Instruction (E7h)
4 0 4 0 4 0 4 0 4 0 4 0 4
4 0
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
7 3 7 37 3 7 37 3 7 3 7 3 7 3
A23-16 A15-8A7-0 M7-0 Byte 1 Byte 2
Dummy Byte 3
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 37
Data Sheet
Figure 7.15 Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Word Read Quad I/O instruction can also be used to access a spec ific portion within a page by issuing a
“Set Burst with Wrap” command prior to E7h. The “Set Burst with Wrap” command can either enable or
disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output
data starts at the initial address specified in the instruction, once it reaches the ending boundary of the
8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is
pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critica l address and then fill
the cache afterwards within a fixed length (8/1 6/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. See Section 7.14, Set Burst with Wrap (77h) on page 39.
7.13 Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not
required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read
Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce in struction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Addres s bits (A23-0), as shown in Figure 7.16, Octal
Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 ¹ 10) on page 38. The upper
nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O in struction through the
inclusion or exclusion of th e first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”).
However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the E3h instruction code, as shown in Figure 7.17, Octal Word
Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) on page 38. This reduces the
instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instru ction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page 40).
CS#
CLK
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
IO Switches from Input to Output
4 0 4 0 4 0 4 0 4 0 4 0 4
4 0
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
7 3 7 37 3 7 37 3 7 3 7 3 7 3
A23-16 A15-8A7-0 M7-0 Byte 1 Byte 2
Dummy Byte 3
38 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Figure 7.16 Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10)
Figure 7.17 Octal Word Read Quad I/O Instruction Sequence (Previou s instruction set M5-4 = 10)
CS#
CLK
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
IO Switches from Input to Output
Instruction (E3h)
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
7 3 7 37 3 7 37 3 7 3 7 3 7 3 7
A23-16 A15-8A7-0 M7-0 Byte 1 Byte 2
Dummy Byte 3
CS#
CLK
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
IO Switches from Input to Output
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
A23-16 A15-8A7-0 M7-0 Byte 1 Byte 2 Byte 3
7 3 7 37 3 7 37 3 7 3 7 3 7 3 7
Byte 4
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 39
Data Sheet
7.14 Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read
Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain
applications can benefit from this feature and improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the CS# pin low and
then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction
sequence is shown in Figure 7.18, Set Burst with Wrap Instruction Sequence on page 39. Wrap bit W7 and
the lower nibble W3-0 are not used.
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page.
To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap
instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case of a
system Reset while W4 = 0, it is recommended that the controller issues a Set Burs t with Wrap ins truction to
reset W4 = 1 prior to any normal Read in structions since S25F L004K/S25FL008K/S2 5FL016K does no t have
a hardware Reset Pin.
Figure 7.18 Set Burst with Wrap Instruction Sequence
7.15 Continuous Read Mode Bits (M7-0)
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad I/O”,
“Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random Flash
memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place) to be
performed on serial flash devices.
M7-0 need to be set by the Dual/Quad I/O Read instructions. M5-4 are used to control whether the 8-bit SPI
instruction code (BBh, EBh, E7h or E3h) is needed or not for the ne xt command. When M5-4 = (1,0), the ne xt
command will be treated same as the current Dual/Quad I/O Read command without needing the 8-bit
instruction code; when M5-4 do not equa l to (1,0), t he devic e re turns to normal SPI mode, all command s can
be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used.
W6, W5 W4 = 0 W4 =1 (DEFAULT)
Wrap Around Wrap Length Wrap Around Wrap Length
0 0 Yes 8-byte No N/A
0 1 Yes 16-byte No N/A
1 0 Yes 32-byte No N/A
1 1 Yes 64-byte No N/A
CS#
CLK
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
Instruction (77h)
X X X X X X w4 X
X X X X X X w5 X
X X X X X X w6 X
X X X X X X X X
don’t care don’t care don’t care wrap bit
40 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.16 Continuous Read Mode Reset (FFh or FFFFh)
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the
Continuous Read Mode and return to normal SPI operation, as shown in Figure 7.19.
Figure 7.19 Continuous Read Mode Reset for Fast Read Dual/Quad I/O
Since S25FL004K/S25FL008K/S25FL016K does not have a hardware Reset pin, so if the controller resets
while S25FL004K/S25FL008K/S25FL016K is set to Continuous Mode Read, the S25FL004K/S25FL008K/
S25FL016K will not recognize any initial standard SPI instructions from the controller. To address this
possibility, it is recommended to issue a Continuous Read Mode Reset instruction as the first instruction after
a system Reset. Doing so will release the device from the Continuous Read Mode and allow Standard SPI
instructions to be recognized.
To reset “Continuous Read Mode” during Quad I/O operation, only eigh t clocks are needed . The instruction is
“FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in
instruction “FFFFh”.
CS#
CLK
IO0
IO1
IO2
IO3
Mode 3
Mode 0
Don’t Care
Mode 3
Mode 0
Don’t Care
Don’t Care
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode Bit Reset
for Quad I/O Mode Bit Reset
for Quad I/O
FFh FFh
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 41
Data Sheet
7.17 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving
the CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least
one data byte, into the SI p in . The CS# pin must be held low for the entire length of the instruction while data
is being sent to the device. The Page Program instruction sequence is shown in Figure 7.20, Page Program
Instruction Sequence Diagram on page 41.
If an entire 256-byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not 0, and the number of clocks exceed the rema ining page
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial
page) can be programmed without having any effect on other bytes within the same page. One condition to
perform a partial page program is that the number of clocks can not exceed the remaining page length. If
more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and
overwrite previously sent data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After CS# is driven
high, the self-timed Page Program instruction will commence for a time duration of tPP. (See AC Electrical
Characteristics on page 64.) While the Page Program cycle is in progress, the Read Status Register
instruction may still be ac cessed for check ing the status of the BUSY bit. The BUSY b it is a 1 during the Page
Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Page Pro gram instruction will not be executed if the addressed page is pro tected
by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.
Figure 7.20 Page Program Instruction Sequence Diagram
CS#
CLK Mode 3
Mode 0
CS#
CLK
SI
Instruction (02h) 24-Bit Address Data Byte 1
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SI7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
= MSB
42 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.18 Quad Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased
(FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve
performance for PROM Programmer and applications that have slow clock speeds <5 MHz. Systems with
faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent
page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by dr iving the CS# pin low then shifting the instruction code
“32h” followed by a 24-bit address (A23-A0) and at least one data by te, into the IO pins. The CS# pin must be
held low for the entire length of the instruction while data is being sent to the device. All other functions of
Quad Page Program are identica l to standard Pa ge Progra m. The Quad Page Program instruction sequence
is shown in Figure 7.21, Quad Page Program Instruction Sequence Diagram on page 42.
Figure 7.21 Quad Page Program Instruction Sequence Diagram
CS#
CLK
IO0
IO1
IO2
IO3
Mode 3
Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction (32h) 24-Bit Address Byte 1 Byte 2 Byte 3Byte 4
23 22 21 3 2 1 0 4 0 4 0 4 0 4 0
5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 3
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
536
537
538
539
540
541
542
543
Mode 3
Mode 0
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
Byte 5 Byte 6 Byte 7 Byte 8Byte 9 Byte 10 Byte 11 Byte 12 Byte 253Byte 254Byte 255 Byte 256
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 37 3 7 3 7 3 7 37 3 7 3 7 3 7 3
CLK
IO0
IO1
IO2
IO3
CS#
= MSB
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 43
Data Sheet
7.19 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4k-bytes) to the erased state of all 1s
(FFh). A Write Enable instruction must be exe cuted before the device will accept the Sector Eras e Instruction
(Status Register bit WEL must equal 1 ). The instru ction is initia ted by driving th e CS# pin low a nd s hifting the
instruction code “20h” followed a 24- bit sector address (A 23-A0). (See Section 1., Block Diagrams on page 9
for the block diagrams of S25FL004K, S25FL0 08K, and S25FL016K.) The Sec tor Erase instruction sequence
is shown in Figure 7.22 on page 43.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After CS# is driven h igh, the self-timed Sector Erase instruc tion
will commence for a time duration of tSE. (See AC Electrical Characteristics on page 64.) While the Sector
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished
the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not
be executed if the addressed sector is protected by the Block Protec t (CMP, SEC, TB, BP2, BP1, and BP0)
bits (see Table 6.2, Table 6.3, and Table 6.4 for Status Register Memory Protection (CMP = 0)).
Figure 7.22 Sector Erase Instruction Sequence Diagram
CS#
CLK
Mode 3
Mode 0 Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 29 30 31
Instruction (20h) 24-Bit Address
23 22 2 1 0
High Impedance
SIO
SO
= MSB
44 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.20 32 KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32k-bytes) to the erased state of all 1s
(FFh). A Wr it e E n ab le in struction mu s t be ex e cuted before the device will accept the Block Erase Instruction
(Status Register bit WEL must equal 1 ). The instru ction is initia ted by driving th e CS# pin low a nd s hifting the
instruction code “52h” followed a 24-bit block address (A23-A0). (See Section 1., Block Diagrams on page 9
for the block diagrams of S25FL004K, S25FL008K,and S25FL016K.) The Block Erase instruction sequence
is shown in Figure 7.23.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE1. (See AC Electrical Characteristics on page 64.) While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed
if the addressed sector is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
Table 6.2, Table 6.3, and Table 6.4 for Status Register Memory Protection (CMP = 0)).
Figure 7.23 32 kB Block Erase Instruction Sequence Diagram
CS#
CLK
Mode 3
Mode 0 Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 29 30 31
Instruction (52h) 24-Bit Address
23 22 2 1 0
High Impedance
SIO
SO
= MSB
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 45
Data Sheet
7.21 64 KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64k-bytes) to the erased state of all 1s
(FFh). A Wr it e E n ab le in struction mu s t be ex e cuted before the device will accept the Block Erase Instruction
(Status Register bit WEL must equal 1 ). The instru ction is initia ted by driving th e CS# pin low a nd s hifting the
instruction code “D8h” followed a 24-bit block address (A23-A0). (See Section 1., Block Diagrams on page 9
for the block diagrams of S25FL004K, S25FL008K,and S25FL016K.) The Block Erase instruction sequence
is shown in Figure 7.24.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE. (See AC Electrical Characteristics on page 64.) While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed
if the addressed sector is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
Table 6.2, Table 6.3, and Table 6.4 for Status Register Memory Protection (CMP = 0)).
Figure 7.24 64 kB Block Erase Instruction Sequence Diagram
Mode 3
Mode 0 Mode 3
Mode 0
CS#
CLK
SI
SO
= MSB
Instruction (D8h) 24-Bit Address
High Impedance
23 22 2 1 0
0 1 2 3 4 5 6 7 8 9 29 30 31
46 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.22 Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register
bit WEL must equal 1). The instruc tion is initiated by driving the CS# pin low and shifting the instruction code
“C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 7.25.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be ex ecuted. After CS# is driv en hig h, the self-timed Chip Erase instruc tion will commence
for a time duration of tCE. (See AC Electrical Characteristics on page 64.) While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be acces sed to check the status of the BUSY bit. The
BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the devic e is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instru ction will not be executed if any p age is protected by the
Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Table 6.2, Table 6.3, and Table 6.4 for Status
Register Memory Protection (CMP = 0)).
Figure 7.25 Chip Erase Instruction Sequence Diagram
Mode 3
Mode 0 Mode 3
Mode 0
CS#
CLK
SI
SO
Instruction (C7h/60h)
High Impedance
0 1 2 3 4 5 6 7
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 47
Data Sheet
7.23 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction 75h, allows the system to interrupt a Sector or Block Erase operation
or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The
Erase/Program Suspend instruction sequence is shown in Figure 7.26, Erase/Program Suspend Instruction
Sequence on page 47.
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h , 44h) are not
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operatio n, the Erase Suspend instruction is ignored. The Write Status Register
instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend.
Program Suspend is valid only during the Page Program or Quad Page Program operation.
The Erase/Program Suspend instruction 75h will be accepted by the device only if the SUS bit in the Status
Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation
is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by
the device. A maximum of time of tSUS (Section 8.6, AC Electrical Characteristics on page 64) is required to
suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0
within tSUS and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program
Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspe nd instruction
75h is not issued earlier than a minimum of time of tSUS following the preceding Resume instruction 7Ah.
Unexpected power off during the Erase/Prog ram suspend sta te will reset the device and release the suspend
state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was
being suspended may become corrupted. It is recommended for the user to implement system design
techniques against the accidental power interruption and preserve data integrity during erase/program
suspend state.
Figure 7.26 Erase/Program Suspend Instruction Sequence
CS#
CLK
SI
SO
Instruction (75h)
High Impedance
Mode 3
Mode 0 Mode 3
Mode 0
0 1 2 3 4 5 6 7
Accept Read or Program Instruction
t
SUS
48 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.24 Erase / Program Resume (7Ah)
The Erase/Program Resume instruction “7Ah” must be written to resu me the Sector or Block Erase operation
or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be
accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0.
After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within
200 ns and the Sector or Block will complete the erase operation or the page will complete the program
operation. If the SUS bit equals to 0 or the BUSY bit equa ls to 1, the Resume instruction “7Ah” will be igno red
by the device. The Erase/Program Resume instruction sequence is shown in Figure 7.27.
Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by
unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be
issued within a minimum of time of “tSUS” following a previous Resume instruction.
Figure 7.27 Erase/Program Resume Instruction Sequence
CS#
CLK
SI
Instruction (7Ah)
Mode 3
Mode 0
0 1 2 3 4 5 6 7
Resume Sector or Block Erase
Mode 3
Mode 0
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 49
Data Sheet
7.25 Deep Power-down (B9h)
Although the standby cu rrent during normal operation is relatively low, standby current can be further redu ced
with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down
instruction especially useful for battery powered applications (see ICC1 and ICC2 in Section 8.4, DC Electrical
Characteristics on page 63). The instruction is initiated by driving the CS# pin low and shifting the instruction
code “B9h” as shown in Figure 7.28.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power-
down instruction will not be executed. After CS# is driven high, the power-down state will entered within the
time duration of tDP. (See AC Electrical Characteristics on page 64.) While in the power-down state only the
Release from Deep Power-down / Device ID instruction, which restores the device to normal operation, will
be recognized. All other instructions are ignored. This inclu des the Read Sta tus Register instru ctio n, which is
always available during normal operation. Ignoring all but one instruction makes the Power Down state a
useful condition for securing maximum write pro tection. The device always powers-up in the normal operation
with the standby current of ICC1.
Figure 7.28 Deep Power-down Instruction Sequence Diagram
CS#
CLK
SI
Mode 3
Mode 0 Mode 3
Mode 0
0 1 2 3 4 5 6 7 tDP
Instruction (B9h)
Standard Current Deep Power-down Current
50 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.26 Release from Deep Power-down / Device ID (ABh)
The Release from Deep Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the deep power-down state, or obtain the devices electronic identification (ID)
number.
To release the device from the deep power-down state, the instructio n is issued by dr iving the CS# pin low,
shifting the instruction code “ABh” and driving CS# high as shown in Figure 7.29. Release from deep power-
down will take the time duration of tRES1 (Section 8.6, AC Electrical Characteristics on page 64) before the
device will resume normal operation and other instructions are accepted. The CS# pin must remain high
during the tRES1 time duration.
When used only to obtain the Device ID while not in the deep power-down state, the instruction is initiated by
driving the CS# pin low and sh ifting the instruction co de “ABh” followed by 3-dummy b ytes. The Device ID b its
are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID values for
the S25FL004K/S25FL008K/S25FL016K is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The instruction is completed by driving CS# high.
When used to release the device from the deep power-down state and obtain the Device ID, the instruction is
the same as previously described, and shown in Figure 7.30, except that after CS# is driven high it must
remain high for a time duration of tRES2. After this time duration the device will resume normal operation and
other instructions will be accepted. If the Release from Deep Power-down / Device ID instruction is issued
while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will
not have any effects on the current cycle.
Figure 7.29 Release from Deep Power-down Instruction Sequence
Figure 7.30 Release from Deep Power-down / Device ID Instruction Sequence Diagram
CS#
CLK
SI
SO
Instruction (ABh)
High Impedance
Mode 3
Mode 0 Mode 3
Mode 0
0 1 2 3 4 5 6 7
Stand-by Current
t
RES1
Deep Power-down Current
CS#
CLK
SI
SO
Instruction (ABh)
High Impedance
Mode 3
Mode 0 Mode 3
Mode 0
3 Dummy BytestRES2
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
= MSB
23 22 21 3 2 1 0
7 6 5 4 3 2 1 0
Device ID
Deep Power-down Current Stand-by Current
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 51
Data Sheet
7.27 Read Manu facturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Deep Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Deep Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code “90h”
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID and the Device ID are
shifted out on the falling edge of CLK with most significant bit (MSB) firs t as shown in Figure 7.31. The Device
ID values for the S25FL004K/S25FL008K/S 25FL016K is listed in Table 7.2, Device Identification o n page 24.
If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read contin uously, alternating from one to the
other. The instruction is completed by driving CS# high.
Figure 7.31 Read Manufacturer / Device ID Diagram
CS#
CLK
SI
SOHigh Impedance
Mode 3
Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Instruction (90h) Address (000000h)
23 22 21 3 2 1 0
CS#
CLK
SI
SOManufacturer ID Device ID ( )
7 6 5 4 3 2 1 0
Mode 3
Mode 0
= MSB
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
52 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.28 Read Manu facturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device
ID instruction that provides both the JEDEC a ssigned man ufacture r ID and the specific device ID at 2x speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The
instruction is initiated by driving the CS# pin low and shifting the instruction code “92h” followed by a 24-bit
address (A23-A0) of 000000h, bu t with the capa bility to in put the Address bits two bits per clock. After w hich,
the Manufacturer ID and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most
significant bits (MSB) first as shown in Figure 7.32. The Device ID values for the S25FL004K/S25FL008K/
S25FL016K is listed in Table 7.2, Device Identification on page 24. If the 24-bit address is initially set to
000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and
Device IDs can be read continuously, alternating from one to the other. The instruction is completed by
driving CS# high.
Figure 7.32 Read Manufacturer / Device ID Dual I/O Diagram
Note:
1. The “Continuous Read Mode” bi ts M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.
CS#
CLK
IO1
IO0
CS#
CLK
IO1
IO0
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 53
Data Sheet
7.29 Read Manu facturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device
ID instruction that provides both the JEDEC a ssigned man ufacture r ID and the specific device ID at 4x speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. The
instruction is initiated by driving the CS# pin low and shifting the instruction code “94h” followed by a four
clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with the capability to input the
Address bits four bits per clock. After which, the Manufacturer ID and the Device ID are shifted out four bits
per clock on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.33. The Device
ID values for the S25FL004K/S25FL008K/S 25FL016K is listed in Table 7.2, Device Identification o n page 24.
If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read contin uously, alternating from one to the
other. The instruction is completed by driving CS# high.
Figure 7.33 Read Manufacturer / Device ID Quad I/O Diagram
Note:
1. The “Continuous Read Mode” bi ts M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.
CS#
CLK
IO1
IO0
IO3
IO2
CS#
CLK
IO1
IO0
IO3
IO2
54 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.30 Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to
each S25FL004K/S25FL008K/S25FL016K device. The ID number can be used in conjunction with user
software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated
by driving the CS# pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks.
After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in Figure 7.34.
Figure 7.34 Read Unique ID Number Instruction Sequence
**
CS#
CLK
SI
SOHigh Impedance
Instruction (4B) Dummy 1 Dummy 2
Mode 3
Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS#
CLK
SI
SO
= MSB
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 101 102 103
Dummy 3Dummy 4 64-bit Unique Serial Number
Mode 3
Mode 0
63 62 61 60 59 2 1 0
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 55
Data Sheet
7.31 Read JEDEC ID (9Fh)
For compatibility reasons, the S25FL004K/S25FL008K/S25FL 016K provides several instructions to
electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the
JEDEC standard for SPI compatible serial flash memories that was adopted in 2003. The instruction is
initiated by driving the CS# pin low and shifting the instruction code “9Fh”. The JEDEC assigned
Manufacturer ID byte and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then
shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.35. For
memory type and capacity values refer to Manufacturer and Device Identification table.
Figure 7.35 Read JEDEC ID Instruction Sequence
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CS#
CLK
SI
SO
Mode 3
Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction (9Fh)
High Impedance
Manufacturer ID (EFh)
CS#
CLK
SI
SO
Mode 3
Mode 0
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Memory Type ID15-ID8Capacity ID7-ID0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
= MSB
56 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.32 Read SFDP Register (5Ah)
The S25FL004K/S25FL008K/S25FL016K features a 256-byte Serial Flash Discoverable Parameter (SFDP)
register that contains information about devices operational capability such as available commands, timing
and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables.
Currently only one PID table is specified but more may be added in the future. The Read SFDP Register
instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications.
The Read SFDP instruction is initiated by driving the CS# pin low and shifting the instruction code “5Ah”
followed by a 24-bit address (A23-A0)(1) into the SI pin. Eight “dummy” clocks are also required before th e
SFDP register contents are shifted out o n the fa lling edge of the 40th CLK wi th most significant bit (MSB) first
as shown in Figure 7.36. For SFDP register values and descriptions, refer to Table 7.6.
Note: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-byte SFDP Register.
Figure 7.36 Read SFDP Register Instruction Sequence Diagram
Table 7.6 Serial Flash Discoverable Parameter Definition Table (Sheet 1 of 2)
Byte Address Data Description Comment
00h 53h SFDP Signature
SFDP Signature = 50444653h
01h 46h SFDP Signature
02h 44h SFDP Signature
03h 50h SFDP Signature
04h 01h SFDP Minor Revisions SFDP revision 1.1
05h 01h SFDP Major Revisions
06h 00h Number of Parameter Headers (NPH) 1 Parameter Header
07h FFh Reserved
08h EFh PID (3)(0): Manufacturer JEDE C ID EFh
09h 00h PID(0): Serial Flash Basics Minor Revisions Serial Flash Basics Revision 1.0
0Ah 01h PID(0): Serial Flash Basics Major Revisions
CS#
CLK
SI
SO
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Instruction (5Ah) 24-bit Address
23 22 21 3 2 1 0
CS#
CLK
SI
SO
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
Data Out 1 Data Out 2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
= MSB
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 57
Data Sheet
Notes:
1. Data stored in Byte Address 18h to 7Fh and 90h to FFh are Reserved, the value is FFh.
2. 1 Dword = 4 by tes.
3. PID(x) = P arameter Identification Table (x).
0Bh 04h PID(0): Serial Flash Basics Length 4 Dwords (2)
0Ch 80h PID(0): Address of Pa rameter ID(0) Table (A7-A0)
PID(0) Table Address = 000080h0Dh 00h PID(0): Address of Pa rameter ID(0) Table (A15-A8)
0Eh 00h PID(0): Address of Parameter ID(0) Table (A23-A16)
0Fh FFh Reserved
10h EFh PID(1): Manufacturer JEDEC ID EFh
11h 00h PID(1): Serial Flash Properties Minor Revisions Serial Flash Properties Revision 1.0
12h 01h PID(1): Serial Flash Properties Major Revisions
13h 00h PID(1): Serial Flash Properties Length 00h = Unimplemented
14h 90h PID(1): Address of Parameter ID(1) Table (A7-A0)
PID(1) Table Address = 000090h15h 00h PID(1): Address of Parameter ID(1) Table (A15-A8)
16h 00h PID(1): Address of Parameter ID(1) Table (A23-A16)
17h FFh Reserved
... (1) FFh Reserved
80h E5h
Bit[7:5] = 111 Reserved
Bit[4:3] = 00 Non-volatile Status Reg ist er
Bit[2] = 1 Page Programmable
Bit[1:0] = 01 Supports 4 kB Erase
81h 20h 4 kbyte Erase Opcode
82h F1h
Bit[7] = 1 Reserved
Bit[6] = 1 Supports Single Input Quad Output
Bit[5] = 1 Supports Quad Input Quad Output
Bit[4] = 1 Supports Dual Input Dual Output
Bit[3] = 0 Dual Transfer Rate not Supported
Bit[2:1] = 00 3-byte/24-bit Addressing
Bit[0] = 1 Supports Single Input Dual Output
83h FFh Reserved
84h FFh Flash Size in Bits
4 Megabits = 003FFFFFh (S25FL004K)
8 Megabits = 007FFFFFh (S25FL008K)
16 Megabits = 00FFFFFFh (S25FL016K)
85h FFh Flash Size in Bits
86h
3Fh
(S25FL004K)
7Fh
(S25FL008K)
FFh
(S25FL016K)
Flash Size in Bits
87h 00h Flash Size in Bits
88h 44h
Bit[7:5] = 010 8 Mode Bits are needed
Bit[4:0] = 00100 16 Dummy Bits are needed Fast Read Quad I/O Setting
89h EBh Quad Input Quad Output Fast Read Opcode
8Ah 08h
Bit[7:5] = 000 No Mode Bits are needed
Bit[4:0] = 01000 8 Dummy Bits are needed Fast Read Quad Output Setting
8Bh 6Bh Single Input Quad Output Fast Read Opcode
8Ch 08h
Bit[7:5] = 000 No Mode Bits are needed
Bit[4:0] = 01000 8 Dummy Bits are needed Fast Read Dual Output Setting
8Dh 3Bh Single Input Dual Output Fast Read Opcode
8Eh 80h
Bit[7:5] = 100 8 Mode bits are needed
Bit[4:0] = 00000 No Dummy bits are needed Fast Read Dual I/O Setting
8Fh BBh Dual Input Dual Output Fast Read Opcode
... (1) FFh Reserved
FFh FFh Reserved
Table 7.6 Serial Flash Discoverable Parameter Definition Table (Sheet 2 of 2)
Byte Address Data Description Comment
58 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.33 Erase Security Registers (44h)
The S25FL004K/S25FL008K/S25FL016K offers three 256-byte Security Registers which can be erased and
programmed individually. These registers may be used by the system manufa cturers to store secur it y and
other important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction
must be executed before the device will accept the Erase Security Register Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.
The Erase Security Register instruction sequence is shown in Figure 7.37. The CS# pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After CS# is driven high, the self-timed Erase Security Register operation will commence for a time duration
of tSE (see AC Electrical Characteristics on page 64). While the Erase Security Register cycle is in progre ss,
the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY
bit is a 1 during th e erase cy cle and b ecomes a 0 wh en the cycle is finished and the device is ready to accep t
other instructions again. After the Era se Security Register cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cle ared to 0. The Security R egister Lock Bits (LB3:1) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will
be permanently locked, and an Erase Security Register instruction to that register will be ignored (see
Security Register Lock Bits (LB3, LB2, LB1) on page 17).
Figure 7.37 Erase Security Registers Instruction Sequence
Address A23-16 A15-12 A11-8 A7-0
Security Register #1 00h 0 0 0 1 b 0 0 0 0 b Don’t Care
Security Register #2 00h 0 0 1 0 b 0 0 0 0 b Don’t Care
Security Register #3 00h 0 0 1 1 b 0 0 0 0 b Don’t Care
= MSB
CS#
CLK
SI
SO
0 1 2 3 4 5 6 7 8 9 29 30 31
Instruction (44h) 24-bit Address
Mode 3
Mode 0
Mode 3
Mode 0
23 22 2 1 0
High Impedance
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 59
Data Sheet
7.34 Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte
to 256 bytes of security register dat a to be programmed at previously erased (FFh) memory locations. A Write
Enable instruction must be executed before the device will accept the Program Security Register Instruction
(Status Register bit WEL= 1). The instruction is initiated by driving the CS# pin low then shifting the ins truction
code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the SI pin. The CS# pin
must be held low for the entire length of the instruction while data is being sent to the device.
The Program Security Registe r instruction sequence is shown in Figure 7.38. The Security Register Lock Bits
(LB3:1) in the Status Register-2 can be us ed to OTP pro tec t the secu rity regi sters. Once a lock bit is s et to 1,
the corresponding security register will b e permanently locked, and a Program Security Register instruction to
that register will be ignored (see Security Register Lock Bits (LB3, LB2, LB1) on page 17 and Page Progra m
(02h) on page 41 for detail descriptions).
Figure 7.38 Program Security Registers Instruction Sequence
Address A23-16 A15-12 A11-8 A7-0
Security Register #1 00h 0 0 0 1 b 0 0 0 0 b Byte Address
Security Register #2 00h 0 0 1 0 b 0 0 0 0 b Byte Address
Security Register #3 00h 0 0 1 1 b 0 0 0 0 b Byte Address
CS#
CLK
SI
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction (42h) 24-bit Address
Mode 3
Mode 0
Data Byte 1
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
= MSB
CS#
CLK
SI
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3
Mode 0
Data Byte 2 Data Byte 3Data Byte 256
2072
2073
2074
2075
2076
2078
2077
2079
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
60 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
7.35 Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the three security registers. The instruction is initiated by driving the
CS# pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight
“dummy” clocks into the SI pin. The code and addres s bits are latched on the rising ed ge of the CLK pin. After
the address is received, the data byte of the addressed memory location will be shifted out on th e SO pin at
the falling edge of CLK with most signi ficant bit (MSB) first. Th e byte ad dress is au toma tically increme nted to
the next byte address after eac h byte of data is shifted out. Once the byte address r eaches the last byte of the
register (byte FFh), it will reset to 00h, the first byte of the register, and continue to increment. The instruction
is completed by driving CS# high. The Read Security Register instruction sequence is shown in Figure 7.39.
If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process
(BUSY=1), the instruction is ignored and will not have any effects on the current cycle. The Read Security
Register instruction allows clock rates from DC to a maximum of FR (see Section 8.6, AC Electrical
Characteristics on page 64).
Figure 7.39 Read Security Registers Instruction Sequence
Address A23-16 A15-12 A11-8 A7-0
Security Register #1 00h 0 0 0 1 b 0 0 0 0 b Byte Address
Security Register #2 00h 0 0 1 0 b 0 0 0 0 b Byte Address
Security Register #3 00h 0 0 1 1 b 0 0 0 0 b Byte Address
CS#
CLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Mode 3
Mode 0
Instruction (48h) 24-bit Address
23 22 21 3 2 1 0
CS#
CLK
SI
SO
Dummy Byte
Data Out 1 Data Out 2
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
= MSB
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 61
Data Sheet
8. Electrical Characteristics
8.1 Absolute Maximum Ratings
Notes:
1. This de vice has been designed and tested for the specified operation ranges. Proper operation outside of thes e levels is not guaranteed.
Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent
damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and t he European directive on
restrictions on hazardous subst ances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
8.2 Operating Ranges
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write)
voltage.
8.3 Power-Up Timing and Write Inhibit Threshold
Note:
1. These parameters are characterized only.
Parameters(1) Symbol Conditions Range Unit
Supply Vo ltage VCC –0.6 to +4.0
V
Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V
Transient Voltage on any Pin VIOT <20 ns Transient Relative to Ground –2.0V to VCC+2.0V V
Storage Temperature TSTG –65 to +150 °C
Lead Temperature TLEAD (Note 2) °C
Electrostatic Discharge Voltage VESD Human Body Model (3) –2000 to +2000 V
Parameter Symbol Conditions Spec Unit
S25FL004K S25FL008K S25FL016K Min Max
Supply Voltage (1) VCC
FR = 104 MHz
fR = 50 MHz
FR = 104 MHz
fR = 50 MHz
FR = 104 MHz 3.0 3.6 V
FR = 80 MHz
fR = 50 MHz FR = 80 MHz
fR = 50 MHz FR = 70 MHz
fR = 50 MHz 2.7
Ambient Temperature,
Operating TA Industrial –40 +85 °C
Parameter Symbol Spec Unit
Min Max
VCC (min) to CS# Low tVSL (1) 10 µs
Time Delay Before Write Instruction tPUW (1) 1 10 ms
Write Inhibit Threshold Voltage VWI (1) 1.0 2.0 V
62 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Figure 8.1 Power-Up Timing and Voltage Levels
VCC
VCC (max)
VCC (min)
VWI
Time
Reset
State
Read instructions
allowed Device is fully
accessible
Program, Erase, and Write instructions are ignored
CS# must trac k VCC
tPUW
tVSL
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 63
Data Sheet
8.4 DC Electrical Characteristics
Notes:
1. Tested on sample basis and spec ified through design and chara ct erization d ata. TA = 25°C, VCC = 3V.
2. Checker Board Pattern.
8.5 AC Measurement Conditions
Note:
1. Output High-Z is defined as the point where data out is no longer driven.
Parameter Symbol Conditions Spec Unit
Min Typ Max
Input Capacitance CIN (1) VIN = 0V (1) 6 pF
Output Capacitance COUT (1) VOUT = 0V (1) 8 pF
Input Leakage ILI ±2 µA
I/O Leakage ILO ±2 µA
Standby Current
(S25FL004K/ S25FL008K) ICC1 CS# = VCC, VIN = GND or VCC 25 50 µA
Standby Current (S25FL016K) 10 25
Power-down Current ICC2 CS# = VCC, VIN = GND or VCC 1 5 µA
Deep Power-down Current (S25FL016K) ICC2 CS# = VCC, VIN = GND or VCC 1 5 µA
Current: Read Data / Dual /Quad 1 MHz
(2) ICC3 C = 0.1 VCC / 0.9 VCC
SO = Open 4/5/6 6/7.5/9 mA
Current: Read Data / Dual /Quad 33 MHz
(2) ICC3 C = 0.1 VCC / 0.9 VCC
SO = Open 6/7/8 9/10.5/12 mA
Current: Read Data / Dual Output Read/
Quad Output read 50 MHz (2)
(S25FL004K) ICC3 C = 0.1 VCC / 0.9 VCC
SO = Open 7/8/9 10/12/13.5 mA
Current: Read Data / Dual /Quad 50 MHz
(2) (S25FL008K/S25FL016K)
Current: Read Data / Dual Output Read/
Quad Output Read 80 MHz (2) ICC3 C = 0.1 VCC / 0.9 VCC
SO = Open 10/11/12 15/16.5/18 mA
Current: Write Status Register
(S25FL004K/S25FL008K) ICC4 CS# = VCC
812
mA
Current: Write Status Register
(S25FL016K) 10 15
Current Page Program ICC5 CS# = VCC 20 25 mA
Current Sector/Block Erase ICC6 CS# = VCC 20 25 mA
Current Chip Erase ICC7 CS# = VCC 20 25 mA
Input Low Voltage VIL V
CC x 0.3 V
Input High Voltage VIH V
CC x 0.7 V
Output Low Voltage VOL I
OL = 100 µA 0.2 V
Output High Voltage VOH I
OH = –100 µA VCC – 0.2 V
Parameter Symbol Spec Unit
Min Max
Load Capacitance CL 30 pF
Input Rise and Fall Times TR, TF 5 ns
Input Pulse Voltages VIN 0.2 VCC to 0.8 VCC V
Input Timing Reference Voltages IN 0.3 VCC to 0.7 VCC V
Output Timing Reference Voltages OUT 0.5 VCC to 0.5 VCC V
64 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Figure 8.2 AC Measurement I/O Waveform
8.6 AC Electrical Characteristics
Input Levels
0.8 VCC
0.2 VCC
0.5 VCC
Input and Output
Timing Reference Levels
Table 8.1 AC Electrical Characteristics (Sheet 1 of 2)
Description Symbol Alt Spec Unit
Min Typ Max
Clock frequenc y f or all instructions ex cept f or Read Data
instruction (03h)
3.0V-3.6V VCC and Industrial Temperature (S25FL004K)
FRfCD.C.
104
MHz
Clock frequency for Sing le/Dual SPI instructions exc ept
for Read Data instruction (03h)
3.0V-3.6V VCC and Industrial Temperature (S25FL008K)
Clock frequency for all instructions except Read data
(03h) and Octal W ord Read(E3h) 2.7V-3.6V / 3.0V-3.6V
(S25FL0016K)80 / 104
Clock frequenc y f or all instructions ex cept f or Read Data
instruction (03h)
2.7V-3.6V VCC and Industrial Temperature
(S25FL004K/ S25FL008K) FRfCD.C.
80 MHz
Clock frequency for Octal Word Read Quad I/O (E3h)
3.0V-3.6V (S25FL0016K)50
Clock frequency for Read Data instruction (03h) fR D.C. 50 MHz
Clock High, Low Time for all instructions except Read
Data (03h) (S25FL004K) tCLH1, tCLL1 (1) tCH, tCL
6
ns
Clock High, Low Time except Read Data (03h)
(S25FL008K) 4
Clock High, Low Time except Read Data (03h)
(S25FL016K) tCLH, tCLL (1) 6
Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL (1) 8 ns
Clock Rise Time peak to peak tCLCH (2) 0.1 V/ns
Clock Fall Time peak to peak tCHCL (2) 0.1 V/ns
CS# Active Setup Time relative to CLK tSLCH t
CSS 5 ns
CS# Not Active Hold Time relative to CLK tCHSL 5 ns
Data In Setup Time tDVCH t
DSU 2 ns
Data In Hold Time tCHDX t
DH 5 ns
CS# Active Hold Time relative to CLK tCHSH 5 ns
CS# Not Active Setup Time relative to CLK tSHCH 5 ns
CS# Deselect Time (for Array Read -> Array Read) tSHSL1 t
CSH 10 ns
CS# Deselect Time (for Erase or Progr am -> Read
Status Registers)
Volatile Status Register Write Time tSHSL2 t
CSH 50
50 ns
Output Disable Time tSHQZ (2) tDIS 7 ns
Clock Low to Output Valid
(S25FL004K) tCLQV1 t
V1
7ns
Clock Low to Output Valid 2.7V-3.6V / 3.0V-3.6V
(S25FL008K/S25FL016K) 7 / 6
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 65
Data Sheet
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint f or a Write Status Register instruction when Sector Protec t bit is set to 1.
4. F or multiple byt es after first by te within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of
bytes programmed.
5. Max Value tSE with <50k cycles is 200 ms and >50k and <100k cycles is 400 ms.
Clock Low to Output Valid (for Read ID instructions)
(S25FL004K) tCLQV2 t
V2
7.5
ns
Clock Low to Output Valid (for Read ID instructions)
2.7V-3.6V / 3.0V-3.6V
(S25FL008K/S25FL016K) 8.5 / 7.5
Output Hold Time tCLQX t
HO 0 ns
HOLD# Active Setup Time relative to CLK tHLCH 5 ns
HOLD# Active Hold Time relative to CLK tCHHH 5 ns
HOLD# Not Active Setup Time relative to CLK tHHCH 5 ns
HOLD# Not Active Hold Time relative to CLK tCHHL 5 ns
HOLD# to Output Low-Z tHHQX (2) tLZ 7 ns
HOLD# to Output High-Z tHLQZ (2) tHZ 12 ns
Write Protect Setup Time Before CS# Low tWHSL (3) 20 ns
Write Protect Hold Time After CS# High tSHWL (3) 100 ns
CS# High to Power-down Mode tDP (2) 3 µs
CS# High to Standb y Mode without Electronic Signature
Read tRES1 (2) 3 µs
CS# High to Standby Mode with Electronic Signature
Read tRES2 (2) 1.8 µs
CS# High to nex t Ins truction after Suspend tSUS (2) 20 µs
Write Status Register Time tW 10 15 ms
Byte Program Tim e (F i r st Byte) (4)
(S25FL004K) tBP1 20 50 µs
Byte Program Tim e (F i r st Byte) (4)
(S25FL008K/S25FL016K) 30
Additional Byte Program Time (After First B yt e) (4) tBP2 2.5 12 µs
Page Program Time tPP 0.7 3 ms
Sector Erase Time (4 kB) tSE 30
200/400
(5) ms
Block Erase Time (32 kB) tBE1 120 800 ms
Block Erase Time (64 kB) tBE2 150 1,000 ms
Chip Erase Time
(S25FL004K)
tCE
14
s
Chip Erase Time
(S25FL008K) 26
Chip Erase Time
(S25FL016K) 310
Table 8.1 AC Electrical Characteristics (Sheet 2 of 2)
Description Symbol Alt Spec Unit
Min Typ Max
66 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
8.7 Serial Output Timing
Figure 8.3 Serial Output Timing
8.8 Serial Input Timing
Figure 8.4 Serial Input Timing
8.9 Hold Timing
Figure 8.5 Hold Timing
*SIO is an output only for the fast read dual output instructions (3Bh)
CS#
CLK
SO/SIO* LSB Out
t
CLQX
t
CLQV
t
CLQX
t
CLQV
t
CLH
t
CLL
t
QLQH
t
QHQL
t
SHQZ
CS#
CLK
SIO
SO
(High Impedance)
MSB IN LSB IN
tCHSLtSLCH
tDVCH tCHDX
tCHSHtSHCH
tCLCH tCHCL
tSHSL
CS#
CLK
SIO
SO
HOLD#
tHLCH tHHCH
tHHQX
tCHHH
tHLQZ
tCHHL
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 67
Data Sheet
9. Physical Dimensions
9.1 SOA008 narrow — 8-pin Plastic Small Outline Package (150-mils Body Width)
PACKAGE SOA 008 (inches)SOA 008 (mm)
JEDEC MS-012(D)AA MS-012(D)AA
SYMBOL MIN MAX MIN MAX
A 0.0531 0.0688 1.35 1.75
A1 0.0039 0.00980.10 0.25
A2 0.052 0.061 1.32 1.55
b0.012 0.020 0.31 0.51
b1 0.011 0.019 0.27 0.48
c 0.0067 0.00980.17 0.25
c1 0.0067 0.009 0.17 0.23
D 0.193 BSC 4.90 BSC
E 0.236 BSC 6.00 BSC
E1 0.1535 BSC 3.90 BSC
e .050 BSC 1.27 BSC
L 0.0161 0.035 0.41 0.89
L1 .041 REF 1.04 REF
L2 .010 BSC 0.25 BSC
N 8 8
h 0.10 0.196 0.25 0.50
θ0˚ 8˚0˚8˚
θ1 5˚ 15˚ 5˚ 15˚
θ2 0˚ 0˚
3528 \ 16-038.03 \ 11.02.05
NOTES:
1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
.
9
C
A
A1
A2
b
e
5
B
D
E
E/2
5
E1/2
43E1
3
SEATING PLANE
4
D
A
0.10 C
0.10 C
A - B 0.20 C
A - BCD 0.25 M
(0.25D x 0.75E)
INDEX AREA
0.33 C
H
9
h
h
SEE
DETAIL B
b1
c1
7
(b)
c
WITH
PLATING
BASE
METAL
SECTION A-A
20
0.07 R MIN.
10
L1
C0L2
A
A
L
GAUGE PLANE
SEATING PLANE
H
DETAIL B
68 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
9.2 SOC008 wide — 8-pin Plastic Small Outline Package (208-mils Body Width)
3602 \ 16-038.03 \ 9.1.6
NOTES:
1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3.DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
PACKAGE SOC 008 (inches)SOC 008 (mm)
JEDEC
SYMBOL MIN MAX MIN MAX
A 0.069 0.085 1.7532.159
A1 0.002 0.00980.051 0.249
A2 0.067 0.075 1.70 1.91
b0.014 0.019 0.356 0.483
b10.0130.0180.330 0.457
c 0.0075 0.0095 0.191 0.241
c1 0.006 0.0080.152 0.203
D 0.208 BSC 5.283 BSC
E 0.315 BSC 8.001 BSC
E1 0.208 BSC 5.283 BSC
e .050 BSC 1.27 BSC
L 0.020 0.0300.5080.762
L1 .049 REF 1.25 REF
L2 .010 BSC 0.25 BSC
N 8 8
θ0˚ 8˚0˚8˚
θ1 5˚ 15˚ 5˚ 15˚
θ2 0˚ 0˚
July 14, 2011 S25FL004K-016K_00_02 S25FL004K / S25FL008K / S25FL016K 69
Data Sheet
10. Revision History
Section Description
Revision 01 (June 10, 2011)
Initial release. Combined S25FL004K_00_02, S25FL008K_00_02, and S25FL016K_00_02.
Revision 02 (July 14, 2011)
Global Promoted data sheet designation from Preliminary to Full Production
70 S25FL004K / S25FL008K / S25FL016K S25FL004K-016K_00_02 July 14, 2011
Data Sheet
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless e xtremely hi gh safety is secured, could ha v e a se rious eff ect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions . I f an y prod ucts desc ribed in this document represent good s or technolog ies subjec t to certain restrictions on e xport under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is pro vided as is wi thout warr anty or guar antee of an y kind as to its accuracy, completeness, operabi lity, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or an y other warr anty, express, im plied, or statutory. Spansion assumes no liability for an y
damages of any kind arising out of the use of the information in this document.
Copyright © 2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
