1M (64K x 16) Static RAM
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 3 8-05301 Rev . ** Revised September 30, 2002
Features
•Very high speed: 55 n s
•Wide voltage range: 1.65V to 2.2V
•Ultra-low active power
—Typical active current: 0.5 mA @ f = 1 MHz
—Typical active current: 3.75 mA @ f = fMAX
•Ultra-low standby power
•Easy memory expansion with CE1, CE2, and OE fea-
tures
•Automatic power-down when deselected
•CMOS for optimum speed/power
•Packages offered in a 48-ba ll FBGA and a 44-pi n TSOP
Type II
Functional Description[1]
The CY62127DV20 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The devic e al so ha s
an automatic power-down feature that significantly reduces
power co nsumption by 99% when address es are not togg ling.
The device can be put into st andby mode reduc ing power con-
sumption by more than 99% when deselected Chip Enable 1
(CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and
BLE are HIGH. Th e i np ut/o utpu t p ins (I/O0 throu gh I/O15) a re
placed in a high-impedance state when: deselected Chip En-
able 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are dis abl ed (BHE , BL E HIGH ) o r duri ng a w ri te op er-
ation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2)
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) inpu t LOW. If Byte Low Ena ble (BLE ) is LOW, then das
pins (A0 through A15). If Byte High Enable (BHE) is LOW , then
data from I/O pin s (I/O8 through I/O15) is written into the loca-
tion specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip En-
able 1 (CE 1) LO W and Chip Enable 2 (CE2) HIGH and Output
Enable (O E) L OW w hil e fo rci ng the W ri te Enab le (WE) HIGH.
If Byte Low Enable (BLE) is low, then data from the memory
location specified by the address pins will appear on I/O0 to
I/O7. If By te High En abl e (BHE) is L OW, then da ta from m em -
ory will app ear on I/O8 to I/O15. See the tru th t able a t the b ack
of this data sheet for a complete description of read and write
modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
64K ×16
RAM ARRAY I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
2048 x 32 x 16
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
WE
BLE
BHE
A
0
A
1
A
9
A
10
Power-down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
Logic Block Diagram