1
Standard Products
UT54ACS163/UT54ACTS163
4-Bit Synchronous Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Synchronously programmable
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS163 - SMD 5962-96554
UT54ACTS163 - SMD 5962-96555
DESCRIPTION
The UT54ACS163 and the UT54ACTS163 are synchronous
presettable 4-bit binary counters that feature internal carry look-
ahead logic for high-speed counting designs. Synchronous op -
eration occurs by having all flip-flo ps clocked sim ultaneously
so that the outputs change coincident with each other when in-
structed by the count-enable inputs and internal gating. A buff-
ered clock input triggers the four flip-flops on the rising (posi-
tive-going) edge of the clock input waveform.
The counters are fully programmable (i.e., they may be preset
to any number between 0 and 15). Presetting is sync hronous;
applying a low level at the load input disables the counter and
causes the outputs to agree with the load data after the next clock
pulse.
The clear function is synchronous and a low level at the clear
input sets all four of the flip-flop outputs low after the next clock
pulse. This synchronous clear allows the count length to be mod-
ified by decoding the Q outputs for the maximum count desired.
The counters feature a fully independent clock circuit. Changes
at control inputs (ENP, ENT, or LOAD) that modify t he operat-
ing mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable setup and hold times.
The devices are characterized over full military temperature
range of -55°C to +125°C.
PINOUTS 16-Pin DIP
Top View
16-Lead Flatpa ck
Top View
LOGIC SYMBOL
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR
CLK
A
B
C
D
ENP
VDD
RCO
QA
QB
QC
QD
ENT
8 9
VSS LOAD
1
2
3
4
5
7
6
16
15
14
13
12
10
11
VDD
89
CLR
CLK
A
B
C
D
ENP
RCO
QA
QB
QC
QD
ENT
VSS LOAD
(1)
CLR (9)
LOAD M1
5CT=0
CTRDIV 16
(10)
ENT G3
(7)
ENP G4
(2)
CLK
(3)
A(4)
B(5)
C(6)
D
(15) RCO
(14) QA
(11) QD
M2
C5/2,3,4+
(12) QC
(13) QB
1,5D (1)
(2)
(4)
(8)
3CT = 15
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publi-
cation 617-12.
2
FUNCTION TABLE
H = High voltage level h = High voltage level one setup time prior to the low-to-high clock transition
L = Low voltage level l = Low voltage level one setup time prior to the low-to-high clock transition
Notes:
1. The RCO output is high when ENT is high and the counter is at terminal count HHHH.
2. The high-to-low transition of ENP or ENT should only occur while CLK is high for conventional operations.
3. The low-to-high transition of LOAD or CLR should only occur while CLK is high for conventional operations.
LOGIC DIAGRAM
Operating Mode CLR CLK ENP ENT LOAD DATA A,B,C,D QNRCO
Reset (Clear) l↑X X X X L L
Parallel Load h3
h3
↑
↑X
XX
Xl
ll
hL
HL
1
Count h3↑h h h X Count 1
Inhibit h3
h3
X
Xl 2
X
X
l 2h3
h3
X
XQN
QN
1
L
(2)
(1)
(9)
(7)
(10)
(3)
(4)
(5)
(6)
(14)
(12)
(13)
(11)
(15)
QA
QB
QC
QD
RCO
DATA D
DATA C
DATA B
DATA A
ENT
ENP
LOAD
CLR
CLK
C
D
Q
Q
C
D
Q
Q
C
D
Q
Q
C
D
Q
Q
3
OPERATIONAL ENVIRONMENT1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Thresh old 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD +.3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 °C
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DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIL Low-level input voltage 1
ACTS
ACS 0.8
.3VDD
V
VIH High-level input voltage 1
ACTS
ACS .5VDD
.7VDD
V
IIN Input leakage current
ACTS/ACS VIN = VDD or VSS -1 1μA
VOL Low-level output voltage 3
ACTS
ACS IOL = 8.0mA
IOL = 100μA0.40
0.25 V
VOH High-level output voltage 3
ACTS
ACS IOH = -8.0mA
IOH = -100μA.7VDD
VDD - 0.25 V
IOS Short-circuit output current 2 ,4
ACTS/ACS VO = VDD and VSS -200 200 mA
IOL Output current10
(Sink)
VIN = VDD or VSS
VOL = 0.4V
8mA
IOH Output current10
(Source)
VIN = VDD or VSS
VOH = VDD - 0.4V
-8 mA
Ptotal Power dissipatio n 2, 8, 9 CL = 50pF 1.9 mW/
MHz
IDDQ Quiescent Supply Current VDD = 5.5V 10 μA
ΔIDDQ Quiescent Supply Current Delta
ACTS For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6 mA
CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz @ 0V 15 pF
5
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-3 8535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal ampl itude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -5 5 °C < TC < +125°C); Unless otherw ise noted, Tc is per the temperature range ordered.
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
3. Based on characterization, hold time (tH1) of 0ns can be assum ed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested.
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPHL CLK to Qn4 24 ns
tPLH CLK to Qn 4 22 ns
tPHL CLK to RCO 4 22 ns
tPLH CLK to RCO 4 24 ns
tPHL ENT to RCO 1 13 ns
tPLH ENT to RCO 1 14 ns
fMAX Maximum clock frequency 77 MHz
tSU1 A, B, C, D
Setup time before CLK ↑ 6ns
tSU2 LOAD, ENP, ENT, CLR low or high
Setup time before CLK↑
6ns
tH13Data hold time after CLK ↑ 1ns
tH2 All synchronous inputs hold time after CLK ↑1ns
tWMinimum pulse width
CLR low
CLK high
CLK low
7ns
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PACKAGING Side-Brazed Packages
8
FLATPACK PACKAGES
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UT54ACS163/U T54ACTS163: SMD
5962 ***** ** * * **
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96554 = UT54ACS163
96555 = UT54AC TS163
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specif i ed.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when o rdering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offer ed with a TID toler ance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-8 83 Test Method 1019 Condition A.
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