1/21October 2004
VNQ830M-E
QUAD CHANNEL HIGH SIDE DRIVER
Rev. 1
Tabl e 1. General Features
(*) Per each channel
■ CMOS COMPATIBLE INPUTS
■ OPEN DRAIN STATUS OUTPUT S
■ ON STAT E O PEN L OAD D ETE C TIO N
■ OFF STATE OPEN LOAD DETECTION
■ SHORT E D LOAD PROTECTIO N
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ LOSS OF GROUND PROT ECTION
■ VERY LOW STAND-BY CURRENT
■ REVERSE BATTERY PROTECTION (**)
■ IN COMPLIANCE WITH THE 2002/95/EC
EURO PEAN DI R ECTIVE
DESCRIPTION
The VNQ830M-E is a quad HSD formed by
assembling two VND830M-E chips in the same
SO-28 package. The VND830M-E is a monolithic
device made by using| STMicroelectronics
VIPower M0-3 Technology. The VNQ830M-E is
intended for driving any type of multiple loads with
one side connected to ground.
Act ive V CC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table).
Figure 1. Package
Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload.
The devi ce detects open load condition both i n on
and off s tate. The openload t hreshold is aimed at
detecting the 5W/12V standard bulb as an
openload fault in the on state. Output shorted to
VCC is detected in the off state. Device
automatically turns off in case of ground pin
disconnection
Tabl e 2. Order Codes
N ote: (**) Se e app l i c a t i on schemati c at pa ge 10
Type RDS(on) Iout VCC
VNQ83 0M-E 60mΩ (*) 6A (*) 36V
SO-28 (DOUBLE ISLAND)
Package Tube Tape and Reel
SO-28 VNQ830M-E VNQ830MTR-E
VNQ830M-E
2/21
Figu re 2. Blo ck D ia gra m
OVERTEMP. 1
VCC1,2
GND1,2
INPUT1 OUTPUT1
OVERVOLTAGE
LOGIC
DRIVER 1
STATUS1
Vcc
CLAMP
UNDERVOLTAGE
CLAMP 1
OPENLOAD ON 1
CURRENT LIMITER 1
OPENLOAD OFF 1
OUTPUT2
DRIVER 2
CLAM P 2
OPENLOAD ON 2
OPENLOAD OFF 2
OVERTEMP. 2
INPUT2
STATUS2
CURRENT LIMITER 2
OVERTEM P. 3
VCC3,4
GND3,4
INPUT3 OUTPUT3
OVERVOLTAGE
LOGIC
DRIVER 3
STATUS3
Vcc
CLAMP
UNDERVOLTAGE
CLAMP 3
OPENLOAD ON 3
CURRENT LIMITER 3
OPENLOAD OFF 3
OUTPUT4
DRIVER 4
CLAMP 4
OPENLOAD ON 4
OPENLOAD OFF 4
OVERTEMP. 4
INPUT4
STATUS4
CURRENT LIM ITER 4
3/21
VNQ830M-E
Table 3. Absolute Maximum Ratings
Figu re 3. Con f ig urat i on Diagram (Top View) & Su gg e st ed Conne ct io ns for U nu s ed an d N .C . Pins
Symbol Parameter Value Unit
VCC DC Supply Voltage 41 V
- VCC Reverse DC Supply Voltage - 0.3 V
- IGND DC Reverse Ground Pin Current - 200 mA
IOUT DC Output Current Internally Limited A
- IOUT Reverse DC Output Current - 6 A
IIN DC Input Current +/- 10 mA
ISTAT DC Status Current +/- 10 mA
VESD
Electrostatic Discharge (Human Body Model:
R=1.5KΩ; C=100pF)
- INPUT
- STATUS
- OUTPUT
- VCC
4000
4000
5000
5000
V
V
V
V
Ptot Power Dissipation Tpins=25°C 6.25 W
EMAX
Maximum Switching Energy
(L=1mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC;
IL=10.5A) 77 mJ
TjJunction Operating Temperature Internally Limited °C
Tstg Storage Temperature - 55 to 150 °C
V
CC
1,2
GND 1,2
INPUT1
STATUS1
STATUS2
V
CC
1,2
V
CC
3,4
GND 3,4
INPUT3
STATUS3
V
CC
3,4 V
CC
3,4
OUTPUT4
OUTPUT4
OUTPUT4
OUTPUT3
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
V
CC
1,2
OUTPUT3
OUTPUT3
OUTPUT1
OUTPUT1
INPUT2
STATUS4
INPUT4
1
14 15
28
Connection / Pin Status N.C. Output Input
Floating X X X X
To Ground X Through 10KΩ resistor
VNQ830M-E
4/21
Figure 4. Current and Voltage Conventions
Table 4. Thermal Data (Pe r isla nd)
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal
mo unting and no artificial air f l ow
Note: 2. When mounted on a standard single-sided FR-4 board wit h 6cm2 of Cu (at least 3 5µm thick) connected to all VCC pins. Horizontal
mo unti ng an d no arti f i ci al ai r fl ow
Symbol Parameter Value Unit
Rthj-lead Thermal Resistance Junction-lead per chip 20 °C/W
Rthj-amb Thermal Resistance Junction-ambient 60 (1) 44 (2) °C/W
Rthj-amb Thermal Resistance Junction-ambient (two chips ON) 46 (1) 31 (2) °C/W
(*) VFn = VCCn - VOUTn during reverse battery condition
IS1,2
IGND1,2
OUTPUT3
VCC1,2
GND1,2
INPUT2
IOUT3
VCC1,2
VOUT4
OUTPUT2 IOUT2
VOUT3
INPUT1
IIN1
STATUS1
ISTAT1 OUTPUT1 IOUT1
OUTPUT4
IOUT4
VOUT2
VOUT1
IIN2
ISTAT2
ISTAT3
IIN4
ISTAT4
STATUS2
STATUS3
STATUS4
INPUT3
INPUT4
VSTAT4
VIN4
VSTAT3
VIN3
VSTAT2 IIN3
VIN2
VSTAT1
VIN1
IGND3,4
GND3,4
IS3,4
VCC3,4
VCC3,4 VF1 (*)
5/21
VNQ830M-E
ELECTRICAL CHARACTERISTICS
(8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified)
(Per each channel)
Tab le 5. P o we r Ou t put
Note: (**) Per i sland
Table 6. Pro tection (Per each channel) (See note 1)
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and n um ber of ac tivation cyc l es
Table 7. VCC - Output Diode (Per each channel)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCC (**) Operating Supply Voltage 5.5 13 36 V
VUSD (**) Undervoltage Shut-down 3 4 5.5 V
VOV (**) Overvo ltage Shut- down 36 V
Ron On State Resistance IOUT=2A; Tj=25°C
IOUT=2A; VCC>8V 60
120 mΩ
mΩ
IS (**) Supply Current
Off State; VCC=13V; VIN=VOUT=0V
Off State; VCC=13V; VIN=VOUT=0V; Tj
=25°C
On State; VCC=13V; VIN=5V; IOUT=0A
12
12
5
40
25
7
µA
µA
mA
IL(off1) Off State Output Current VIN=VOUT=0V 0 50 µA
IL(off2) Off State Output Current VIN=0V; VOUT=3.5V -75 0 µA
IL(off3) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =125°C 5 µA
IL(off4) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =25°C 3 µA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
TTSD Shut-down Temperature 150 175 200 °C
TRReset Temperature 135 °C
Thyst Thermal Hysteresis 7 15 °C
tSDL Status Delay in Overload
Conditions Tj>TTSD 20 µs
Ilim Current limitation 5.5V<VCC<36V 6 10.5 15
15 A
A
Vdemag Turn-off Output Clamp
Voltage IOUT=2A; L=6mH VCC-41 VCC-48 VCC-55 V
Symbol Parameter Test Conditions Min Typ Max Unit
VFForward on Voltage -IOUT=1.3A; Tj=150°C 0.6 V
VNQ830M-E
6/21
ELECTRICAL CHARACTERISTICS (contin ued)
Table 8. Status Pin (Per each channel)
Table 9. Switching (Per each channel ) (VCC=13V)
Table 10. Openload Detection (Per eac h channel)
Table 11. Logic Input (Per each ch annel)
Symbol Parameter Test Conditions Min Typ Max Unit
VSTAT Status Low Output Voltage ISTAT=1.6mA 0.5 V
ILSTAT Status Leakage Current Normal Operation; VSTAT=5V 10 µA
CSTAT Status Pin Input
Capacitance Normal Operation; VSTAT=5V 100 pF
VSCL Status Clamp Voltage ISTAT=1mA
ISTAT=-1mA 6 6.8
-0.7 8V
V
Symbol Parameter Test Conditions Min Typ Max Unit
td(on) Tur n-on Delay Time RL=6.5Ω from V IN rising edge to
VOUT=1.3V 30 µs
td(off) Tur n-off Delay Time RL=6.5Ω from V IN falling edge to
VOUT=11.7V 30 µs
dVOUT/dt(on) Tur n-on Voltag e Slope RL=6.5Ω from V OUT=1.3V to
VOUT=10.4V
See
relative
diagram V/µs
dVOUT/dt(off) Tur n-off Voltag e Slope RL=6.5Ω from V OUT=11.7V to
VOUT=1.3V
See
relative
diagram V/µs
Symbo l Param eter Test Conditions Min Ty p Max Unit
IOL Openload ON State
Detection Threshold VIN=5V 0.6 0.9 1.2 A
tDOL(on) Openload ON State
Detection Delay IOUT=0A 200 µs
VOL Openload OFF State
Voltage Detection
Threshold VIN=0V 1.5 2.5 3.5 V
tDOL(off) Openload Detection Delay
at Turn Off 1000 µs
Symbol Parameter Test Conditions Min Typ Max Unit
VIL Input Low Level 1.25 V
IIL Low Level Input Current VIN=1.25V 1 µA
VIH Input High Level 3.25 V
IIH High Level Input Current VIN=3.25V 10 µA
VI(hyst) Input Hysteresis Voltage 0.5 V
VICL Input Clamp Voltage IIN=1mA
IIN=-1mA 6 6.8
-0.7 8V
V
7/21
VNQ830M-E
Table 12 . Truth Ta ble
Figure 5.
CONDITIONS INPUT OUTPUT SENSE
Normal Operation L
HL
HH
H
Current Limitation L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Overtemperature L
HL
LH
L
Undervoltage L
HL
LX
X
Overvoltage L
HL
LH
H
Output Voltage > VOL L
HH
HL
H
Output Current < IOL L
HL
HH
L
V
INn
V
STATn
t
DOL(off)
OPEN LOAD STATUS TIM ING (with external pull-up)
V
INn
V
STATn
OVER TEMP STATUS TIMING
t
SDL
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
T
j
> T
TSD
t
SDL
VNQ830M-E
8/21
Figure 6. Switching time Wavefor ms
Table 13. Electrical Tr ansient Req uiremen ts On VCC Pin
ISO T/R 7637/1
Test Pulse TEST LEVELS
I II III IV Delays and
Impedance
1 -25 V -50 V -75 V -100 V 2 ms 10 Ω
2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω
4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω
5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2 Ω
ISO T/R 7637/1
Test Pulse TEST LEVELS RESULTS
I II III IV
1CCCC
2CCCC
3aCCCC
3bCCCC
4CCCC
5C E E E
CLASS CONTENTS
C All functions of the device are performed as designed after exposure to disturbance.
E One or more functions of the device is not performed as designed after exposure and cannot be
returned to proper operation without replacing the device.
t
t
VOUTn
VINn
80%
10%
dVOUT/dt(on)
td(off)
90%
dVOUT/dt(off)
td(on)
9/21
VNQ830M-E
Figure 7. Waveforms
OPEN LOAD without external pull-up
STATUSn
INPUTn
NORMAL OPER ATION
UNDERVOLTAGE
VCC VUSD
VUSDhyst
INPUTn
OVERVOLTAGE
VCC
VCC>VOV
STATUS
INPUTn
STATUSn
STATUSn
INPUTn
STATUSn
INPUTn
OPEN LOAD with external pull-up
undefined
OVERTEMPERATURE
INPUTn
STATUSn
TTSD
TR
Tj
LOAD VOLTAGEn
VCC<VOV
LOAD VOLTA GEn
LOAD VOLTAGEn
LOAD VOLTAGEn
LOAD VOLTAGEn
LOAD CURRENTn
VOL
VOUT>VOL
VNQ830M-E
10/21
Figure 8. Application Schematic
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
Solution 1 : Resistor in the gr ound line (R
GND
only). T his
can be used with any type of load.
The following is an indication on how to dimension the
R
GND
resistor.
1) R
GND
≤ 600mV / 2(IS(on)max).
2) R
GND
≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in R
GND
(when VCC< 0: durin g rever se
battery situations) is:
PD= (-VCC)2/R
GND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with fo rmula (1) where IS(on)max becom es the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the R
GND
will
produce a shif t (IS(on)max * R
GND
) in the input thr esholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2.
V
CC1,2
OUTPUT2
+5V
R
prot
OUTPUT1
STATUS1
INPUT1
+5V
STATUS2
INPUT2
+5V
D
GND
R
GND
V
GND
GND1,2 GND3,4
OUTPUT3
OUTPUT4
µ
C
V
CC3,4
STATUS3
INPUT3
STATUS4
INPUT4
+5V
+5V
R
prot
R
prot
R
prot
R
prot
R
prot
R
prot
R
prot
D
ld
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
11/21
VNQ830M-E
Solution 2: A diode (D
GND
) in the ground line.
A resistor (R
GND
=1kΩ) should be inserted in parallel to
D
GND
if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several diffe rent HSD. Also i n this case, the pr esence of
the ground n etwork will produce a shift (
j
600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also
required to p reven t tha t, d uring batt ery voltag e tr ansie nt,
the current exceeds the Absolute Maximum Rating.
Safest co nfigu ration for unu sed INPU T a nd S TAT US p in
is to leave them unconnected.
LO AD DUMP PROT ECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
The same applies if the device will be subject to
transients on the V CC line that are greater than the ones
shown in the ISO T/R 7637/1 table.
.µC I/Os PROTECTION:
If a ground protection network is used and negative
transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-V
GND
) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommen ded Rpr ot value is 10kΩ.
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up
resistor (RPU) connected between OUTPUT pin and a
positive supply voltage (VPU) like the +5V line used to
supply the microprocessor.
The extern al res istor has to be s electe d ac cordin g to t he
following requirements:
1) no fa lse o pen load indic ation whe n lo ad is con necte d:
in this cas e we have to avoid VOUT to be higher th an
VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2) no misdetection when load is disconnected: in this
case the VOUT has to be higher than VOLmax; this
results in the following condition RPU<(VPU–VOLmax)/
IL(off2).
Because Is(OFF) may significantly increase if Vout is
pulled high (up to several mA), the pull-up resistor RPU
should be connected to a supply that is switched OFF
when the module is in standby.
The values of V OLmin, VOLmax and IL(off2) are ava ilable in
the Electrical Characteristics section.
Figure 9. Open Load detection in off state
VOL
V batt. VPU
RPU
RL
R
DRIVER
+
LOGIC
+
-
INPUT
STATUS
VCC
OUT
GROUND
IL(off2)
VNQ830M-E
12/21
Figure 10. Off State Output Current
Figure 11. Input Clamp Voltage
Figu re 12. S t at us Low Output V ol ta ge
Figure 13. High Level Input Current
Figure 14. Status Leakage Current
Figure 15. Status Clamp V oltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
IL (off1) (u A)
Off state
Vcc=36V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vicl (V)
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Vstat (V)
Istat=1.6mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (uA)
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.01
0.02
0.03
0.04
0.05
Ilstat (uA)
Vstat=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vscl (V)
Istat=1mA
13/21
VNQ830M-E
Figure 16. Overvoltage Shutdown
Figure 17. Turn-on Voltage Slope
Figure 18. On State Resistance Vs Tcase
Figure 19. I LIM Vs T case
Figure 20. Turn-off Voltage Slope
Figure 21. On State Resistance Vs VCC
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
30
32
34
36
38
40
42
44
46
48
50
Vov (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
100
200
300
400
500
600
700
800
dVout / dt( on) (V/ms)
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
20
40
60
80
100
120
140
160
Ron (mOhm )
Iout=2A
Vcc=8V; 13V & 36V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
2
4
6
8
10
12
14
16
18
20
Ilim (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
200
250
300
350
400
450
500
550
600
dVout/dt(off) (V/ms)
Ri=6.5Ohm
5 10152025303540
Vcc (V)
0
10
20
30
40
50
60
70
80
90
100
110
120
Ron (mOhm )
Iout=5A
Tc= - 40°C
Tc=25°C
Tc=150°C
VNQ830M-E
14/21
Figure 22. Input High Level
Figure 23. Openloa d On St ate Detection
Threshold
Figure 24. Input Hysteresis Voltage
Figure 25. Input Low Level
Figure 26. Openloa d Off State Detection
Threshold
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc
(
°C
)
750
800
850
900
950
1000
1050
1100
1150
1200
1250
Io l (mA)
Vcc= 13 V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Vhyst (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vil (V)
-50 -25 0 25 50 75 100 125 150 175
Tc
(
°C
)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vo l (V)
Vin=0V
15/21
VNQ830M-E
Figure 27. Maxi m um turn off curren t versus load i nductance
A = Single Pulse at TJstart=150ºC
B= Repet iti ve pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
Conditions:
VCC=13.5V
Values are generated wit h RL=0Ω
In case of repetitive pulses , Tjstart (at beginning of
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
1
10
100
0.1 1 10 100
L(mH)
ILMA X (A)
A
B
C
VIN, IL
t
Demagnetization Demagnetization Demagnetization
VNQ830M-E
16/21
SO-28 Double Island Thermal Data
Figure 28. Double Island PC Board
Table 14. The rmal Calculation Accord ing To The Pcb Heatsink Area
RthA = The rmal resis tance Ju nction to Ambient with o ne
chip ON
RthB = Therm al resistance Jun ction to Ambient with bo th
chips ON and Pdchip1=Pdchip2
RthC = Mutual thermal resistance
Figure 29. Rthj-amb Vs. PCB Copper Area In
Open Box Free Air Condi tion
Chip 1 Chip 2 Tjchip1 Tjchip2 Note
ON OFF RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb
OFF ON RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb
ON ON RthB x (Pdchip1 + Pdchip2) + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1=Pdchip2
ON ON (RthA x Pdchip1) + RthC x Pdchip2 + Tamb (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1≠Pdchip2
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.5cm2, 3cm2, 6cm2).
10
20
30
40
50
60
70
01234567
PCB Cu heatsink area (cm^2)/island
RTHj_amb
(°C/W)
RthA
RthB
RthC
17/21
VNQ830M-E
Figure 30. S O-28 Thermal Imp edance Jun ction Ambient Single Pulse
Figu re 31 . Th e rm al fit tin g m odel of a do ubl e
channel HSD in SO-28 Pulse calculation formula
Table 15. Thermal Parameter
0.01
0.1
1
10
100
1E-04 0.001 0.01 0.1 1 10 100 1000
time(s)
Zth(°C/W)
6 cm ^2/island
3 cm^2/ island
0,5 cm^2/ island
One channel ON
Two chan nels ON
on same chip
Pd1
C1
R4
C3 C4
R3R1 R6R5R2
C5 C6C2
Pd2 R14
C13 C14
R13
Tj_1
Tj_2
T_amb
Pd3
C7
R10
C9 C10
R9R7 R12R11
R8
C11 C12
C8
Pd4 R16
C15 C16
R15
Tj_3
Tj_4
R17 R18
Area/island (cm2) 0.5 6
R1=R7= R13= R15 (°C /W) 0.05
R2=R8= R14= R16 (°C /W) 0.3
R3=R9 (°C /W) 3.4
R4=R10 (°C/W) 11
R5=R11 (°C/W) 15
R6=R12 (°C/W) 30 13
C1=C7= C13= C15 (W.s/ °C) 0.001
C2=C8= C14= C16 (W.s/ °C) 5.0 0E-0 3
C3=C9 (W.s/° C) 1.00E-0 2
C4=C10 (W.s/°C) 0.2
C5=C11 (W.s/°C) 1.5
C6=C12 (W.s/°C) 5 8
R17=R18 (°C/W) 150
ZTHδRTH δZTHtp 1δ–()+⋅=
where δtpT⁄=
VNQ830M-E
18/21
PACKAGE MECHANICAL
Table 16. SO -28 Mechani cal Data
Figure 32. SO-28 Package Dimensi ons
Symbol millimeters
Min Typ Max
A 2.65
a1 0.10 0.30
b 0.35 0.49
b1 0.23 0.32
C 0.50
c1 45° (typ.)
D 17.7 18.1
E 10.00 10.65
e 1.27
e3 16.51
F 7.40 7.60
L 0.40 1.27
S 8° (max.)
19/21
VNQ830M-E
Figure 33. SO-28 Tube Shipment (No Suffix)
Figure 34. Tape And Reel Shipment (Suffix “TR”)
All dimensions are in mm.
Base Q.ty 28
Bulk Q.ty 700
Tube le ngt h ( ± 0.5) 532
A3.5
B13.8
C (± 0.1) 0.6
A
CB
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
N o co m ponentsNo com ponents Co m ponents
500m m min
500m m min
Em pty co m ponents pocke ts
sa led with cover ta p e .
User direction of feed
REEL DIMENSIONS
VNQ830M-E
20/21
RE VISION HIST ORY
Date Revision Descri ption of Change s
Oct. 2004 1 - First Issue
21/21
VNQ830M-E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by i m plicati on or otherwise under any pate nt or patent ri ghts o f STMic roelectronics. Specifications mentioned i n t hi s publ i cation are subject
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The ST l ogo is a re gi stered tr ademar k of STM i croel ectro ni cs .
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