EVALUATION KIT AVAILABLE MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface General Description The MAX5214/MAX5216 are pin-compatible, 14-bit and 16-bit digital-to-analog converters (DACs). The MAX5214/ MAX5216 are single-channel, low-power, buffered voltage-output DACs. The devices use a precision external reference applied through the high resistance input for rail-to-rail operation and low system power consumption. The MAX5214/MAX5216 accept a wide 2.7V to 5.5V supply voltage range. Power consumption is extremely low to accommodate most low-power and low-voltage applications. These devices feature a 3-wire SPI-/QSPITM-/ MICROWIRE-/DSP-compatible serial interface to save board space and to reduce the complexity in isolated applications. The MAX5214/MAX5216 minimize the digital noise feedthrough from input to output with SCLK and DIN input buffers powered down after completion of each serial input frame. On power-up, the MAX5214/MAX5216 reset the DAC output to zero, providing additional safety for applications that drive valves or other transducers that need to be off on power-up. The DAC output is buffered resulting in a low supply current of 80A (max) and a low offset error of 0.25mV. A zero level applied to the CLR pin asynchronously clears the contents of the input and DAC registers and sets the DAC output to zero independent of the serial interface. The MAX5214/MAX5216 are available in an ultra-small (3mm x 5mm), 8-pin MAX(R) package and are specified over the -40C to +105C extended industrial temperature range. Applications 2-Wire Sensors Communication Systems Automatic Tuning Gain and Offset Adjustment Power Amplifier Control Process Control and Servo Loops Portable Instrumentation Programmable Voltage and Current Sources Automatic Test Equipment Ordering Information appears at end of data sheet. QSPI is a trademark of Motorola, Inc. MAX is a registered trademark of Maxim Integrated Products, Inc. 19-5651; Rev 2; 7/13 Benefits and Features Low Power Consumption (80A max) 14-/16-Bit Resolution in a 3mm x 5mm, 8-Pin MAX Package Relative Accuracy * 0.40 LSB INL (MAX5214, 14-Bit typ, 1 LSB max) * 1.2 LSB INL (MAX5216, 16-Bit typ, 4 LSB max) Guaranteed Monotonic Over All Operating Ranges Low Gain and Offset Error Wide 2.7V to 5.5V Supply Range Rail-to-Rail Buffered Output Operation Safe Power-On Reset (POR) to Zero DAC Output Fast 50MHz, 3-Wire, SPI/QSPI/MICROWIRE Compatible Serial Interface Schmitt-Trigger Inputs for Direct Optocoupler Interface Asynchronous CLR Clears DAC Output to Code 0 High Reference Input Resistance for Power Reduction Buffered Voltage Output Directly Drives 10k Loads Functional Diagram VDD REF MAX5214 MAX5216 POR CS SCLK DIN SERIAL-TOPARALLEL CONVERTER INPUT REGISTER DAC REGISTER 14-/16-BIT DAC CLR GND BUFFER OUT MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Absolute Maximum Ratings VDD to GND..............................................................-0.3V to +6V REF, OUT, CLR to GND............................... -0.3V to the lower of (VDD + 0.3V) and +6V SCLK, DIN, CS to GND............................................-0.3V to +6V Continuous Power Dissipation (TA = +70NC) FMAX (derate at 4.8mW/NC above +70NC)..................387mW Maximum Current into Any Input or Output..................... Q50mA Operating Temperature Range......................... -40NC to +105NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) FMAX Junction-to-Ambient Thermal Resistance (BJA).........206NC/W Junction-to-Case Thermal Resistance (BJC)................42NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Note 3) Resolution Integral Nonlinearity N INL Differential Nonlinearity DNL Offset Error OE MAX5214 14 MAX5216 16 MAX5214 (14-bit) (Note 4) -1 0.4 +1 MAX5216 (16-bit) (Note 4) -4 1.2 +4 MAX5216B (16-bit) (Note 4) -8 3 +8 MAX5214 (14-bit) (Note 4) -1 0.1 +1 MAX5216 (16-bit) (Note 4) -1 0.25 +1 -1.25 0.25 +1.25 (Note 5) Offset-Error Drift Gain Error Bits 1.6 GE (Note 5) -0.06 Gain Temperature Coefficient -0.04 LSB LSB mV V/C 0 %FS ppmFS/ C 2 REFERENCE INPUT Reference-Input Voltage Range Reference-Input Impedance DAC OUTPUT VREF 2 RREF 200 256 No load (typical) Output Voltage Range (Note 6) www.maximintegrated.com CL V k VDD 10k load to GND 0 VDD 0.2 10k load to VDD 0.2 VDD 0.2 DC Output Impedance Capacitive Load (No Sustained Oscillations) VDD V 0.1 Series resistance = 0 0.1 nF Series resistance = 1k 15 F Maxim Integrated 2 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Electrical Characteristics (continued) (VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL Resistive Load (Note 6) RL Short-Circuit Current Power-Up Time DIGITAL INPUTS (SCLK, DIN, CS, CLR) Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIN Input Capacitance CIN Hysteresis Voltage DYNAMIC PERFORMANCE (Note 7) Voltage-Output Slew Rate CONDITIONS MIN MAX UNITS 6 +25 mA 5 VDD = 5.5V -25 From power-down mode k 25 s 0.7 x VDD VIN = 0V or VDD V 0.1 VHYS SR TYP 0.3 x VDD V 1 A 10 pF 0.15 V Positive and negative 0.5 V/s Voltage-Output Settling Time 1/4 scale to 3/4 scale, to P 0.5 LSB, 14-bit 18 s Reference -3dB Bandwidth Hex code = 2000 (MAX5214), Hex code = 8000 (MAX5216) 100 kHz Digital Feedthrough Code = 0, all digital inputs from 0V to VDD, SCLK < 50MHz 0.5 nV*s DAC Glitch Impulse Major code transition 2 nV*s 1kHz 73 10kHz 70 0.1Hz to 10Hz 3.5 BW Output Noise Integrated Output Noise nV/Hz VP-P POWER REQUIREMENTS Supply Voltage Supply Current Power-Down Supply Current VDD 2.7 IDD No load; all digital inputs at 0V or VDD, supply current only; excludes reference input current, midscale PDIDD No load, all digital inputs at 0V or VDD 5.5 V 70 80 A 0.4 2 A 50 MHz TIMING CHARACTERISTICS (Notes 7 and 8) (Figures 1 and 2) Serial Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup Time CS Fall to SCLK Fall Hold Time CS Rise to SCLK Fall Hold Time CS Rise to SCLK Fall SCLK Fall to CS Fall DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time CS Pulse-Width High www.maximintegrated.com fSCLK 0 tCH 8 ns tCL 8 ns tCSS0 8 ns tCSH0 0 ns tCSH1 0 tCSF 100 ns 5 ns tDH 4.5 ns 20 ns tCSA tDS tCSPW ns 12 ns Maxim Integrated 3 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Electrical Characteristics (continued) (VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN tCLPW CLR Pulse-Width Low tCSC CLR Rise to CS Fall TYP MAX UNITS 20 ns 20 ns Note 2: Electrical specifications are production tested at TA = +25NC and TA = +105NC. Specifications over the entire operating temperature range are guaranteed by design and characterization. Typical specifications are at TA = +25NC and are not guaranteed. Note 3: Static accuracy tested without load. Note 4: Linearity is tested within 20mV of GND and VDD. Note 5: Gain and offset is tested within 100mV of GND and VDD. Note 6: Subject to offset and gain error limits and VREF settings. Note 7: Guaranteed by design; not production tested. Note 8: All timing specifications measured with VIL = VGND, VIH = VDD. DIN DIN15 DIN14 DIN13 DIN12 tDS SCLK 1 tCSH0 2 DIN11 tDH 3 4 DIN10 DIN9 DIN8 6 7 8 DIN2 5 14 DIN0 DIN15 tCL CS 15 16 1 tCSA tCSH1 tCH tCSS0 DIN1 tCP tCSF tCSPW CLR tCLPW tCSC Figure 1. 16-Bit Serial-Interface Timing Diagram (MAX5214) DIN DIN23 DIN22 DIN21 DIN20 tDS SCLK 1 2 DIN19 tDH 3 4 5 tCSS0 CS DIN17 DIN16 DIN2 6 7 8 22 DIN1 DIN0 DIN23 23 24 1 tCSH1 tCSA tCH tCSH0 DIN18 tCP tCL tCSPW tCSF CLR tCLPW tCSC Figure 2. 24-Bit Serial-Interface Timing Diagram (MAX5216) www.maximintegrated.com Maxim Integrated 4 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Typical Operating Characteristics (TA = +25C, unless otherwise noted.) 0 -0.2 1 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -2 -3 -1.0 -1.0 8192 12288 4096 0 16384 -1 -3 MAX5216 32768 49152 0.50 1.0 0.5 0 -0.5 -1.0 3 5 7 0 MIN 11 13 15 17 2.7 DEVICE NUMBER 3.5 3.9 4.3 4.7 SUPPLY VOLTAGE (V) INTEGRAL NONLINEARITY vs. TEMPERATURE INTEGRAL NONLINEARITY vs. TEMPERATURE MAX5214 0.50 3 0 3.1 MIN 5.1 5.5 MAX5216 2 MAX 1 MAX 0.25 -0.25 -1 -1.00 19 0.75 INL (LSB) 1 9 MAX5214 toc05a 1.00 MAX MIN -0.75 1 MAX5214 toc04b 2 0 -0.50 INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE MAX5216 MAX 0.25 -0.25 DIGITAL INPUT CODE (LSB) 3 65536 MAX5214 0.75 -3.0 65536 49152 1.00 INL (LSB) 16384 32768 INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE -1.5 -2.0 -2.5 -2 0 16384 DIGITAL INPUT CODE (LSB) INL (LSB) 0 VREF = 5.0V VREF = 2.5V VREF = 5.0V VREF = 2.5V 2.5 2.0 1.5 INL MIN/MAX (LSB) INL (LSB) 3.0 MAX5214 toc02b MAX5216 VREF = 2.5V 1 INL (LSB) 0 16384 INL MIN/MAX (VREF = 5.0V/2.5V) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 2 12288 DIGITAL INPUT CODE (LSB) DIGITAL INPUT CODE (LSB) 3 8192 MAX5214 toc03 4096 0 0 MAX5214 toc04a 0.2 MAX5214 toc05b 0.4 0.2 MAX5216 VREF = 5V 2 INL (LSB) 0.4 MAX5214 toc02a 0.6 INL (LSB) INL (LSB) 0.6 MAX5214 VREF = 2.5V 0.8 3 MAX5214 toc01b MAX5214 VREF = 5V 0.8 1.0 MAX5214 toc01a 1.0 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 0 MIN -1 -0.50 -2 -2 -0.75 -3 -1.00 -3 2.7 3.1 3.5 3.9 4.3 4.7 SUPPLY VOLTAGE (V) www.maximintegrated.com 5.1 5.5 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 Maxim Integrated 5 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) MAX(ABS(INL)) DISTRIBUTION vs. TEMPERATURE 40 30 20 20 10 10 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 0.5 0.1 -0.1 -0.5 -0.1 0 -0.1 -0.3 -0.3 -0.4 -0.4 -0.5 65536 16384 0 32768 49152 65536 DIGITAL INPUT CODE (LSB) DNL MIN/MAX (VREF = 5.0V/2.5V) DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE MAX5216 0.5 0.3 0.2 0.1 0 -0.2 MAX5214 0.4 0.2 0.5 0.3 0.2 MAX 0 MIN -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.8 -0.4 -0.4 -1.0 -0.5 7 9 11 13 DEVICE NUMBER www.maximintegrated.com 15 17 19 MAX 0.1 -0.6 5 MAX5216 0.4 -0.4 3 MAX5214 toc07a 0.3 -0.2 49152 MAX5216 VREF = 2.5V 0.4 -0.2 0.4 1 16384 DIGITAL INPUT CODE (LSB) DNL (LSB) DNL (LSB) 0.6 0.5 0.1 0 32768 12288 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 0.2 16384 8192 DIGITAL INPUT CODE (LSB) 0.1 0 4096 0 2.8 DIGITAL INPUT CODE (LSB) VREF = 5.0V VREF = 2.5V VREF = 5.0V VREF = 2.5V 0.8 2.4 0.2 -0.5 16384 MAX5214 toc08 1.0 12288 2.0 0.3 -0.3 8192 1.2 1.6 LSB MAX5216 VREF = 5V 0.4 DNL (LSB) DNL (LSB) 0.3 4096 0.8 DNL (LSB) MAX5214 VREF = 2.5V 0 0.4 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5214 toc07b 0.5 -0.1 -0.5 0 0.10 0.20 0.30 0.40 0.50 0.60 0.70 LSB DNL (LSB) 0 0.1 -0.3 0 0 0.3 MAX5214 toc07d 30 50 MAX5214 VREF = 5V MAX5214 toc09b 40 -40C +25C +105C 60 MAX5214 toc09a COUNT (units) 50 70 0.5 DNL (LSB) -40C +25C +105C 60 MAX5216 MAX5214 toc07c 70 80 COUNT (units) MAX5214 MAX5214 toc06a 80 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5214 toc06b MAX(ABS(INL)) DISTRIBUTION vs. TEMPERATURE MIN -0.5 2.7 3.1 3.5 3.9 4.3 4.7 SUPPLY VOLTAGE (V) 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 SUPPLY VOLTAGE (V) Maxim Integrated 6 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. TEMPERATURE 0.5 0.3 0.4 MAX5216 0.3 0.2 0.2 0.1 DNL (LSB) DNL (LSB) MAX5214 toc10b MAX5214 MAX 0 -0.1 MIN -0.2 0 -0.1 -0.3 -0.4 -0.4 -0.5 -20 0 20 MIN -0.2 -0.3 -40 MAX 0.1 40 60 80 -0.5 100 -40 -20 0 20 TEMPERATURE (C) OFFSET ERROR vs. SUPPLY VOLTAGE 0.6 1.00 MAX5214 0.2 0.75 0.50 MAX5214 MAX5216 0.25 0 3.1 3.5 3.9 4.3 4.7 5.1 0 5.5 -40 -20 SUPPLY VOLTAGE (V) 8 6 4 40 60 80 100 GAIN ERROR vs. SUPPLY VREF = 2.5V -0.01 GAIN ERROR (%FS) COUNT (UNITS) 10 20 0 MAX5214 toc13 -40C TO +105C BOX METHOD 12 0 TEMPERATURE (C) OFFSET ERROR DRIFT vs. TEMPERATURE DISTRIBUTION 14 100 OFFSET ERROR vs. TEMPERATURE OFFSET ERROR (mV) OFFSET ERROR (mV) 0.8 2.7 80 MAX5214 toc12 VREF = 2.5V MAX5216 60 1.25 MAX5214 toc11 1.0 0.4 40 TEMPERATURE (C) MAX5214 toc14 0.4 MAX5214 toc10a 0.5 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE -0.02 -0.03 MAX5214 -0.04 2 -0.05 0 -0.06 MAX5216 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 DRIFT (V/C) www.maximintegrated.com 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 SUPPLY VOLTAGE (V) Maxim Integrated 7 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) VREF = 2.5V -0.01 -40C TO +105C BOX METHOD 12 10 -0.02 COUNT (UNITS) GAIN ERROR (%FS) 14 MAX5214 toc15 0 MAX5214 toc16 GAIN ERROR DRIFT vs. TEMPERATURE DISTRIBUTION GAIN ERROR vs. TEMPERATURE -0.03 MAX5214 -0.04 8 6 4 -0.05 2 MAX5216 -0.06 -40 -20 0 20 40 60 80 0 100 0 0.10 0.20 0.30 0.40 DRIFT (ppmFS/C) TEMPERATURE (C) FULL-SCALE OUTPUT vs. SUPPLY VOLTAGE FULL-SCALE OUTPUT vs. TEMPERATURE 2.498 OUTPUT VOLTAGE (V) MAX5214 2.496 2.494 2.492 MAX5214 toc18 2.498 OUTPUT VOLTAGE (V) 2.500 MAX5214 toc17 2.500 MAX5216 MAX5216 MAX5214 2.496 2.494 2.492 VREF = 2.5V VREF = 2.5V 2.490 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.490 -40 -20 0 SUPPLY VOLTAGE (V) 74 72 70 68 64 62 60 -40 -20 0 20 40 VDD = 4V 65 100 80 100 MAX5214 toc19b VDD = 5.25V VDD = 5V VDD = 4V 60 55 MAX5214/MAX5216 NO LOAD VDD = VREF VOUT = ZEROSCALE 50 VDD = 2.7V 40 TEMPERATURE (C) www.maximintegrated.com 70 45 60 80 75 SUPPLY CURRENT (A) SUPPLY CURRENT (A) VDD = 5.25V VDD = 2.7V MAX5214/MAX5216 NO LOAD VDD = VREF VOUT = MIDSCALE 60 80 MAX5214 toc19a 78 VDD = 5V 40 SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE 76 20 TEMPERATURE (C) 80 66 0.50 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Maxim Integrated 8 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE 74 MAX5216 72 70 68 MAX5214 66 64 65 MAX5214 60 55 50 MAX5216 45 62 60 2.7 3.1 3.5 3.9 4.3 4.7 5.1 40 5.5 2.7 3.1 3.5 3.9 4.3 4.7 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. SUPPLY VOLTAGE (POWER-DOWN MODE) SUPPLY CURRENT (A) 0.4 0.3 0.2 0.1 NO LOAD VDD = VREF 75 SUPPLY CURRENT (A) -40C 0C +25C +85C +105C 0.5 5.1 5.5 SUPPLY CURRENT vs. DAC CODE 80 MAX5214 toc21 0.6 MAX5214 70 65 VREF = 5.0V VREF = 2.5V 60 55 50 0 80 3.1 3.5 3.9 4.3 5.1 5.5 45 0 2500 5000 7500 10,000 12,500 15,000 SUPPLY VOLTAGE (V) CODE SUPPLY CURRENT vs. DAC CODE VOUT vs. TIME (EXITING POWER-DOWN MODE) MAX5216 NO LOAD VDD = VREF 75 4.7 MAX5214 toc23 MAX5214 toc22b 2.7 SUPPLY CURRENT (A) MAX5214 toc20b 70 MAX5214 toc22a SUPPLY CURRENT (A) 76 NO LOAD VDD = VREF VOUT = ZERO SCALE 75 SUPPLY CURRENT (A) NO LOAD VDD = VREF VOUT = MIDSCALE 78 80 MAX5214 toc20a 80 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX5214/MAX5216 RL = 10kI VREF = 5V 70 65 VREF = 5.0V VREF = 2.5V OUT = MIDSCALE 1V/div 60 55 0V 50 45 0 10,000 20,000 30,000 40,000 50,000 60,000 10s/div CODE www.maximintegrated.com Maxim Integrated 9 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) MAJOR CODE TRANSITION (0x7FFF TO 0x8000) MAJOR CODE TRANSITION (0x8000 TO 0x7FFF) MAX5214 toc24b MAX5214 toc24a MAX5216 VDD = 5V REF = 5V NO LOAD MAX5216 VDD = 5V NO LOAD REF = 5V OUT = MIDSCALE AC-COUPLED OUT = MIDSCALE AC-COUPLED 1mV/div 1mV/div 4s/div 4s/div MAJOR CODE TRANSITION (0x2000 TO 0x1FFF) MAJOR CODE TRANSITION (0x1FFF TO 0x2000) MAX5214 toc24c MAX5214 toc24d MAX5214 VDD = 5V REF = 5V NO LOAD MAX5214 VDD = 5V REF = 5V NO LOAD OUT = MIDSCALE AC-COUPLED OUT = MIDSCALE AC-COUPLED 1mV/div 1mV/div 4s/div 4s/div SETTLING TO 0.5 LSB 14 BIT (VDD = VREF = 5V, CL = 100pF) SETTLING TO 0.5 LSB 14 BIT (VDD = VREF = 5V, CL = 100pF) MAX5214 toc25a MAX5214 toc25b MAX5214/MAX5216 3/4 SCALE TO 1/4 SCALE 18s 17s MAX5214/MAX5216 1/4 SCALE TO 3/4 SCALE 4s/div www.maximintegrated.com 4s/div Maxim Integrated 10 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) OUTPUT VOLTAGE vs. OUTPUT CURRENT DIGITAL FEEDTHROUGH MAX5214 toc26 2.50 OUTPUT VOLTAGE (V) VOUT AC-COUPLED 1mV/div MAX5214 toc27 2.55 2.45 2.40 2.35 2.30 VSCLK 5V/div VDD = 5V VREF = 5V 2.25 0 40ns/div 1 2 3 4 5 6 OUTPUT CURRENT (mA) REFERENCE INPUT BANDWIDTH vs. FREQUENCY SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE VDDI = 5V HIGH T0 LOW 2000 1500 VDDI = 2.7V LOW T0 HIGH 1000 VDDI = 2.7V HIGH T0 LOW 0 ATTENUATION (dB) VDD = 5V LOW T0 HIGH MAX5214 toc29 3000 2500 5 MAX5214 toc28 -5 -10 -15 500 0 -20 0 1 2 3 4 5 10 1 100 1000 DIGITAL INPUT VOLTAGE (V) INPUT FREQUENCY (kHz) INTEGRATED OUTPUT NOISE (0.1Hz TO 10Hz) DAC OUPUT NOISE DENSITY vs. FREQUENCY MAX5214 toc30 200 MAX5214/MAX5216 OUT 1V/div NOISE (nVRMS /Hz) 175 MAX5214 toc31 DIGITAL SUPPLY CURRENT (A) 3500 FULL-SCALE (CODE 0XFF00) 150 ZERO-SCALE (CODE 0x00FF) 125 MIDSCALE (CODE 0x8000) 100 75 50 1s/div 10 100 1k 10k 100k FREQUENCY (Hz) www.maximintegrated.com Maxim Integrated 11 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Pin Configuration TOP VIEW REF 1 + CS 2 SCLK 3 MAX5214 MAX5216 DIN 4 8 GND 7 VDD 6 OUT 5 CLR MAX Pin Description PIN NAME FUNCTION 1 REF 2 CS 3 SCLK 4 DIN Data In 5 CLR Active-Low Asynchronous Digital-Clear Input. Drive CLR low to clear the contents of the input and DAC registers and set the DAC output to zero. 6 OUT Buffered DAC Voltage Output 7 VDD Supply Voltage. Bypass VDD with a 0.1F capacitor to GND. 8 GND Ground Reference Voltage Input. Bypass REF with a 0.1F capacitor to GND. Active-Low Chip-Select Input Serial-Clock Input Detailed Description The MAX5214/MAX5216 are pin-compatible and software-compatible 14-bit and 16-bit DACs. The MAX5214/ MAX5216 are single-channel, low-power, high-reference input resistance, and buffered voltage-output DACs. The MAX5214/MAX5216 minimize the digital noise feedthrough from their inputs to their outputs by powering down the SCLK and DIN input buffers after completion of each data frame. The data frames are 16-bit for the MAX5214 and 24-bit for the MAX5216. On power-up, the MAX5214/MAX5216 reset the DAC output to zero, providing additional safety for applications that drive valves or other transducers which need to be off on power-up. The MAX5214/MAX5216 contain a segmented resistor string-type DAC, a serial-in/parallel-out shift register, a DAC register, power-on-reset (POR) circuit, CLR to asynchronously clear the device independent of the serial interface, and control logic. On the falling edge of the clock (SCLK) pulse, the serial input (DIN) data is shifted into the device, MSB first. www.maximintegrated.com Output Amplifier (OUT) The MAX5214/MAX5216 include an internal buffer on the DAC output. The internal buffer provides improved load regulation and transition glitch suppression for the DAC output. The output buffer slews at 0.5V/Fs and drives up to 10kI in parallel with 100pF. The analog supply voltage (VDD) determines the maximum output voltage range of the device as VDD powers the output buffer. DAC Reference (REF) The external reference input features a typical input impedance of 256kI and accepts an input voltage from +2V to VDD. Connect an external voltage supply between REF and GND to apply an external reference. Visit www.maximintegrated.com/products/references for a list of available voltage-reference devices. Maxim Integrated 12 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Serial Interface transfers its contents to the input registers after loading 16/24 bits of data and updates the DAC output immediately after the data is received on the 16-/24-bit falling edge of the clock. To initiate a new data transfer, drive CS high and keep CS high for a minimum of 20ns before the next write sequence. The SCLK can be either high or low between CS write pulses. Figure 1 and Figure 2 show the timing diagram for the complete 3-wire serial interface transmission. The MAX5216 DAC code is unipolar binary with VOUT = (code/65,535) x VREF. The MAX5214 DAC code is unipolar binary with VOUT = (code/16,383) x VREF. See Table 1 and Table 2. The MAX5214/MAX5216 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSP. The interface provides three inputs: SCLK, CS, and DIN. The chip-select input (CS) frames the serial data loading at DIN. Following a chip-select input high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial-clock input (SCLK). Each serial word is 16-bit for the MAX5214 and 24-bit for the MAX5216. The first 2 bits are the control bits followed by 14 data bits (MSB first) for the MAX5214 and 22 data bits (MSB first) for the MAX5216 as shown in Table 1 and Table 2. The serial input register Table 1. Operating Mode Truth Table (MAX5214) 16-BIT WORD CONTROL BITS DATA BITS MSB FUNCTION LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 X X X X X X X X X X X X X X No operation 1 0 0 X A1 A0 X X X X X X X X X X Power-down (see Table 3) 0 1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Write through 1 1 Reserved, Do Not Use Table 2. Operating Mode Truth Table (MAX5216) 24-BIT WORD CONTROL BITS DATA BITS MSB LSB FUNCTION D9 D8 D7 D6 D5- D0 X X X X X X No operation X X X X X X X Power-down (see Table 3) B5 B4 B3 B2 B1 B0 X Write through D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 0 0 X X X X X X X X X X X 1 0 0 X A1 A0 X X X X X X 0 1 B9 B8 B7 B6 1 1 B15 B14 B13 B12 B11 B10 www.maximintegrated.com Reserved, Do Not Use Maxim Integrated 13 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Writing to the Devices Power-Down Mode 1) Drive CS low, enabling the shift register. The MAX5214/MAX5216 feature a software-controlled power-down mode. In power-down, the output disconnects from the buffer and is grounded with one of the three selectable internal resistors. See Table 3 for the selectable internal resistor values in power-down mode. The selected mode takes effect on the 16th SCLK falling edge of the MAX5214 and 24th SCLK falling edge of the MAX5216. The serial interface remains active in powerdown mode. In order to abort the power-down mode selection, pull CS high prior to the 16th (MAX5214) or 24th (MAX5216) SCLK falling edge. The contents of the DAC register remain valid while in power-down mode, allowing for the DAC to return to previous code by writing 0x8000 for the MAX5214 or 0x800000 for the MAX5216 (Table 3). A write to the write-through register causes the device to immediately exit power-down mode and transition to the requested code (see Table 1 and Table 2). 2) Clock 16/24 bits of data into DIN (MSB first and LSB last), observing the specified setup and hold times. 3) After clocking in the last data bit, drive CS high. CS must remain high for 20ns before the next transmission is started. Figure 1 shows a write operation for the transmission of 16 bits. If CS is driven high at any point prior to receiving 16 bits, the transmission is discarded. Figure 2 shows a write operation for the transmission of 24 bits. If CS is driven high at any point prior to receiving 24 bits, the transmission is discarded. Clear (CLR) The MAX5214/MAX5216 feature an asynchronous activelow CLR logic input that sets the DAC output to zero. Driving CLR low clears the contents of both the input and DAC registers and also aborts the on-going SPI command. To allow a new SPI command, drive CLR high. Table 3. Power-Down Modes DAC OPERATION CONDITION A1 A0 DESCRIPTION 0 0 DAC powers up and returns to its previous code setting. 0 1 DAC powers down; OUT is high impedance. 1 0 DAC powers down; OUT connects to ground through an internal 100kI resistor. 1 1 DAC powers down; OUT connects to ground through an internal 1kI resistor. Normal operation Power-down Table 4. MAX5216 Input Code vs. Output Voltage DAC LATCH CONTENTS MSB g LSB ANALOG OUTPUT (VOUT) 1111 1111 1111 1111 VREF x (65,535/65,535) 1000 0000 0000 0000 VREF x (32,768/65,535) = 1/2 VREF 0000 0000 0000 0001 VREF x (1/65,535) 0000 0000 0000 0000 0V Table 5. MAX5214 Input Code vs. Output Voltage DAC LATCH CONTENTS MSB g LSB ANALOG OUTPUT (VOUT) 1111 1111 1111 11XX VREF x (16,383/16,383) 1000 0000 0000 00XX VREF x (8,192/16,383) = 1/2 VREF 0000 0000 0000 01XX VREF x (1/16,383) 0000 0000 0000 00XX 0V www.maximintegrated.com Maxim Integrated 14 MAX5214/MAX5216 Applications Information Power-On Reset (POR) When first power is applied to VDD, the input registers are set to zero so the DAC output is set to code zero. To optimize DAC linearity, wait until the supplies have settled. The MAX5214/MAX5216 output voltage range is 0 to VREF. Power Supplies and Bypassing Considerations Bypass VDD with high-quality 0.1F ceramic capacitors to a low-impedance ground as close as possible to the device. Minimize lead lengths to reduce lead inductance. Connect the GND to the analog ground plane. Layout Considerations Digital and AC transient signals on GND can create noise at the output. Connect GND to the star ground for the DAC system. Refer the remote DAC loads to this system ground for the best possible performance. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the MAX5214/MAX5216 GND. Carefully lay out the traces between channels to reduce AC cross-coupling. Do not use wire-wrapped boards and sockets. Use shielding to improve noise immunity. Do not run analog and digital signals parallel to one another, especially clock signals. Avoid routing digital lines underneath the MAX5214/MAX5216 package. 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Offset Error Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. Gain Error Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time The settling time is the amount of time required from the start of a transition, until the DAC output settles to the new output value within the converter's specified accuracy. Digital Feedthrough Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled. Digital-to-Analog Glitch Impulse Definitions A major carry transition occurs at the midscale point where the MSB changes from low to high and all other bits change from high to low, or where the MSB changes from high to low and all other bits change from low to high. The duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. Integral Nonlinearity (INL) Digital-to-Analog Power-Up Glitch Impulse INL is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. The digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. Differential Nonlinearity (DNL) DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the DNL is greater than -1 LSB, the DAC guarantees no missing codes and is monotonic. www.maximintegrated.com Maxim Integrated 15 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Typical Operating Circuit POWER SUPPLY IN 100pF 100nF MAX6029 OUT 4.7F VDD OUT DAC OUTPUT CLR C MAX5214 MAX5216 CS REF SCLK DIN GND Package Information Chip Information For the latest package outline information and land patterns, go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PROCESS: BiCMOS Ordering Information PART PINRESOLUTION PACKAGE (BITS) MAX5214GUA+ 8 FMAX 14 MAX5216GUA+ 8 FMAX 16 MAX5216BGUA+ 8 FMAX 16 INL MAX (LSB) 1 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 FMAX U8+3 21-0036 90-0092 4 8 Note: All devices are specified over the -40C to +105C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. www.maximintegrated.com Maxim Integrated 16 MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with SPI Interface Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 12/10 Initial release 1 6/13 Added an additional electrical grade for MAX5216. Made multiple text edits and updated the Typical Operating Characteristics. 1-17 2 7/13 Updated General Description, Features, and the Electrical Characteristics. 1, 3 DESCRIPTION -- For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. (c) 2013 Maxim Integrated Products, Inc. 17