Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 7 1Publication Order Number:
SN74LS257B/D
SN74LS257B, SN74LS258B
Quad 2-Input Multiplexer
with 3-State Outputs
The LSTTL/MSI SN74LS257B and the SN74LS258B are Quad
2-Input Multiplexers with 3-state outputs. Four bits of data from two
sources can be selected using a Common Data Select input. The four
outputs present the selected data in true (non-inverted) form. The
outputs may be switched to a high impedance state with a HIGH on the
common Output Enable (EO) Input, allowing the outputs to interface
directly with bus oriented systems. It is fabricated with the Schottky
barrier diode process for high speed and is completely compatible with
all ON Semiconductor TTL families.
•Schottky Process For High Speed
•Multiplexer Expansion By Tying Outputs Together
•Non-Inverting 3-State Outputs
•Input Clamp Diodes Limit High Speed Termination Effects
•Special Circuitry Ensures Glitch Free Multiplexing
•ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –2.6 mA
IOL Output Current – Low 24 mA
LOW
POWER
SCHOTTKY
SOEIAJ
M SUFFIX
CASE 966
16
1
Device Package Shipping
ORDERING INFORMATION
SN74LS257BN 16 Pin DIP 2000 Units/Box
SN74LS257BD SOIC–16 38 Units/Rail
SN74LS257BDR2 SOIC–16 2500/Tape & Reel
SN74LS257BM SOEIAJ–16 See Note 1
SN74LS257BMEL SOEIAJ–16
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
See Note 1
http://onsemi.com
16 Pin DIP 2000 Units/Box
SN74LS258BD SOIC–16 38 Units/Rail
SN74LS258BDR2 SOIC–16 2500/Tape & Reel
SN74LS258BM SOEIAJ–16 See Note 1
SN74LS258BMEL SOEIAJ–16 See Note 1
SN74LS258BN
SOIC
D SUFFIX
CASE 751B
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS257B, SN74LS258B
http://onsemi.com
2
CONNECTION DIAGRAM DIP (TOP VIEW)
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual InLine Package.
14 13 12 11 10 9
123456 7
16 15
8
VCC
S
E0I0c I1c ZcI1d
I0d Zd
I0a I1a ZaI0b I1b ZbGND
SN74LS257B
SN74LS258B
VCC = PIN 16
GND = PIN 8
14 13 12 11 10 9
123456 7
16 15
8
VCC
S
E0I0c I1c ZcI1d
I0d Zd
I0a I1a ZaI0b I1b ZbGND
SN74LS257B, SN74LS258B
http://onsemi.com
3
LOGIC DIAGRAMS
SN74LS257B
E0I0a I1a I0b I1b I0c I1c I0d I1d S
ZaZbZcZd
SN74LS258B
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
E0I0a I1a I0b I1b I0c I1c I0d I1d S
ZaZbZcZd
14 1
26
7
3
4
5
9
11
12
10
13
15
14 1
26
3511 10
13
15
7
4 912
SN74LS257B, SN74LS258B
http://onsemi.com
4
FUNCTIONAL DESCRIPTION
The LS257B and LS258B are Quad 2-Input Multiplexers
with 3-state outputs. They select four bits of data from two
sources each under control of a Common Data Select Input.
When the Select Input is LOW, the I0 inputs are selected and
when Select is HIGH, the I1 inputs are selected. The data on
the selected inputs appears at the outputs in true
(non-inverted) form for the LS257B and in the inverted form
for the LS258B.
The LS257B and LS258B are the logic implementation of
a 4-pole, 2-position switch where the position of the switch
is determined by the logic levels supplied to the Select Input.
The logic equations for the outputs are shown below:
When the Output Enable Input (E0) is HIGH, the outputs
are forced to a high impedance “off” state. If the outputs are
tied together, all but one device must be in the high
impedance state to avoid high currents that would exceed the
maximum ratings. Designers should ensure that Output
Enable signals to 3-state devices whose outputs are tied
together are designed so there is no overlap.
LS257B
Za = E0 • (I1a • S + I0a • S) Zb = E0 • (I1b • S + I0b • S)
Zc = E0 • (I1c • S + I0c • S) Zd = E0 • (I1d • S + I0d • S)
LS258B
Za = E0 • (I1a • S + I0a • S) Zb = E0 • (I1b • S + I0b • S)
Zc = E0 •(I1c • S + I0c • S) Zd = E0 • (I1d • S + I0d • S)
TRUTH TABLE
OUTPUT
ENABLE SELECT
INPUT DATA
INPUTS OUTPUTS
LS257B OUTPUTS
LS258B
EOS I0I1Z Z
H X X X (Z) (Z)
L H X LL H
L H X HH L
L L L XL H
L L H X H L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
(Z) = High Impedance (off)
SN74LS257B, SN74LS258B
http://onsemi.com
5
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.4 3.1 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 12 mA VCC = VCC MIN,
VIN VIL or VIH
VOL Output LOW Voltage 0.35 0.5 V IOL = 24 mA VIN = VIL or VIH
per Truth Table
IOZH Output Off Current — HIGH 20 µA VCC = MAX, VOUT = 2.7 V
IOZL Output Off Current — LOW –20 µA VCC = MAX, VOUT = 0.4 V
I
IH
Input HIGH Current
Other Inputs
S Inputs 20
40 µA VCC = MAX, VIN = 2.7 V
IIH
Other Inputs
S Inputs 0.1
0.2 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
All Inputs –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 2) –30 –130 mA VCC = MAX
Power Supply Current
Total, Output HIGH LS257B
LS258B 10
9.0 mA
ICC Total, Output LOW LS257B
LS258B 16
14 mA VCC = MAX
Total, Output 3-State LS257B
LS258B 19
16 mA
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) See SN74LS251 for Waveforms
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tPLH
tPHL Propagation Delay, Data to Output 10
12 13
15 ns Figures 1 & 2
CL=45
p
F
tPLH
tPHL Propagation Delay, Select to Output 14
14 21
21 ns Figures 1 & 2 CL = 45 pF
tPZH Output Enable Time to HIGH Level 20 25 ns Figures 4 & 5 C
L
= 45 pF
tPZL Output Enable Time to LOW Level 20 25 ns Figures 3 & 5
CL
=
45
F
RL = 667 Ω
tPLZ Output Disable Time to LOW Level 16 25 ns Figures 3 & 5 C
L
= 5.0 pF
tPHZ Output Disable Time from HIGH Level 18 25 ns Figures 4 & 5
CL
=
5
.
0
F
RL = 667 Ω
SN74LS257B, SN74LS258B
http://onsemi.com
6
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
SN74LS257B, SN74LS258B
http://onsemi.com
7
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019

SN74LS257B, SN74LS258B
http://onsemi.com
8
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
M SUFFIX
SOEIAJ PACKAGE
CASE 966–01
ISSUE O
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For additional information, please contact your local
Sales Representative.
SN74LS257B/D
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