54175DMQB - National Semiconductor

TL/F/6557

54174/DM54174/DM74174, 54175/DM54175/DM74175 Hex/Quad D Flip-Flops with Clear

June 1989

54174/DM54174/DM74174, 54175/DM54175/DM74175

Hex/Quad D Flip-Flops with Clear

General Description

These positive-edge triggered flip-flops utilize TTL circuitry

to implement D-type flip-flop logic. All have a direct clear

input, and the quad (175) version features complementary

outputs from each flip-flop.

Information at the D inputs meeting the setup and hold time

requirements is transferred to the Q outputs on the positive-

going edge of the clock pulse. Clock triggering occurs at a

particular voltage level and is not directly related to the tran-

sition time of the positive-going pulse. When the clock input

is at either the high or low level, the D input signal has no

effect at the output.

Features

Y174 contains six flip-flops with single-rail outputs

Y175 contains four flip-flops with double-rail outputs

YBuffered clock and direct clear inputs

YIndividual data input to each flip-flop

YApplications include:

Buffer/storage registers

Shift registers

Pattern generators

YTypical clock frequency 40 MHz

YTypical power dissipation per flip-flop 38 mW

YAlternate Military/Aerospace device (54174, 54175) is

available. Contact a National Semiconductor Sales Of-

fice/Distributor for specifications.

Connection Diagrams

Dual-In-Line Package

TL/F/6557–1

Order Number 54174DMQB, 54174FMQB, DM54174J,

DM54174W or DM74174N

See NS Package Number J16A, N16E or W16A

Dual-In-Line Package

TL/F/6557–2

Order Number 54175DMQB, 54175FMQB, DM54175J,

DM54175W or DM74175N

See NS Package Number J16A, N16E or W16A

Function Table (Each Flip-Flop)

Inputs Outputs

Clear Clock D Q Q²

LXXLH

HH L

LL H

HLXQ

High Level (steady state)

LeLow Level (steady state)

XeDon’t Care

eTransition from low to high level

Q0eThe level of Q before the indicated steady-state input conditions were established.

²e175 only

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range

DM54 and 54 b55§Ctoa

125§C

DM74 0§Ctoa

70§C

Storage Temperature Range b65§Ctoa

150§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter DM54174 DM74174 Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.8 0.8 V

IOH High Level Output Current b0.8 b0.8 mA

IOL Low Level Output Current 16 16 mA

fCLK Clock Frequency (Note 4) 0 30 0 30 MHz

tWPulse Width Clock Low 25 25

(Note 4) Clock High 10 10 ns

Clear 20 20

tSU Data Setup Time (Note 4) 20 20 ns

tHData Hold Time (Note 4) 0 0 ns

tREL Clear Release Time (Note 4) 30 30 ns

TAFree Air Operating Temperature b55 125 0 70 §C

’174 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

12 mA b1.5 V

VOH High Level Output VCC eMin, IOH eMax 2.4 V

Voltage VIL eMax, VIH eMin

VOL Low Level Output VCC eMin, IOL eMax 0.4 V

Voltage VIH eMin, VIL eMax

IIInput Current @Max VCC eMax, VIe5.5V 1mA

Input Voltage

IIH High Level Input Current VCC eMax, VIe2.4V 40 mA

IIL Low Level Input Current VCC eMax, VIe0.4V b1.6 mA

IOS Short Circuit VCC eMax DM54 b20 b57 mA

Output Current (Note 2) DM74 b18 b57

ICC Supply Current VCC eMax (Note 3) 45 65 mA

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time.

Note 3: With all outputs open and all DATA and CLEAR inputs at 4.5V, ICC is measured after a momentary ground, then 4.5V applied to the CLOCK input.

Note 4: TAe25§C and VCC e5V.

’174 Switching Characteristics

at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)

Symbol Parameter From (Input) RLe400X,C

Le15 pF Units

To (Output) Min Max

fMAX Maximum Clock 30 MHz

Frequency

tPLH Propagation Delay Time Clock to 25 ns

Low to High Level Output Any Q

tPHL Propagation Delay Time Clock to 25 ns

High to Low Level Output Any Q

tPHL Propagation Delay Time Clear to 40 ns

High to Low Level Output Any Q

Recommended Operating Conditions

Symbol Parameter DM54175 DM74175 Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.8 0.8 V

IOH High Level Output Current b0.8 b0.8 mA

IOL Low Level Output Current 16 16 mA

fCLK Clock Frequency (Note 1) 0 30 0 30 MHz

tWPulse Width Clock Low 25 25

(Note 1) Clock High 10 10 ns

Clear 20 20

tSU Data Setup Time (Note 1) 20 20 ns

tHData Hold Time (Note 1) 0 0 ns

tREL Clear Release Time (Note 1) 30 30 ns

TAFree Air Operating Temperature b55 125 0 70 §C

Note 1: TAe25§C and VCC e5V.

’175 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

12 mA b1.5 V

VOH High Level Output VCC eMin, IOH eMax 2.4 V

Voltage VIL eMax, VIH eMin

VOL Low Level Output VCC eMin, IOL eMax 0.4 V

Voltage VIH eMin, VIL eMax

IIInput Current @Max VCC eMax, VIe5.5V 1mA

Input Voltage

IIH High Level Input Current VCC eMax, VIe2.4V 40 mA

IIL Low Level Input Current VCC eMax, VIe0.4V b1.6 mA

IOS Short Circuit VCC eMax DM54 b20 b57 mA

Output Current (Note 2) DM74 b18 b57

ICC Supply Current VCC eMax (Note 3) 30 45 mA

’175 Switching Characteristics

at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)

Symbol Parameter From (Input) RLe400X,C

Le15 pF Units

To (Output) Min Max

fMAX Maximum Clock 30 MHz

Frequency

tPLH Propagation Delay Time Clock to 25 ns

Low to High Level Output Any Q or Q

tPHL Propagation Delay Time Clock to 25 ns

High to Low Level Output Any Q or Q

tPLH Propagation Delay Time Clear to 25 ns

Low to High Level Output Any Q

tPHL Propagation Delay Time Clear to 40 ns

High to Low Level Output Any Q

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time.

Note 3: With all outputs open and 4.5V applied to all DATA and CLEAR inputs, ICC is measured after a momentary ground then 4.5V applied to the CLOCK.

Logic Diagrams

174

TL/F/6557–3

175

TL/F/6557–4

Physical Dimensions inches (millimeters)

16-Lead Ceramic Dual-In-Line Package (J)

Order Number 54174DMQB, 54175DMQB, DM54174J or DM54175J

NS Package Number J16A

16-Lead Molded Dual-In-Line Package (N)

Order Number DM74174N or DM74175N

NS Package Number N16E

54174/DM54174/DM74174, 54175/DM54175/DM74175 Hex/Quad D Flip-Flops with Clear

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (W)

Order Number 54174FMQB, 54175FMQB, DM54174W or DM54175W

NS Package Number W16A

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