UC3845D - STMicroelectronics - Datasheet.Directory

L296

L296P

April1993

HIGH CURRENT SWITCHING REGULATORS

.4 AOUTPUT CURRENT

.5.1 V TO 40 V OUTPUT VOLTAGERANGE

.0 TO 100 % DUTY CYCLE RANGE

.PRECISE(±2 %)ON-CHIP REFERENCE

.SWITCHING FREQUENCY UP TO 200 KHz

.VERYHIGH EFFICIENCY (UP TO 90 %)

.VERYFEW EXTERNAL COMPONENTS

.SOFTSTART

.RESETOUTPUT

.EXTERNAL PROGRAMMABLE LIMITING

CURRENT (L296P)

.CONTROL CIRCUIT FOR CROWBAR SCR

.INPUT FOR REMOTE INHIBIT AND

SYNCHRONUS PWM

.THERMAL SHUTDOWN

DESCRIPTION

TheL296andL296Parestepdownpowerswitching

regulatorsdelivering 4 Aat a voltagevariable from

5.1 V to 40 V.

Featuresofthedevicesincludesoftstart,remotein-

hibit, thermal protection, a reset output for micro-

processors and a PWM comparator input for syn-

chronizationin multichip configurations.

The L296Pincudesexternalprogrammablelimiting

current.

TheL296and L296Paremountedin a15-leadMul-

tiwattplasticpowerpackageandrequiresveryfew

externalcomponents.

Efficient operation at switching frequencies up to

200 KHz allows a reductionin the size and costof

external filter components. A voltage sense input

and SCR drive output are provided for optional

crowbar overvoltage protection with an external

SCR.

Multiwatt

(15 lead)

ORDERING NUMBERS :

L296 (Vertical) L296HT (Horizontal)

L296P (Vertical) L296PHT (Horizontal)

PIN CONNECTION (top view)

1/21

PIN FUNCTIONS

N°Name Function

1 CROWBAR INPUT Voltage Sense Input for Crowbar Overvoltage Protection. Normally connected to the

feedback input thus triggering the SCR when V out exceeds nominal by 20 %. May

also monitor the input and a voltage divider can be added to increase the threshold.

Connected to ground when SCR not used.

2 OUTPUT Regulator Output

3 SUPPLY VOLTAGE Unrergulated Voltage Input. An internal Regulator Powers the L296s Internal Logic.

4 CURRENT LIMIT A resistor connected between this terminal and ground sets the current limiter

threshold. If this terminal is left unconnected the threshold is internally set (see

electrical characteristics).

5 SOFT START Soft Start Time Constant. A capacitor is connected between this terminal and ground

to define the soft start time constant. This capacitor also determines the average

short circuit output current.

6 INHIBIT INPUT TTL – Level Remote Inhibit. A logic high level on this input disables the device.

7 SYNC INPUT Multiple L296s are synchronized by connecting the pin 7 inputs together and omitting

the oscillator RC network on all but one device.

8 GROUND Common Ground Terminal

9 FREQUENCY

COMPENSATION A series RC network connected between this terminal and ground determines the

regulation loop gain characteristics.

10 FEEDBACK INPUT The Feedback Terminal on the Regulation Loop. The output is connected directly to

this terminal for 5.1V operation ; it is connected via a divider for higher voltages.

11 OSCILLATOR A parallel RC networki connected to this terminal determines the switching frequency.

This pin must be connected to pin 7 input when the internal oscillator is used.

12 RESET INPUT Input of the Reset Circuit. The threshold is roughly 5 V. It may be connected to the

feedback point or via a divider to the input.

13 RESET DELAY A capacitor connected between this terminal and ground determines the reset signal

delay time.

14 RESET OUTPUT Open collector reset signal output. This output is high when the supply is safe.

15 CROWBAR OUTPUT SCR gate drive output of the crowbar circuit.

BLOCK DIAGRAM

L296 - L296P

2/21

CIRCUIT OPERATION

(refer to the block diagram)

The L296 and L296P are monolithic stepdown

switching regulatorsprovidingoutputvoltages from

5.1Vto 40V and delivering 4A.

Theregulationloopconsistsofasawtoothoscillator,

erroramplifier,comparatorandtheoutputstage.An

error signal is produced by comparing the output

voltagewithaprecise5.1Von-chipreference(zener

zaptrimmed to±2%).Thiserrorsignalisthencom-

paredwiththesawtoothsignalto generatethe fixed

frequencypulsewidthmodulatedpulseswhichdrive

theoutputstage.Thegainandfrequencystabilityof

theloopcanbeadjustedbyan externalRC network

connectedtopin9.Closingtheloopdirectlygivesan

outputvoltageof5.1V.Highervoltagesareobtained

byinserting a voltagedivider.

Outputovercurrents at switch on are preventedby

the soft start function. The error amplifier output is

initially clamped by the externalcapacitorCss and

allowedto rise, linearly, asthis capacitor is charged

bya constantcurrentsource.

Outputoverloadprotectionis providedin theformof

a current limiter. The load current is sensedby an

internal metal resistor connectedto a comparator.

When the loadcurrent exceedsa preset threshold

this comparator sets a flip flop which disables the

outputstageanddischargesthesoftstartcapacitor.

A second comparator resets the flip flop when the

voltage across the softstart capacitorhas fallen to

0.4V.The output stage is thus re-enabledand the

output voltage rises under control of the soft start

network.If theoverloadcondition is still presentthe

limiterwill triggeragain when the thresholdcurrent

is reached. The averageshort circuit current islim-

ited to a safe value by the dead time introduced by

the softstart network.

The reset circuit generates an output signal when

the supply voltage exceeds a threshold pro-

grammedbyan externaldivider. Theresetsignalis

generatedwitha delaytime programmed byan ex-

ternal capacitor. When the supply falls below the

threshold the reset output goes low immediately.

Thereset outputis anopen collector.

The scrowbar circuit sensesthe output voltageand

the crowbaroutput can providea currentof 100mA

toswitchonanexternalSCR. ThisSCRis triggered

when the output voltage exceeds the nominal by

20%. There is no internal connection between the

outputandcrowbar sense inputthereforethe crow-

bar can monitor either the input or the output.

ATTL -level inhibitinputisprovidedforapplications

suchasremoteon/offcontrol.Thisinputisactivated

byhighlogiclevel anddisablescircuitoperation.Af-

ter an inhibit the L296 restarts under control of the

soft startnetwork.

Thethermaloverload circuit disables circuit opera-

tion when the junction temperature reaches about

150 °C andhashysteresisto preventunstablecon-

ditions.

Figure 1 : Reset Output Waveforms

L296 - L296P

3/21

Figure 2 : SoftStartWaveforms

Figure 3 : CurrentLimiter Waveforms

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

ViInput Voltage (pin 3) 50 V

Vi–V

2Input to Output Voltage Difference 50 V

V2Output DC Voltage

Output Peak Voltage at t = 0.1 µsec f = 200KHz –1

–7 V

12 Voltage at Pins 1, 12 10 V

V15 Voltage at Pin 15 15 V

V4,V

13 Voltage at Pins 4, 5, 7, 9 and 13 5.5 V

V10,V

6Voltage at Pins 10 and 6 7 V

V14 Voltage at Pin 14 (I14 ≤1 mA) Vi

I9Pin 9 Sink Current 1 mA

I11 Pin 11 Source Current 20 mA

I14 Pin 14 Sink Current (V14 < 5 V) 50 mA

Ptot Power Dissipation at Tcase ≤90 °C20W

stg Junction and Storage Temperature – 40 to 150 °C

L296 - L296P

4/21

THERMAL DATA

Symbol Parameter Value Unit

Rth j-case Thermal Resistance Junction-case Max. 3 °C/W

Rth j-amb Thermal Resistance Junction-ambient Max. 35 °C/W

ELECTRICAL CHARACTERISTICS

(refer to the test circuits Tj=25

C, Vi= 35V, unless otherwise specified)

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

DYNAMIC CHARACTERISTICS (pin 6 to GND unless otherwise specified)

VoOutput Voltage Range Vi= 46V, Io=1A V

ref 40 V 4

ViInput Voltage Range Vo=V

ref to 36V, Io≤3A 9 46 V 4

ViInput Voltage Range Note (1), Vo=V

REF to 36V Io=4A 46 V 4

∆V

oLine Regulation Vi=10V to 40V, Vo=V

ref,I

o=2A 15 50 mV 4

∆V

oLoad Regulation Vo=V

ref

Io=2Ato4A

o= 0.5A to 4A 10

15 30

mV 4

Vref Internal Reference Voltage (pin 10) Vi= 9V to 46V, Io= 2A 5 5.1 5.2 V 4

∆Vref

∆TAverage Temperature Coefficient

of Reference Voltage Tj=0°C to 125°C, Io= 2A 0.4 mV/°C

VdDropout Voltage Between Pin 2

and Pin 3 Io=4A

o=2A 2

1.3 3.2

2.1 V

I2L Current Limiting Threshold (pin 2) L296 - Pin 4 Open,

Vi= 9V to 40V, Vo=V

ref to 36V 4.5 7.5 A 4

L296P - Vi= 9V to 40V, Vo=V

ref

Pin 4 Open

RIim = 22kΩ5

2.5 7

4.5

SH Input Average Current Vi= 46V, Output Short-circuited 60 100 mA 4

ηEfficiency Io=3A

o=V

ref

Vo= 12V 75

SVR Supply Voltage Ripple Rejection ∆Vi=2V

rms,f

ripple = 100Hz

Vo=V

ref,I

o=2A 50 56 dB 4

f Switching Frequency 85 100 115 kHz 4

∆f

∆Vi

Voltage Stability of Switching

Frequency Vi= 9V to 46V 0.5 % 4

∆f

∆Tj

Temperature Stability of Switching

Frequency Tj=0°C to 125°C1%4

max Maximum Operating Switching

Frequency Vo=V

ref,I

o= 1A 200 kHz –

Tsd Thermal Shutdown Junction

Temperature Note (2) 135 145 °C–

DC CHARACTERISTICS

I3Q Quiescent Drain Current Vi= 46V, V7= 0V, S1 : B, S2 : B

V6=0V

6=3V 66

30 85

–I

2L Output Leakage Current Vi= 46V, V6= 3V, S1 : B, S2 : A,

V7=0V 2mA

Note (1) :Using min. 7 A schottky diode.

(2) :Guaranteed by design,not 100 % tested in production.

L296 - L296P

5/21

ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

SOFT START

I5so Source Current V6= 0V, V5= 3V 80 130 150 µA6b

5si Sink Current V6= 3V, V5= 3V 50 70 120 µA6b

INHIBIT

V6L

V6H

Input Voltage

Low Level

High Level

Vi= 9V to 46V, V7= 0V,

S1 : B, S2 : B – 0.3

20.8

5.5

V6a

–I

Input Current

with Input Voltage

Low Level

High Level

Vi= 9V to 46V, V7= 0V,

S1 : B, S2 : B

V6= 0.8V

V6=2V 10

µA6a

ERROR AMPLIFIER

V9H High Level Output Voltage V10 = 4.7V, I9= 100µA,

S1 : A, S2 : A 3.5 V 6c

V9L Low Level Output Voltage V10 = 5.3V, I9= 100µA,

S1 : A, S2 : E 0.5 V 6c

I9si Sink Output Current V10 = 5.3V, S1 : A, S2 : B 100 150 µA6c

–I

9so Source Output Current V10 = 4.7V, S1 : A, S2 : D 100 150 µA6c

10 Input Bias Current V10 = 5.2V, S1 : B

V10 = 6.4V, S1 : B, L296P 2

210

10 µA

µA6c

GvDC Open Loop Gain V9= 1V to 3V, S1 : A, S2 : C 46 55 dB 6c

OSCILLATOR AND PWM COMPARATOR

–I

7Input Bias Current of

PWM Comparator V7= 0.5V to 3.5V 5 µA6a

–I

11 Oscillator Source Current V11 = 2V, S1 : A, S2 : B 5 mA

RESET

V12 R Rising Threshold Voltage Vi= 9V to 46V,

S1 : B, S2 : B

Vref

-150mV Vref

-100mV Vref

-50mV V6d

12 F Falling Threshold Voltage 4.75 Vref

-150mV Vref

-100mV V6d

13 D Delay Thershold Voltage V12 = 5.3V, S1 : A, S2 : B 4.3 4.5 4.7 V 6d

V13 H Delay Threshold Voltage

Hysteresis 100 mV 6d

V14 S Output Saturation Voltage I14 = 16mA, V12 = 4.7V, S1, S2 : B 0.4 V 6d

I12 Input Bias Current V12 =0VtoV

ref,S1:B,S2:B 1 3 µA6d

–I

13 so

I13 si Delay Source Current

Delay Sink Current

V13 = 3V, S1 : A, S2 : B

V12 = 5.3V

V12 = 4.7V 70

10 110 140 µA

I14 Output Leakage Current Vi= 46V, V12 = 5.3V, S1 : B, S2 : A 100 µA6d

CROWBAR

V1Input Threshold Voltage S1 : B 5.5 6 6.4 V 6b

V15 Output Saturation Voltage Vi= 9V to 46V, Vi= 5.4V,

I15 = 5mA, S1 : A 0.2 0.4 V 6b

I1Input Bias Current V1= 6V, S1 : B 10 µA6b

–I

15 Output Source Current Vi= 9V to 46V, V1= 6.5V,

V15 = 2V, S1 : B 70 100 mA 6b

L296 - L296P

6/21

Figure 4 : DynamicTest Circuit

C7,C8 : EKR(ROE)

L1 : L = 300 µH at8 A Coretype : MAGNETICS58930 - A2 MPP

N°turns :43 Wire Gauge :1 mm (18 AWG) COGEMA 946044

(*) Minimumsuggested value (10 µF) toavoid oscillations. Ripple consideration leads to typical value of 1000 µF or higher.

Figure5 : PC.Board andComponent Layoutof the Circuit of Figure4 (1:1scale)

L296 - L296P

7/21

Figure 6 : DC Test Circuits.

Figure 6a. Figure 6b.

Figure 6c.

Figure 6d.

1 - Set V10 FORV9=1V

2 - Change V10 to obtain V9=3V

3-G

V=DV9=2V

∆V10 ∆V10

L296 - L296P

8/21

Figure 7 : QuienscentDrain Current vs. Supply

Voltage(0 %Duty Cycle - see fig. 6a). Figure 8 : QuienscentDrain Current vs.Supply

Voltage(100 % Duty Cyclesee fig. 6a).

Figure 9 : QuiescentDrain Current vs. Junction

Temperature (0 % DutyCycle -

seefig.6a).

Figure 10 : QuiescentDrain Current vs. Junction

Temperature(100 % Duty Cycle -

see fig. 6a).

Figure 11 : ReferenceVoltage (pin 10) vs. VI

(seefig. 4). Figure12: ReferenceVoltage(pin 10)vs. Junction

Temperature(see fig. 4).

L296 - L296P

9/21

Figure 13 : OpenLoop FrequencyandPhase

Responseof Error Amplifier

(see fig. 6c).

Figure 14 : Switching Frequency vs. Input

Voltage(see fig.4).

Figure 15 : SwitchingFrequency vs. Junction

Temperature(seefig. 4). Figure 16 : Switching Frequency vs. R1

(see fig. 4).

Figure 17 : LineTransient Response(see fig.4). Figure 18 : Load Transient Response (see fig.4).

L296 - L296P

10/21

Figure 19 : SupplyVoltageRipple Rejectionvs.

Frequency(see fig. 4). Figure 20 : DropoutVoltageBetweenPin3 and

Pin2 vs. Current at Pin 2.

Figure 21 : DropoutVoltageBetweenPin 3 and

Pin 2 vs. Junction Temperature. Figure 22 : Power DissipationDerating Curve.

Figure 23 : PowerDissipation(device only) vs.

Input Voltage. Figure 24 : Power Dissipation(device only)vs.

Inputvoltage.

L296 - L296P

11/21

Figure 25 : PowerDissipation(device only) vs.

OutputVoltage(seefig. 4). Figure 26 : Power Dissipation(device only)vs.

OutputVoltage(see fig. 4).

Figure 28 : Efficiencyvs. OutputCurrent.

Figure 29 : Efficiency vs. OutputVoltage. Figure 30 : Efficiencyvs. OutputVoltage.

Figure27: VoltageandCurrentWaveformsatPin2

(seefig. 4).

L296 - L296P

12/21

Figure 31 : CurrentLimiting Thresholdvs. Rpin 4

(L296Ponly). Figure32: Current LimitingThresholdvs. Junction

Temperature.

Figure 33 : CurrentLimiting Thresholdvs.

SupplyVoltage.

L296 - L296P

13/21

APPLICATION INFORMATION

Figure 34 : TypicalApplicationCircuit.

(*) Minimum value (10 µF) to avoid oscillations ; ripple consideration leadsto typical value of 1000µF orhigher L1 : 58930 - MPP COGEMA

946044 ; GUP 20 COGEMA 946045

SUGGESTED INDUCTOR (L1)

Core Type No Turns Wire Gauge Air Gap

Magnetics 58930 – A2MPP 43 1.0 mm –

Thomson GUP 20 x 16 x 7 65 0.8 mm 1 mm

Siemens EC 35/17/10 (B6633& – G0500 – X127) 40 2 x 0.8 mm –

VOGT 250 µH Toroidal Coil, Part Number 5730501800

Resistor Values for Standard Output Voltages

V0R8 R7

12 V

15 V

18 V

24 V

4.7 KΩ

6.2 KΩ

9.1 KΩ

12 KΩ

18 KΩ

L296 - L296P

14/21

Figure35 : P.C.Boardand Component Layoutof the Circuit of fig. 34 (1:1 scale)

SELECTION OF COMPONENT VALUES (see fig. 34)

Component Recommended

Value Purpose Allowed Rage Notes

Min. Max.

R2 –

100 kΩSet Input Voltage

Threshold for Reset. –220kΩR1/R2 Vi min

5−1

If output voltage is sensed R1 and

R2 may be limited and pin 12

connected to pin 10.

R3 4.3 kΩSets Switching Frequency 1 kΩ100kΩ

R4 10 kΩPull-down Resistor 22kΩMay be omitted and pin 6 grounded

if inhibit not used.

R5 15 kΩFrequency Compensation 10kΩ

R6 Collector Load For Reset

Output VO

0.05A Omitted if reset function not used.

R8 –

4.7 kΩDivider to Set Output

Voltage –

––

1kΩR7/R8 = VO−VREF

VREF -

Riim – Sets Current Limit Level 7.5kΩIf Riim is omitted and pin 4 left open

the current limit is internally fixed.

C1 10 µF Stability 2.2µF

C2 2.2 µF Sets Reset Delay – – Omitted if reset function not used.

C3 2.2 nF Sets Switching Frequency 1 nF 3.3nF

C4 2.2 µF Soft Start 1 µF – Also determines average short

circuit current.

C5 33 nF Frequency Compensation

C6 390 pF High Frequency

Compensation – – Not required for 5 V operation.

C7, C8

L1 100 µF

300 µHOutput Filter –

100µH–

Q1 Crowbar Protection The SCR must be able to withstand

the peak discharge current of the

output capacitor and the short

circuit current of the device.

D1 Recirculation Diode 7A Schottky or 35 ns trr Diode.

L296 - L296P

15/21

Figure 36 : A Minimal5.1 V Fixed Regulator.Very Few Componentsare Required.

Figure 37 : 12 V/10 A Power Supply.

L296 - L296P

16/21

Figure 38 : ProgrammablePowerSupply.

Vo= 5.1 to 15 V

Io= 4 A max. (min. load current = 100 mA)

ripple ≤20mV

load regulation (1 A to 4 A)= 10 mV(V o=5.1V)

lineregulation (220 V ±15 % and to Io= 3 A) = 15 mV(V o= 5.1 V)

Figure 39 : PreregulatorforDistributedSupplies.

(*)L2 and C2 are necessary to reduce the switching frequency spikes.

L296 - L296P

17/21

Figure 40 : InMultiple SuppliesSeveralL296s

canbe SynchronizedAs Shown. Figure 41 : VoltageSensing for RemoteLoad.

Figure 42 : A 5.1V/15 V/24 V Multiple Supply. Notethe Synchronization of theThree L296s.

L296 - L296P

18/21

Figure 43 : 5.1V/2APower SupplyusingExternal

Limiting CurrentResistor andCrow-

bar Protectionon the Supply Voltage

(L296Ponly)

SOFT-START AND REPETITIVE POWER-ON

Whenthedeviceisrepetitivelypowered-on,thesoft-

startcapacitor, CSS, must be dischargedrapidly to

ensurethateachstartis”soft”.Thiscanbeachieved

economicallyusingtheresetcircuit,asshowninFig-

ure44.

In this circuit thedividerR1, R2 connectedto pin 12

determines the minimum supply voltage, below

which theopencollectortransistoratthepin14out-

put discharges CSS.

Figure44

Figure 45

Figure 46

Theapproximatedischargetimesobtainedwith this

circuit are :

CSS (µF) tDIS (µs)

2.2

4.7

200

300

600

Ifthesetimesarestilltoolong,anexternalPNPtran-

sistor may be added, as shown in Figure45 ; with

this circuit discharge times of a few microseconds

may be obtained.

HOW TO OBTAIN BOTH RESET AND

POWER FAIL

Figure46illustrateshowitispossibletoobtainatthe

same time both the power fail and reset functions

simply by addingonediode(D) andoneresistor(R).

In this case the Reset delay time (pin 13) can only

start when theoutputvoltageis VO≥VREF - 100mV

and the voltageaccross R2 is higherthan 4.5V.

With thehysteresisresistor itis possibletofix thein-

put pin 12 hysteresis in order to increaseimmunity

to the 100Hz ripple present on the supplyvoltage.

Moreover, the power fail and reset delay time are

automaticallylocked to the soft-start.Soft-startand

delayedresetare thustwo sequentialfunctions.

The hysteresis resistor should be In the range of

aboit 100kΩandthe pull-up resistor of 1 to 2.2kΩ.

L296 - L296P

19/21

PMMUL15V.EPS

MULTIWATT15 VERTICAL PACKAGE MECHANICAL DATA

Dimensions Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 5 0.197

B 2.65 0.104

C 1.6 0.063

D 1 0.039

E 0.49 0.55 0.019 0.022

F 0.66 0.75 0.026 0.030

G 1.14 1.27 1.4 0.045 0.050 0.055

G1 17.57 17.78 17.91 0.692 0.700 0.705

H1 19.6 0.772

H2 20.2 0.795

L 22.1 22.6 0.870 0.890

L1 22 22.5 0.866 0.886

L2 17.65 18.1 0.695 0.713

L3 17.25 17.5 17.75 0.679 0.689 0.699

L4 10.3 10.7 10.9 0.406 0.421 0.429

L7 2.65 2.9 0.104 0.114

M 4.2 4.3 4.6 0.165 0.169 0.181

M1 4.5 5.08 5.3 0.177 0.200 0.209

S 1.9 2.6 0.075 0.102

S1 1.9 2.6 0.075 0.102

Dia. 1 3.65 3.85 0.144 0.152

MUL15V.TBL

L296 - L296P

20/21

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for

the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its

use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifica-

tions mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information pre-

viously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of SGS-THOMSON Microelectronics.

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L296 - L296P

21/21

L4960

2.5APOWER SWITCHING REGULATOR

2.5AOUTPUTCURRENT

5.1V TO 40V OPUTPUT VOLTAGE RANGE

PRECISE (±2%)ON-CHIP REFERENCE

HIGHSWITCHING FREQUENCY

VERYHIGH EFFICIENCY (UPTO 90%)

VERY FEW EXTERNALCOMPONENTS

SOFTSTART

INTERNAL LIMITING CURRENT

THERMAL SHUTDOWN

DESCRIPTION

The L4960 is a monolithicpower switching regula-

tor delivering2.5A at avoltage variable from 5V to

40V in stepdown configuration.

Featuresof thedevice include currentlimiting, soft

start,thermal protection and 0 to 100% duty cycle

for continuousoperation mode.

April 1995

ORDERING NUMBERS: L4960 (Vertical)

L4960H (Horizontal)

HEPTAWATT

BLOCK DIAGRAM

TheL4960is mountedinaHeptawattplasticpower

package and requires very few external compo-

nents.

Efficient operation at switching frequencies up to

150KHz allows a reductionin the size and cost of

externalfilter components.

1/15

PIN CONNECTION (Top view)

2/15

N°NAME FUNCTION

1 SUPPLY VOLTAGE Unregulated voltage input. An internal regulator powers the

internal logic.

2 FEEDBACK INPUT The feedback terminal of the regulation loop. The output is

connected directly to this terminal for 5.1V operation; it is

connected via a dividerfor higher voltages.

3 FREQUENCY

COMPENSATION A series RC network connected between this terminal and

ground determines the regulation loop gain characteristics.

4 GROUND Common ground terminal.

5 OSCILLATOR A parallel RC network connected to this terminal determines the

switching frequency.

6 SOFT START Soft start time constant. A capacitor is connected between this

terminal and ground to define the soft start time constant. This

capacitor also determines the average short circuit output

current.

7 OUTPUT Regulator output.

PIN FUNCTIONS

Symbol Parameter Value Unit

V1Input voltage 50 V

V1-V

7Input to output voltage difference 50 V

V7Negative output DC voltage -1 V

Negative output peak voltage at t = 0.1µs; f = 100KHz -5 V

V3,V

6Voltage at pin 3 and 6 5.5 V

V2Voltage at pin 2 7V

Pin 3 sink current 1 mA

I5Pin 5 source current 20 mA

Ptot Power dissipation at Tcase ≤90°C15 W

Tj,T

stg Junction and storage temperature -40 to 150 °C

ABSOLUTE MAXIMUM RATINGS

L4960

Symbol Parameter Test Conditions Min. Typ. Max. Unit

DYNAMIC CHARACTERISTICS

VoOutput voltage range Vi= 46V Io=1A V

ref 40 V

ViInput voltage range Vo=V

ref to 36V Io= 2.5A 9 46 V

∆VoLine regulation Vi= 10V to 40V Vo=V

ref Io=1A 15 50 mV

∆V

oLoad regulation Vo=V

ref Io= 0.5Ato 2A 10 30 mV

Vref Internal reference voltage

(pin 2) Vi= 9V to 46V Io= 1A 5 5.1 5.2 V

∆Vref

∆TAverage temperature

coefficient of refer voltage Tj=0°C to 125°C

Io=1A 0.4 mV/°C

VdDropout voltage Io= 2A 1.4 3 V

Iom Maximum operating load

current Vi= 9V to 46V

Vo=V

ref to 36V 2.5 A

I7L Current limiting threshold

(pin 7) Vi= 9V to 46V

Vo=V

ref to 36V 3 4.5 A

ISH Input average current Vi= 46V; output short-circuit 30 60 mA

ηEfficiency f = 100KHz Vo=V

ref 75 %

Io=2A V

o= 12V 85 %

SVR Supply voltage ripple

rejection ∆Vi=2V

rms

fripple = 100Hz

Vo=V

ref Io = 1A

50 56 dB

f Switching frequency 85 100 115 KHz

∆f

∆Vi

Voltage stability of

switching frequency Vi= 9V to 46V 0.5 %

∆f

∆Tj

Temperature stability of

switching frequency Tj=0°C to 125°C1%

max Maximum operating

switching frequency Vo=V

ref Io= 2A 120 150 KHz

Tsd Thermal shutdown

junction temperature 150 °C

ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj=25°C, Vi= 35V, unless otherwise

specified)

Symbol Parameter Value Unit

Rth j-case Thermalresistance junction-case max 4 °C/W

Rth j-amb Thermalresistance junction-ambient max 50 °C/W

THERMAL DATA

3/15

L4960

4/15

Symbol Parameter TestConditions Min. Typ. Max. Unit

DC CHARACTERISTICS

I1Q Quiescent draincurrent 100% duty cycle

pins 5 and 7 open Vi= 46V

30 40 mA

0% duty cycle 15 20 mA

-I7L Output leakagecurrent 0% duty cycle 1 mA

SOFT START

I6SO Source current 100 140 180 µA

I6SI Sink current 50 70 120 µA

ERROR AMPLIFIER

V3H High leveloutput voltage V2= 4.7V I3= 100µA3.5 V

V3L Low leveloutput voltage V2= 5.3V I3= 100µA0.5 V

I3SI Sink output current V2= 5.3V 100 150 µA

-I3SO Source outputcurrent V2= 4.7V 100 150 µA

I2Input bias current V2= 5.2V 2 10 µA

GvDC open loop gain V3=1Vto3V 46 55 dB

OSCILLATOR

-I5Oscillator source current 5 mA

ELECTRICAL CHARACTERISTICS (continued)

L4960

CIRCUIT OPERATION (refer to the block diagram)

TheL4960isamonolithicstepdownswitchingregu-

latorprovidingoutputvoltagesfrom5.1Vto40Vand

delivering 2.5A.

The regulation loop consistsof a sawtooth oscilla-

tor, error amplifier, comparator and the output

stage.An errorsignalisproducedbycomparingthe

output voltage with a precise 5.1V on-chip refer-

ence (zener zap trimmedto ±2%).

Thiserrorsignalisthencomparedwiththesawtooth

signal to generatethe fixedfrequency pulse width

modulatedpulseswhich drivethe output stage.

The gain andfrequency stability of the loop can be

adjusted by an external RC network connected to

pin 3. Closing the loop directly gives an output

voltage of 5.1V. Higher voltages are obtained by

inserting a voltage divider.

Outputovercurrents at switch on are preventedby

the soft start function. The error amplifier output is

initially clamped by the external capacitor Css and

allowedto rise, linearly,asthiscapacitorischarged

by a constantcurrent source. Output overloadpro-

tection is providedin the form of a current limiter.

The load current is sensed by an internal metal

resistor connectedto a comparator. Whenthe load

currentexceedsa presetthresholdthiscomparator

sets a flip flop which disables the output stageand

dischargesthe soft startcapacitor. A second com-

parator resets the flipflop when the voltage across

the soft start capacitorhas fallen to 0.4V.

The output stage is thus re-enabled and the output

voltage risesunder controlof the soft startnetwork.

If the overload condition is still present the limiter

will trigger again when the threshold current is

reached.Theaverageshortcircuitcurrentislimited

to a safe value by the dead time introduced by the

softstart network.The thermaloverload circuit dis-

ables circuit operation when the junction tempera-

ture reaches about 150°C and has hysteresis to

preventunstable conditions.

Figure 1. Soft start waveforms

Figure 2. Current limiter waveforms

5/15

L4960

6/15

Figure 4. Quiescent drain

current vs.supply voltage (0%

duty cycle)

Figure 5. Quiescent drain

current vs. supply voltage

(100% duty cycle)

Figure 6. Quiescent drain

current vs. junction tem-

perature (0% duty cycle)

Figure 3. Test and applicationcircuit

C6, C7: EKR (ROE)

L1 = 150µH at 5A(COGEMA 946042)

CORE TYPE: MAGNETICS 58206-A2 MPP

N°TURNS 45, WIRE GAUGE: 0.8mm (20 AWG)

L4960

Figure 7. Quiescent drain

current vs. junction tem-

perature (100% duty cycle)

Figure 8. Reference voltage

(pin 2) vs. ViFigure 9. Reference voltage

versus junction temperature

(pin 2)

Figure 10. Open loop fre-

quency and phase responde

of error amplifier

Figure 11. Switching fre-

quency vs. input voltage Figure 12. Switching fre-

quency vs. junction tem-

perature

Figure 13. Switching fre-

quencyvs.R2(seetest circuit) Figure 14. Line transient

response Figure 15. Load transient

response

7/15

L4960

8/15

Figure 16. Supply voltage

ripple rejection vs. frequency Figure 17. Dropout voltage

between pin 1 and pin 7 vs.

current at pin 7

Figure 18. Dropout voltage

between pin 1 and 7 vs.

junction temperature

Figure 19. Power dissipation

derating curve Figure 20. Efficiency vs.

output current Figure 21. Efficiency vs.

output current

Figure 22. Efficiency vs.

output current Figure 23. Efficiency vs.

output voltage

L4960

APPLICATION INFORMATION

Figure 24. Typical application circuit

C1,C

: EKR (ROE)

D1: BYW80 OR 5ASCHOTTKY DIODE

SUGGESTED INDUCTOR: L1= 150µHat5A

CORE TYPE: MAGNETICS 58206- A2 -MPP

N°TURNS: 45, WIRE GAUGE: 0.8mm (20 AWG), COGEMA 946042

U15/GUP15: N°TURNS: 60, WIRE GAUGE: 0.8mm (20 AWG), AIR GAP: 1mm, COGEMA 969051.

Figure 25. P.C. board and component layout of

the Fig. 24 (1 : 1 scale)

Resistor values for

standard output voltages

VoR3 R4

12V

15V

18V

24V

4.7KΩ

6.2KΩ

9.1KΩ

12KΩ

18KΩ

9/15

L4960

10/15

APPLICATION INFORMATION

Figure 26. A minimal 5.1V fixed regulator; Very few component are required

* COGEMA946042 (TOROID CORE)

969051 (U15 CORE)

** EKR (ROE)

Figure 27. Programmable power supply

Vo= 5.1V to 15V

Io= 2.5Amax

Loadregulation (1A to 2A) = 10mV (Vo= 5.1V)

L4960

APPLICATION INFORMATION (continued)

Figure 28. Microcomputer supply with + 5.1V, -5V, +12V and -12V outputs

11/15

L4960

12/15

APPLICATION INFORMATION (continued)

Figure 29. DC-DC converter5.1V/4A,±12V/2.5A;a suggestionhowtosynchronize anegativeoutput

L1, L3 = COGEMA946042 (969051)

L2 = COGEMA 946044 (946045)

D1,D

3= BYW80

Figure 30. - In multiple supplies several L4960s can besynchronizedas shown

L4960

APPLICATION INFORMATION (continued)

Figure 31. Regulator for distributed supplies

MOUNTING INSTRUCTION

Thepowerdissipatedinthecircuitmustberemoved

by addingan external heatsink.

Thanks to the Heptawatt package attaching the

hetsink is very simple, a screw or a compression

spring (clip)being sufficient. Betweenthe heatsink

and thepackageit isbettertoinserta layerofsilicon

grease, to optimize the thermal contact, no electri-

cal isolationis needed between the two surfaces.

Figure 32. Mounting example

13/15

L4960

14/15

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.8 0.189

C 1.37 0.054

D 2.4 2.8 0.094 0.110

D1 1.2 1.35 0.047 0.053

E 0.35 0.55 0.014 0.022

F 0.6 0.8 0.024 0.031

F1 0.9 0.035

G 2.41 2.54 2.67 0.095 0.100 0.105

G1 4.91 5.08 5.21 0.193 0.200 0.205

G2 7.49 7.62 7.8 0.295 0.300 0.307

H2 10.4 0.409

H3 10.05 10.4 0.396 0.409

L 16.97 0.668

L1 14.92 0.587

L2 21.54 0.848

L3 22.62 0.891

L5 2.6 3 0.102 0.118

L6 15.1 15.8 0.594 0.622

L7 6 6.6 0.236 0.260

M 2.8 0.110

M1 5.08 0.200

Dia 3.65 3.85 0.144 0.152

HEPTAWATT PACKAGE MECHANICAL DATA

L4960

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products arenot authorized for useas critical components in life supportdevices or systems without express

written approvalof SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil -France - Germany - Hong Kong - Italy - Japan- Korea - Malaysia -Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan -Thaliand - United Kingdom - U.S.A.

15/15

L4960

L4962

1.5APOWER SWITCHING REGULATOR

1.5AOUTPUTCURRENT

5.1VTO 40V OUTPUT VOLTAGE RANGE

PRECISE (±2%) ON-CHIP REFERENCE

HIGH SWITCHING FREQUENCY

VERYHIGH EFFICIENCY (UP TO 90%)

VERYFEW EXTERNAL COMPONENTS

SOFTSTART

INTERNALLIMITINGCURRENT

THERMAL SHUTDOWN

DESCRIPTION

The L4962is a monolithic powerswitching regula-

tor delivering 1.5A at a voltagevariable from5V to

40Vin stepdown configuration.

Featuresof the device include current limiting, soft

start,thermal protection and 0 to 100% duty cycle

for continuousoperating mode.

March 1996

ORDERING NUMBERS : L4962/A(12+2+2Powerdip)

L4962E/A (Heptawatt)

L4962EH/A (Horizontal

Heptawatt)

TheL4962ismountedina16-leadPowerdipplastic

packageandHeptawattpackageandrequiresvery

few externalcomponents.

Efficient operation at switching frequencies up to

150KHz allows a reduction in the size and cost of

externalfilter components.

HEPTAWATT

POWERDIP

(12 + 2 + 2)

BLOCK DIAGRAM

Pin X = Powerdip

Pin (X) = Heptawatt

1/15

PIN CONNECTION (Top view)

2/15

Symbol Parameter Heptawatt Powerdip

Rth j-case Thermal resistance junction-case max 4°C/W -

Rth j-pins Thermal resistance junction-pins max - 14°C/W

Rth j-amb Thermal resistance junction-ambient max 50°C/W 80°C/W*

* Obtained with the GND pins soldered to printed circuit with minimized copper area.

THERMAL DATA

HEPTAWATT POWERDIP NAME FUNCTION

1 7 SUPPLY VOLTAGE Unregulated voltage input. An internal regulator powers

the internallogic.

2 10 FEEDBACK INPUT The feedback terminal of theregulation loop. The output

is connected directly to this terminal for 5.1V operation;

it is connected via a divider for higher voltages.

3 11 FREQUENCY

COMPENSATION A series RC network connected between this terminal

and ground determines the regulation loop gain

characteristics.

PIN FUNCTIONS

Symbol Parameter Value Unit

V7Inputvoltage 50 V

V7-V

2Inputto output voltagedifference 50 V

V2Negativeoutput DC voltage -1 V

Output peak voltage at t = 0.1µs; f = 100KHz -5 V

V11,V

15 Voltage at pin 11,15 5.5 V

V10 Voltage at pin 10 7 V

I11 Pin 11 sink current 1 mA

I14 Pin 14 source current 20 mA

Ptot Power dissipation at Tpins ≤90°C (Powerdip)

Tcase ≤90°C (Heptawatt) 4.3

15 W

Tj,T

stg Junctionand storage temperature -40 to 150 °C

ABSOLUTE MAXIMUM RATINGS

L4962

Symbol Parameter Test Conditions Min. Typ. Max. Unit

DYNAMIC CHARACTERISTICS

VoOutput voltage range Vi= 46V Io=1A V

ref 40 V

ViInput voltage range Vo=V

ref to 36V Io= 1.5A 9 46 V

∆VoLine regulation Vi= 10V to 40V Vo=V

ref Io=1A 15 50 mV

∆V

oLoad regulation Vo=V

ref Io= 0.5A to 1.5A 8 20 mV

Vref Internal reference voltage

(pin 10) Vi= 9V to 46V Io= 1A 5 5.1 5.2 V

∆Vref

∆TAverage temperature

coefficient of refer. voltage Tj=0°C to 125°C

Io=1A 0.4 mV/°C

VdDropout voltage Io= 1.5A 1.5 2 V

Iom Maximum operating load

current Vi= 9V to 46V

Vo=V

ref to 36V 1.5 A

I2L Current limiting threshold

(pin 2) Vi= 9V to 46V

Vo=V

ref to 36V 2 3.3 A

ISH Input average current Vi= 46V; output short-circuit 15 30 mA

ηEfficiency f = 100KHz Vo=V

ref 70 %

Io=1A V

o= 12V 80 %

SVR Supply voltage ripple

rejection ∆Vi=2V

rms

fripple = 100Hz

Vo=V

ref Io = 1A

50 56 dB

ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj=25°C, Vi= 35V, unless otherwise

specified)

HEPTAWATT POWERDIP NAME FUNCTION

4 4, 5, 12, 13 GROUND Common ground terminal.

5 14 OSCILLATOR A parallel RC network connected to this terminal

determines the switching frequency. This pin must be

connected to pin 7 input when the internal oscillator is

used.

6 15 SOFT START Soft start time constant. A capacitor is connected

between this terminal and ground to define the soft start

time constant. This capacitor also determines the

average short circuit output current.

7 2 OUTPUT Regulator output.

1, 3,6,

8, 9, 16 N.C.

PIN FUNCTIONS (cont’d)

3/15

L4962

4/15

Symbol Parameter Test Conditions Min. Typ. Max. Unit

DYNAMIC CHARACTERISTICS (cont’d)

f Switching frequency 85 100 115 KHz

∆f

∆ViVoltagestability of

switching frequency Vi= 9V to 46V 0.5 %

∆f

∆TjTemperature stability of

switching frequency Tj=0°C to 125°C1%

max Maximum operating

switching frequency Vo=V

ref Io= 1A 120 150 KHz

Tsd Thermal shutdown

junction temperature 150 °C

DC CHARACTERISTICS

I7Q Quiescent drain current 100% duty cycle

pins 2 and 14 open Vi= 46V

30 40 mA

0% duty cycle 15 20 mA

-I2L Output leakage current 0% duty cycle 1 mA

SOFTSTART

I15SO Source current 100 140 180 µA

I15SI Sink current 50 70 120 µA

ERROR AMPLIFIER

V11H High level output voltage V10 = 4.7V I11 = 100µA 3.5 V

V11L Low level output voltage V10 = 5.3V I11 = 100µA 0.5 V

I11SI Sink output current V10 = 5.3V 100 150 µA

-I11SO Source output current V10 = 4.7V 100 150 µA

I10 Input bias current V10 = 5.2V 2 10 µA

GvDC open loop gain V11 =1Vto3V 46 55 dB

OSCILLATOR

-I14 Oscillator source current 5 mA

ELECTRICALCHARACTERISTICS (continued)

L4962

CIRCUIT OPERATION (refer tothe block diagram)

TheL4962isamonolithicstepdownswitchingregu-

latorprovidingoutputvoltagesfrom5.1Vto40Vand

delivering 1.5A.

The regulation loop consistsof a sawtoothoscilla-

tor, error amplifier, comparator and the output

stage.Anerrorsignalisproducedbycomparingthe

output voltage with a precise 5.1V on-chip refer-

ence (zenerzap trimmed to ±2%).

Thiserrorsignalisthencomparedwiththesawtooth

signal to generate the fixed frequency pulse width

modulatedpulses which drive the output stage.

The gain and frequencystability of theloop can be

adjusted by an external RC network connected to

pin 11. Closing the loop directly gives an output

voltage of 5.1V. Higher voltages are obtained by

inserting a voltagedivider.

Output overcurrents at switch on are prevented by

the soft start function. The error amplifier output is

initially clamped by the external capacitor Css and

allowedto rise, linearly,as this capacitoris charged

by a constant currentsource. Output overloadpro-

tection is provided in the form of a current limiter.

The load current is sensed by an internal metal

resistorconnectedto a comparator.When theload

current exceedsa presetthresholdthis comparator

sets a flip flop which disables the output stage and

dischargesthe soft start capacitor. Asecond com-

parator resets the flip flop when the voltage across

the soft start capacitorhas fallento 0.4V.

The output stage is thus re-enabledand theoutput

voltagerises undercontrolof thesoftstart network.

If the overload condition is still present the limiter

will trigger again when the threshold current is

reached.Theaverageshortcircuitcurrentis limited

to a safevalue by the dead time introducedby the

soft start network.The thermal overload circuit dis-

ables circuit operation when the junction tempera-

ture reaches about 150°C and has hysteresis to

prevent unstableconditions.

Figure 1. Softstart waveforms

Figure 2. Current limiter waveforms

5/15

L4962

6/15

Figure 4. Quiescent drain

currentvs.supplyvoltage(0%

duty cycle)

Figure 5. Quiescent drain

current vs. supply voltage

(100% duty cycle)

Figure 6. Quiescent drain

current vs. junction tem-

perature (0% duty cycle)

Figure 3. Test and applicationcircuit (Powerdip)

1) D1: BYW98 or 3A Schottky diode, 45V of VRRM;

2) L1: CORE TYPE- MAGNETICS 58120 - A2 MPP

N°TURNS 45, WIRE GAUGE: 0.8mm (20 AWG)

3) C6,C

: ROE, EKR 220µF 40V

L4962

Figure 7. Quiescent drain

current vs. junction tem-

perature(100% duty cycle)

Figure 8. Reference voltage

(pin 10) vs. Virdip) vs. ViFigure 9. Reference voltage

(pin 10 ) vs. junction tem-

perature

Figure 10. Open loop fre-

quency and phase re- sponse

of error amplifier

Figure 11. Switching fre-

quency vs. input voltage Figure 12. Switching fre-

quency vs. junction tem-

perature

Figure 13. Switching fre-

quencyvs.R2(seetestcircuit) Figure 15. Load transient

response

Figure 14. Line transient

response

7/15

L4962

8/15

Figure 16. Supply voltage

ripple rejectionvs. frequency Figure 17. Dropout voltage

between pin 7 and pin 2 vs.

current at pin 2

Figure 18. Dropout voltage

between pin 7 and 2 vs.

junction temperature

Figure 19. Efficiency vs.

output current Figure 20. Efficiency vs.

output current Figure 21. Efficiency vs.

output current

Figure 22. Efficiency vs.

output voltage Figure 23. Efficiency vs.

output voltage Figure 24. Maximum allow-

able power dissipationvs.am-

bient temperature(Powerdip)

L4962

APPLICATION INFORMATION

Figure 25. Typical application circuit

C1,C

: EKR (ROE)

D1: BYW98 OR VISK340 (SCHOTTKY)

SUGGESTED INDUCTORS: (L1) = MAGNETICS 58120 - A2MPP- 45 TURNS - WIRE GAUGE 0.8mm (20AWG)

COGEMA946043

OR U15, GUP15, 60 TURNS 1mm, AIR GAP 0.8mm (20 AWG) - COGEMA969051.

Figure 26. P.C.board and component layout of the circuit of Fig. 25 (1 : 1 scale)

Resistor valuesfor

standard output 7 voltages

VoR3 R4

12V

15V

18V

24V

4.7KΩ

6.2KΩ

9.1KΩ

12KΩ

18KΩ

9/15

L4962

10/15

APPLICATION INFORMATION (continued)

Figure 27. - Aminimal 5.1V fixed regulator; Veryfew component arerequired

* COGEMA946043 (TOROID CORE)

969051 (U15 CORE)

** EKR (ROE)

Figure 28. Programmablepower supply

Vo= 5.1V to 15V

Io= 1.5Amax

Load regulation (0.5A to 1.5A) = 10mV (Vo= 5.1V)

Line regulation (220V ±15% and to Io= 1A) = 15mV (Vo= 5.1V)

L4962

APPLICATION INFORMATION (continued)

Figure 29. DC-DC converter 5.1V/4A,±12V/1A.A suggestion how to synchronize a negative output

L1, L3 = COGEMA 946043 (969051)

L2 = COGEMA946044 (946045)

Figure 30. In multiple suppliesseveral

L4962s can be synchronizedas shown Figure 31. Preregulator for distributedsupplies

* L2 and C2 are necessary to reduce the switchingfrequency spikes

when linear regulators are remote from L4962

11/15

L4962

12/15

MOUNTING INSTRUCTION

The Rth-j-amb of the L4962 can be reduced by

solderingtheGND pinsto a suitablecopperareaof

the printed circuit board (Fig. 32).

The diagram of figure 33 shows the Rth-j-amb as a

function of the side ”l” of two equal square copper

areashavingthethicknessof35µ(1.4mils). During

soldering the pins temperature must not exceed

260°C and the soldering time must not be longer

than 12 seconds.

The external heatsink or printed circuit copper are

must be connected to electrical ground.

Figure 32.Exampleof P.C.boardcopperareawhichis used

as heatsink Figure 33. Maximum dissipable

power and junction to ambient

thermal resistance vs. side ”l”

L4962

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 20.0 0.787

E 8.80 0.346

e 2.54 0.100

e3 17.78 0.700

F 7.10 0.280

I 5.10 0.201

L 3.30 0.130

Z 1.27 0.050

POWERDIPPACKAGE MECHANICAL DATA

13/15

L4962

14/15

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.8 0.189

C 1.37 0.054

D 2.4 2.8 0.094 0.110

D1 1.2 1.35 0.047 0.053

E 0.35 0.55 0.014 0.022

F 0.6 0.8 0.024 0.031

F1 0.9 0.035

G 2.41 2.54 2.67 0.095 0.100 0.105

G1 4.91 5.08 5.21 0.193 0.200 0.205

G2 7.49 7.62 7.8 0.295 0.300 0.307

H2 10.4 0.409

H3 10.05 10.4 0.396 0.409

L 16.97 0.668

L1 14.92 0.587

L2 21.54 0.848

L3 22.62 0.891

L5 2.6 3 0.102 0.118

L6 15.1 15.8 0.594 0.622

L7 6 6.6 0.236 0.260

M 2.8 0.110

M1 5.08 0.200

Dia 3.65 3.85 0.144 0.152

HEPTAWATT PACKAGE MECHANICAL DATA

L4962

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is grantedby implication orotherwise under anypatent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are notauthorized for use as critical components in life support devices or systems without express

written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil -France - Germany- Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden- Switzerland - Taiwan- Thaliand - United Kingdom - U.S.A.

15/15

L4962

L4963

L4963D

1.5ASWITCHING REGULATOR

October 1991

Thisisadvanced informationon anewproduct now in development or underogin evaluation. Details aresubject tochange withoutnotice.

1.5AOUTPUTLOADCURRENT

5.1 TO 36V OUTPUT VOLTAGERANGE

DISCONTINUOUS VARIABLE FREQUENCY

MODE

PRECISE (+/–2%) ON CHIP REFERENCE

VERYHIGH EFFICIENCY

VERYFEW EXTERNALCOMPONENTS

NO FREQ. COMPENSATION REQUIRED

RESET AND POWER FAIL OUTPUT FOR MI-

CROPROCESSOR

INTERNALCURRENT LIMITING

THERMAL SHUTDOWN

DESCRIPTION

The L4963is a monolithicpower switching regulator

delivering1.5Aat5.1V.The outputvoltageis adjust-

able from 5.1V to 36V, working in discontinuous

variable frequency mode. Features of the device

include remote inhibit, internal current limiting and

thermal protection, reset and power fail outputs for

microprocessor.

BLOCKDIAGRAM

Powerdip12+3+3 SO20

ORDERING NUMBERS:

L4963W L4963D

The L4963is mounted in a 12+3+3lead Powerdip

(L4963) and SO20 large (L4963D) plastic pack-

ages and requires very few external components.

1/17

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

SO20 Powerdip

ViInput Voltage (pin 1 and pin 3 connected togheter) 47 V

V3–V2Input to Output VoltageDifference 47 V

V2Negative Output DC Voltage –1 V

V2Negative Output Peak Voltageat t=0.2 µs, f=50kHz –5 V

V8V7Power FailInput 25 V

V9,V

11 V8,V

10 Reset and Power Fail Output Vi

V10 V9Reset Delay Input 5.5 V

V13,V

18 V12,V

16 Feedback and Inhibit Inputs 7V

19,V

20 V17,V

18 Oscillator Inputs 5.5 V

Ptot TotalPower Dissipation Tpins ≤90°C (Power DIP)

(Tamb =70°C no copper area on PCB)

(Tamb =70°C, 4cm2copper area on PCB)

1.3

Tstg,T

jStorage & JunctionTemperature

(Tamb = 70°C 6cm2copper area on PCB) –40 to 150

1.45 °C

Ptot TotalPower Dissipation Tpins ≤90°C (SO20L) 4W

PIN CONNECTION (top view)

Powerdip18

SO20

L4963 - L4963D

2/17

PIN FUNCTIONS

SO20L Power DIP Name Description

SIGNAL SUPPLY VOLTAGE Must be Connected to pin 3

2 2 OUTPUT Regulator output

SUPPLY VOLTAGE Unregulated voltage input. An internal regulator

powers the internal logic.

4, 5, 6, 7

14, 15, 16, 17 4, 5, 6

13, 14, 15 GROUND Common ground terminal

POWER FAILINPUT Input of the power fail circuit. The threshold can be

modified introducing an externalvoltage divider

between the Supply Voltageand GND.

POWER FAILOUTPUT Open collector power fail signal output. This output

is high when the supplyvoltage is safe.

10 9 RESET DELAY Acapacitor connected between this terminal and

ground determines the reset signal delay time.

11 10 RESET OUTPUT Open collector reset signal output. This output is

high when the output voltage value is correct.

12 11 REFERENCE VOLTAGE Reference voltage output.

13 12 FEEDBACK INPUT Feedback terminal of the regulation loop.

The output is connected directly to this terminal for

5.1V operation; it is connected via a divider for

higher voltages.

18 16 INHIBIT INPUT TTLlevel remote inhibit. A logic low level on this

input disables the device.

19 17 C OSCILLATOR Oscillator waveform. A capacitor connected

between this terminal and ground modifies the

maximum oscillator frequency.

20 18 R OSCILLATOR FREQ. Aresistor connected betweenthis terminal and

ground defines the maximum switching frequency.

THERMAL DATA

Symbol Parameter SO20 Powerdip Unit

Rth j-pins Thermal Resistance Junction to Pins max. 15 12 °C/W

Rth j-amb Thermal Resistance Junction to Ambient (*) max. 85 80 °C/W

(*) See Fig. 28

L4963 - L4963D

3/17

CIRCUIT DESCRIPTION (Refer to Block Dia-

gram)

The L4963 is a monolithic stepdown regulatorpro-

viding 1.5A at 5.1V working in discontinuousvari-

able frequency mode. In normal operation the

device resonatesata frequencydepending primar-

ily on the inductance value, the input and output

voltage and theloadcurrent. Themaximum switch-

ing howevercan be limited byaninternaloscillator,

which can be programmed by only one external

resistor.

The fondamental regulation loop consists of two

comparators, a precision 5.1V on-chip reference

and adrive latch. Briefly the operation is as follows:

when the choke ends its discharge the catch free-

wheeling recirculation filter diode begins to come

out of forward conductionso the output voltage of

the device approaches ground. When the output

voltagereaches–0.1Vtheinternalcomparatorsets

the latch and the power stage is turned on. Then

the inductor current rises linearly until the voltage

sensed at the feedback input reaches the 5.1V

reference.

The second comparator then resets the latch and

the output stage is turned off. The current in the

choke falls linearly until it is fully discharged, then

the cyclerepeats.Closing the loop directlygivesan

output voltage of 5.1V. Higher output voltages are

obtained by inserting a voltage divider and this

method of controlrequires no frequencycompen-

sation network. At output voltages greater than

5.1V the availableoutput current must be derated

due to the increased power dissipation of the de-

vice.

Outputoverload protectionis provided byan inter-

nal current limiter. The load currentis sensed by a

on-chip metal resistor connected to a comparator

which resetsthe latchandturnsoff the powerstage

in overloadcondition.The reset circuits (see fig. 1)

generates an output high signal when the output

voltage value is correct. It has an open collector

output and the output signal delay time can be

programmed with an external capacitor. A power-

fail circuit is also available and is used to monitor

the supply voltage. Its output goes high when the

supplyvoltagereachesapre-programmedtreshold

set by a voltagedividerto its inputfrom thesupply

to ground. With the input left open the thresholdis

approximately equal to 5.1V. The output of the

powerfail is anopen collector.

ATTLlevel inhibit isprovided for applicationssuch

as remote on/off control. This input is activatedby

a low logic level and disables circuits operation.

The thermal overload circuit disables the device

when thejunction temperature is about 150°C and

has hysteresisto preventunstable conditions.

Figure 1: Reset and Power Fail Function

L4963 - L4963D

4/17

ELECTRICAL CHARACTERISTIC (Refer to the test circuit Vi=30VT

j=25°C unless otherwise specified)

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

DYNAMIC CHARACTERISTICS

VoOutput Voltage Range Vi= 46V Io= 0.5A Vref 36 V 2

ViInputVoltage Range Vo=V

ref to 36V Io= 0.5A 946V2

12 Feedback Voltage Vi= 9 to 46V Io= 0.5A 5 5.1 5.2 V 2

I12 InputBias Current Vi= 15V V12 =6V

17f =5V 520µA3a

OS12 InputOffsetVoltage 5 10 mV 3a

∆VoLineRegulation Vi= 9 to 46V Vo=V

ref

Io= 0.5A 15 50 mV 2

∆VoLoadRegulation Vo=V

ref

Io= 0.5 to 1.5A 15 45 mV 2

VdDropoutVoltage Between

pin 3 and pin 2 I2=3A

i= 20V 1.5 2 V 2

I2L Current Limiting Vi= 9 to 46V

Vo=V

ref to 28V 3.5 6.5 A 2

IoMaximum Operating Load

Current Vi= 9 to 46V Vo=V

ref 1.5 A 2

SVR SupplyVoltage Ripple

Rejection Vi= 2Vrms Vo=V

ref

fripple= 100Hz Io= 1.5A 50 56 dB 2

V11 Reference Voltage Vi= 9 to 46V

O<I

11 < 5mA 5 5.1 5.2 V 3a

AverageTemperature

Coefficient of Ref. Volt. Tj= 0 to 125 °C0.4 mV/°C–

∆V

11 Vref Line Regulation Vi= 9 to 46V 10 20 mV 3a

∆V11 Vref Line Regulation Iref = 0 to 5mA

Vi= 46V Rosc = 51KΩ65

69 715mV3a

ηEfficiency Io= 1.5AVo=V

ref 65 75 % 2

Tsd Thermal Shutdown

JunctionTemperature 145 150 °C–

Hysteresis 30 °C–

DC CHARACTERISTICS

IqQuescentDrain Current Vi= 46V

Io= 0mA V16 =V

12 = 0 14 20 mA 3a

V16 =V

ref

V12 = 5.3V 11 16 mA 3a

INHIBIT

V16L Low Input Voltage Vi= 9 to 46V 0.3 0.8 V 2

V16H HighInput Voltage Vi= 9 to 46V 2 5.5 V 2

I16L InputCurrent with Low

InputVoltage V16 = 0.8V 50 100 µA2

16L InputCurrent with High

InputVoltage V16 =2V 10 20 µA2

L4963 - L4963D

5/17

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

RESET

V12 Rising Threshold Voltage Vi= 9 to 46V Vref

–150 Vref

–100 Vref

–50 mV 3b

V12 FallingThreshold Voltage Vi= 9 to 46V Vref

–150 Vref

–200 Vref

–250 mV 3b

V9D DelayRising Thereshold

Voltage V7= OPEN 4.3 4.5 4.7 V 3b

V9F DelayFalling Thereshold

Voltage 1 1.5 2 V 3b

–I9SO DelaySource Current V9= 4.7V V12 = 5.3V 70 110 140 µA3b

9SI DelaySink Current V9= 4.7V V12 = 4.7V 10 mA 3b

I10 Output Leakage Current Vi= 46V V7= 8.5V 50 µA3b

10 Output Saturation Volt. I10 = 15mA; VI= 3 to 46V 0.4 V 3b

POWER FAIL

VRRising Threshold Voltage Pin7 = open 17.5 19 20.5 V 3C

VFFalling Threshold Voltage Pin7 = open 14.25 15 15.75 V 3c

V7Rising Threshold Voltage Vi= 20V 4.14 4.5 4.86 V –

V7FallingThreshold Voltage Vi= 20V 3.325 3.5 3.675 V –

VsOutput Saturation Volt. Ia= 5mA 0.4 V 3c

IsOutput Leakage Current Vi= 46V 50 µA3c

OSCILLATOR

f Oscillator Frequency RT= 51KΩ46 60 79 kHz –

fOscillator Frequency VI= 9 to 46V

Tj= 0 to 125°C

RT= 51KΩ42 83 kHz –

ELECTRICALCHARACTERISTIC (Continued)

L4963 - L4963D

6/17

Figure 2: TestCircuit

Figure 3: DC TestCircuit

Figure 3a

Figure 3b

L4963 - L4963D

7/17

Figure 3c

Figure 4: QuiescentDrain Current vs. Supply

Voltage(0% Duty Cycle) Figure5: QuiescentDrain Current vs. Supply

Voltage (100%Duty Cycle)

Figure 6: QuiescentDrain Current vs. Junction

Temperature(0% Duty Cycle) Figure 7: QuiescentDrain Current vs. Junction

Temperature(100% Duty Cycle)

L4963 - L4963D

8/17

Figure 8: Reference Voltage vs. ViFigure 9: ReferenceVoltagevs. Tj

Figure 10: Line TransientResponse Figure 11: Load Transient

Figure 12: SupplyVoltage Ripple Rejection vs.

Frequency Figure 13: Dropout VoltageBetween pi3 and 2

vs. Current at pin2

L4963 - L4963D

9/17

Figure 14: DropoutVoltage Between pin3 and 2

vs. JunctionTemperature Figure15: Maximum AllowablePowerDissipation

vs. AmbientTemperature(Powerdip

PackageOnly)

Figure 16: PowerDissipation (deviceonly) vs. In-

put Voltage(Powerdip PackageOnly) Figure 17: PowerDissipation (deviceonly) vs.

Output Voltage (Powerdip Package

Only)

Figure 18: Voltageand CurrentWaveform at pin2 Figure19: Efficiencyvs. Output Current (Power-

dip PackageOnly)

L4963 - L4963D

10/17

Figure 20: Efficiency vs. Output Voltage(Power-

dip Package Only) Figure 21: CurrentLimit vs. JunctionTempera-

ture Vi=30V

Figure 22: CurrentLimit vs. InputVoltage Figure 23: Oscillator Frequencyvs. R2 (see fig. 26)

Figure 24: Oscillator Frequency vs. Junction

Temperature Figure 25: Oscillator Frequency vs. InputVoltage

L4963 - L4963D

11/17

Figure 26: EvaluationBoard Circuit

PART LIST

CAPACITOR

C1 1000µF 50V EKR (*)

C2 2.2mF 16V

C3 1000µF 40V with low ESR

C4 1µF 50V film

RESISTOR

R1 1KΩ

R2 51KΩ

R3 1KΩ

R4 1KΩ

R5, R6 see table

Resistor Values for Standard Output Voltages

VOR6 R5

12 4.7KΩ6.2KΩ

15 4.7KΩ9.1KW

18 4.7KΩ12KW

24 4.7KΩ18KW

Diode: BYW98

Core: L=40µHMagnetics58121-A2MPP34Turns

0.9mm (20AWG)

(*) Minimum100µFifV

iis apreregulated offline SMPS outputor 1000µF if a50Hz transformer plus rectifiers isused.

L4963 - L4963D

12/17

Figure 28: ThermalCharacteristics

Figure 27: P.C. Board and Component Layout of the Circuit of fig. 26 (Powerdip Package)(1:1 scale).

Figure 29: Junctionto Ambient Thermal Resis-

tance vs. Areaon Board Heatsink

(SO20)

L4963 - L4963D

13/17

Figure 30: AMinimal 5.1 Fixed Regulator — Very Few Componentsare Required

Figure 31: AMinimal Componentscount forVO= 12V

L4963 - L4963D

14/17

POWERDIP18 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 24.80 0.976

E 8.80 0.346

e 2.54 0.100

e3 20.32 0.800

F 7.10 0.280

I 5.10 0.201

L 3.30 0.130

Z 2.54 0.100

L4963 - L4963D

15/17

SO20 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

a2 2.45 0.096

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45 (typ.)

D 12.6 13.0 0.496 0.512

E 10 10.65 0.394 0.419

e 1.27 0.050

e3 11.43 0.450

F 7.4 7.6 0.291 0.299

L 0.5 1.27 0.020 0.050

M 0.75 0.030

S 8 (max.)

L4963 - L4963D

16/17

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such informationnor for any infringementof patents or other rights of third parties which may result from its use.No

license is grantedby implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are notauthorized foruse ascritical components inlife support devices or systems without express

written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - France -Germany -Hong Kong - Italy- Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

L4963 - L4963D

17/17

L4970A

10A SWITCHING REGULATOR

10A OUTPUT CURRENT

5.1V TO 40V OUTPUT VOLTAGERANGE

0 TO 90% DUTY CYCLE RANGE

INTERNAL FEED-FORWARD LINE REGULA-

TION

INTERNAL CURRENT LIMITING

PRECISE 5.1V ±2% ON CHIP REFERENCE

RESETAND POWER FAIL FUNCTIONS

SOFT START

INPUT/OUTPUT SYNC PIN

UNDER VOLTAGE LOCK OUT WITH HYS-

TERETIC TURN-ON

PWM LATCH FOR SINGLE PULSE PER PE-

RIOD

VERYHIGH EFFICIENCY

SWITCHING FREQUENCY UP TO 500KHz

THERMAL SHUTDOWN

CONTINUOUS MODE OPERATION

DESCRIPTION

The L4970A is a stepdown monolithic power

switching regulator delivering 10A at a voltage

variable from5.1 to 40V.

Realized with BCD mixed technology, the device

usesa DMOSoutput transistorto obtain very high

efficiency and very fast switching times. Features

of the L4970A include reset and power fail for mi-

croprocessors, feed forward line regulation, soft

start, limiting current and thermal protection. The

device is mounted in a 15-lead multiwatt plastic

power package and requiresfew external compo-

nents. Efficient operation at switching frequencies

up to 500KHz allows reduction in the size and

cost of external filter components.

This isadvanced information on anew productnow in development or undergoing evaluation. Details are subject to change without notice.

November 1991

BLOCK DIAGRAM

Multiwatt15V

ORDERING NUMBER: L4970A

MULTIPOWER BCD TECHNOLOGY

1/21

PIN CONNECTION (Top view)

ABSOLUTE MAXIMUMRATINGS

Symbol Parameter Value Unit

V9Input Voltage 55 V

V9Input Operating Voltage 50 V

V7Output DC Voltage

Output Peak Voltage at t = 0.1µs f = 200KHz -1

-7 V

I7Maximum Output Current Internally Limited

V6Bootstrap Voltage

Bootstrap Operating Voltage 65

V9+15 V

12 Input Voltage at Pins 3, 12 12 V

V4Reset Output Voltage 50 V

I4Reset Output Sink Current 50 mA

V5,V

10, V11, V13 Input Voltage at Pin 5, 10, 11, 13 7 V

I5Reset Delay Sink Current 30 mA

I10 Error Amplifier Output Sink Current 1 A

I12 Soft Start Sink Current 30 mA

Ptot Total Power Dissipation at Tcase < 120°C30W

stg Junction and Storage Temperature -40 to 150 °C

THERMAL DATA

Symbol Parameter Value Unit

Rth j-case

Rth j-amb Thermal Resistance Junction-case max

Thermal Resistance Junction-ambient max 1

35 °C/W

°C/W

L4970A

2/21

CIRCUIT OPERATION (refer to the block dia-

gram)

The L4970A is a 10A monolithic stepdownswitching

regulatorworking in continuousmode realized in the

new BCD Technology.This technologyallows thein-

tegrationof isolated vertical DMOS power transistors

plusmixed CMOS/Bipolartransistors.

The device can deliver 10A at an output voltage

adjustable from 5.1V to 40V, and contains diag-

nostic and control functions that make it particu-

larlysuitable for microprocessor based systems.

BLOCK DIAGRAM

The block diagram shows the DMOS power tran-

sistor and the PWM control loop. Integrated func-

tions include a referencevoltage trimmed to 5.1V

±2%, soft start, undervoltage lockout, oscillator

with feedforward control, pulse by pulse current

limit, thermal shutdown and finally the reset and

power fail circuit. The reset and power fail circuit

provides an output signal for a microprocessor in-

dicating the statusof the system.

Device turn on is around 11V with a typical 1V

hysteresis, this threshold provides a correct volt-

age for the driving stage of the DMOS gate and

the hysteresisprevents instabilities.

An external bootstrap capacitor charged to 12V

by an internal voltage reference is needed to pro-

vide correct gate drive to the power DMOS. The

driving circuit is able to source and sink peak cur-

rents of around 0.5A to the gate of the DMOS

transistor. A typical switching time of the current

in the DMOS transistor is 50ns. Due to the fast

commutation switching frequencies up to 500kHz

arepossible.

The PWM control loop consists of a sawtooth os-

cillator, error amplifier, comparator, latch and the

output stage. An error signal is produced by com-

paring the output voltage with the precise 5.1V ±

2% on chip reference. This error signal is then

compared with the sawtooth oscillator, in order to

generatea fixedfrequencypulse width modulated

drive for the output stage. A PWM latch is in-

cluded to eliminate multiple pulsing within a pe-

riod even in noisy environments. The gain and

PIN FUNCTIONS

NoName Function

1 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging

current of Cosc.

2 OSCILLATOR Cosc. External capacitor connected to grounddetermines (with Rosc) the

switching frequency.

3 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a

dividerto the input for power failfunction. It must be connected to the pin 14 an

external 30KΩresistorwhen power fail signal not required.

4 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the

supply and the output voltages are safe.

5 RESET DELAY A Cdcapacitor connected between this terminal and ground determines the

reset signaldelay time.

6 BOOTSTRAP A Cboot capacitor connected between thisterminal and the output allows to

drive properly the internal D-MOS transistor.

7 OUTPUT Regulator Output.

8 GROUND Common Ground Terminal

9 SUPPLY VOLTAGE UnregulatedInput Voltage.

10 FREQUENCY

COMPENSATION A series RC network connected between this terminal and ground determines

the regulation loop gain characteristics.

11 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected

directly to this terminal for 5.1V operation; It is connected via a divider for higher

voltages.

12 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and

ground to define the soft start time constant.

13 SYNC INPUT Multiple L4970A are synchronized by connecting pin 13inputs together or via

an external syncr. pulse.

14 Vref 5.1V Vref Device Reference Voltage.

15 Vstart Internal Start-up Circuit to Drive the Power Stage.

L4970A

3/21

Figure1: FeedforwardWaveform

Figure3: LimitingCurrent Function

Figure2: Soft Start Function

L4970A

4/21

stability of the loop can be adjusted by an exter-

nal RC network connected to the output of the er-

ror amplifier. A voltage feedforward control has

been added to the oscillator, this maintains supe-

rior line regulation over a wide input voltage

range. Closing the loop directly gives an output

voltage of 5.1V, higher voltages are obtained by

inserting a voltagedivider.

At turn on output overcurrents are prevented by

the soft start function(fig. 2). The error amplifieris

initiallyclamped by an external capacitorCss and

allowed to rise linearly under the charge of an in-

ternal constant current source.

Output overload protection is provided by a cur-

rentlimit circuit (fig. 3). Theload current is sensed

by an internal metal resistor connected to a com-

parator. When the load current exceeds a preset

threshold the output of the comparator sets a flip

flop which turns off the power DMOS. The next

clock pulse, from an internal 40kHz oscillator will

reset the flip flop and the power DMOS will again

conduct. This current protection method, ensures

a constant current output when the system is

overloaded or short circuited and limits the

switching frequency,in this condition,to 40kHz.

The Reset and Power fail circuitry (fig 4) gener-

ates an output signal when the supply voltage ex-

ceeds a threshold programmed by an external

voltage divider. The reset signal, is generated

with a delay time programmed by an external ca-

pacitor on the delay pin. Whenthe supply voltage

falls below the threshold or the output voltage

goes below 5V the reset output goes low immedi-

ately. The reset output is an open collector-drain.

Fig 4A shows the case when the supply voltage is

higher than the threshold, but the output voltage

isnot yet 5V.

Fig 4B shows the case when the output is 5.1V

but the supply voltage is not yet higher than the

fixedthreshold.

The thermal protection disables circuit operation

when the junction temperature reaches about

150°C and has an hysterysis to prevent unstable

conditions.

Figure4: Reset and Power Fail Functions.

L4970A

5/21

ELECTRICALCHARACTERISTICS (Refer to the test circuit, Tj=25°C, Vi= 35V, R4= 16KΩ,

C9= 2.2nF, fSW = 200KHz typ, unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

Viinput Voltage Range (pin 9) Vo=V

ref to 40V

Io= 10A 15 50 V 5

VoOutput Votage Vi= 15V to 50V

Io= 5A; Vo=V

ref5 5.1 5.2 V 5

∆VoLine Regulation Vi= 15V to 50V

Io= 5A; Vo=V

ref12 30 mV 5

∆VoLoad Regulation Vo=V

ref

Io=3Ato6A

o= 2A to 10A 10

20 30

50 mV

VdDropout VoltageBetween

Pin 9 and 7 Io=5A

o= 10A 0.55

1.1 0.8

1.6 V

I7L Max. LimitingCurrent Vi= 15 to 50V 11 13 15 A 5

ηEfficiency Io=5A

o=V

ref

Vo= 12V 80 85

92 %

Io= 10A

Vo=V

ref

Vo= 12V 75 80

87 %

SVR Supply Voltage Ripple

Reject. Vi= 2VRMS; Io=5A

f = 100Hz; Vo=V

ref 56 60 dB 5

f Switching Frequency 180 200 220 KHz 5

∆f

∆ViVoltage Stability of

Swiching Frequency Vi= 15V to 45V 2 6 % 5

∆f

TjTemperature Stability of

Swiching Frequency Tj= 0 to 125°C1%5

max Maximum Operating

Switching Frequency Vo=V

ref;R

4= 10KΩ

Io= 10A; C9= 1nF 500 KHz 5

Vref SECTION(pin 14)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V14 Reference Voltage 5 5.1 5.2 V 7

∆V14 Line Regulation Vi= 15V to 50V 10 25 mV 7

∆V14 Load Regulation I14 = 0 to 1mA 20 40 mV 7

∆V14

∆TAverage Temperature

CoefficientReference

Voltage

Tj=0°C to 125°C 0.4 mV/°C7

14 short Short Circuit Current Limit V14 = 0 70 mA 7

VSTART SECTION(pin 15)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V15 Reference Voltage 11.4 12 12.6 V 7

∆V15 Line Regulation Vi= 15 to 50V 0.6 1.4 V 7

∆V15 Load Regulation I15 = 0 to 1mA 50 200 mV 7

I15 short Short Circuit Current Limit V15 =0V 80 mA 7

L4970A

6/21

ELECTRICALCHARACTERISTICS (continued)

DCCHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V9on Turn-on Threshold 10 11 12 V 7A

V9 Hyst Turn-off Hysteresys 1 V 7A

I9Q Quiescent Current V12 =0; S1=D 13 19 mA 7A

9OQ Operating SupplyCurrent V12 = 0; S1 = C; S2 = B 16 23 mA 7A

I7L Out Leak Current Vi= 55V; S3 = A; V12 =0 2 mA 7A

SOFTSTART

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

I12 Soft Start Source Current V12 = 3V; V11 = 0V 70 100 130 µA7B

12 Output Saturation Voltage I12 = 20mA; V9= 10V

I12 = 200µA; V9= 10V 1

0.7 V

V7B

ERROR AMPLIFIER

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V10H High Level Out Voltage I10 = -100µA; S1 = C

V11 = 4.7V 6V7C

10L Low Level Out Voltage I10 = +100µA; S1 = C

V11 = 5.3V; 1.2 V 7C

I10H Source Output Current V10 = 1V; S1 = E

V11 = 4.7V 100 150 µA7C

10L Sink Output Current V10 = 6V; S1 = D

V11 = 5.3V 100 150 µA7C

11 Input Bias Current RS= 10KΩ0.4 3 µA–

VDC Open Loop Gain VVCM = 4V;

RS=10Ω60 dB –

SVR Supply Voltage Rejection 15 < Vi< 50V;

RS=10Ω60 80 dB –

VOS Input Offset Voltage RS=50Ω210mV–

RAMP GENERATOR(pin 2)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V2Ramp Valley S1 = C; S2 = B 1.2 1.5 V 7A

V2Ramp Peak S1 = C; Vi= 15V

S2 = B; Vi= 45V 2.5

5.5 V

V7A

I2Min. Ramp Current S1 = A; I1= 100µA 270 300 µA7A

2Max. Ramp Current S1 = A; I1 = 1mA 2.4 2.7 mA 7A

SYNC FUNCTION (pin 13)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V13 Low Input Voltage Vi= 15V to 50V; V12 =0;

S1 = C; S2 = B; S4 = B –0.3 0.9 V 7A

V13 High Input voltage V12 =0;

S1 = C; S2 = B; S4 = B 3.5 5.5 V 7A

I13L Sync Input Current with

Low Input Voltage V13 =V

= 0.9V; S4 = A;

S1 = C; S2 = B 0.4 mA 7A

I13H Input Current with High

Input Voltage V13 = 3.5V; S4 = A;

S1 = C; S2 = B 1.5 mA 7A

V13 Output Amplitude 4 5 V –

tWOutput Pulse Width Vthr = 2.5V 0.3 0.5 0.8 µs–

L4970A

7/21

ELECTRICALCHARACTERISTICS (continued)

RESETAND POWERFAIL FUNCTIONS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V11R Rising Threshold Voltage

(pin 11) Vi= 15 to 50V

V3= 5.3V Vref

–120 Vref

–100 Vref

–80 V

mV 7D

V11F Falling Threshold Voltage

(pin 11) Vi = 15 to 50V

V3= 5.3V 4.77 Vref

–200 Vref

–160 V

mV 7D

V5H Delay High Threshold

Voltage Vi= 15 to 50V

V14 =V

11 V3= 5.3V 4.95 5.1 5.25 V 7D

V5L Delay Low Threshold

Voltage Vi = 15 to 50V

V14 =V

11 V3= 5.3V 1 1.1 1.2 V 7D

–I5SO Delay Source Current V3= 5.3V; V5=3V 406080µA7D

5SI Delay Sink Current V3= 4.7V; V5=3V 10 mA 7D

4S Out Saturation Voltage I4= 15mA; S1 = B

V3= 4.7V 0.4 V 7D

I4Output Leak Current V4= 50V; S1 = A

V3= 5.3V 100 µA7D

3R Rising Threshold Voltage V11 =V

14 4.95 5.1 5.25 V 7D

V3H Hysteresys 0.4 0.5 0.6 V 7D

I3Input Bias Current 1 3 µA7D

Figure5: Test andEvaluationBoard Circuit

TYPICAL PERFORMANCES (using evaluationboard) :

n =83% (Vi=35V ; Vo=VREF ;I

o=10A ; fSW = 200KHz)

Vo RIPPLE =30mV (at 10A)with output filter capacitorESR ≤60mΩ

Line regulation = 5mV (Vi=15 to 50V)

Load regulation= 15mV (Io= 2 to 10A)

For componentvalues,refer to test circuit partlist.

L4970A

8/21

PARTS LIST

R1= 30KΩC1,C

2= 3300µF 63VLEYF (ROE

R2= 10KΩC3,C

6= 2.2µF

R3= 15KΩC7= 390pF Film

R4= 16KΩC8= 22nF MKT 1817 (ERO)

R5=22Ω0,5W

R6= 4K7 C9= 2.2nF KP1830

R7=10ΩC

10 = 220nF MKT

R8= see tab. A C11 = 2.2nF MP1830

R9= OPTION **C12,C

13,C

14 = 220µF 40VLEKR

R10 = 4K7 C15 =1µF Film

R11 =10Ω

D1 = MBR 1560CT (or 16A/60V or equivalent)

L1 = 40µH core 58071 MAGNETICS

27 TURNS Ø 1,3mm (AWG 16)

COGEMA 949178

* 2 capacitors in parallel to increase input RMS current capability

** 3 capacitorsin parallel to reduce total outputESR

Table B

SUGGESTEDBOOTSTRAP CAPACITORS

Operating Frequency Bootstrap Cap.c10

f = 20KHz ≥680nF

f = 50KHz ≥470nF

f = 100KHz ≥330nF

f = 200KHz ≥220nF

f = 500KHz ≥100nF

Figure6a: P.C. Board (componentsside) and Components Layout of Figure 5 (1:1 scale).

Table A

V0R9R7

12V

15V

18V

24V

4.7kΩ

6.2kW

9.1kΩ

12kΩ

18kΩ

L4970A

9/21

Figure7: DC Test Circuits

Figure6b: P.C. Board(Back side) and ComponentsLayoutof the Circuit of Fig.5. (1:1 scale)

L4970A

10/21

Figure7A

Figure7B

L4970A

11/21

Figure7C

Figure7D

L4970A

12/21

Figure8: QuiescentDrain Current vs. Supply

Voltage (0% duty cycle - see fig. 7A).

Figure10: QuiescentDrain Current vs. Duty

Cycle

Figure12: ReferenceVoltage (pin 14) vs.

Junction Temperature(see fig.7)

Figure 9: QuiescentDrain Current vs. Junction

Temperature(0% duty cycle).

Figure 11: ReferenceVoltage(pin14) vs. Vi(see

fig. 7)

Figure 13: ReferenceVoltage(pin15) vs. Vi(see

fig. 7)

L4970A

13/21

Figure14: ReferenceVoltage (pin 15) vs.

Junction Temperature(see fig.7)

Figure16: SwitchingFrequencyvs. Input

Voltage (see fig. 5)

Figure18: SwitchingFrequencyvs. R4 (see fig. 5)

Figure 15: Reference Voltage 5.1V (pin 14)

SupplyVoltageRipple Rejection vs.

Frequency

Figure 17: SwitchingFrequency vs. Junction

Temperature(see fig 5)

Figure 19: Max.Duty Cyclevs. Frequency

L4970A

14/21

Figure20: SupplyVoltage Ripple Rejectionvs.

Frequency (see fig. 5)

Figure22: Load Transient Response(see fig. 5)

Figure24: DropoutVoltage Between Pin 9 and

Pin 7 vs. Junction Temperature

Figure 21: Line TransientResponse(see fig. 5)

Figure 23: DropoutVoltageBetween Pin 9 and

Pin 7 vs. Current at Pin 7

Figure 25: PowerDissipation (device only) vs.

InputVoltage

L4970A

15/21

Figure26: PowerDissipation(device only) vs.

OutputVoltage

Figure28: Efficiency vs. OutputCurrent

Figure30: Efficiency vs. OutputVoltage

Figure 27: Heatsink Used to Derive the Device’s

PowerDissipation

Rth -Heatsink = Tcase−Tamb

Figure 29: Efficiency vs. Output Voltage

Figure 31: Open Loop Frequency andPhase

Responseof ErrorAmplifier (see

fig.7C)

L4970A

16/21

Figure32: PowerDissipationDerating Curve

Figure33: A5.1V/12VMultiple Supply. Note the Synchronizationbetween the L4970A and the L4974A

L4970A

17/21

Figure34: 5.1V/ 10A Low CostApplication

Figure35: 10ASwitchingRegulator, Adjustable from 0V to 25V.

L4970A

18/21

Figure36: L4970A’sSync. Example

L4970A

19/21

MULTIWATT15 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 5 0.197

B 2.65 0.104

C 1.6 0.063

D 1 0.039

E 0.49 0.55 0.019 0.022

F 0.66 0.75 0.026 0.030

G 1.14 1.27 1.4 0.045 0.050 0.055

G1 17.57 17.78 17.91 0.692 0.700 0.705

H1 19.6 0.772

H2 20.2 0.795

L 22.1 22.6 0.870 0.890

L1 22 22.5 0.866 0.886

L2 17.65 18.1 0.695 0.713

L3 17.25 17.5 17.75 0.679 0.689 0.699

L4 10.3 10.7 10.9 0.406 0.421 0.429

L7 2.65 2.9 0.104 0.114

M 4.2 4.3 4.6 0.165 0.169 0.181

M1 4.5 5.08 5.3 0.177 0.200 0.209

S 1.9 2.6 0.075 0.102

S1 1.9 2.6 0.075 0.102

Dia1 3.65 3.85 0.144 0.152

L4970A

20/21

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom itsuse. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-

tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-

press written approval of SGS-THOMSON Microelectronics.

1994 SGS-THOMSON Microelectronics - All RightsReserved

MULTIWATTis a Registered Trademark of SGS-THOMSON Microelectronics

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil- France -Germany - Hong Kong - Italy - Japan - Korea -Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

L4970A

21/21

L4972A

L4972AD

January1995

2A SWITCHINGREGULATOR

.2A OUTPUT CURRENT

.5.1V TO40V OUTPUT VOLTAGERANGE

.0 TO90% DUTY CYCLE RANGE

.INTERNAL FEED-FORWARD LINEREG.

.INTERNAL CURRENT LIMITING

.PRECISE 5.1V ±2%ON CHIP REFERENCE

.RESET AND POWER FAILFUNCTIONS

.INPUT/OUTPUTSYNCPIN

.UNDER VOLTAGE LOCK OUT WITH HYS-

TERETIC TURN-ON

.PWM LATCH FOR SINGLE PULSE PER PE-

RIOD

.VERY HIGH EFFICIENCY

.SWITCHING FREQUENCY UP TO 200KHz

.THERMAL SHUTDOWN

.CONTINUOUS MODE OPERATION

DESCRIPTION

TheL4972Aisastepdownmonolithicpowerswitch-

ingregulatordelivering2Aata voltagevariablefrom

5.1to 40V.

Realized with BCD mixed technology, the device

uses a DMOS output transistorto obtain very high

efficiencyandveryfastswitching times. Featuresof

BLOCK DIAGRAM

POWERDIP

(16 + 2 + 2)

the L4972A include reset and power fail for micro-

processors,feed forward line regulation, soft start,

limiting current and thermal protection. The device

ismountedinaPowerdip 16+2 +2 andSO20large

plastic packagesand requires few externalcompo-

nents. Efficient operation at switching frequencies

up to 200KHz allows reductionin the size and cost

of externalfilter component.

ORDERING NUMBERS : L4972A (Powerdip)

L4972AD (SO20)

1/23

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

SO20

MULTIPOWER BCD TECHNOLOGY

PIN CONNECTION (top view)

THERMAL DATA

Symbol Parameter Powerdip SO-20

Rthj-pins

Rth j-amb ThermalResistance Junction-Pins max

ThermalResistance Junction-ambient max 12°C/W

60°C/W 16°C/W

80°C/W

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V11 InputVoltage 55 V

V11 Input Operating Voltage 50 V

V20 Output DC Voltage

Output Peak Voltage at t = 0.1µs f = 200khz -1

-5 V

I20 Maximum Output Current Internally Limited

VIBoostrapVoltage

BoostrapOperating Voltage 65

V11 +15 V

8InputVoltage at Pins 4, 12 12 V

V3Reset OutputVoltage 50 V

I3Reset OutputSink Current 50 mA

V2,V

10 InputVoltage at Pin2, 7, 9, 10 7 V

I2Reset Delay Sink Current 30 mA

I7Error Amplifier OutputSink Current 1 A

I8Soft StartSink Current 30 mA

Ptot Total Power Dissipation at TPINS ≤90°C

at Tamb=70°C(No copperarea on PCB) 5 / 3.75(*)

1.3/1(*) W

TJ,T

stg Junction and Storage Temperature -40 to 150 °C

(*) SO-20

L4972A-L4972AD

2/23

PINFUNCTIONS

NoName Function

1 BOOTSTRAP A Cboot capacitor connected between this terminal and the output allows to drive

properly the internalD-MOS transistor.

2 RESET DELAY A Cdcapacitor connected between this terminal and ground determines the reset

signaldelay time.

3 RESET OUT Open Collector Reset/power Fail Signal Output. This output ishigh when the supply

and the output voltages are safe.

4 RESET INPUT Inputof PowerFail Circuit. The thresholdis 5.1V. It may be connected via a divider

to theinput for power fail function. Itmust be connected tothe pin 14an external 30KΩ

resistorwhen power fail signal not required.

5, 6

15, 16 GROUND Common Ground Terminal

7 FREQUENCY

COMPENSATION A series RC network connected between this terminal and ground determines the

regulation loop gain characteristics.

8 SOFT START Soft StartTime Constant. A capacitor is connected between thisterminal and ground

to define the soft start time constant.

9 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to

thisterminal for 5.1V operation; It isconnected via a dividerfor higher voltages.

10 SYNC INPUT Multiple L4972A’s are synchronized by connecting pin 10 inputs together or via an

external syncr. pulse.

11 SUPPLY VOLTAGE Unregulated Input Voltage.

12, 19 N.C. Not Connected.

13 Vref 5.1VVref Device Reference Voltage.

14 Vstart Internal Start-up Circuit to Drive the PowerStage.

17 OSCILLATOR Rosc. External resistor connected toground determines theconstant charging current

of Cosc.

18 OSCILLATOR Cosc. External capacitor connected to ground determines (with Rosc) the switching

frequency.

20 OUTPUT Regulator Output.

L4972A-L4972AD

3/23

TheL4972Ais a 2A monolithicstepdownswitching

regulatorworkingincontinuousmoderealizedinthe

new BCD Technology. This technology allows the

integration of isolated vertical DMOSpower transi-

storsplusmixed CMOS/Bipolar transistors.

The device can deliver 2A at an output voltage ad-

justablefrom 5.1V to 40V and contains diagnostic

andcontrolfunctionsthat make it particularly suita-

ble for microprocessor basedsystems.

BLOCKDIAGRAM

The block diagram shows theDMOS powertran-

sistors and the PWM control loop. Integratedfun-

ctions include a referencevoltagetrimmed to 5.1V

±2%,softstart,undervoltagelockout,oscillatorwith

feedforward control, pulse by pulse current limit,

thermal shutdown and finally the reset and power

fail circuit. The reset and power fail circuit provides

an outputsignalfora microprocessor indicatingthe

statusof thesystem.

Device turn on is around 11V with a typical 1V hy-

sterysis,thisthresholdporvidesacorrectvoltagefor

thedriving stage of the DMOS gateand the hyste-

rysis preventsinstabilities.

Anexternalbootstrapcapacitorchargeto12Vbyan

internalvoltagereferenceis neededto providecor-

rect gatedrive to the power DMOS. The driving cir-

cuit is able to source and sink peak currents of

around0.5A to the gate of the DMOS transistor.A

typical switching time of the current in the DMOS

transistoris50ns.Duetothefastcommutationswit-

ching frequenciesup to 200kHzare possible.

ThePWM controlloopconsists of a sawtoothoscil-

lator, error amplifier,comparator,latchand theout-

putstage.Anerrorsignalis producedbycomparing

theoutputvoltagewiththeprecise5.1V±2%onchip

reference. This error signal is then compared with

the sawtooth oscillator in order to generate frixed

frequencypulse width modulateddrive forthe out-

putstage.APWMlatchisincludedtoeliminatemul-

tiple pulsing within a period even in noisy

environments.

Thegain andstability oftheloopcanbe adjustedby

an externalRC network connectedto the output of

the error amplifier. A voltage feedforward control

has been addedto the oscillator, thismaintainssu-

periorline regulationover a wide input voltageran-

ge.Closingtheloopdirectlygivesanoutputvol-tage

of 5.1V,higher voltages are obtainedby inserting a

voltage divider.

Atturn on,outputovercurrentsare preventedby the

soft start function (fig. 2). The error amplifier is in-

itiallyclampedbyan externalcapacitor,Css,andal-

lowedtorise linearlyunderthechargeof aninternal

constant current source.

Outputoverload protection isprovided bya current

limit circuit. The loadcurrent is sensed bya internal

metalresistorconnectedtoacomparator.Whenthe

load current exceedsa presetthreshold, theoutput

of the comparator setsa flipflop which turns off the

powerDMOS.Thenextclockpulse,fromaninternal

40kHzoscillator,willresettheflipflopandthepower

DMOS will again conduct. This current protection

method,ensuresaconstantcurrentoutputwhenthe

systemisoverloadedorshortcircuitedandlimitsthe

switchingfrequency,inthiscondition,to40kHz.The

Reset and Power fail circuit (fig. 4), generates an

output signal when the supply voltage exceeds a

threshold programmed by an external voltage di-

vider. The reset signal, is generated with a delay

timeprogrammedbya externalcapacitoronthede-

lay pin. When the supply voltage falls below the

thresholdor the outputvoltage goes below 5V, the

resetoutputgoeslowimmediately.The resetoutput

is anopen drain.

Fig. 4A shows the case when the supplyvoltage is

higher than the threshold,but the output voltage is

not yet 5V.

Fig. 4Bshowsthecasewhentheoutputis5.1V,but

the supply voltage is not yet higher than the fixed

threshold.

The thermal protection disables circuit operation

when the junction temperature reaches about

150°C and has a hysterysis to prevent unstable

conditions.

CIRCUIT OPERATION

L4972A-L4972AD

4/23

Figure 1 : FeedforwardWaveform.

Figure 2 : Soft StartFunction.

Figure 3 : Limiting Current Function.

L4972A-L4972AD

5/23

Figure 4 : Reset andPower Fail Functions.

L4972A-L4972AD

6/23

ELECTRICAL CHARACTERISTICS (referto the test circuit, TJ=25°C, Vi= 35V,R4=30KΩ,

C9= 2.7nF, fSW = 100KHztyp,unlessotherwise specified)

DYNAMIC CHARACTERISTICS

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

ViInput Volt. Range (pin 11) Vo=V

ref to 40V

Io=2A(**) 15 50 V 5

VoOutput Voltage Vi=15V to 50V

Io= 1A;Vo=V

ref 5 5.1 5.2 V 5

∆VoLineRegulation Vi= 15Vto 50V

Io= 0.5A; Vo=V

ref 12 30 mV

∆VoLoadRegulation Vo=V

ref Io=0.5A to2A 7 20 mV

VdDropout Voltage between

Pin 11 and 20 Io= 2A 0.25 0.4 V

I20L Max Limiting Current Vi= 15Vto 50V

Vo=V

ref to 40V 2.5 2.8 3.5 A

ηEfficiency (*) Io= 2A,f = 100KHz

Vo=V

ref

Vo= 12V 75 85

90 %

SVR Supply Voltage Ripple

Rejection Vi= 2VRMS;Io=1A

f = 100Hz;Vo=V

ref 56 60 dB 5

f Switching Frequency 90 100 110 KHz 5

∆f/∆Vi Voltage Stability of

Switching

Frequency

Vi= 15Vto 45V 2 6 % 5

∆f/TjTemperature Stability of

Switching Frequency Tj=0 to 125°C1%5

max Maximum Operating

Switching Frequency Vo=V

ref R4=15KΩ

o=2AC

9= 2.2nF 200 KHz 5

(*) Only for DIP version (**) Pulse testing with a low duty cycle

Vref SECTION(pin 13)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V13 Reference Voltage 5 5.1 5.2 V 7

∆V13 LineRegulation Vi= 15Vto 50V 10 25 mV 7

∆V13 LoadRegulation I13 = 0 to 1mA 20 40 mV 7

∆V13

∆TAverage Temperature

Coefficient Reference

Voltage

Tj=0°C to 125°C 0.4 mV/°C7

13 short Short CircuitCurrent Limit V13 = 0 70 mA 7

VSTART SECTION (pin 15)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V14 Reference Voltage 11.4 12 12.6 V 7

∆V14 LineRegulation Vi= 15to 50V 0.6 1.4 V 7

∆V14 LoadRegulation I14 = 0to 1mA 50 200 mV 7

I14 short Short CircuitCurrent Limit V15 =0V 80 mA 7

L4972A-L4972AD

7/23

ELECTRICAL CHARACTERISTICS (continued)

DC CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V11on Turn-on Threshold 10 11 12 V 7A

V11 Hyst Turn-off Hysteresys 1 V 7A

I11Q Quiescent Current V8=0; S1=D 13 19 mA 7A

11OQ Operating Supply Current V8= 0; S1= B; S2 = B 16 23 mA 7A

I20L Out Leak Current Vi= 55V; S3 = A; V8=0 2 mA 7A

SOFTSTART(pin 8)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

I8Soft Start Source Current V8= 3V; V9= 0V 80 115 150 µA7B

8Output Saturation Voltage I8= 20mA; V11 =10V

I8= 200µA; V11 = 10V 1

0.7 V

V7B

ERROR AMPLIFIER

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V7H High Level Out Voltage I7= 100µA; S1 = C

V9= 4.7V 6V7C

7L Low Level Out Voltage I7= 100µA; S1 = C

V9= 5.3V; 1.2 V 7C

I7H Source Output Current V7= 1V;V7= 4.7V 100 150 µA7C

-I7L Sink Output Current V7= 6V;V9= 5.3V 100 150 µA7C

9InputBias Current S1 = B; RS=10KΩ0.4 3 µA7C

VDC Open Loop Gain S1 = A; RS=10Ω60 dB 7C

SVR Supply Voltage Rejection 15 < Vi< 50V 60 80 dB 7C

VOS Input Offset Voltage RS=50Ω S1 = A 2 10 mV 7C

RAMP GENERATOR (pin 18)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V18 Ramp Valley S1 = B; S2 = B 1.2 1.5 V 7A

V18 Ramp Peak S1 = B Vi= 15V

S2 = B Vi=45V 2.5

5.5 V

V7A

I18 Min.Ramp Current S1 = A; I17 =100µA 270 300 µA7A

18 Max. Ramp Current S1 = A; I17 =1mA 2.4 2.7 mA 7A

SYNC FUNCTION (pin 10)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V10 Low Input Voltage Vi= 15Vto 50V; V8=0;

S1 = B; S2 = B; S4 = B –0.3 0.9 V 7A

V10 HighInput voltage V8 = 0;

S1 = B; S2 = B; S4 = B 2.5 5.5 V 7A

I10L SyncInput Current withLow

InputVoltage V10 =V

18 = 0.9V; S4 = B;

S1 = B; S2= B 0.4 mA 7A

I10H Input Current with High

InputVoltage V10 = 2.5V 1.5 mA 7A

V10 Output Amplitude 4 5 V –

tWOutput Pulse Width Vthr = 2.5V 0.3 0.5 0.8 µs–

L4972A-L4972AD

8/23

RESETAND POWER FAIL FUNCTIONS

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

V9R Rising Thereshold Voltage

(pin 9) Vi=15 to 50V

V4= 5.3V Vref

-130 Vref

-100 Vref

-80 V

mV 7D

V9F Falling Thereshold Voltage

(pin 9) Vi = 15 to 50V

V4= 5.3V 4.77 Vref

-200 Vref

-160 V

mV 7D

V2H Delay High Threshold Volt. Vi = 15 to 50V

V4= 5.3V V9=V

13 4.95 5.1 5.25 V 7D

V2L Delay Low Threshold Volt. Vi = 15 to 50V

V4=4.7V V9=V

13 1 1.1 1.2 V 7D

I2SO DelaySource Current V4=5.3V; V2=3V 306080µA7D

2SI Delay Source Sink Current V4=4.7V; V2=3V 10 mA 7D

3S Output Saturation Voltage I3= 15mA; S1 = B V4= 4.7V 0.4 V 7D

I3Output Leak Current V3 = 50V; S1 = A 100 µA7D

4R Rising Threshold Voltage V9 = V13 4.95 5.1 5.25 V 7D

V4H Hysteresis 0.4 0.5 0.6 V 7D

I4Input Bias Current 1 3 µA7D

ELECTRICAL CHARACTERISTICS (continued)

TYPICALPERFORMANCES (usingevaluationboard) :

n = 83% (Vi=35V ; Vo=VREF;I

o=2A;f

sw =100KHz)

o RIPPLE = 30mV (at 1A)

Lineregulation = 12mV(Vi= 15 to 50V)

Loadregulation = 7mV (Io=0.5 to2A)

for componentvalues Refer to the fig. 5 (Part list).

L4972A-L4972AD

9/23

PART LIST

R1= 30KΩ

R2= 10KΩ

R3= 15KΩ

R4= 30KΩ

R5=22Ω

6= 4.7KΩ

R7= see table A

R8= OPTION

R9= 4.7KΩ

1=C

2=1000µF 63V EYF (ROE)

C3=C

4=C

5=C6=2,2µF 50V

C7= 390pF Film

C8= 22nF MKT 1837 (ERO)

C9= 2.7nF KP 1830 (ERO)

C10 = 0.33µF Film

C11 =1nF

** C12 =C

13 =C

14 =100µF 40V EKR(ROE)

C15 =1µF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150µH

core 58310MAGNETICS

45 TURNS 0.91mm (AWG 19)

COGEMA 949181

* 2 capacitors in parallel to increase input RMS current capability.

* * 3 capacitors in parallel to reduce total output ESR.

Note:

In the Test and Application Circuit for L4972D are not

mounted C2, C14 and R8.

Table B

SUGGESTEDBOOSTRAP CAPACITORS

Operating Frequency Boostrap Cap.c10

f = 20KHz ≥680nF

f = 50KHz ≥470nF

f =100KHz ≥330nF

f =200KHz ≥220nF

f =500KHz ≥100nF

Figure 6a : ComponentLayout of fig.5 (1 : 1scale). Evaluation Board Available (only forDIP version)

Table A

V0R9R7

12V

15V

18V

24V

4.7kΩ

6.2kW

9.1kΩ

12Ω

18Ω

L4972A-L4972AD

10/23

Figure 7 : DCTest Circuits.

Figure 6b: P.C. Board and Component Layout of the Circuit of Fig. 5. (1:1 scale)

L4972A-L4972AD

11/23

Figure 7C.

Figure 7B.

Figure 7A.

L4972A-L4972AD

12/23

Figure 7D.

Figure 8 : QuiescentDrain Current vs.Supply

Voltage (0% duty cycle - seefig. 7A). Figure 9 : QuiescentDrain Currentvs. Junction

Temperature(0% dutycycle).

L4972A-L4972AD

13/23

Figure 10 : QuiescentDrain Current vs. Duty Cy-

cle. Figure 11 : ReferenceVoltage (pin 13)vs. Vi

(see fig. 7).

Figure 12 : ReferenceVoltage(pin 13) vs. Junc-

tion Temperature(see fig. 7). Figure 13 : ReferenceVoltage (pin 14) vs. Vi

(seefig. 7).

Figure 14 : ReferenceVoltage (pin14) vs. Junc-

tion Temperature(see fig. 7). Figure 15 : ReferenceVoltage5.1V(pin 13)Sup-

ply Voltage RippleRejection vs. Fre-

SVR

(dB)

L4972A-L4972AD

14/23

Figure 16 : Switching Frequencyvs. Input Voltage

(see fig.5). Figure 17 : Switching Frequency vs. Junction

Temperature(see fig.5).

Figure 18 : Switching Frequencyvs. R4

(see fig.5). Figure 19 : Maximum DutyCycle vs. Frequency.

Figure 20 : SupplyVoltage Ripple Rejection vs.

Frequency(see fig.5). Figure 21 : Efficiency vs. Output Voltage.

L4972A-L4972AD

15/23

Figure 22 : LineTransient Response(see fig. 5). Figure 23 : LoadTransient Response(see fig. 5).

Figure 24 : Dropout VoltagebetweenPin 11 and

Pin 20 vs. Current at Pin 20. Figure 25 : .DropoutVoltagebetweenPin 11 and

Pin 20 vs. JunctionTemperature.

Figure 26 : Power Dissipation (device only) vs.

Input Voltage. Figure 27 : PowerDissipation (device only) vs.

InputVoltage.

L4972A-L4972AD

16/23

Figure 28 : Power Dissipation (device only) vs.

OutputVoltage. Figure 29 : Power Dissipation (device only) vs.

OutputVoltage.

Figure 30 : Power Dissipation (device only) vs.

OutputCurrent. Figure 31 : Power Dissipation (deviceonly) vs.

OutputCurrent.

Figure 32 : Efficiency vs. OutputCurrent. Figure33 : TestPCB ThermalCharacteristic.

L4972A-L4972AD

17/23

Figure 34 : Junctionto AmbientThermal Resistance

vs.AreaonBoardHeatsink(DIP16+2+2) Figure 35: JunctiontoAmbient ThermalResistance

vs.Area on Board Heatsink(SO20)

Figure 36: Maximum Allowable Power Dissipa-

tion vs. Ambient Temperature (Pow-

erdip)

Figure 37: Maximum Allowable Power Dissipa-

tion vs. Ambient Temperature

(SO20)

Figure 38: Open LoopFrequencyandPhase of Er-

ror Amplifier (see fig. 7C).

L4972A-L4972AD

18/23

Figure 39 : 2A – 5.1VLow Cost ApplicationCircuit.

Figure 40 : A 5.1V/12VMultiple Supply.Note the Synchronizationbetweenthe L4972Aand L4970A.

L4972A-L4972AD

19/23

Figure 41 : L4972A’sSync.Example.

Figure 42: 1A/24V Multiple Supply. Note the synchronization between the L4972A and L4962

L4972A-L4972AD

20/23

POWERDIP20 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 24.80 0.976

E 8.80 0.346

e 2.54 0.100

e3 22.86 0.900

F 7.10 0.280

I 5.10 0.201

L 3.30 0.130

Z 1.27 0.050

L4972A-L4972AD

21/23

SO20PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

a2 2.45 0.096

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45 (typ.)

D 12.6 13.0 0.496 0.512

E 10 10.65 0.394 0.419

e 1.27 0.050

e3 11.43 0.450

F 7.4 7.6 0.291 0.299

L 0.5 1.27 0.020 0.050

M 0.75 0.030

S 8 (max.)

L4972A-L4972AD

22/23

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for

the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its

use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifica-

tions mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information pre-

viously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore-

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

L4972A-L4972AD

23/23

L4974A

January1995

3.5A SWITCHINGREGULATOR

.3.5A OUTPUT CURRENT

.5.1V TO40V OUTPUT VOLTAGERANGE

.0 TO90% DUTY CYCLE RANGE

.INTERNAL FEED-FORWARD LINEREG.

.INTERNAL CURRENT LIMITING

.PRECISE 5.1V ±2%ON CHIP REFERENCE

.RESET AND POWER FAILFUNCTIONS

.INPUT/OUTPUTSYNCPIN

.UNDER VOLTAGE LOCK OUT WITH HYS-

TERETIC TURN-ON

.PWM LATCH FOR SINGLE PULSE PER PE-

RIOD

.VERY HIGH EFFICIENCY

.SWITCHING FREQUENCY UP TO 200KHz

.THERMAL SHUTDOWN

.CONTINUOUS MODE OPERATION

DESCRIPTION

TheL4974Aisastepdownmonolithicpowerswitch-

ing regulator delivering 3.5A at a voltage variable

from5.1 to 40V.

Realized with BCD mixed technology, the device

uses a DMOS output transistorto obtain very high

efficiencyandveryfastswitching times. Featuresof

BLOCK DIAGRAM

POWERDIP (16+2+2)

the L4974Ainclude reset and power fail for micro-

processors, feed forward line regulation, soft start,

limiting current and thermal protection. The device

is mountedinaPowerdip16+2+2 plasticpackage

and requires few external components. Efficient

operationatswitching frequenciesup to200KHzal-

lows reduction in the size andcost of externalfilter

component.

ORDERING NUMBER : L4974A

1/22

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

MULTIPOWER BCD TECHNOLOGY

PIN CONNECTION (top view)

THERMAL DATA

Symbol Parameter Value Unit

Rthj-pins

Rth j-amb ThermalResistance Junction-Pins max

ThermalResistance Junction-ambient max 12

60 °C/W

°C/W

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V11 InputVoltage 55 V

V11 Input Operating Voltage 50 V

V20 Output DC Voltage

Output Peak Voltage at t = 0.1µs f = 200khz -1

-5 V

I20 Maximum Output Current Internally Limited

VIBoostrapVoltage

BoostrapOperating Voltage 65

V11 +15 V

8InputVoltage at Pins 4, 12 12 V

V3Reset OutputVoltage 50 V

I3Reset OutputSink Current 50 mA

V2,V

10 InputVoltage at Pin2, 7, 9, 10 7 V

I2Reset Delay Sink Current 30 mA

I7Error Amplifier OutputSink Current 1 A

I8Soft StartSink Current 30 mA

Ptot Total Power Dissipation at TPINS ≤90°C

at Tamb=70°C(No copperarea on PCB) 5

1.3 W

TJ,T

stg Junction and Storage Temperature -40 to 150 °C

L4974A

2/22

PINFUNCTIONS

NoName Function

1 BOOTSTRAP A Cboot capacitor connected between this terminal and the output allows to drive

properly the internalD-MOS transistor.

2 RESET DELAY A Cdcapacitor connected between this terminal and ground determines the reset

signaldelay time.

3 RESET OUT Open Collector Reset/power Fail Signal Output. This output ishigh when the supply

and the output voltages are safe.

4 RESET INPUT Inputof PowerFail Circuit. The thresholdis 5.1V. It may be connected via a divider

to theinput for power fail function. Itmust be connected tothe pin 14an external 30KΩ

resistorwhen power fail signal not required.

5, 6

15, 16 GROUND Common Ground Terminal

7 FREQUENCY

COMPENSATION A series RC network connected between this terminal and ground determines the

regulation loop gain characteristics.

8 SOFT START Soft StartTime Constant. A capacitor is connected between thisterminal and ground

to define the soft start time constant.

9 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to

thisterminal for 5.1V operation; It isconnected via a dividerfor higher voltages.

10 SYNC INPUT Multiple L4974A’s are synchronized by connecting pin 10 inputs together or via an

external syncr. pulse.

11 SUPPLY VOLTAGE Unregulated Input Voltage.

12, 19 N.C. Not Connected.

13 Vref 5.1VVref Device Reference Voltage.

14 Vstart Internal Start-up Circuit to Drive the PowerStage.

17 OSCILLATOR Rosc. External resistor connected toground determines theconstant charging current

of Cosc.

18 OSCILLATOR Cosc. External capacitor connected to ground determines (with Rosc) the switching

frequency.

20 OUTPUT Regulator Output.

L4974A

3/22

The L4974A is a 3.5A monolithic stepdown swit-

chingregulatorworkingincontinuousmoderealized

inthenewBCDTechnology.Thistechnologyallows

theintegrationofisolatedverticalDMOSpowertran-

sistors plus mixed CMOS/Bipolar transistors.

Thedevicecandeliver3.5Aatanoutputvoltagead-

justablefrom 5.1V to 40V and contains diagnostic

andcontrolfunctionsthat make it particularly suita-

ble for microprocessor basedsystems.

BLOCKDIAGRAM

The block diagram shows theDMOS powertran-

sistors and the PWM control loop. Integratedfun-

ctions include a referencevoltagetrimmed to 5.1V

±2%,softstart,undervoltagelockout,oscillatorwith

feedforward control, pulse by pulse current limit,

thermal shutdown and finally the reset and power

fail circuit. The reset and power fail circuit provides

an outputsignalfora microprocessor indicatingthe

statusof thesystem.

Device turn on is around 11V with a typical 1V hy-

sterysis,thisthresholdporvidesacorrectvoltagefor

thedriving stage of the DMOS gateand the hyste-

rysis preventsinstabilities.

Anexternalbootstrapcapacitorchargeto12Vbyan

internalvoltagereferenceis neededto providecor-

rect gatedrive to the power DMOS. The driving cir-

cuit is able to source and sink peak currents of

around0.5A to the gate of the DMOS transistor.A

typical switching time of the current in the DMOS

transistoris50ns.Duetothefastcommutationswit-

ching frequenciesup to 200kHzare possible.

ThePWM controlloopconsists of a sawtoothoscil-

lator, error amplifier,comparator,latchand theout-

putstage.Anerrorsignalis producedbycomparing

theoutputvoltagewiththeprecise5.1V±2%onchip

reference. This error signal is then compared with

the sawtooth oscillator in order to generate frixed

frequencypulse width modulateddrive forthe out-

putstage.APWMlatchisincludedtoeliminatemul-

tiple pulsing within a period even in noisy

environments.

Thegain andstability oftheloopcanbe adjustedby

an externalRC network connectedto the output of

the error amplifier. A voltage feedforward control

has been addedto the oscillator, thismaintainssu-

periorline regulationover a wide input voltageran-

ge.Closingtheloopdirectlygivesanoutputvol-tage

of 5.1V,higher voltages are obtainedby inserting a

voltage divider.

Atturn on,outputovercurrentsare preventedby the

soft start function (fig. 2). The error amplifier is in-

itiallyclampedbyan externalcapacitor,Css,andal-

lowedtorise linearlyunderthechargeof aninternal

constant current source.

Outputoverload protection isprovided bya current

limit circuit. The loadcurrent is sensed bya internal

metalresistorconnectedtoacomparator.Whenthe

load current exceedsa presetthreshold, theoutput

of the comparator setsa flipflop which turns off the

powerDMOS.Thenextclockpulse,fromaninternal

40kHzoscillator,willresettheflipflopandthepower

DMOS will again conduct. This current protection

method,ensuresaconstantcurrentoutputwhenthe

systemisoverloadedorshortcircuitedandlimitsthe

switchingfrequency,inthiscondition,to40kHz.The

Reset and Power fail circuit (fig. 4), generates an

output signal when the supply voltage exceeds a

threshold programmed by an external voltage di-

vider. The reset signal, is generated with a delay

timeprogrammedbya externalcapacitoronthede-

lay pin. When the supply voltage falls below the

thresholdor the outputvoltage goes below 5V, the

resetoutputgoeslowimmediately.The resetoutput

is anopen drain.

Fig. 4A shows the case when the supplyvoltage is

higher than the threshold,but the output voltage is

not yet 5V.

Fig. 4Bshowsthecasewhentheoutputis5.1V,but

the supply voltage is not yet higher than the fixed

threshold.

The thermal protection disables circuit operation

when the junction temperature reaches about

150°C and has a hysterysis to prevent unstable

conditions.

CIRCUIT OPERATION

L4974A

4/22

Figure 1 : FeedforwardWaveform.

Figure 2 : Soft StartFunction.

Figure 3 : Limiting Current Function.

L4974A

5/22

Figure 4 : Reset andPower Fail Functions.

L4974A

6/22

ELECTRICAL CHARACTERISTICS (referto the test circuit, TJ=25°C, Vi= 35V,R4=30KΩ,

C9= 2.7nF, fSW = 100KHztyp,unlessotherwise specified)

DYNAMIC CHARACTERISTICS

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

ViInput Volt. Range (pin 11) Vo=V

ref to 40V

Io= 3.5A (*) 15 50 V 5

VoOutput Voltage Vi=15V to 50V

Io= 2A;Vo=V

ref 5 5.1 5.2 V 5

∆VoLineRegulation VI= 15V to 50V

Io= 1A; Vo=V

ref 12 30 mV

∆VoLoadRegulation VO=V

ref Io= 1Ato 3.5A

Io=2Ato3A 825mV

410mV

dDropout Voltage between

Pin 11 and 20 Io=2A

o= 3.5A 0.25

0.45 0.4

0.7 V

I20L Max Limiting Current Vi= 15Vto 50V

Vo=V

ref to 40V 4 4.75 5.5 A

ηEfficiency Io= 3.5A, f = 100KHz

Vo=V

ref

Vo= 12V 80 85

90 %

SVR Supply Voltage Ripple

Rejection Vi= 2VRMS;Io=5A

f = 100Hz;Vo=V

ref 56 60 dB 5

f Switching Frequency 90 100 110 KHz 5

∆f/∆Vi Voltage Stability of

Switching

Frequency

Vi= 15Vto 45V 2 6 % 5

∆f/TjTemperature Stability of

Switching Frequency Tj=0 to 125°C1%5

max Maximum Operating

Switching Frequency Vo=V

ref R4=15KΩ

o= 3.5A C9= 2.2nF 200 KHz 5

(*) Pulse testing with a low duty cycle

Vref SECTION(pin 13)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V13 Reference Voltage 5 5.1 5.2 V 7

∆V13 LineRegulation Vi= 15Vto 50V 10 25 mV 7

∆V13 LoadRegulation I13 = 0 to 1mA 20 40 mV 7

∆V13

∆TAverage Temperature

Coefficient Reference

Voltage

Tj=0°C to 125°C 0.4 mV/°C7

13 short Short CircuitCurrent Limit V13 = 0 70 mA 7

VSTART SECTION (pin 15)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V14 Reference Voltage 11.4 12 12.6 V 7

∆V14 LineRegulation Vi= 15to 50V 0.6 1.4 V 7

∆V14 LoadRegulation I14 = 0to 1mA 50 200 mV 7

I14 short Short CircuitCurrent Limit V15 =0V 80 mA 7

L4974A

7/22

ELECTRICAL CHARACTERISTICS (continued)

DC CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V11on Turn-on Threshold 10 11 12 V 7A

V11 Hyst Turn-off Hysteresys 1 V 7A

I11Q Quiescent Current V8=0; S1=D 13 19 mA 7A

11OQ Operating Supply Current V8= 0; S1 = B; S2 = B 16 23 mA 7A

I20L Out Leak Current Vi= 55V; S3 = A; V8=0 2 mA 7A

SOFTSTART(pin 8)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

I8Soft Start Source Current V8= 3V; V9= 0V 80 115 150 µA7B

8Output Saturation Voltage I8= 20mA; V11 =10V

I8= 200µA; V11 = 10V 1

0.7 V

V7B

ERROR AMPLIFIER

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V7H High Level Out Voltage I7=-100µA; S1 = C

V9= 4.7V 6V7C

7L Low Level Out Voltage I7= 100µA; S1 = C

V9= 5.3V; 1.2 V 7C

I7H Source Output Current V7= 1V;V7= 4.7V 100 150 µA7C

-I7L Sink Output Current V7= 6V;V9= 5.3V 100 150 µA7C

9InputBias Current S1 = B; RS=10KΩ0.4 3 µA7C

VDC Open Loop Gain S1 = A; RS=10Ω60 dB 7C

SVR Supply Voltage Rejection 15 < Vi< 50V 60 80 dB 7C

VOS Input Offset Voltage RS=50Ω S1 = A 2 10 mV 7C

RAMP GENERATOR (pin 18)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V18 Ramp Valley S1 = B; S2 = B 1.2 1.5 V 7A

V18 Ramp Peak S1 = B Vi= 15V

S2 = B Vi=45V 2.5

5.5 V

V7A

I18 Min.Ramp Current S1 = A; I17 =100µA 270 300 µA7A

18 Max. Ramp Current S1 = A; I17 =1mA 2.4 2.7 mA 7A

SYNC FUNCTION (pin 10)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V10 Low Input Voltage Vi= 15Vto 50V; V8=0;

S1 = B; S2 = B; S4 = B –0.3 0.9 V 7A

V10 HighInput voltage V8=0;

S1 = B; S2 = B; S4 = B 2.5 5.5 V 7A

+I10L SyncInput Current withLow

InputVoltage V10 =V

18 = 0.9V; S4 = B;

S1 = B; S2= B 0.4 mA 7A

+I10H Input Current with High

InputVoltage V10 = 2.5V 1.5 mA 7A

V10 Output Amplitude 4 5 V –

tWOutput Pulse Width Vthr = 2.5V 0.3 0.5 0.8 µs–

L4974A

8/22

RESETAND POWER FAIL FUNCTIONS

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

V9R Rising Thereshold Voltage

(pin 9) Vi=15 to 50V

V4= 5.3V Vref

-130 Vref

-100 Vref

-80 V

mV 7D

V9F Falling Thereshold Voltage

(pin 9) Vi = 15 to 50V

V4= 5.3V 4.77 Vref

-200 Vref

-160 V

mV 7D

V2H Delay High Threshold Volt. Vi = 15 to 50V

V4= 5.3V V9=V

13 4.95 5.1 5.25 V 7D

V2L Delay Low Threshold Volt. Vi = 15 to 50V

V4=4.7V V9=V

13 1 1.1 1.2 V 7D

I2SO DelaySource Current V4=5.3V; V2=3V 306080µA7D

2SI Delay Source Sink Current V4=4.7V; V2=3V 10 mA 7D

3S Output Saturation Voltage I3= 15mA; S1 = B V4= 4.7V 0.4 V 7D

I3Output Leak Current V3 = 50V; S1 = A 100 µA7D

4R Rising Threshold Voltage V9 = V13 4.955 5.1 5.25 V 7D

V4H Hysteresis 0.4 0.5 0.6 V 7D

I4Input Bias Current 1 3 µA7D

ELECTRICAL CHARACTERISTICS (continued)

Figure 5 : Testand EvaluationBoardCircuit.

TYPICALPERFORMANCES (usingevaluationboard) :

n = 83% (Vi=35V ; Vo=VREF;I

o= 3.5A; fsw =100KHz)

Vo RIPPLE = 30mV (at 1A)

Lineregulation = 12mV(Vi= 15 to 50V)

Loadregulation = 8mV (Io=1 to 3.5A)

for componentvalues Refer to the fig. 5 (Part list).

L4974A

9/22

PART LIST

R1= 30KΩ

R2= 10KΩ

R3= 15KΩ

R4= 30KΩ

R5=22Ω

6= 4.7KΩ

R7= see table A

R8= OPTION

R9= 4.7KΩ

1=C

2=1000µF 63V EYF (ROE)

C3=C

4=C

5=C6=2,2µF 50V

C7= 390pF Film

C8= 22nF MKT 1837 (ERO)

C9= 2.7nF KP 1830 (ERO)

C10 = 0.33µF Film

C11 =1nF

** C12 =C

13 =C

14 =100µF 40V EKR(ROE)

C15 =1µF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150µH

core 58310MAGNETICS

45 TURNS 0.91mm (AWG 19)

COGEMA 949181

* 2 capacitors in parallel to increase input RMS current capability.

* * 3 capacitors in parallel to reduce total output ESR.

Table A

V0R9R7

12V

15V

18V

24V

4.7kΩ

6.2kW

9.1kΩ

12Ω

18Ω

Table B

SUGGESTEDBOOSTRAP CAPACITORS

Operating Frequency Boostrap Cap.c10

f = 20KHz ≥680nF

f = 50KHz ≥470nF

f =100KHz ≥330nF

f =200KHz ≥220nF

f =500KHz ≥100nF

Figure 6a : ComponentLayout of fig.5 (1 : 1scale). Evaluation Board Available

L4974A

10/22

Figure 7 : DCTest Circuits.

Figure 6b: P.C. Board and Component Layout of the Circuit of Fig. 5. (1:1 scale)

L4974A

11/22

Figure 7C.

Figure 7B.

Figure 7A.

L4974A

12/22

Figure 7D.

Figure 8 : QuiescentDrain Current vs.Supply

Voltage (0% duty cycle - seefig. 7A). Figure 9 : QuiescentDrain Currentvs. Junction

Temperature(0% dutycycle).

L4974A

13/22

Figure 10 : QuiescentDrain Current vs. Duty Cy-

cle. Figure 11 : ReferenceVoltage (pin 13)vs. Vi

(see fig. 7).

Figure 12 : ReferenceVoltage(pin 13) vs. Junc-

tion Temperature(see fig. 7). Figure 13 : ReferenceVoltage (pin 14) vs. Vi

(seefig. 7).

Figure 14 : ReferenceVoltage (pin14) vs. Junc-

tion Temperature(see fig. 7). Figure 15 : ReferenceVoltage5.1V(pin 13)Sup-

ply Voltage RippleRejection vs. Fre-

SVR

(dB)

L4974A

14/22

Figure 16 : Switching Frequencyvs. Input Voltage

(see fig.5). Figure 17 : Switching Frequency vs. Junction

Temperature(see fig.5).

Figure 18 : Switching Frequencyvs. R4

(see fig.5). Figure 19 : Maximum DutyCycle vs. Frequency.

Figure 20 : SupplyVoltage Ripple Rejection vs.

Frequency(see fig.5). Figure 21 : Efficiency vs. Output Voltage.

L4974A

15/22

Figure 22 : LineTransient Response(see fig. 5). Figure 23 : LoadTransient Response(see fig. 5).

Figure 24 : Dropout VoltagebetweenPin 11 and

Pin 20 vs. Current at Pin 20. Figure 25 : .DropoutVoltagebetweenPin 11 and

Pin 20 vs. JunctionTemperature.

Figure 26 : Power Dissipation (device only) vs.

Input Voltage. Figure 27 : PowerDissipation (device only) vs.

InputVoltage.

L4974A

16/22

Figure 28 : Power Dissipation (device only) vs.

OutputVoltage. Figure 29 : Power Dissipation (device only) vs.

OutputVoltage.

Figure 30 : Power Dissipation (device only) vs.

OutputCurrent. Figure 31 : Power Dissipation (deviceonly) vs.

OutputCurrent.

Figure 32 : Efficiency vs. OutputCurrent. Figure33 : TestPCB ThermalCharacteristic.

L4974A

17/22

Figure 34 : Junctionto AmbientThermal Resistance

vs.AreaonBoardHeatsink(DIP16+2+2) Figure 35: Maximum Allowable Power Dissipa-

tion vs. Ambient Temperature (Pow-

erdip)

Figure 36: Open LoopFrequencyandPhase of Er-

ror Amplifier (see fig. 7C).

L4974A

18/22

Figure 37 : 3.5A – 5.1VLow Cost ApplicationCircuit.

Figure 38 : A 5.1V/12VMultiple Supply.Note the Synchronizationbetweenthe L4974Aand L4970A.

L4974A

19/22

Figure 39 : L4974A’sSync.Example.

Figure 40: 1A/24V Multiple Supply. Note the synchronization between the L4974A and L4962

L4974A

20/22

POWERDIP20 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 24.80 0.976

E 8.80 0.346

e 2.54 0.100

e3 22.86 0.900

F 7.10 0.280

I 5.10 0.201

L 3.30 0.130

Z 1.27 0.050

L4974A

21/22

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for

the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its

use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifica-

tions mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information pre-

viously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore-

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

L4974A

22/22

L4975A

5A SWITCHING REGULATOR

5A OUTPUT CURRENT

5.1V TO 40V OUTPUT VOLTAGERANGE

0 TO 90% DUTY CYCLE RANGE

INTERNAL FEED-FORWARD LINE REGULA-

TION

INTERNAL CURRENT LIMITING

PRECISE 5.1V ±2% ON CHIP REFERENCE

RESETAND POWER FAIL FUNCTIONS

SOFT START

INPUT/OUTPUT SYNC PIN

UNDER VOLTAGE LOCK OUT WITH HYS-

TERETIC TURN-ON

PWM LATCH FOR SINGLE PULSE PER PE-

RIOD

VERYHIGH EFFICIENCY

SWITCHING FREQUENCY UP TO 500KHz

THERMAL SHUTDOWN

CONTINUOUS MODE OPERATION

DESCRIPTION

The L4975A is a stepdown monolithic power

switching regulator delivering 5A at a voltagevari-

able from 5.1 to 40V.

Realized with BCD mixed technology, the device

usesa DMOSoutput transistorto obtain very high

efficiency and very fast switching times. Features

of the L4975A include reset and power fail for mi-

croprocessors, feed forward line regulation, soft

start, limiting current and thermal protection. The

device is mounted in a 15-lead multiwatt plastic

power package and requiresfew external compo-

nents. Efficient operation at switching frequencies

up to 500KHz allows reduction in the size and

cost of external filter components.

This isadvanced information on anew productnow in development or undergoing evaluation. Details are subject to change without notice.

November 1991

BLOCK DIAGRAM

Multiwatt15V

ORDERING NUMBER: L4975A

MULTIPOWER BCD TECHNOLOGY

1/21

PIN CONNECTION (Top view)

ABSOLUTE MAXIMUMRATINGS

Symbol Parameter Value Unit

V9Input Voltage 55 V

V9Input Operating Voltage 50 V

V7Output DC Voltage

Output Peak Voltage at t = 0.1µs f = 200KHz -1

-7 V

I7Maximum Output Current Internally Limited

V6Bootstrap Voltage

Bootstrap Operating Voltage 65

V9+15 V

12 Input Voltage at Pins 3, 12 12 V

V4Reset Output Voltage 50 V

I4Reset Output Sink Current 50 mA

V5,V

10, V11, V13 Input Voltage at Pin 5, 10, 11, 13 7 V

I5Reset Delay Sink Current 30 mA

I10 Error Amplifier Output Sink Current 1 A

I12 Soft Start Sink Current 30 mA

Ptot Total Power Dissipation at Tcase < 120°C30W

stg Junction and Storage Temperature -40 to 150 °C

THERMAL DATA

Symbol Parameter Value Unit

Rth j-case

Rth j-amb Thermal Resistance Junction-case max

Thermal Resistance Junction-ambient max 1

35 °C/W

°C/W

L4975A

2/21

CIRCUIT OPERATION (refer to the block dia-

gram)

The L4975Ais a 5A monolithicstepdownswitching

regulator working in continuous mode realized in

the new BCD Technology. This technology allows

the integration of isolated vertical DMOS power

transistors plus mixed CMOS/Bipolar transistors.

The device can deliver 5A at an output voltage

adjustable from 5.1V to 40V, and contains diag-

nostic and control functions that make it particu-

larlysuitable for microprocessor based systems.

BLOCK DIAGRAM

The block diagram shows the DMOS power tran-

sistor and the PWM control loop. Integrated func-

tions include a referencevoltage trimmed to 5.1V

±2%, soft start, undervoltage lockout, oscillator

with feedforward control, pulse by pulse current

limit, thermal shutdown and finally the reset and

power fail circuit. The reset and power fail circuit

provides an output signal for a microprocessor in-

dicating the statusof the system.

Device turn on is around 11V with a typical 1V

hysteresis, this threshold provides a correct volt-

age for the driving stage of the DMOS gate and

the hysteresisprevents instabilities.

An external bootstrap capacitor charged to 12V

by an internal voltage reference is needed to pro-

vide correct gate drive to the power DMOS. The

driving circuit is able to source and sink peak cur-

rents of around 0.5A to the gate of the DMOS

transistor. A typical switching time of the current

in the DMOS transistor is 50ns. Due to the fast

commutation switching frequencies up to 500kHz

arepossible.

The PWM control loop consists of a sawtooth os-

cillator, error amplifier, comparator, latch and the

output stage. An error signal is produced by com-

paring the output voltage with the precise 5.1V ±

2% on chip reference. This error signal is then

compared with the sawtooth oscillator, in order to

generatea fixedfrequencypulse width modulated

drive for the output stage. A PWM latch is in-

cluded to eliminate multiple pulsing within a pe-

riod even in noisy environments. The gain and

PIN FUNCTIONS

NoName Function

1 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging

current of Cosc.

2 OSCILLATOR Cosc. External capacitor connected to grounddetermines (with Rosc) the

switching frequency.

3 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a

dividerto the input for power failfunction. It must be connected to the pin 14 an

external 30KΩresistorwhen power fail signal not required.

4 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the

supply and the output voltages are safe.

5 RESET DELAY A Cdcapacitor connected between this terminal and ground determines the

reset signaldelay time.

6 BOOTSTRAP A Cboot capacitor connected between thisterminal and the output allows to

drive properly the internal D-MOS transistor.

7 OUTPUT Regulator Output.

8 GROUND Common Ground Terminal

9 SUPPLY VOLTAGE UnregulatedInput Voltage.

10 FREQUENCY

COMPENSATION A series RC network connected between this terminal and ground determines

the regulation loop gain characteristics.

11 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected

directly to this terminal for 5.1V operation; It is connected via a divider for higher

voltages.

12 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and

ground to define the soft start time constant.

13 SYNC INPUT Multiple L4975A are synchronized by connecting pin 13inputs together or via

an external syncr. pulse.

14 Vref 5.1V Vref Device Reference Voltage.

15 Vstart Internal Start-up Circuit to Drive the Power Stage.

L4975A

3/21

Figure1: FeedforwardWaveform

Figure3: LimitingCurrent Function

Figure2: Soft Start Function

L4975A

4/21

stability of the loop can be adjusted by an exter-

nal RC network connected to the output of the er-

ror amplifier. A voltage feedforward control has

been added to the oscillator, this maintains supe-

rior line regulation over a wide input voltage

range. Closing the loop directly gives an output

voltage of 5.1V, higher voltages are obtained by

inserting a voltagedivider.

At turn on output overcurrents are prevented by

the soft start function(fig. 2). The error amplifieris

initiallyclamped by an external capacitorCss and

allowed to rise linearly under the charge of an in-

ternal constant current source.

Output overload protection is provided by a cur-

rentlimit circuit (fig. 3). Theload current is sensed

by an internal metal resistor connected to a com-

parator. When the load current exceeds a preset

threshold the output of the comparator sets a flip

flop which turns off the power DMOS. The next

clock pulse, from an internal 40kHz oscillator will

reset the flip flop and the power DMOS will again

conduct. This current protection method, ensures

a constant current output when the system is

overloaded or short circuited and limits the

switching frequency,in this condition,to 40kHz.

The Reset and Power fail circuitry (fig 4) gener-

ates an output signal when the supply voltage ex-

ceeds a threshold programmed by an external

voltage divider. The reset signal, is generated

with a delay time programmed by an external ca-

pacitor on the delay pin. Whenthe supply voltage

falls below the threshold or the output voltage

goes below 5V the reset output goes low immedi-

ately. The reset output is an open collector-drain.

Fig 4A shows the case when the supply voltage is

higher than the threshold, but the output voltage

isnot yet 5V.

Fig 4B shows the case when the output is 5.1V

but the supply voltage is not yet higher than the

fixedthreshold.

The thermal protection disables circuit operation

when the junction temperature reaches about

150°C and has an hysterysis to prevent unstable

conditions.

Figure4: Reset and Power Fail Functions.

L4975A

5/21

ELECTRICALCHARACTERISTICS (Refer to the test circuit, Tj=25°C, Vi= 35V, R4= 16KΩ,

C9= 2.2nF, fSW = 200KHz typ, unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

Viinput Voltage Range (pin 9) Vo=V

ref to 40V

Io=5A 15 50 V 5

VoOutput Votage Vi= 15V to 50V

Io= 3A; Vo=V

ref5 5.1 5.2 V 5

∆VoLine Regulation Vi= 15V to 50V

Io= 2A; Vo=V

ref12 30 mV 5

∆VoLoad Regulation Vo=V

ref

Io=2Ato4A

o=1Ato5A 10

20 30

50 mV

VdDropout VoltageBetween

Pin 9 and 7 Io=3A

o=5A 0.4

0.55 0.6

0.8 V

I7L Max. LimitingCurrent Vi= 15 to 50V

Vo=V

ref to 40V 5.5 6.5 7.5 A 5

ηEfficiency Io=3A

o=V

ref

Vo= 12V 70 75

80 %

Io=5A

o=V

ref

Vo= 12V 80 85

92 %

SVR Supply Voltage Ripple

Reject. Vi= 2VRMS; Io=3A

f = 100Hz; Vo=V

ref 56 60 dB 5

f Switching Frequency 180 200 220 KHz 5

∆f

∆ViVoltage Stability of

Swiching Frequency Vi= 15V to 45V 2 6 % 5

∆f

TjTemperature Stability of

Swiching Frequency Tj= 0 to 125°C1%5

max Maximum Operating

Switching Frequency Vo=V

ref;R

4= 10KΩ

Io= 5A; C9= 1nF 500 KHz 5

Vref SECTION(pin 14)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V14 Reference Voltage 5 5.1 5.2 V 7

∆V14 Line Regulation Vi= 15V to 50V 10 25 mV 7

∆V14 Load Regulation I14 = 0 to 1mA 20 40 mV 7

∆V14

∆TAverage Temperature

CoefficientReference

Voltage

Tj=0°C to 125°C 0.4 mV/°C7

14 short Short Circuit Current Limit V14 = 0 70 mA 7

VSTART SECTION(pin 15)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V15 Reference Voltage 11.4 12 12.6 V 7

∆V15 Line Regulation Vi= 15 to 50V 0.6 1.4 V 7

∆V15 Load Regulation I15 = 0 to 1mA 50 200 mV 7

I15 short Short Circuit Current Limit V15 =0V 80 mA 7

L4975A

6/21

ELECTRICALCHARACTERISTICS (continued)

DCCHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V9on Turn-on Threshold 10 11 12 V 7A

V9 Hyst Turn-off Hysteresys 1 V 7A

I9Q Quiescent Current V12 =0; S1=D 13 19 mA 7A

9OQ Operating SupplyCurrent V12 = 0; S1 = C; S2 = B 16 23 mA 7A

I7L Out Leak Current Vi= 55V; S3 = A; V12 =0 2 mA 7A

SOFTSTART

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

I12 Soft Start Source Current V12 = 3V; V11 = 0V 70 100 130 µA7B

12 Output Saturation Voltage I12 = 20mA; V9= 10V

I12 = 200µA; V9= 10V 1

0.7 V

V7B

ERROR AMPLIFIER

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V10H High Level Out Voltage I10 = -100µA; S1 = C

V11 = 4.7V 6V7C

10L Low Level Out Voltage I10 = +100µA; S1 = C

V11 = 5.3V; 1.2 V 7C

I10H Source Output Current V10 = 1V; S1 = E

V11 = 4.7V 100 150 µA7C

10L Sink Output Current V10 = 6V; S1 = D

V11 = 5.3V 100 150 µA7C

11 Input Bias Current RS= 10KΩ0.4 3 µA–

VDC Open Loop Gain VVCM = 4V;

RS=10Ω60 dB –

SVR Supply Voltage Rejection 15 < Vi< 50V;

RS=10Ω60 80 dB –

VOS Input Offset Voltage RS=50Ω210mV–

RAMP GENERATOR(pin 2)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V2Ramp Valley S1 = C; S2 = B 1.2 1.5 V 7A

V2Ramp Peak S1 = C Vi= 15V

S2 = B Vi= 45V 2.5

5.5 V

V7A

I2Min. Ramp Current S1 = A; I1= 100µA 270 300 µA7A

2Max. Ramp Current S1 = A; I1 = 1mA 2.4 2.7 mA 7A

SYNC FUNCTION (pin 13)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V13 Low Input Voltage Vi= 15V to 50V; V12 =0;

S1 = C; S2 = B; S4 = B –0.3 0.9 V 7A

V13 High Input voltage V12=0;

S1 = C; S2 = B; S4 = B 3.5 5.5 V 7A

I13L Sync Input Current with

Low Input Voltage V2=V

13 = 0.9V; S4 = A;

S1 = C; S2 = B 0.4 mA 7A

I13H Input Current with High

Input Voltage V13 = 3.5V; S4 = A;

S1 = C; S2 = B 1.5 mA 7A

V13 Output Amplitude 4 5 V –

tWOutput Pulse Width Vthr = 2.5V 0.3 0.5 0.8 µs–

L4975A

7/21

ELECTRICALCHARACTERISTICS (continued)

RESETAND POWERFAIL FUNCTIONS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V11R Rising Threshold Voltage

(pin 11) Vi= 15 to 50V

V3= 5.3V Vref

–120 Vref

–100 Vref

–80 V

mV 7D

V11F Falling Threshold Voltage

(pin 11) Vi = 15 to 50V

V3= 5.3V 4.77 Vref

–200 Vref

–160 V

mV 7D

V5H Delay High Threshold

Voltage Vi= 15 to 50V

V11 =V

14 4.95 5.1 5.25 V 7D

V5L Delay Low Threshold

Voltage Vi = 15 to 50V

V11 =V

14 V3= 5.3V 1 1.1 1.2 V 7D

–I5SO Delay Source Current V3= 5.3V; V5=3V 406080µA7D

5SI Delay Sink Current V3= 4.7V; V5=3V 10 mA 7D

4S Out Saturation Voltage I4= 15mA; S1 = B

V3= 4.7V 0.4 V 7D

I4Output Leak Current V4= 50V; S1 = A

V3= 5.3V 100 µA7D

3R Rising Threshold Voltage V11 =V

14 4.95 5.1 5.25 V 7D

V3H Hysteresys 0.4 0.5 0.6 V 7D

I3Input Bias Current 1 3 µA7D

Figure5: Test andEvaluationBoard Circuit

TYPICAL PERFORMANCES (using evaluationboard) :

n =83% (Vi=35V ; Vo=VREF ;I

o=5A;fSW =200KHz)

Vo RIPPLE =30mV (at 5A)with output filter capacitor ESR ≤60mΩ

Line regulation = 5mV (Vi=15 to 50V)

Load regulation= 15mV (Io= 2 to 5A)

For componentvalues,refer to test circuit partlist.

L4975A

8/21

PARTS LIST

R1= 30KΩC1,C

2= 3300µF 63VLEYF (ROE

R2= 10KΩC3,C

6= 2.2µF

R3= 15KΩC7= 390pF Film

R4= 16KΩC8= 22nF MKT 1817 (ERO)

R5=22Ω0,5W

R6= 4K7 C9= 2.2nF KP1830

R7=10ΩC

10 = 220nF MKT

R8= see tab. A C11 = 2.2nF MP1830

R9= OPTION **C12,C

13,C

14 = 220µF 40VLEKR

R10 = 4K7 C15 =1µF Film

R11 =10Ω

D1 = MBR 760CT (or 7.5A/60Vor equivalent)

L1 = 80µH core 58930 MAGNETICS

24 TURNS Ø 1.1mm (AWG 17)

COGEMA 949178

* 2 capacitors in parallel to increase input RMS current capability

** 3 capacitorsin parallel to reduce total outputESR

Table B

SUGGESTEDBOOTSTRAP CAPACITORS

Operating Frequency Bootstrap Cap.c10

f = 20KHz ≥680nF

f = 50KHz ≥470nF

f = 100KHz ≥330nF

f = 200KHz ≥220nF

f = 500KHz ≥100nF

Figure6a: P.C. Board (componentsside) and Components Layout of Figure 5 (1:1 scale).

Table A

V0R9R7

12V

15V

18V

24V

4.7kΩ

6.2kW

9.1kΩ

12kΩ

18kΩ

L4975A

9/21

Figure7: DC Test Circuits

Figure6b: P.C. Board(Back side) and ComponentsLayoutof the Circuit of Fig.5. (1:1 scale)

L4975A

10/21

Figure7A

Figure7B

L4975A

11/21

Figure7C

Figure7D

L4975A

12/21

Figure8: QuiescentDrain Current vs. Supply

Voltage (0% duty cycle - see fig. 7A).

Figure10: QuiescentDrain Current vs. Duty

Cycle

Figure12: ReferenceVoltage (pin 14) vs.

Junction Temperature(see fig.7)

Figure 9: QuiescentDrain Current vs. Junction

Temperature(0% duty cycle).

Figure 11: ReferenceVoltage(pin14) vs. Vi(see

fig. 7)

Figure 13: ReferenceVoltage(pin15) vs. Vi(see

fig. 7)

L4975A

13/21

Figure14: ReferenceVoltage (pin 15) vs.

Junction Temperature(see fig.7)

Figure16: SwitchingFrequencyvs. Input

Voltage (see fig. 5)

Figure18: SwitchingFrequencyvs. R4 (see fig. 5)

Figure 15: Reference Voltage 5.1V (pin 14)

SupplyVoltageRipple Rejection vs.

Frequency

Figure 17: SwitchingFrequency vs. Junction

Temperature(see fig 5)

Figure 19: Max.Duty Cyclevs. Frequency

L4975A

14/21

Figure20: SupplyVoltage Ripple Rejectionvs.

Frequency (see fig. 5)

Figure22: Load Transient Response(see fig. 5)

Figure24: DropoutVoltage Between Pin 9 and

Pin 7 vs. Junction Temperature

Figure 21: Line TransientResponse(see fig. 5)

Figure 23: DropoutVoltageBetween Pin 9 and

Pin 7 vs. Current at Pin 7

Figure 25: PowerDissipation (device only) vs.

InputVoltage

L4975A

15/21

Figure26: PowerDissipation(device only) vs.

OutputVoltage

Figure28: Efficiency vs. OutputCurrent

Figure30: Efficiency vs. OutputVoltage

Figure 27: Heatsink Used to Derive the Device’s

PowerDissipation

Rth -Heatsink = Tcase−Tamb

Figure 29: Efficiency vs. Output Voltage

Figure 31: Open Loop Frequency andPhase

Responseof ErrorAmplifier (see

fig.7C)

L4975A

16/21

Figure32: PowerDissipationDerating Curve

Figure33: 5.1V/12VMultiple Supply. Note the Synchronizationbetween the L4975A and theL4974A

L4975A

17/21

Figure34: 5.1V/ 5A Low CostApplication

Figure35: 5A Switching Regulator, Adjustable from 0V to 25V.

L4975A

18/21

Figure36: L4975A’sSync. Example

L4975A

19/21

MULTIWATT15 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 5 0.197

B 2.65 0.104

C 1.6 0.063

D 1 0.039

E 0.49 0.55 0.019 0.022

F 0.66 0.75 0.026 0.030

G 1.14 1.27 1.4 0.045 0.050 0.055

G1 17.57 17.78 17.91 0.692 0.700 0.705

H1 19.6 0.772

H2 20.2 0.795

L 22.1 22.6 0.870 0.890

L1 22 22.5 0.866 0.886

L2 17.65 18.1 0.695 0.713

L3 17.25 17.5 17.75 0.679 0.689 0.699

L4 10.3 10.7 10.9 0.406 0.421 0.429

L7 2.65 2.9 0.104 0.114

M 4.2 4.3 4.6 0.165 0.169 0.181

M1 4.5 5.08 5.3 0.177 0.200 0.209

S 1.9 2.6 0.075 0.102

S1 1.9 2.6 0.075 0.102

Dia1 3.65 3.85 0.144 0.152

L4975A

20/21

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom itsuse. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-

tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-

press written approval of SGS-THOMSON Microelectronics.

1994 SGS-THOMSON Microelectronics - All RightsReserved

MULTIWATTis a Registered Trademark of SGS-THOMSON Microelectronics

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil- France -Germany - Hong Kong - Italy - Japan - Korea -Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

L4975A

21/21

L4977A

7A SWITCHING REGULATOR

7A OUTPUT CURRENT

5.1V TO 40V OUTPUT VOLTAGERANGE

0 TO 90% DUTY CYCLE RANGE

INTERNAL FEED-FORWARD LINE REGULA-

TION

INTERNAL CURRENT LIMITING

PRECISE 5.1V ±2% ON CHIP REFERENCE

RESETAND POWER FAIL FUNCTIONS

SOFT START

INPUT/OUTPUT SYNC PIN

UNDER VOLTAGE LOCK OUT WITH HYS-

TERETIC TURN-ON

PWM LATCH FOR SINGLE PULSE PER PE-

RIOD

VERYHIGH EFFICIENCY

SWITCHING FREQUENCY UP TO 500KHz

THERMAL SHUTDOWN

CONTINUOUS MODE OPERATION

DESCRIPTION

The L4977A is a stepdown monolithic power

switching regulator delivering 7A at a voltagevari-

able from 5.1 to 40V.

Realized with BCD mixed technology, the device

usesa DMOSoutput transistorto obtain very high

efficiency and very fast switching times. Features

of the L4977A include reset and power fail for mi-

croprocessors, feed forward line regulation, soft

start, limiting current and thermal protection. The

device is mounted in a 15-lead multiwatt plastic

power package and requiresfew external compo-

nents. Efficient operation at switching frequencies

up to 500KHz allows reduction in the size and

cost of external filter components.

This isadvanced information on anew productnow in development or undergoing evaluation. Details are subject to change without notice.

November 1991

BLOCK DIAGRAM

Multiwatt15V

ORDERING NUMBER: L4977A

MULTIPOWER BCD TECHNOLOGY

1/21

PIN CONNECTION (Top view)

ABSOLUTE MAXIMUMRATINGS

Symbol Parameter Value Unit

V9Input Voltage 55 V

V9Input Operating Voltage 50 V

V7Output DC Voltage

Output Peak Voltage at t = 0.1µs f = 200KHz -1

-7 V

I7Maximum Output Current Internally Limited

V6Bootstrap Voltage

Bootstrap Operating Voltage 65

V9+15 V

12 Input Voltage at Pins 3, 12 12 V

V4Reset Output Voltage 50 V

I4Reset Output Sink Current 50 mA

V5,V

10, V11, V13 Input Voltage at Pin 5, 10, 11, 13 7 V

I5Reset Delay Sink Current 30 mA

I10 Error Amplifier Output Sink Current 1 A

I12 Soft Start Sink Current 30 mA

Ptot Total Power Dissipation at Tcase < 120°C30W

stg Junction and Storage Temperature -40 to 150 °C

THERMAL DATA

Symbol Parameter Value Unit

Rth j-case

Rth j-amb Thermal Resistance Junction-case max

Thermal Resistance Junction-ambient max 1

35 °C/W

°C/W

L4977A

2/21

CIRCUIT OPERATION (refer to the block dia-

gram)

The L4977Ais a 7A monolithicstepdownswitching

regulator working in continuous mode realized in

the new BCD Technology. This technology allows

the integration of isolated vertical DMOS power

transistors plus mixed CMOS/Bipolar transistors.

The device can deliver 7A at an output voltage

adjustable from 5.1V to 40V, and contains diag-

nostic and control functions that make it particu-

larlysuitable for microprocessor based systems.

BLOCK DIAGRAM

The block diagram shows the DMOS power tran-

sistor and the PWM control loop. Integrated func-

tions include a referencevoltage trimmed to 5.1V

±2%, soft start, undervoltage lockout, oscillator

with feedforward control, pulse by pulse current

limit, thermal shutdown and finally the reset and

power fail circuit. The reset and power fail circuit

provides an output signal for a microprocessor in-

dicating the statusof the system.

Device turn on is around 11V with a typical 1V

hysteresis, this threshold provides a correct volt-

age for the driving stage of the DMOS gate and

the hysteresisprevents instabilities.

An external bootstrap capacitor charged to 12V

by an internal voltage reference is needed to pro-

vide correct gate drive to the power DMOS. The

driving circuit is able to source and sink peak cur-

rents of around 0.5A to the gate of the DMOS

transistor. A typical switching time of the current

in the DMOS transistor is 50ns. Due to the fast

commutation switching frequencies up to 500kHz

arepossible.

The PWM control loop consists of a sawtooth os-

cillator, error amplifier, comparator, latch and the

output stage. An error signal is produced by com-

paring the output voltage with the precise 5.1V ±

2% on chip reference. This error signal is then

compared with the sawtooth oscillator, in order to

generatea fixedfrequencypulse width modulated

drive for the output stage. A PWM latch is in-

cluded to eliminate multiple pulsing within a pe-

riod even in noisy environments. The gain and

PIN FUNCTIONS

NoName Function

1 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging

current of Cosc.

2 OSCILLATOR Cosc. External capacitor connected to grounddetermines (with Rosc) the

switching frequency.

3 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a

dividerto the input for power failfunction. It must be connected to the pin 14 an

external 30KΩresistorwhen power fail signal not required.

4 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the

supply and the output voltages are safe.

5 RESET DELAY A Cdcapacitor connected between this terminal and ground determines the

reset signaldelay time.

6 BOOTSTRAP A Cboot capacitor connected between thisterminal and the output allows to

drive properly the internal D-MOS transistor.

7 OUTPUT Regulator Output.

8 GROUND Common Ground Terminal

9 SUPPLY VOLTAGE UnregulatedInput Voltage.

10 FREQUENCY

COMPENSATION A series RC network connected between this terminal and ground determines

the regulation loop gain characteristics.

11 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected

directly to this terminal for 5.1V operation; It is connected via a divider for higher

voltages.

12 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and

ground to define the soft start time constant.

13 SYNC INPUT Multiple L4977A are synchronized by connecting pin 13inputs together or via

an external syncr. pulse.

14 Vref 5.1V Vref Device Reference Voltage.

15 Vstart Internal Start-up Circuit to Drive the Power Stage.

L4977A

3/21

Figure1: FeedforwardWaveform

Figure3: LimitingCurrent Function

Figure2: Soft Start Function

L4977A

4/21

stability of the loop can be adjusted by an exter-

nal RC network connected to the output of the er-

ror amplifier. A voltage feedforward control has

been added to the oscillator, this maintains supe-

rior line regulation over a wide input voltage

range. Closing the loop directly gives an output

voltage of 5.1V, higher voltages are obtained by

inserting a voltagedivider.

At turn on output overcurrents are prevented by

the soft start function(fig. 2). The error amplifieris

initiallyclamped by an external capacitorCss and

allowed to rise linearly under the charge of an in-

ternal constant current source.

Output overload protection is provided by a cur-

rentlimit circuit (fig. 3). Theload current is sensed

by an internal metal resistor connected to a com-

parator. When the load current exceeds a preset

threshold the output of the comparator sets a flip

flop which turns off the power DMOS. The next

clock pulse, from an internal 40kHz oscillator will

reset the flip flop and the power DMOS will again

conduct. This current protection method, ensures

a constant current output when the system is

overloaded or short circuited and limits the

switching frequency,in this condition,to 40kHz.

The Reset and Power fail circuitry (fig 4) gener-

ates an output signal when the supply voltage ex-

ceeds a threshold programmed by an external

voltage divider. The reset signal, is generated

with a delay time programmed by an external ca-

pacitor on the delay pin. Whenthe supply voltage

falls below the threshold or the output voltage

goes below 5V the reset output goes low immedi-

ately. The reset output is an open collector-drain.

Fig 4A shows the case when the supply voltage is

higher than the threshold, but the output voltage

isnot yet 5V.

Fig 4B shows the case when the output is 5.1V

but the supply voltage is not yet higher than the

fixedthreshold.

The thermal protection disables circuit operation

when the junction temperature reaches about

150°C and has an hysterysis to prevent unstable

conditions.

Figure4: Reset and Power Fail Functions.

L4977A

5/21

ELECTRICALCHARACTERISTICS (Refer to the test circuit, Tj=25°C, Vi= 35V, R4= 16KΩ,

C9= 2.2nF, fSW = 200KHz typ, unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

Viinput Voltage Range (pin 9) Vo=V

ref to 40V

Io=7A 15 50 V 5

VoOutput Votage Vi= 15V to 50V

Io= 3A; Vo=V

ref5 5.1 5.2 V 5

∆VoLine Regulation Vi= 15V to 50V

Io= 2A; Vo=V

ref12 30 mV 5

∆VoLoad Regulation Vo=V

ref

Io=3Ato5A

o=2Ato7A 10

20 25

40 mV

VdDropout VoltageBetween

Pin 9 and 7 Io=5A

o=7A 0.4

0.8 0.6

1.1 V

I7L Max. LimitingCurrent Vo=V

ref to 40V

Vi= 15 to 50V 8 9.5 11 A 5

ηEfficiency Io=3A

o=V

ref

Vo= 12V 70 75

80 %

Io=7A

o=V

ref

Vo= 12V 75 80

87 %

SVR Supply Voltage Ripple

Reject. Vi= 2VRMS; Io=3A

f = 100Hz; Vo=V

ref 56 60 dB 5

f Switching Frequency 180 200 220 KHz 5

∆f

∆ViVoltage Stability of

Swiching Frequency Vi= 15V to 45V 2 6 % 5

∆f

TjTemperature Stability of

Swiching Frequency Tj= 0 to 125°C1%5

max Maximum Operating

Switching Frequency Vo=V

ref;R

4= 10KΩ

Io= 7A; C9= 1nF 500 KHz 5

Vref SECTION(pin 14)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V14 Reference Voltage 5 5.1 5.2 V 7

∆V14 Line Regulation Vi= 15V to 50V 10 25 mV 7

∆V14 Load Regulation I14 = 0 to 1mA 20 40 mV 7

∆V14

∆TAverage Temperature

CoefficientReference

Voltage

Tj=0°C to 125°C 0.4 mV/°C7

14 short Short Circuit Current Limit V14 = 0 70 mA 7

VSTART SECTION(pin 15)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V15 Reference Voltage 11.4 12 12.6 V 7

∆V15 Line Regulation Vi= 15 to 50V 0.6 1.4 V 7

∆V15 Load Regulation I15 = 0 to 1mA 50 200 mV 7

I15 short Short Circuit Current Limit V15 =0V 80 mA 7

L4977A

6/21

ELECTRICALCHARACTERISTICS (continued)

DCCHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V9on Turn-on Threshold 10 11 12 V 7A

V9 Hyst Turn-off Hysteresys 1 V 7A

I9Q Quiescent Current V12 =0; S1=D 13 19 mA 7A

9OQ Operating SupplyCurrent V12 = 0; S1 = C; S2 = B 16 23 mA 7A

I7L Out Leak Current Vi= 55V; S3 = A; V12 =0 2 mA 7A

SOFTSTART

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

I12 Soft Start Source Current V12 = 3V; V11 = 0V 70 100 130 µA7B

12 Output Saturation Voltage I12 = 20mA; V9= 10V

I12 = 200µA; V9= 10V 1

0.7 V

V7B

ERROR AMPLIFIER

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V10H High Level Out Voltage I10 = -100µA; S1 = C

V11 = 4.7V 6V7C

10L Low Level Out Voltage I10 = +100µA; S1 = C

V11 = 5.3V; 1.2 V 7C

I10H Source Output Current V10 = 1V; S1 = E

V11 = 4.7V 100 150 µA7C

10L Sink Output Current V10 = 6V; S1 = D

V11 = 5.3V 100 150 µA7C

11 Input Bias Current RS= 10KΩ0.4 3 µA–

VDC Open Loop Gain VVCM = 4V;

RS=10Ω60 dB –

SVR Supply Voltage Rejection 15 < Vi< 50V;

RS=10Ω60 80 dB –

VOS Input Offset Voltage RS=50Ω210mV–

RAMP GENERATOR(pin 2)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V2Ramp Valley S1 = C; S2 = B 1.2 1.5 V 7A

V2Ramp Peak S1 = C Vi= 15V

S2 = B Vi= 45V 2.5

5.5 V

V7A

I2Min. Ramp Current S1 = A; I1= 100µA 270 300 µA7A

2Max. Ramp Current S1 = A; I1= 1mA 2.4 2.7 mA 7A

SYNC FUNCTION (pin 13)

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V13 Low Input Voltage Vi= 15V to 50V; V12 =0;

S1 = C; S2 = B; S4 = B –0.3 0.9 V 7A

V13 High Input voltage V12 =0;

S1 = C; S2 = B; S4 = B 3.5 5.5 V 7A

I13L Sync Input Current with

Low Input Voltage V13 =V

= 0.9V; S4 = A;

S1 = C; S2 = B 0.4 mA 7A

I13H Input Current with High

Input Voltage V13 = 3.5V; S4 = A;

S1 = C; S2 = B 1.5 mA 7A

V13 Output Amplitude 4 5 V –

tWOutput Pulse Width Vthr = 2.5V 0.3 0.5 0.8 µs–

L4977A

7/21

ELECTRICALCHARACTERISTICS (continued)

RESETAND POWERFAIL FUNCTIONS

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V11R Rising Threshold Voltage

(pin 11) Vi= 15 to 50V

V3= 5.3V Vref

–120 Vref

–100 Vref

–80 V

mV 7D

V11F Falling Threshold Voltage

(pin 11) Vi = 15 to 50V

V3= 5.3V 4.77 Vref

–200 Vref

–160 V

mV 7D

V5H Delay High Threshold

Voltage Vi= 15 to 50V

V11 =V

14 V3= 5.3V 4.95 5.1 5.25 V 7D

V5L Delay Low Threshold

Voltage Vi = 15 to 50V

V11 =V

14 V3= 5.3V 1 1.1 1.2 V 7D

–I5SO Delay Source Current V3= 5.3V; V5=3V 406080µA7D

5SI Delay Sink Current V3= 4.7V; V5=3V 10 mA 7D

4S Out Saturation Voltage I4= 15mA; S1 = B

V3= 4.7V 0.4 V 7D

I4Output Leak Current V4= 50V; S1 = A

V3= 5.3V 100 µA7D

3R Rising Threshold Voltage V11 =V

14 4.95 5.1 5.25 V 7D

V3H Hysteresys 0.4 0.5 0.6 V 7D

I3Input Bias Current 1 3 µA7D

Figure5: Test andEvaluationBoard Circuit

TYPICAL PERFORMANCES (using evaluationboard) :

n =83% (Vi=35V ; Vo=VREF ;I

o=7A;fSW =200KHz)

Vo RIPPLE =30mV (at 7A)with output filter capacitor ESR ≤60mΩ

Line regulation = 5mV (Vi=15 to 50V)

Load regulation= 15mV (Io= 2 to 7A)

For componentvalues,refer to test circuit partlist.

L4977A

8/21

PARTS LIST

R1= 30KΩC1,C

2= 3300µF 63VLEYF (ROE

R2= 10KΩC3,C

6= 2.2µF

R3= 15KΩC7= 390pF Film

R4= 16KΩC8= 22nF MKT 1817 (ERO)

R5=22Ω0,5W

R6= 4K7 C9= 2.2nF KP1830

R7=10ΩC

10 = 220nF MKT

R8= see tab. A C11 = 2.2nF MP1830

R9= OPTION **C12,C

13,C

14 = 220µF 40VLEKR

R10 = 4K7 C15 =1µF Film

R11 =10Ω

D1 = MBR 1560CT (or 16A/60V or equivalent)

L1 = 40µH core 58071 MAGNETICS

27 TURNS Ø 1,3mm (AWG 16)

COGEMA 949178

* 2 capacitors in parallel to increase input RMS current capability

** 3 capacitorsin parallel to reduce total outputESR

Table B

SUGGESTEDBOOTSTRAP CAPACITORS

Operating Frequency Bootstrap Cap.c10

f = 20KHz ≥680nF

f = 50KHz ≥470nF

f = 100KHz ≥330nF

f = 200KHz ≥220nF

f = 500KHz ≥100nF

Figure6a: P.C. Board (componentsside) and Components Layout of Figure 5 (1:1 scale).

Table A

V0R9R7

12V

15V

18V

24V

4.7kΩ

6.2kW

9.1kΩ

12kΩ

18kΩ

L4977A

9/21

Figure7: DC Test Circuits

Figure6b: P.C. Board(Back side) and ComponentsLayoutof the Circuit of Fig.5. (1:1 scale)

L4977A

10/21

Figure7A

Figure7B

L4977A

11/21

Figure7C

Figure7D

L4977A

12/21

Figure8: QuiescentDrain Current vs. Supply

Voltage (0% duty cycle - see fig. 7A).

Figure10: QuiescentDrain Current vs. Duty

Cycle

Figure12: ReferenceVoltage (pin 14) vs.

Junction Temperature(see fig.7)

Figure 9: QuiescentDrain Current vs. Junction

Temperature(0% duty cycle).

Figure 11: ReferenceVoltage(pin14) vs. Vi(see

fig. 7)

Figure 13: ReferenceVoltage(pin15) vs. Vi(see

fig. 7)

L4977A

13/21

Figure14: ReferenceVoltage (pin 15) vs.

Junction Temperature(see fig.7)

Figure16: SwitchingFrequencyvs. Input

Voltage (see fig. 5)

Figure18: SwitchingFrequencyvs. R4 (see fig. 5)

Figure 15: Reference Voltage 5.1V (pin 14)

SupplyVoltageRipple Rejection vs.

Frequency

Figure 17: SwitchingFrequency vs. Junction

Temperature(see fig 5)

Figure 19: Max.Duty Cyclevs. Frequency

L4977A

14/21

Figure20: SupplyVoltage Ripple Rejectionvs.

Frequency (see fig. 5)

Figure22: Load Transient Response(see fig. 5)

Figure24: DropoutVoltage Between Pin 9 and

Pin 7 vs. Junction Temperature

Figure 21: Line TransientResponse(see fig. 5)

Figure 23: DropoutVoltageBetween Pin 9 and

Pin 7 vs. Current at Pin 7

Figure 25: PowerDissipation (device only) vs.

InputVoltage

L4977A

15/21

Figure26: PowerDissipation(device only) vs.

OutputVoltage

Figure28: Efficiency vs. OutputCurrent

Figure30: Efficiency vs. OutputVoltage

Figure 27: Heatsink Used to Derive the Device’s

PowerDissipation

Rth -Heatsink = Tcase−Tamb

Figure 29: Efficiency vs. Output Voltage

Figure 31: Open Loop Frequency andPhase

Responseof ErrorAmplifier (see

fig.7C)

L4977A

16/21

Figure32: PowerDissipationDerating Curve

Figure33: A5.1V/12VMultiple Supply. Note the Synchronizationbetween the L4977A and the L4974A

L4977A

17/21

Figure34: 5.1V/ 7A Low CostApplication

Figure35: 7A Switching Regulator, Adjustable from 0V to 25V.

L4977A

18/21

Figure36: L4977A’sSync. Example

L4977A

19/21

MULTIWATT15 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 5 0.197

B 2.65 0.104

C 1.6 0.063

D 1 0.039

E 0.49 0.55 0.019 0.022

F 0.66 0.75 0.026 0.030

G 1.14 1.27 1.4 0.045 0.050 0.055

G1 17.57 17.78 17.91 0.692 0.700 0.705

H1 19.6 0.772

H2 20.2 0.795

L 22.1 22.6 0.870 0.890

L1 22 22.5 0.866 0.886

L2 17.65 18.1 0.695 0.713

L3 17.25 17.5 17.75 0.679 0.689 0.699

L4 10.3 10.7 10.9 0.406 0.421 0.429

L7 2.65 2.9 0.104 0.114

M 4.2 4.3 4.6 0.165 0.169 0.181

M1 4.5 5.08 5.3 0.177 0.200 0.209

S 1.9 2.6 0.075 0.102

S1 1.9 2.6 0.075 0.102

Dia1 3.65 3.85 0.144 0.152

L4977A

20/21

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom itsuse. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-

tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-

press written approval of SGS-THOMSON Microelectronics.

1994 SGS-THOMSON Microelectronics - All RightsReserved

MULTIWATTis a Registered Trademark of SGS-THOMSON Microlectronics

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil- France -Germany - Hong Kong - Italy - Japan - Korea -Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

L4977A

21/21

SG2525A/2527A

SG3525A/3527A

December 1995

REGULATING PULSE WIDTH MODULATORS

.8 TO 35 V OPERATION

.5.1 V REFERENCE TRIMMED TO ±1%

.100Hz TO 500 KHz OSCILLATORRANGE

.SEPARATEOSCILLATORSYNC TERMINAL

.ADJUSTABLEDEADTIME CONTROL

.INTERNAL SOFT-START

.PULSE-BY-PULSESHUTDOWN

.INPUT UNDERVOLTAGE LOCKOUT WITH

HYSTERESIS

.LATCHING PWM TO PREVENT MULTIPLE

PULSES

.DUAL SOURCE/SINK OUTPUT DRIVERS

DESCRIPTION

The SG3525A/3527Aseries ofpulsewidthmodula-

torintegratedcircuitsaredesignedtoofferimproved

performanceandloweredexternalpartscountwhen

usedin designing all types of switching power sup-

plies.The on-chip + 5.1 V referenceis trimmed to±

1 % and the input common-mode rangeof theerror

amplifierincludes the referencevoltage eliminating

external resistors. A sync input to the oscillator al-

lowsmultiple unitstobe slavedor asingle unittobe

synchronizedto an externalsystem clock. A single

resistorbetweentheCTandthedischargeterminals

provide a wide range of dead time ad- justment.

Thesedevicesalsofeaturebuilt-insoft-startcircuitry

with only an external timing capacitor required. A

shutdownterminalcontrolsboth thesoft-startcircu-

ity and the output stages, providing instantaneous

turn off through the PWM latch with pulsed shut-

down, aswell as soft-startrecycle with longer shut-

down commands. Thesefunctionsare also control-

led byanundervoltagelockoutwhichkeeps theout-

puts off and the soft-start capacitor discharged for

sub-normalinputvoltages. This lockoutcircuitry in-

cludesapproximately500mVofhysteresisforjitter-

free operation.Another feature of these PWM cir-

cuits is a latch following the comparator. Once a

PWM pulses has been terminated for any reason,

the outputswill remain offfor the durationof the pe-

riod. The latch is reset with each clock pulse. The

output stages are totem-pole designs capable of

sourcing or sinking in excess of 200 mA. The

SG3525AoutputstagefeaturesNOR logic, giving a

LOWoutputforanOFFstate.TheSG3527Autilizes

OR logicwhich results in aHIGH output level when

OFF.

DIP16 16(Narrow)

Type Plastic DIP SO16

SG2525A SG2525AN SG2525AP

SG2527A SG2527AN SG2527AP

SG3525A SG3525AN SG3525AP

SG3527A SG3527AN SG3527AP

PIN CONNECTIONS AND ORDERING NUMBERS (top view)

1/12

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

ViSupply Voltage 40 V

VCCollector Supply Voltage 40 V

IOSC Oscillator Charging Current 5 mA

IoOutput Current, Source or Sink 500 mA

IRReference Output Current 50 mA

ITCurrent through CTTerminal

Logic Inputs

Analog Inputs

– 0.3 to + 5.5

– 0.3 to Vi

Ptot Total Power Dissipation at Tamb =70°C 1000 mW

TjJunction Temperature Range – 55 to 150 °C

Tstg Storage Temperature Range – 65 to 150 °C

Top Operating Ambient Temperature : SG2525A/27A

SG3525A/27A –– 25 to 85

0to70 °C

°C

THERMAL DATA

Symbol Parameter SO16 DIP16 Unit

Rth j-pins

Rth j-amb

Rth j-alumina

Thermal Resistance Junction-pins Max

Thermal Resistance Junction-ambient Max

Thermal Resistance Junction-alumina (*) Max 50

80 °C/W

°C/W

*Thermal resistancejunction-alumina withthedevice solderedon themiddleofanalumina supportingsubstratemeasuring 15×20mm ; 0.65mm

thickness with infinite heatsink.

BLOCK DIAGRAM

SG2525A/27A-SG3525A/27A

2/12

ELECTRICAL CHARACTERISTICS

(V# i = 20 V, and over operating temperature, unless otherwise specified)

Symbol Parameter Test Conditions SG2525A

SG2527A SG3525A

SG3527A Unit

Min. Typ. Max. Min. Typ. Max.

REFERENCE SECTION

VREF Output Voltage Tj=25°C 5.05 5.1 5.15 5 5.1 5.2 V

∆VREF Line Regulation Vi= 8 to 35 V 10 20 10 20 mV

∆VREF Load Regulation IL= 0 to 20 mA 20 50 20 50 mV

∆VREF/∆T* Temp. Stability Over Operating Range 20 50 20 50 mV

* Total Output Variation Line, Load and

Temperature 5 5.2 4.95 5.25 V

Short Circuit Current VREF =0T

j=25°C 80 100 80 100 mA

* Output Noise Voltage 10 Hz ≤f≤10 kHz,

Tj=25°C40 200 40 200 µVrms

∆VREF* Long Term Stability Tj= 125 °C, 1000 hrs 20 50 20 50 mV

OSCILLATOR SECTION * *

*, •Initial Accuracy Tj=25°C±2±6±2±6%

*, •Voltage Stability Vi= 8 to 35 V ±0.3 ±1±1±2%

∆f/∆T* Temperature Stability Over Operating Range ±3±6±3±6%

MIN Minimum Frequency RT= 200 KΩCT= 0.1 µF 120 120 Hz

fMAX Maximum Frequency RT=2KΩC

T= 470 pF 400 400 KHz

Current Mirror IRT = 2 mA 1.7 2 2.2 1.7 2 2.2 mA

*, •Clock Amplitude 3 3.5 3 3.5 V

*, •Clock Width Tj=25°C 0.3 0.5 1 0.3 0.5 1 µs

Sync Threshold 1.2 2 2.8 1.2 2 2.8 V

Sync Input Current Sync Voltage = 3.5 V 1 2.5 1 2.5 mA

ERROR AMPLIFIER SECTION (VCM = 5.1 V)

VOS Input Offset Voltage 0.5 5 2 10 mV

IbInput Bias Current 1 10 1 10 µA

Ios Input Offset Current 1 1 µA

DC Open Loop Gain RL≥10 MΩ60 75 60 75 dB

* Gain Bandwidth

Product Gv= 0 dB Tj=25°C1 2 1 2 MHz

*, DC Transconduct. 30 KΩ≤RL≤1MΩ

j=25°C1.1 1.5 1.1 1.5 ms

Output Low Level 0.2 0.5 0.2 0.5 V

Output High Level 3.8 5.6 3.8 5.6 V

CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB

PSR Supply Voltage

Rejection Vi= 8 to 35 V 50 60 50 60 dB

SG2525A/27A-SG3525A/27A

3/12

ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Conditions SG2525A

SG2527A SG3525A

SG3527A Unit

Min. Typ. Max. Min. Typ. Max.

PWM COMPARATOR

Minimum Duty-cycle 0 0 %

Maximum Duty-cycle 45 49 45 49 %

•Input Threshold Zero Duty-cycle 0.7 0.9 0.7 0.9 V

Maximum Duty-cycle 3.3 3.6 3.3 3.6 V

* Input Bias Current 0.05 1 0.05 1 µA

SHUTDOWN SECTION

Soft Start Current VSD = 0 V, VSS =0V 255080255080 µA

Soft Start Low Level VSD = 2.5 V 0.4 0.7 0.4 0.7 V

Shutdown Threshold To outputs, VSS = 5.1 V

Tj=25°C0.6 0.8 1 0.6 0.8 1 V

Shutdown Input Current VSD = 2.5 V 0.4 1 0.4 1 mA

* Shutdown Delay VSD = 2.5 V Tj=25°C 0.2 0.5 0.2 0.5 µs

OUTPUT DRIVERS (each output) (VC=20V)

Output Low Level Isink = 20 mA 0.2 0.4 0.2 0.4 V

Isink = 100 mA 1 2 1 2 V

Output High Level Isource =20mA 18 19 18 19 V

source = 100 mA 17 18 17 18 V

Under-Voltage Lockout Vcomp and Vss = High 6 7 8 6 7 8 V

ICCollector Leakage VC= 35 V 200 200 µA

tr* Rise Time CL= 1 nF, Tj=25°C 100 600 100 600 ns

tf* Fall Time CL= 1 nF, Tj=25°C 50 300 50 300 ns

TOTAL STANDBY CURRENT

IsSupply Current Vi= 35 V 14 20 14 20 mA

*These parameters, although guaranteed over the recommended operating conditions, arenot 100% tested in production.

•Testedat fosc =40 KHz (RT=3.6KΩ,C

T=0.1µF, RD=0Ω). Approximate oscillator frequency is defined by :

f= C

T(0.7 RT+3R

)

.DC transconductance (gM) relatestoDC open-loop voltage gain (Gv) according to thefollowingequation :Gv=g

MRLwhereRLis the resistance

from pin 9 to ground. The minimumgMspecificationis used to calculate minimum Gvwhen the erroramplifier output isloaded.

SG2525A/27A-SG3525A/27A

4/12

TEST CIRCUIT

SG2525A/27A-SG3525A/27A

5/12

Figure 1 : Oscillator Charge Time vs. RT

and CT.Figure 2 : Oscillator Discharge Time vs. RD

and CT.

RECOMMENDED OPERATING CONDITIONS (•)

Parameter Value

Input Voltage (Vi)8to35V

Collector Supply Voltage (VC) 4.5 to 35 V

Sink/Source Load Current (steady state) 0 to 100 mA

Sink/Source Load Current (peak) 0 to 400 mA

Reference Load Current 0to20mA

Oscillator Frequency Range 100 Hz to 400 KHz

Oscillator Timing Resistor 2 KΩto 150 KΩ

Oscillator Timing Capacitor 0.001 µF to 0.1 µF

Dead Time Resistor Range 0 to 500 Ω

•(⋅) Range over which the device is functional and parameter limitsare guaranteed.

Figure3 : SG1525A OutputSaturation

Characteristics. Figure 4 :Error AmplifierVoltageGainand

Phasevs. Frequency.

SG2525A/27A-SG3525A/27A

6/12

SHUTDOWN OPTIONS(see Block Diagram)

Since both the compensation and soft-start termi-

nals (Pins 9 and 8) have current source pull-ups,

either can readily accept a pull-down signal which

onlyhastosinkamaximumof 100

µA

toturnoffthe

outputs.Thisis subject totheaddedrequirementof

dischargingwhatever externalcapacitancemay be

attachedto thesepins.

Analternateapproachistheuseoftheshutdowncir-

cuitry of Pin 10 which has been improved to en-

hance the available shutdown options. Activating

this circuit by applying a positive signal on Pin 10

performstwo functions: the PWM latchis immedi-

ately set providing the fastestturn-off signalto the

outputs; and a 150 µA current sink begins to dis-

chargethe external soft-startcapacitor. If the shut-

down command is short, the PWM signal is termi-

nated without significant discharge of the soft-start

capacitor,thus,allowing, for example,a convenient

implementation of pulse-by-pulse current limiting.

Holding Pin 10 high for a longerduration,however,

will ultimately dischargethisexternalcapacitor,re-

cycling slow turn-on uponrelease.

Pin 10 should not be left floating as noise pickup

couldconceivablyinterruptnormal operation.

Figure 5 : SG1525AError Amplifier.

PRINCIPLES OF OPERATION

SG2525A/27A-SG3525A/27A

7/12

Figure7:SG1525A Output Circuit (1/2 circuit shown).

Figure6 : SG1525AOscillator Schematic.

SG2525A/27A-SG3525A/27A

8/12

Figure 10. Figure 11.

For single-ended supplies, the driver outputs are

grounded.The VCterminalis switchedto groundby

thetotem-polesourcetransistorson alternateoscil-

latorcycles.

In conventional push-pull bipolar designs, forward

base drive is controlled by R1-R

. Rapid turn-off

times for the power devices are achieved with

speed-upcapacitors C1and C2.

Thelowsourceimpedanceoftheoutputdriverspro-

vides rapid charging of Power Mos input capaci-

tancewhile minimizing externalcomponents.

Low power transformers can be driven directly by

the SG1525A.Automatic reset occurs during dead

time, when both ends of the primary winding are

switched to ground.

Figure8. Figure 9.

SG2525A/27A-SG3525A/27A

9/12

DIP16 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 0.050

SG2525A/27A-SG3525A/27A

10/12

SO16 NARROW PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.75 0.069

a1 0.1 0.25 0.004 0.009

a2 1.6 0.063

b 0.35 0.46 0.014 0.018

b1 0.19 0.25 0.007 0.010

C 0.5 0.020

c1 45°(typ.)

D 9.8 10 0.386 0.394

E 5.8 6.2 0.228 0.244

e 1.27 0.050

e3 8.89 0.350

F 3.8 4.0 0.150 0.157

L 0.4 1.27 0.150 0.050

M 0.62 0.024

S8°(max.)

SG2525A/27A-SG3525A/27A

11/12

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for

the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its

use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifica-

tions mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information pre-

viously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland- Taiwan - Thaliand - United Kingdom - U.S.A.

SG2525A/27A-SG3525A/27A

12/12

UC2842/3/4/5

UC3842/3/4/5

May 1995

CURRENTMODE PWM CONTROLLER

.OPTIMIZED FOR OFF-LINE AND DC TO DC

CONVERTERS

.LOWSTART-UP CURRENT (< 1 mA)

.AUTOMATIC FEED FORWARD COMPENSA-

TION

.PULSE-BY-PULSECURRENT LIMITING

.ENHANCED LOAD RESPONSE CHARAC-

TERISTICS

.UNDER-VOLTAGELOCKOUTWITH HYSTER-

ESIS

.DOUBLE PULSE SUPPRESSION

.HIGHCURRENT TOTEM POLEOUTPUT

.INTERNALLY TRIMMED BANDGAP REFER-

ENCE

.500 KHz OPERATION

.LOWROERROR AMP

DESCRIPTION

TheUC3842/3/4/5familyofcontrolICsprovidesthe

necessaryfeatures to implement off-line or DC to

DC fixed frequencycurrent mode controlschemes

with aminimalexternalpartscount.Internallyimple-

mentedcircuitsincludeundervoltagelockoutfeatur-

ingstart-up current less than1 mA, a precision ref-

erencetrimmed for accuracyat theerror ampinput,

logic to insure latchedoperation, aPWM compara-

torwhichalsoprovidescurrentlimit control,andato-

tem pole output stage designed to source or sink

high peak current. The output stage, suitable for

driving N-ChannelMOSFETs, islowin the off-state.

Differencesbetweenmembersof thisfamilyare the

under-voltage lockout thresholds and maximum

duty cycle ranges.The UC3842 and UC3844 have

UVLO thresholdsof 16V (on) and 10V (off), ideally

suited off-line applications The corresponding

thresholdsfor the UC3843 and UC3845 are 8.5 V

and 7.9 V. The UC3842and UC3843 can operate

to duty cycles approaching 100%. A range of the

zero to < 50 % is obtained by the UC3844 and

UC3845bytheadditionof an internaltoggleflip flop

which blankstheoutput off every otherclock cycle.

BLOCK DIAGRAM (toggle flip flop used only in U3844 and UC3845)

Minidip SO14

1/11

*Allvoltages are with respect to pin 5, all currents are positive intothe specified terminal.

PIN CONNECTIONS (top views)

SO14 Minidip

ORDERING NUMBERS

Type Minidip SO14

UC2842

UC3843

UC2844

UC2845

UC2842N

UC2843N

UC2844N

UC2845N

UC2842D

UC2843D

UC2844D

UC2845D

UC3842

UC3843

UC3844

UC3845

UC3842N

UC3843N

UC3844N

UC3845N

UC3842D

UC3843D

UC3844D

UC3845D

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

ViSupply Voltage (low impedance source) 30 V

ViSupply Voltage (Ii < 30mA) Self Limiting

IOOutput Current ±1A

Output Energy (capacitive load) 5 µJ

Analog Inputs (pins 2, 3) –0.3 to 6.3 V

Error Amplifier Output Sink Current 10 mA

Ptot Power Dissipation at Tamb ≤50 °C (minidip, DIP-14) 1 W

Ptot Power Dissipation at Tamb ≤25 °C (SO14) 725 mW

Tstg Storage Temperature Range – 65 to 150 °C

TLLead Temperature (soldering 10s) 300 °C

THERMAL DATA

Symbol Description Minidip SO14 Unit

Rthj-amb ThermalResistance Junction-ambient. max. 100 165 °C

UC2842/3/4/5-UC3842/3/4/5

2/11

ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specificationsapply for -25 < Tamb <

85°C forUC2824X;0 < Tamb <70°C for UC384X;Vi= 15V (note 5); RT=10K;C

T=3.3nF)

Symbol Parameter Test Conditions UC284X UC384X Unit

Min. Typ. Max. Min. Typ. Max.

REFERENCE SECTION

VREF Output Voltage Tj=25°CI

o= 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V

∆VREF Line Regulation 12V ≤Vi≤25V 6 20 6 20 mV

∆VREF Load Regulation 1 ≤Io≤20mA 6 25 6 25 mV

∆VREF/∆T Temperature Stability (Note 2) 0.2 0.4 0.2 0.4 mV/°C

Total Output Variant Line, Load, Temperature (2) 4.9 5.1 4.82 5.18 V

eNOutput Noise Voltage 10Hz ≤f≤10KHz Tj=25°C

(2) 50 50 µV

Long Term Stability Tamb = 125°C, 1000Hrs (2) 5 25 5 25 mV

ISC Output Short Circuit -30 -100 -180 -30 -100 -180 mA

OSCILLATOR SECTION

fsInitial Accuracy Tj=25°C (6) 47 52 57 47 52 57 KHz

Voltage Stability 12 ≤Vi≤25V 0.2 1 0.2 1 %

Temperature Stability TMIN ≤Tamb ≤TMAX (2) 5 5 %

V4Amplitude VPIN4 Peak to Peak 1.7 1.7 V

ERROR AMP SECTION

V2Input Voltage VPIN1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V

IbInput Bias Current -0.3 -1 -0.3 -2 µA

AVOL 2≤Vo≤4V 65 90 65 90 dB

B Unity Gain Bandwidth (2) 0.7 1 0.7 1 MHz

SVR Supply Voltage Rejection 12V ≤Vi≤25V 60 70 60 70 dB

IoOutput Sink Current VPIN2 = 2.7V VPIN1 = 1.1V 2 6 2 6 V

IoOutput Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -0.8 -0.5 -0.8 mA

VOUT High VPIN2 = 2.3V;

RL= 15KΩto Ground 56 56 V

OUT Low VPIN2 = 2.7V;

RL= 15KΩto Pin 8 0.7 1.1 0.7 1.1 V

CURRENT SENSE SECTION

GVGain (3 & 4) 2.85 3 3.15 2.8 3 3.2 V/V

V3Maximum Input Signal VPIN1 = 5V (3) 0.9 1 1.1 0.9 1 1.1 V

SVR Supply Voltage Rejection 12 ≤Vi≤25V (3) 70 70 dB

IbInput Bias Current -2 -10 -2 -10 µA

Delay to Output 150 300 150 300 ns

OUTPUT SECTION

IOL Output Low Level ISINK = 20mA 0.1 0.4 0.1 0.4 V

ISINK = 200mA 1.5 2.2 1.5 2.2 V

IOH Output High Level ISOURCE = 20mA 13 13.5 13 13.5 V

ISOURCE = 200mA 12 13.5 12 13.5 V

trRise Time Tj=25°CC

= 1nF (2) 50 150 50 150 ns

tfFall Time Tj=25°CC

= 1nF (2) 50 150 50 150 ns

UC2842/3/4/5-UC3842/3/4/5

3/11

Notes : 2. These parameters, although guaranteed, are not 100% tested in production.

3. Parameter measured at trip point of latch withVPIN2 =0.

4. Gaindefined as :

∆VPIN1

A= ;0≤V

PIN3 ≤0.8V

∆VPIN3

5. Adjust Viabove the start threshold before setting at 15 V.

6. Outputfrequency equals oscillator frequency for theUC3842 and UC3843.

Outputfrequency is one half oscillator frequency for the UC3844 andUC3845.

ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Conditions UC284X UC384X Unit

Min. Typ. Max. Min. Typ. Max.

UNDER-VOLTAGE LOCKOUT SECTION

Start Threshold X842/4 15 16 17 14.5 16 17.5 V

X843/5 7.8 8.4 9.0 7.8 8.4 9 V

Min Operating Voltage

After Turn-on X842/4 9 10 11 8.5 10 11.5 V

X843/5 7.0 7.6 8.2 7.0 7.6 8.2 V

PWM SECTION

Maximum Duty Cycle X842/3 93 97 100 93 97 100 %

X844/5 46 48 50 47 48 50 %

Minimum Duty Cycle 0 0 %

TOTAL STANDBY CURRENT

Ist Start-up Current 0.5 1 0.5 1 mA

IiOperating Supply Current VPIN2 =V

PIN3 =0V 1120 1120mA

iz Zener Voltage Ii= 25mA 34 34 V

UC2842/3/4/5-UC3842/3/4/5

4/11

Figure 1 : ErrorAmpConfiguration.

Error amp can source or

sink up to 0.5mA

Figure 2 : UnderVoltageLockout.

During Under-Voltage Lockout,the outputdriver is

biased to sink minor amounts of current. Pin 6

shouldbe shuntedtoground with a bleederresistor

to preventactivatingthe powerswitch withextrane-

ous leakage currents.

Figure 3 : Current Sense Circuit .

Peak current (is) is determinedby the formula

1.0 V

IS max ≈RS

A small RC filter may be required to suppress switch transients.

UC2842/3/4/5-UC3842/3/4/5

5/11

Figure 4. Figure 5 : Deadtimevs. CT(RT>5KΩ).

1.72

for RT>5KΩf= R

Figure 7 : OutputSaturationCharacteristics.Figure 6 : Timing Resistance vs. Frequency.

Figure 8 : Error Amplifier Open-loopFrequency

Response.

UC2842/3/4/5-UC3842/3/4/5

6/11

Figure 9 : OpenLoop TestCircuit.

Highpeakcurrentsassociatedwithcapacitiveloads

necessitate careful grounding techniques. Timing

and bypass capacitors should be connectedclose

to pin5 ina single pointground.The transistor and

5KΩpotentiometerareusedtosampletheoscillator

waveformand apply an adjustableramp to pin 3.

Figure 10 : ShutdownTechniques.

Shutdownof the UC2842 canbe accomplishedby

two methods;eitherraise pin 3above1Vorpullpin

1 belowa voltage two diode drops above ground.

Eithermethod cause the output of the PWM com-

parator to be high (refer to block diagram). The

PWM latchis reset dominantso that the output will

remain low until the next clock cycle afterthe shut-

downconditionat pins1and/or3is removed.Inone

example, an externally latched shutdown may be

accomplishedbyaddinganSCRwhichwillbe reset

bycyclingVibelowthelowerUVLOthreshold.Atthis

pointthereferenceturnsoff,allowingtheSCRtore-

set.

UC2842/3/4/5-UC3842/3/4/5

7/11

Figure 11 : Off-line Flyback Regulator.

Power Supply Specifications

1. InputVoltage : 95 VACto 130 VAC

(50 Hz/60 Hz)

2. LineIsolation : 3750 V

3. Switching Frequency: 40 KHz

4. Efficiency @Full Load : 70 %

5. OutputVoltage:

A. + 5 V, ±5 % : 1 A to 4A load

Ripple voltage: 50 mV P-P Max.

B. + 12 V, ±3 % : 0.1 A to 0.3 A load

Ripplevoltage: 100 mV P-P Max.

C. – 12 V, ±3 % : 0.1A to 0.3 A load

Ripplevoltage: 100 mV P-P Max.

Figure 12 : SlopeCompensation.

A fraction of the oscillator ramp can be resistively

summed with the current sense signal to provide

slope compensation for converters requiring duty

cycles over 50 %.

Note that capacitor,C, forms a filter with R2to su-

press theleading edge switch spikes.

UC2842/3/4/5-UC3842/3/4/5

8/11

SO14 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.75 0.069

a1 0.1 0.25 0.004 0.009

a2 1.6 0.063

b 0.35 0.46 0.014 0.018

b1 0.19 0.25 0.007 0.010

C 0.5 0.020

c1 45 (typ.)

D 8.55 8.75 0.336 0.344

E 5.8 6.2 0.228 0.244

e 1.27 0.050

e3 7.62 0.300

F 3.8 4.0 0.15 0.157

L 0.4 1.27 0.016 0.050

M 0.68 0.027

S 8 (max.)

UC2842/3/4/5-UC3842/3/4/5

9/11

DIP14 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e 2.54 0.100

e3 7.62 0.300

e4 7.62 0.300

F 6.6 0.260

I 5.08 0.200

L 3.18 3.81 0.125 0.150

UC2842/3/4/5-UC3842/3/4/5

10/11

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no

responsibility for the consequences of use of such information nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by implication or otherwise under any patent or

patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change

without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Micro-

electronics products are not authorized for use as critical components in life support devices or systems without

express written approval of SGS-THOMSON Microelectronics.

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UC2842/3/4/5-UC3842/3/4/5

11/11