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General Description
The MAX9320B low-skew, 1-to-2 differential driver is
designed for clock and data distribution. The input is
reproduced at two differential outputs. The differential
input can be adapted to accept single-ended inputs by
applying an external reference voltage.
The MAX9320B features ultra-low propagation delay
(208ps), part-to-part skew (20ps), and output-to-output
skew (6ps) with 30mA maximum supply current, mak-
ing this device ideal for clock distribution. For interfac-
ing to differential PECL and LVPECL signals, this
device operates over a +3.0V to +5.5V supply range,
allowing high-performance clock or data distribution in
systems with a nominal 3.3V or 5V supply. For differen-
tial ECL and LVECL operation, this device operates
from a -3.0V to -5.5V supply.
The MAX9320B is offered in industry-standard 8-pin
TSSOP and SO packages.
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Protection Switching
Features
♦Improved Second Source of the MC10EP11D
♦+3.0V to +5.5V Differential PECL/LVPECL
Operation
♦-3.0V to -5.5V ECL/LVECL Operation
♦Low 22mA Supply Current
♦20ps Part-to-Part Skew
♦6ps Output-to-Output Skew
♦208ps Propagation Delay
♦Minimum 300mV Output at 3GHz
♦Outputs Low for Open Input
♦ESD Protection >2kV (Human Body Model)
MAX9320B
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
________________________________________________________________ Maxim Integrated Products 1
60kΩ
100kΩ
80kΩ
50kΩ
6
TSSOP/SO
Q0
Q1
1
2
3
4
8
D
5VEE
7D
VCC
MAX9320B
Q1
Q0
Pin Configuration
19-2383; Rev 1; 11/03
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX9320BESA -40°C to +85°C 8 SO
MAX9320BEUA -40°C to +85°C 8 TSSOP
Figure 1. Differential Transition Time and Propagation Delay
Timing Diagram
0V (DIFFERENTIAL)
80%
20%
80%
20%
0V (DIFFERENTIAL)
VOH - VOL
VIHD - VILD
VIHD
VILD
VOH
VOL
Q_
Q
tPLHD tPHLD
tRtF
D
D
(Q_) - (Q_)
MAX9320B
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1.0V, VILD
= VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to VEE .............................................................................+6V
D or D....................................................VEE - 0.3V to VCC + 0.3V
D or Dwith the Other Floating............. VCC - 5.0V to VCC + 0.3V
D to D.................................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
Continuous Output Power Dissipation (TA= +70°C)
8-Pin TSSOP
(derate 4.5mW/°C above +70°C).................................362mW
8-Pin SO
(derate 5.9mW/°C above +70°C).................................471mW
Junction-to-Ambient Thermal Resistance in Still Air
8-Pin TSSOP ............................................................+221°C/W
8-Pin SO...................................................................+170°C/W
Junction-to-Ambient Thermal Resistance with 500
LFPM Airflow
8-Pin TSSOP ............................................................+155°C/W
8-Pin SO.....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin TSSOP ..............................................................+39°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (D, D, Q_, Q_) .................................>2kV
Soldering Temperature (10s) ...........................................+300°C
-40°C +25°C +85°C
PARAMETER SYM BOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DIFFERENTIAL INPUT (D, D)
High Voltage of
Differential
Input
VIHD VEE
+ 1.2 VCC VEE
+ 1.2 VCC VEE
+ 1.2 VCC V
Low Voltage of
Differential
Input
VILD VEE VCC
- 0.1 VEE VCC
- 0.1 VEE VCC
- 0.1 V
Differential
Input Voltage
VIHD -
VILD 0.1 3.0 0.1 3.0 0.1 3.0 V
Input High
Current IIH 150 150 150 µA
VCC - VEE ≤ 3.8V -100 +100 -100 +100 -100 +100
D Input Low
Current IILD VCC - VEE ≥ 3.8V -140 +140 -140 +140 -140 +140 µA
VCC - VEE ≤ 3.8V -150 +150 -150 +150 -150 +150
D Input Low
Current IILDVCC - VEE ≥ 3.8V -175 +175 -175 +175 -175 +175 µA
DIFFERENTIAL OUTPUTS (Q_, Q__)
Single-Ended
Output High
Voltage
VOH Figure 1 VCC
- 1.135
VCC
- 0.885
VCC
- 1.07
VCC
- 0.82
VCC
- 1.01
VCC
- 0.76 V
MAX9320B
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1.0V, VILD
= VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V, input frequency ≤1.5GHz, input transition time = 125ps (20% to
80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3.0V. Typical values are at VCC - VEE = 5.0V, VIHD
= VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5)
-40°C +25°C +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Single-Ended
Output Low
Voltage
VOL Figure 1 VCC
- 1.935
VCC
- 1.685
VCC
- 1.87
VCC
- 1.62
VCC
- 1.81
VCC
- 1.56 V
Differential
Output Voltage
VOH
- VOL Figure 1 550 550 550 mV
POWER SUPPLY
Supply Current IEE (Note 4) 20 28 22 28 23 30 mA
-40°C +25°C +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Differential
Input-to-
Output Delay
tPLHD,
tPHLD Figure 1 145 220 265 155 208 265 160 203 270 ps
Output-to-
Output Skew tSKOO (Note 6) 6 30 6 30 6 30 ps
Part-to-Part
Skew tSKPP (Note 7) 20 120 20 110 20 110 ps
fIN = 1.5GHz, clock
pattern (Note 8) 1.7 2.8 1.7 2.8 1.7 2.8
Added
Random Jitter tRJ fIN = 3.0GHz, clock
pattern (Note 8) 0.6 1.5 0.6 1.5 0.6 1.5
ps
(RMS)
Added
Deterministic
Jitter
tDJ
3.0Gbps
223 - 1 PRBS pattern
(Note 8)
57 80 57 80 57 80 ps
(P-P)
Typical Operating Characteristics
(VCC = 5V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with
50Ωto VCC - 2V, TA= +25°C, unless otherwise noted.)
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters production tested at TA= +25°C. Guaranteed by design and characterization over the full operating temper-
ature range.
Note 4: All pins open except VCC and VEE.
Note 5: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 8: Device jitter added to the input signal.
MAX9320B
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
4 _______________________________________________________________________________________
-40°C +25°C +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VOH - VOL ≥ 300mV,
clock pattern,
Figure 1
3.0 3.0 3.0
Switching
Frequency fMAX
VOH - VOL ≥ 550mV,
clock pattern,
Figure 1
2.0 2.0 2.0
GHz
Output
Rise/Fall Time
(20% to 80%)
tR, tFFigure 1 50 95 120 50 98 120 50 105 120 ps
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V, input frequency ≤1.5GHz, input transition time = 125ps (20% to
80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3.0V. Typical values are at VCC - VEE = 5.0V, VIHD
= VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5)
TRANSITION TIME vs. TEMPERATURE
MAX9320B toc03
TEMPERATURE (°C)
TRANSITION TIME (ps)
603510-15
85
90
95
100
105
110
80
-40 85
tR
tF
OUTPUT AMPLITUDE, VOH - VOL
vs. FREQUENCY
MAX9320B toc02
FREQUENCY (MHz)
OUTPUT AMPLITUDE (V)
30002500500 1000 1500 2000
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
03500
SUPPLY CURRENT, IEE
vs. TEMPERATURE
MAX9320B toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
16
17
18
19
20
21
22
23
24
25
15
-40 85
MAX9320B
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VCC = 5V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with
50Ωto VCC - 2V, TA= +25°C, unless otherwise noted.)
Pin Description
PIN NAME FUNCTION
1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
2Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
3 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
4Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
5V
EE Negative Supply Voltage
6DInverting Differential Input. 50kΩ pullup to VCC and 100kΩ pulldown to VEE.
7 D Noninverting Differential Input. 80kΩ pullup to VCC and 60kΩ pulldown to VEE.
8V
CC Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
PROPAGATION DELAY vs. TEMPERATURE
MAX9320B toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
6035-15 10
170
180
190
200
210
220
230
240
160
-40 85
tPLHD
tPHLD
PROPAGATION DELAY vs. HIGH VOLTAGE
OF DIFFERENTIAL INPUT, VIHD
MAX9320B toc04
VIHD (V)
PROPAGATION DELAY (ps)
5.24.84.44.03.63.22.82.42.01.6
195
200
205
210
215
220
190
1.2 5.6
tPLHD
tPHLD
VIHD - VILD = 0.5V
MAX9320B
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
6 _______________________________________________________________________________________
Detailed Description
The MAX9320B low-skew, 1-to-2 differential driver is
designed for clock and data distribution. For interfacing
to differential PECL and LVPECL signals, this device
operates over a +3.0V to +5.5V supply range, allowing
high-performance clock and data distribution in sys-
tems with a nominal 3.3V or 5V supply. For differential
ECL and LVECL operation, this device operates from a
-3.0V to -5.5V supply.
Inputs
The maximum magnitude of the differential input from D
to Dis 3.0V. This limit also applies to the difference
between any reference voltage input and a single-
ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting input, D, is biased with a 50kΩpullup to
VCC and a 100kΩpulldown to VEE. The noninverting
input, D, is biased with an 80kΩpullup to VCC and a
60kΩpulldown to VEE.
Specifications for the high and low voltages of the dif-
ferential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously (VILD cannot
be higher than VIHD).
Outputs
Output levels are referenced to VCC and are consid-
ered PECL/LVPECL or ECL/LVECL, depending on the
level of the VCC supply. With VCC connected to a posi-
tive supply and VEE connected to GND, the outputs are
PECL/LVPECL. The outputs are ECL/LVECL when VCC
is connected to GND and VEE is connected to a nega-
tive supply.
A differential input of at least ±100mV switches the out-
puts to the VOH and VOL levels specified in the DC
Electrical Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF value
capacitor closest to the device. Use multiple parallel
ground vias for low inductance.
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9320B. Connect each signal of a differ-
ential input or output to a 50Ωcharacteristic impedance
trace. Minimize the number of vias to prevent impedance
discontinuities. Reduce reflections by maintaining the
50Ωcharacteristic impedance through connectors and
across cables. Reduce skew within a differential pair by
matching the electrical length of the traces.
Output Termination
Terminate outputs through 50Ωto VCC - 2V or use an
equivalent Thevenin termination. Terminate both out-
puts and use the same termination on each for the low-
est output-to-output skew. When a single-ended signal
is taken from a differential output, terminate both out-
puts. For example, if Q0 is used as a single-ended out-
put, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 182
MAX9320B
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
9LUCSP, 3x3.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
