LTC3528B-2
1
3528b2fa
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
1A, 2MHz Synchronous
Step-Up DC/DC Converter
in 2mm × 3mm DFN
The LTC
®
3528B-2 is a synchronous, fixed frequency
step-up DC/DC converter with output disconnect. High
efficiency synchronous rectification, in addition to a 700mV
start-up voltage and operation down to 500mV once
started, provides longer run-time for single or multiple
cell battery-powered products.
A switching frequency of 2MHz minimizes solution
footprint by allowing the use of tiny, low profile induc-
tors and ceramic capacitors. The current mode PWM is
internally compensated, simplifying the design process.
The LTC3528B-2 features continuous switching at light
loads. Anti-ringing circuitry reduces EMI by damping the
inductor in discontinuous mode. Additional features include
a low shutdown current, open-drain power good output,
short-circuit protection and thermal overload protection.
The LTC3528B-2 is offered in an 8-lead 2mm × 3mm ×
0.75mm DFN package.
n Delivers 3.3V at 200mA from a Single Alkaline/
NiMH Cell or 3.3V at 400mA from Two Cells
n VIN Start-Up Voltage: 700mV
n 0.50V to 5.5V Input Range
n 1.6V to 5.25V VOUT Range
n Up to 94% Efficiency
n Output Disconnect
n 2MHz Fixed Frequency Operation
n VIN > VOUT Operation
n Integrated Soft-Start
n Current Mode Control with Internal Compensation
n Low Noise PWM Operation
n Internal Synchronous Rectifier
n Logic Controlled Shutdown: <1µA
n Anti-Ringing Control
n Low Profile (2mm × 3mm × 0.75mm) DFN Package
n Medical Instruments
n Flash-Based MP3 Players
n Noise Canceling Headphones
n Wireless Mice
n Bluetooth Headsets
Efficiency and Power Loss
SW
VIN
499k
2.2µH
287k
4.7µF
10µF
68pF
35282 TA01a
LTC3528B-2
SHDN
PGOOD
VOUT
FB
VIN
1.8V TO 3.2V
VOUT
3.3V
400mA
OFF ON
GND
LOAD CURRENT (mA)
0.1
80
90
100
35282 TA01b
70
60
1 10 100 1000
50
40
30
20
10
0
100
1000
10
1
EFFICIENCY (%)
POWER LOSS (mW)
EFFICIENCY
POWER LOSS
VOUT = 3.3V
VIN = 2.4V
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
LTC3528B-2
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3528b2fa
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
VIN Voltage ................................................... –0.3V to 6V
SW Voltage
DC ............................................................ –0.3V to 6V
Pulsed < 100ns ........................................ –0.3V to 7V
SHDN, FB Voltage ........................................ –0.3V to 6V
VOUT ............................................................. –0.3V to 6V
PGOOD ......................................................... –0.3V to 6V
Operating Junction Temperature Range
(Notes 2, 5) ............................................ –40°C to 125°C
Junction Temperature ........................................... 125°C
Storage Temperature Range ................... –65°C to 125°C
(Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Start-Up Voltage ILOAD = 1mA l0.70 0.88 V
Output Voltage Adjust Range
TA = 0°C to 85°C
l1.7
1.6
5.25
5.25
V
V
Feedback Voltage (Note 7) l1.170 1.200 1.230 V
Feedback Input Current VFB = 1.3V 1 50 nA
Quiescent Current—Shutdown VSHDN = 0V, Not Including Switch Leakage, VOUT = 0V 0.01 1 µA
Quiescent Current—Active Measured on VOUT, Nonswitching (Note 4) 300 500 µA
N-Channel MOSFET Switch Leakage Current VSW = 5V 0.1 10 µA
P-Channel MOSFET Switch Leakage Current VSW = 5V, VOUT = 0V 0.1 10 µA
N-Channel MOSFET Switch On Resistance 0.175 Ω
P-Channel MOSFET Switch On Resistance 0.250 Ω
N-Channel MOSFET Current Limit l1.0 1.5 A
Current Limit Delay Time to Output (Note 3) 60 ns
Maximum Duty Cycle VFB = 1.15V l87 92 %
Minimum Duty Cycle VFB = 1.3V l0 %
Frequency l1.8 2.0 2.4 MHz
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 1.2V, VOUT = 3.3V, unless otherwise noted.
TOP VIEW
9
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
5
6
7
8
4
3
2
1SHDN
FB
PGOOD
VOUT
VIN
SGND
PGND
SW
TJMAX = 125°C, θJA = 76°C/W (NOTE 6)
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3528BEDDB-2#PBF LTC3528BEDDB-2#TRPBF LDPB 8-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
PIN CONFIGURATION
ORDER INFORMATION
LTC3528B-2
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3528b2fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3528B-2 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3528BE-2 is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors. The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD • θJA)
where θJA = 76°C/W is the package thermal impedance.
PARAMETER CONDITIONS MIN TYP MAX UNITS
SHDN Input High Voltage 0.88 V
SHDN Input Low Voltage 0.25 V
SHDN Input Current VSHDN = 1.2V 0.3 1 µA
PGOOD Threshold Percentage Referenced to Feedback Voltage Falling –7 –10 –13 %
PGOOD Low Voltage IPGOOD = 1mA
VOUT = 1.6V, IPGOOD = 1mA
0.05
0.05
0.1
0.2
V
V
PGOOD Leakage Current VPGOOD = 5.5V 0.01 1 µA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 1.2V, VOUT = 3.3V, unless otherwise noted.
Note 3: Specification is guaranteed by design and not 100% tested in
production.
Note 4: Current measurements are made when the output is not switching.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may result in device degradation or failure.
Note 6: Failure to solder the exposed backside of the package to the PC
board ground plane will result in a thermal resistance much higher than
76°C/W.
Note 7: The IC is tested in a feedback loop to make the measurement.
LTC3528B-2
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LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
60
80
100
100
35282 G03
40
20
50
70
90
30
10
10
100
10000
1000
1
110 1000
VIN = 2.4V
VIN = 3.6V
VIN = 4.2V
EFFICIENCY
POWER
LOSS
Maximum Output Current vs VIN
Minimum Load Resistance During
Start-Up vs VIN Start-Up Delay Time vs VIN
Efficiency vs Load Current and VIN
for VOUT = 5V
Efficiency vs Load Current and VIN
for VOUT = 3.3V
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
60
80
100
100
35282 G02
40
20
50
70
90
30
10
10
100
1000
1
110 1000
VIN = 1.8V
VIN = 2.4V
VIN = 3V
EFFICIENCY
POWER
LOSS
VIN (V)
1
IOUT (mA)
700
2.5
35282 G05
400
200
1.5 2 3
100
0
800
600
500
300
3.5 4 4.5
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5V
VIN (V)
0.7
10
RLOAD (Ω)
1000
100
10000
0.8 0.9 1
35282 G06
VIN (V)
1
DELAY (µs)
120
2.5
35282 G07
90
70
1.5 2 3
60
50
130
110
100
80
3.5 4 4.5
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Efficiency vs Load Current and VIN
for VOUT = 1.8V
Efficiency vs Load Current and VIN
for VOUT = 3V
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
60
80
100
100
35282 G01
40
20
50
70
90
30
10
0
10
100
1000
1
0.1
110 1000
VIN = 1V
VIN = 1.2V
VIN = 1.5V
EFFICIENCY
POWER
LOSS
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
60
80
100
100
35282 G26
40
20
50
70
90
30
10
0
10
100
1000
1
110 1000
VIN = 1V
VIN = 1.5V
VIN = 2.4V
EFFICIENCY
POWER
LOSS
LTC3528B-2
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TEMPERATURE (°C)
–50 –25
600
START-UP VOLTAGE (mV)
700
850
050 75
35282 G17
650
800
750
25 100 125
Oscillator Frequency Change
vs VOUT RDS(ON) vs VOUT
Oscillator Frequency Change
vs Temperature
RDS(ON) Change vs Temperature VFB vs Temperature Start-Up Voltage vs Temperature
Fixed Frequency VOUT Ripple and
Inductor Current Waveforms
VOUT (V)
1.5
FREQUENCY CHANGE (%)
–1.50
0
0.25
0.50
2.5 3.5 4
35282 G12
–2.00
–0.50
–1.00
–1.75
–0.25
–2.25
–0.75
–1.25
234.5 5
VOUT (V)
1.5
300
350
450
3 4
35282 G13
250
200
2 2.5 3.5 4.5 5
150
100
400
RDS(ON) (mΩ)
PMOS
NMOS
TEMPERATURE (˚C)
–50
FREQUENCY CHANGE (%)
0
1
2
25 75
35282 G14
–1
–2
–25 0 50 100 125
–3
–4
TEMPERATURE (˚C)
–50
CHANGE (%)
20
30
40
25 75
35282 G15
10
0
–25 0 50 100 125
–10
–20
TEMPERATURE (°C)
–50
1.196
VFB (V)
1.197
1.198
1.199
1.200
–25 0 25 50
35282 G16
75 100 125
VOUT
20mV/DIV
500ns/DIV 35282 G19
VIN = 1.2V
VOUT = 3.3V
COUT = 10µF
CFF = 33pF
IOUT = 100mA
L = 2.2µH
IL
200mA/DIV
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C unless otherwise noted)
VOUT and IIN During Soft-Start
VOUT
1V/DIV
SHDN PIN
200µs/DIV 35282 G21
VIN = 1.2V
VOUT = 3.3V
COUT = 10µF
L = 2.2µH
IIN
200mA/DIV
LTC3528B-2
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PIN FUNCTIONS
Load Step Response
(1.2V to 3.3V)
SHDN (Pin 1): Logic Controlled Shutdown Input. There is
an internal 4MΩ pull-down resistor on this pin.
• SHDN = High: Normal operation
• SHDN = Low: Shutdown, quiescent current < 1µA
FB (Pin 2): Feedback Input. Connect resistor divider tap
to this pin. The output voltage can be adjusted from 1.6V
to 5.25V by:
VOUT =1.20V •1+R2
R1
PGOOD (Pin 3): Power Good Comparator Output. This
open-drain output is low when VFB < 10% from its regu-
lation voltage.
VOUT (Pin 4): Output Voltage Sense and Drain Connection
of the Internal Synchronous Rectifier. PCB trace length
from VOUT to the output filter capacitor (4.7µF minimum)
should be as short and wide as possible.
SW (Pin 5): Switch Pin. Connect inductor between SW
and VIN. Keep PCB trace lengths as short and wide as
possible to reduce EMI. If the inductor current falls to
zero, or SHDN is low, an internal anti-ringing switch is
connected from SW to VIN to minimize EMI.
PGND (Pin 6): Power Ground. Provide a short direct PCB
path between PGND and the (–) side of the input and
output capacitors.
SGND (Pin 7): Signal Ground. Provide a short direct PCB
path between SGND and the (–) side of the input and
output capacitors.
VIN (Pin 8): Battery Input Voltage. Connect a minimum of
1µF ceramic decoupling capacitor from this pin to ground.
GND (Exposed Pad Pin 9): The exposed pad must be
soldered to the PCB ground plane. It serves as another
ground connection and as a means of conducting heat
away from the die.
Load Step Response
(3.6V to 5V)
VOUT
100mV/DIV
20µs/DIV 35282 G22
VIN = 3.6V
VOUT = 5V
COUT = 10µF
L = 2.2µH
LOAD CURRENT = 100mA TO 550mA
LOAD
CURRENT
200mA/DIV
VOUT
100mV/DIV
20µs/DIV 35282 G24
VIN = 1.2V
VOUT = 3.3V
COUT = 10µF
L = 2.2µH
LOAD CURRENT = 20mA TO 170mA
LOAD
CURRENT
100mA/DIV
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C unless otherwise noted)
LTC3528B-2
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BLOCK DIAGRAM
8
Σ
+
–
+
–
GATE DRIVERS
AND
ANTI-CROSS
CONDUCTION
LOGIC
CLK
UVLO PK
PK
COMP
SLOPE
COMP
IZERO
COMP
ERROR AMP
IZERO
WAKE
EXPOSED
PAD
+
–
WELL
SWITCH
UVLO
VREF VREF
4M
SHDN
VBEST
START-UP
2MHz
OSC
TSD
THERMAL
SHUTDOWN
SHUTDOWN
ANTI-RING
VSEL
VIN
5
4
SW
VOUT
L1
2.2µH
VB
SHUTDOWN
CLAMP
SOFT-START
VREF
+
–
VREF – 10%
FB
FB
VOUT
2
9
SGND
35282 BD
7
PGND
6
FB
R2
COUT
10µF
VOUT
1.6V
TO 5.25V
R1
1
PGOOD
3
CIN
4.7µF
VIN
0.7V
TO 5V
LTC3528B-2
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OPERATION
The LTC3528B-2 is a 2MHz synchronous boost converter
housed in an 8-lead 3mm × 2mm DFN package. With the
ability to start-up and operate from inputs less than 0.88V,
the device features fixed frequency, current mode PWM
control for exceptional line and load regulation. The cur-
rent mode architecture with adaptive slope compensation
provides excellent transient load response and requires
minimal output filtering. Internal soft-start and internal
loop compensation simplifies the design process while
minimizing the number of external components.
With its low RDS(ON) and low gate charge internal N-channel
MOSFET switch and P-channel MOSFET synchronous
rectifier, the LTC3528-2 achieves high efficiency over a
wide range of load current. The LTC3528B-2 features
continuous PWM operation at 2MHz. At very light loads,
the LTC3528B-2 will exhibit pulse-skip operation. Operation
can be best understood by referring to the Block Diagram.
LOW VOLTAGE START-UP
The LTC3528B-2 includes an independent start-up oscillator
designed to operate at an input voltage of 0.70V (typical).
Soft-start and inrush current limiting are provided during
start-up, as well as normal operating mode.
When either VIN or VOUT exceeds 1.6V typical, the IC enters
normal operating mode. Once the output voltage exceeds
the input by 0.24V, the IC powers itself from VOUT instead of
VIN. At this point the internal circuitry has no dependency
on the VIN input voltage, eliminating the requirement for
a large input capacitor. The input voltage can drop as low
as 0.5V. The limiting factor for the application becomes
the availability of the power source to supply sufficient
power to the output at the low voltages, and the maximum
duty cycle, which is clamped at 92% typical. Note that
at low input voltages, small voltage drops due to series
resistance become critical, and greatly limit the power
delivery capability of the converter.
LOW NOISE FIXED FREQUENCY OPERATION
Soft-Start
The LTC3528B-2 contains internal circuitry to provide
soft-start operation. The internal soft-start circuitry slowly
ramps the peak inductor current from zero to its peak
value of 1.5A (typical), allowing start-up into heavy loads.
The soft-start time is approximately 0.5ms. The soft-start
circuitry is reset in the event of a commanded shutdown
or a thermal shutdown.
Oscillator
An internal oscillator sets the frequency of operation to
2MHz.
Shutdown
The converter is shut down by pulling the SHDN pin below
0.25V, and activated by pulling SHDN above 0.88V. Although
SHDN can be driven above VIN or VOUT (up to the absolute
maximum rating) without damage, the LTC3528B-2 has a
proprietary test mode that may be engaged if SHDN is held
in the range of 0.5V to 1V higher than the greater of VIN or
VOUT. If the test mode is engaged, normal PWM switching
action is interrupted, which can cause undesirable opera-
tion in some applications. Therefore, in applications where
SHDN may be driven above VIN, a resistor divider or other
means must be employed to keep the SHDN voltage below
(VIN + 0.4V) to prevent the possibility of the test mode
being engaged. Please refer to Figure 1 for two possible
implementations
(Refer to Block Diagram)
4M
±30% SHDN
LTC3528B-2
R
1M
VCNTRL
VCNTRL
4M
±30% SHDN
LTC3528B-2
ZETEX ZC2811E
R > (VCNTRL/(VIN + 0.4) – 1) MΩ
VIN
1M
3528 F01
Figure 1. Recommended Shutdown Circuits
when Driving SHDN Above VIN
LTC3528B-2
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Error Amplifier
The error amplifier is a transconductance type. The nonin-
verting input is internally connected to the 1.20V reference
and the inverting input is connected to FB. Clamps limit
the minimum and maximum error amp output voltage for
improved large-signal transient response. Power converter
control loop compensation is provided internally. A voltage
divider from VOUT to ground programs the output voltage
via FB from 1.6V to 5.25V.
VOUT =1.20V •1+R2
R1
Current Sensing
Lossless current sensing converts the peak current signal
of the N-channel MOSFET switch into a voltage which
is summed with the internal slope compensation. The
summed signal is compared to the error amplifier output
to provide a peak current control command for the PWM.
Current Limit
The current limit comparator shuts off the N-channel
MOSFET switch once its threshold is reached. The cur-
rent limit comparator delay to output is typically 60ns.
Peak switch current is limited to approximately 1.5A,
independent of input or output voltage, unless VOUT falls
below 0.7V, in which case the current limit is cut in half.
Zero Current Comparator
The zero current comparator monitors the inductor cur-
rent to the output and shuts off the synchronous rectifier
when this current reduces to approximately 20mA. This
prevents the inductor current from reversing in polarity,
improving efficiency at light loads.
Synchronous Rectifier
To control inrush current and to prevent the inductor
current from running away when VOUT is close to VIN, the
P-channel MOSFET synchronous rectifier is only enabled
when VOUT > (VIN + 0.24V).
Anti-Ringing Control
The anti-ringing control connects a resistor across the
inductor to prevent high frequency ringing on the SW pin
during discontinuous current mode operation. The ringing
of the resonant circuit formed by L and CSW (capacitance
on SW pin) is low energy, but can cause EMI radiation.
Output Disconnect
The LTC3528B-2 is designed to allow true output discon-
nect by eliminating body diode conduction of the internal
P-channel MOSFET rectifier. This allows for VOUT to go to
zero volts during shutdown, drawing no current from the
input source. It also enables inrush current limiting at turn-
on, minimizing surge currents seen by the input supply.
Note that to obtain the advantages of output disconnect,
a Schottky diode cannot be connected between SW and
VOUT. The output disconnect feature also allows VOUT to be
forced above the programmed regulation voltage, without
any reverse current into a battery on VIN.
Thermal Shutdown
If the die temperature exceeds 160°C, the LTC3528B-2
enters thermal shutdown. All switches will be turned off
and the soft-start capacitor will be discharged. The device
will be enabled again when the die temperature drops by
approximately 15°C.
OPERATION
(Refer to Block Diagram)
LTC3528B-2
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APPLICATIONS INFORMATION
VIN > VOUT OPERATION
The LTC3528B-2 maintains voltage regulation even when
the input voltage is above the desired output voltage. Note
that the efficiency is much lower in this mode, and the
maximum output current capability will be less. Refer to
the Typical Performance Characteristics.
SHORT-CIRCUIT PROTECTION
The LTC3528B-2 output disconnect feature allows an output
short circuit while maintaining a maximum internally set
current limit. To reduce power dissipation under short-
circuit conditions, the peak switch current limit is reduced
to 750mA (typical).
SCHOTTKY DIODE
Although not required, adding a Schottky diode from
SW to VOUT will improve efficiency by about 2%. Note
that this defeats the output disconnect and short-circuit
protection features.
PCB LAYOUT GUIDELINES
The high speed operation of the LTC3528B-2 demands
careful attention to board layout. A careless layout will
not produce the advertised performance. Figure 2 shows
the recommended component placement. A large ground
copper area with the package backside metal pad properly
soldered will help to lower the chip temperature. A multi-
layer board with a separate ground plane is ideal, but not
absolutely necessary.
COMPONENT SELECTION
Inductor Selection
The LTC3528B-2 can utilize small surface mount chip
inductors due to their fast 2MHz switching frequency.
Inductor values between 1.5µH and 3.3µH are suitable for
most applications. Larger values of inductance will allow
slightly greater output current capability by reducing the
inductor ripple current. Increasing the inductance above
10µH will increase size while providing little improvement
in output current capability.
The minimum inductance value is given by:
L>VIN(MIN) •VOUT(MAX) – VIN(MIN)
( )
2•Ripple •VOUT(MAX)
µH
where:
Ripple = Allowable inductor current ripple (amps peak-
peak)
VIN(MIN) = Minimum input voltage
VOUT(MAX) = Maximum output voltage
Figure 2. Recommended Component Placement for Single Layer Board
SHDN
FB
PGOOD
LTC3528B-2
VOUT
35282 F02
COUT
VIN
VIN CIN
SGND
PGND
SW
MULTIPLE VIAS
TO GROUND PLANE
8
5
6
7
1
4
3
2
+
LTC3528B-2
11
3528b2fa
APPLICATIONS INFORMATION
The inductor current ripple is typically set for 20% to
40% of the maximum inductor current. High frequency
ferrite core inductor materials reduce frequency dependent
power losses compared to cheaper powdered iron types,
improving efficiency. The inductor should have low ESR
(series resistance of the windings) to reduce the I2R power
losses, and must be able to handle the peak inductor current
without saturating. Molded chokes and some chip induc-
tors usually do not have enough core area to support the
peak inductor currents of 1.5A seen on the LTC3528B-2.
To minimize radiated noise, use a shielded inductor. See
Table 1 for suggested components and suppliers.
Table 1. Recommended Inductors
VENDOR PART/STYLE
Coilcraft
(847) 639-6400
www.coilcraft.com
DO1606T, MSS5131, MSS5121
MSS6122, MOS6020
ME3220, DO1608C
1812PS
Coiltronics SD12, SD14, SD20
SD25, SD52
Sumida
(847) 956-0666
www.sumida.com
CD43
CDC5D23B
CDRH5D18
TDK VLP, VLF
VLCF, SLF, VLS
Toko
(408) 432-8282
www.tokoam.com
D53, D62, D63
D73, D75
Wurth
(201) 785-8800
www.we-online.com
WE-TPC type M, MH
Output and Input Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
be used to minimize the output voltage ripple. Multilayer
ceramic capacitors are an excellent choice as they have
extremely low ESR and are available in small footprints.
A 10µF to 22µF output capacitor is sufficient for most ap-
plications. Values larger than 22µF may be used to obtain
extremely low output voltage ripple and improve transient
response. X5R and X7R dielectric materials are preferred
for their ability to maintain capacitance over wide voltage
and temperature ranges. Y5V types should not be used.
The internal loop compensation of the LTC3528B-2 is
designed to be stable with output capacitor values of 10µF
or greater. Although ceramic capacitors are recommended,
low ESR tantalum capacitors may be used as well.
A small ceramic capacitor in parallel with a larger tantalum
capacitor may be used in demanding applications which
have large load transients. Another method of improving the
transient response is to add a small feed-forward capaci-
tor across the top resistor of the feedback divider (from
VOUT to FB). A typical value of 33pF will generally suffice.
Low ESR input capacitors reduce input switching noise
and reduce the peak current drawn from the battery. It
follows that ceramic capacitors are also a good choice
for input decoupling and should be located as close as
possible to the device. A 10µF input capacitor is sufficient
for most applications. Larger values may be used without
limitations. Table 2 shows a list of several ceramic capaci-
tor manufacturers. Consult the manufacturers directly for
detailed information on their selection of ceramic parts.
Table 2. Capacitor Vendor Information
SUPPLIER PHONE WEBSITE
AVX (803) 448-9411 www.avxcorp.com
Murata (714) 852-2001 www.murata.com
Taiyo-Yuden (408) 573-4150 www.t-yuden.com
TDK (847) 803-6100 www.component.tdk.com
LTC3528B-2
12
3528b2fa
TYPICAL APPLICATIONS
1 Cell to 1.8V
SW
VIN
499k
2.2µH
1M
4.7µF
10µF
68pF
35282 TA02a
LTC3528B-2
SHDN
PGOOD
VOUT
FB
VIN
0.88V TO 1.6V
VOUT
1.8V
250mA
OFF ON
GND
Dual 1 Cell to 1.8V, 3V Sequenced Supply
SW
VIN
499k
475k
2.2µH
1M
4.7µF
10µF
LTC3528B-2
SHDN
PGOOD
VOUT
FB
VIN
0.88V TO 1.6V
VOUT1
1.8V
250mA
OFF ON
GND
SW
VIN
499k
2.2µH
324k
4.7µF
10µF
68pF
3528 TA03a
LTC3528B-2
SHDN
PGOOD
VOUT
FB
VOUT2
3V
200mA
GND
68pF
Efficiency
Output Voltage Sequencing
VOUT2
VOUT1
VIN
PGOOD1
200µs/DIV
0.5V/DIV
35282 TA03b
LOAD CURRENT (mA)
20
EFFICIENCY (%)
40
50
70
80
90
100
0.1 10 100 1000
35282 TA02b
1
60
30
10
VIN = 0.9V
VIN = 1.2V
VIN = 1.5V
LTC3528B-2
13
3528b2fa
TYPICAL APPLICATIONS
1 Cell to 3.3V Efficiency
Efficiency2 Cell to 3.3V
SW
VIN
499k
2.2µH
287k
4.7µF
10µF
68pF
35282 TA04a
LTC3528B-2
SHDN
PGOOD
VOUT
FB
VIN
0.88V TO 1.6V
VOUT
3.3V
200mA
OFF ON
GND
SW
VIN
499k
2.2µH
287k
4.7µF
10µF
68pF
35282 TA05a
LTC3528B-2
SHDN
PGOOD
VOUT
FB
VIN
1.8V TO 3.2V
VOUT
3.3V
400mA
OFF ON
GND
LOAD CURRENT (mA)
1
50
EFFICIENCY (%)
70
90
10 100 1000
36282 TA04b
30
40
60
80
20
10
VIN = 0.9V
VIN = 1.2V
VIN = 1.5V
LOAD CURRENT (mA)
20
EFFICIENCY (%)
40
50
70
80
90
100
0.1 10 100 1000
35282 TA05b
1
60
30
10
VIN = 1.8V
VIN = 2.4V
VIN = 3V
LTC3528B-2
14
3528b2fa
TYPICAL APPLICATIONS
2 Cell to 5V
Efficiency
SW
VIN
1M
2.2µH
316k
4.7µF
22µF
35282 TA06a
LTC3528B-2
SHDN
PGOOD
VOUT
FB
VIN
1.8V TO 3.2V
VOUT
5V
300mA
OFF ON
GND
LOAD CURRENT (mA)
20
EFFICIENCY (%)
40
50
70
80
90
100
0.1 10 100 1000
35282 TA06b
1
60
30
10
VIN = 1.8V
VIN = 2.4V
VIN = 3V
LTC3528B-2
15
3528b2fa
TYPICAL APPLICATIONS
Efficiency
Li-Ion to 5V
SW
VIN
1M
2.2µH
316k
4.7µF
22µF
35282 TA07a
LTC3528B-2
SHDN
PGOOD
VOUT
FB
VIN
2.7V TO 4.2V
VOUT
5V
400mA
OFF ON
GND
LOAD CURRENT (mA)
20
EFFICIENCY (%)
40
50
70
80
90
100
0.1 10 100 1000
35282 TA07b
1
60
30
10
VIN = 2.8V
VIN = 3.6V
VIN = 4.2V
LTC3528B-2
16
3528b2fa
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
0.56 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.15 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
14
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0 – 0.05
(DDB8) DFN 0905 REV B
0.25 ± 0.05
0.50 BSC
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
0.25 ± 0.05
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 ±0.05
(2 SIDES)
1.15 ±0.05
0.70 ±0.05
2.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
PACKAGE DESCRIPTION
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
LTC3528B-2
17
3528b2fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 01/11 Change to Operating Temperature Range
Update to Note 2 reflected in Electrical Characteristics
Replaced graphs G14, G15, G16 and G17
Operations section update Pin 9 to read GND
Operations section update to Shutdown
2
2, 3
5
6
8
LTC3528B-2
18
3528b2fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2008
LT 0111 REV A • PRINTED IN USA
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