1
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1104, Rev. D
256-Kb I2C CMOS Serial EEPROM
CAT24C256
PIN CONFIGURATION FUNCTIONAL SYMBOL
FEATURES
n Supports Standard and Fast I2C Protocol
n 1.8 V to 5.5 V Supply Voltage Range
n 64-Byte Page Write Buffer
n Hardware Write Protection for entire memory
n Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
n Low power CMOS technology
n 1,000,000 program/erase cycles
n 100 year data retention
n Industrial temperature range
n RoHS-compliant 8-pin PDIP and SOIC packages
PDIP (L)
SOIC (W, X)
VCC
VSS
SD
A
SCL
WP
CAT24C256
A2, A1, A0
DEVICE DESCRIPTION
The CAT24C256 is a 256-Kb Serial CMOS EEPROM,
internally organized as 512 pages of 64 bytes each, for
a total of 32,768 bytes of 8 bits each.
It features a 64-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory).
External address pins make it possible to address up to
eight CAT24C256 devices on the same bus.
8
7
6
5
VCC
WP
SCL
SDA
A2
A0
A1
VSS
1
2
3
4
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTIONS
A0, A1, A2Device Address
SDA Serial Data
SCL Serial Clock
WP Write Protect
VCC Power Supply
VSS Ground
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
For Ordering Information details, see page 13.
CAT24C256
2
Doc. No. 1104, Rev. D © 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature -65°C to +150°C
Voltage on Any Pin with Respect to Ground(2) -0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter Min Units
NEND(4) Endurance 1,000,000 Program/ Erase Cycles
TDR Data Retention 100 Years
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specied.
Symbol Parameter Test Conditions Min Max Units
ICC Supply Current Read or Write at 400 kHz 1 mA
ISB Standby Current All I/O Pins at GND or VCC 1 µA
ILI/O Pin Leakage Pin at GND or VCC 1 µA
VIL Input Low Voltage -0.5 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC > 1.8 V, IOL = 1.0 mA 0.2 V
PIN IMPEDANCE CHARACTERISTICS
TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol Parameter Conditions Min Max Units
CIN(3) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN(3) Input Capacitance (other pins) VIN = 0 V 6 pF
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
CAT24C256
3Doc No. 1104, Rev. D
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A.C. CHARACTERISTICS(1)
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specied.
Symbol Parameter
1.8 V - 5.5 V 2.5 V - 5.5 V
Units
Min Max Min Max
FSCL Clock Frequency 100 400 kHz
TI(2) Noise Suppression Time Constant at
SCL, SDA Inputs
0.1 0.1 µs
tAA SCL Low to SDA Data Out 3.5 0.9 µs
tBUF(2) Time the Bus Must be Free Before a
New Transmission Can Start
4.7 1.3 µs
tHD:STA Start Condition Hold Time 4 0.6 µs
tLOW Clock Low Period 4.7 1.3 µs
tHIGH Clock High Period 4 0.6 µs
tSU:STA Start Condition Setup Time 4.7 0.6 µs
tHD:DAT Data In Hold Time 0 0 µs
tSU:DAT Data In Setup Time 0.25 0.1 µs
tR(2) SDA and SCL Rise Time 1 0.3 µs
tF(2) SDA and SCL Fall Time 0.3 0.3 µs
tSU:STO Stop Condition Setup Time 4 0.6 µs
tDH Data Out Hold Time 0.1 0.1 µs
tWR Write Cycle Time 5 5 ms
tPU(2), (3) Power-up to Ready Mode 1 1 ms
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times ≤ 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
CAT24C256
4
Doc. No. 1104, Rev. D © 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device ad-
dress. These pins have on-chip pull-down resistors.
WP: The Write Protect input pin inhibits all write op-
erations, when pulled HIGH. This pin has an on-chip
pull-down resistor.
FUNCTIONAL DESCRIPTION
The CAT24C256 supports the Inter-Integrated Circuit
(I2C) Bus data transmission protocol, which denes a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data ow is controlled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C256
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver. Up to 8 devices may be
connected to the bus as determined by the device ad-
dress inputs A0, A1, and A2.
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake-up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when follow-
ing a Write command) or sends the Slave into standby
mode (when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The rst 4 bits of the Slave
address are set to 1010, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices. The last bit, R/W,
species whether a Read (1) or Write (0) operation is
to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge the byte address and every data
byte presented in Write mode. In Read mode the Slave
shifts out a data byte, and then releases the SDA line
during the 9th clock cycle. If the Master acknowledges
the data, then the Slave continues transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by sending a STOP to
the Slave. Bus timing is illustrated in Figure 4.
CAT24C256
5Doc No. 1104, Rev. D
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 3. Acknowledge Timing
Figure 2. Slave Address Bits
Figure 1. Start/Stop Timing
Figure 4. Bus Timing
1 0 1 0
DEVICE ADDRESS
A2A1A0R/W
START
CONDITION
STOP
CONDITION
SDA
SCL
1 8 9
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK DELAY (≤ tAA)
ACK SETUP (≥ tSU:DAT)
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA tDH
CAT24C256
6
Doc. No. 1104, Rev. D © 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be
written (Figure 5). The Slave acknowledges all 4 bytes,
and the Master then follows up with a STOP, which in
turn starts the internal Write operation (Figure 6). During
internal Write, the Slave will not acknowledge any Read
or Write request from the Master.
Page Write
The CAT24C256 contains 32,768 bytes of data, arranged
in 512 pages of 64 bytes each. A two byte address word,
following the Slave address, points to the rst byte to be
written. The most signicant bit of the address word is
‘don’t care’, the next 9 bits identify the page and the last
6 bits identify the byte within the page. Up to 64 bytes
can be written in one Write cycle (Figure 7).
The internal byte address counter is automatically in-
cremented after each data byte is loaded. If the Master
transmits more than 64 data bytes, then earlier bytes will
be overwritten by later bytes in a ‘wrap-around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT24C256 is busy writing or is ready to accept com-
mands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS).
The CAT24C256 will not acknowledge the Slave address,
as long as internal Write is in progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is pro-
tected against Write operations. If the WP pin is left
oating or is grounded, it has no impact on the operation
of the CAT24C256.
CAT24C256
7Doc No. 1104, Rev. D
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 7. Page Write Timing
Figure 6. Write Cycle Timing
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS
DATA n+63DATA
A
C
K
S
T
O
P
A
C
K
DATA n
A
C
K
P
A
C
K
*
*
= Don't Care Bit
Figure 5. Byte Write Timing
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS
A
C
K
*
*
= Don't Care Bit
CAT24C256
8
Doc. No. 1104, Rev. D © 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
READ OPERATIONS
Immediate Address Read
In standby mode, the CAT24C256 internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If that ‘previ-
ous’ byte was the last byte in memory, then the address
counter will point to the 1st memory byte, etc.
When, following a START, the CAT24C256 is presented
with a Slave address containing a ‘1’ in the R/W bit
position (Figure 8), it will acknowledge (ACK) in the 9th
clock cycle, and will then transmit data being pointed
at by the internal address counter. The Master can stop
further transmission by issuing a NoACK, followed by a
STOP condition.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address
counter. The address counter can be initialized by per-
forming a ‘dummy’ Write operation (Figure 9). Here the
START is followed by the Slave address (with the R/W
bit set to ‘0’) and the desired two byte address. Instead
of following up with data, the Master then issues a 2nd
START, followed by the ‘Immediate Address Read’ se-
quence, as described earlier.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAT24C256, then the device will continue trans-
mitting as long as each data byte is acknowledged by
the Master (Figure 10). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap-around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
byte address.
CAT24C256
9Doc No. 1104, Rev. D
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+xDATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
Figure 9. Selective Read Timing
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
A
R
TDATA
P
S
T
O
P
*
* = Don't Care Bit
Figure 8. Immediate Address Read Timing
SCL
SDA 8th Bit
STOPNO ACKDATA OUT
8 9
SLAVE
ADDRESS
S
A
C
K
DATA N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
CAT24C256
10
Doc. No. 1104, Rev. D © 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
Notes:
(1) Complies with JEDEC Standard MS001.
(2) All dimensions are in millimeters.
(3) Dimensioning and tolerancing per ANSI Y14.5M-1982
A
e
b
c
E1
b2
L
A2
A1
E
D
eB
SYMBOL
A
A1
b
b2
D
E
E1
e
eB
L
MIN
0.38
0.36
9.02
7.62
6.09 6.35
7.87
2.92 3.81
NOM
0.46
1.771.14
7.87
2.54 BSC
MAX
4.57
A2 3.05 3.81
0.56
c 0.21 0.26 0.35
10.16
8.25
7.11
9.65
For current Tape and Reel information, download the PDF le from:
http://www.catsemi.com/documents/tapeandreel.pdf
PACKAGE OUTLINES
CAT24C256
11 Doc No. 1104, Rev. D
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8-LEAD 150 MIL WIDE SOIC (W)
Notes:
(1) Complies with JEDEC specication MS-012 dimensions.
(2) All linear dimensions are in millimeters.
SYMBOL
A1
A
b
C
D
E
E1
h
L
MIN
0.10
1.35
0.33
4.80
5.80
3.80
0.25
0.40
NOM
0.250.19
MAX
0.25
1.75
0.51
5.00
6.20
4.00
e 1.27 BSC
0.50
1.27
Ө1
0° 8°
E
E1
D
A1
e
L
Ө1
C
b
h x 45
A
For current Tape and Reel information, download the PDF le from:
http://www.catsemi.com/documents/tapeandreel.pdf
CAT24C256
12
Doc. No. 1104, Rev. D © 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8-LEAD 208 MIL WIDE SOIC, EIAJ (X)
Notes:
(1) Complies with EIAJ specication.
(2) All linear dimensions are in millimeters.
L
A1
A
b
E
e
D
θ1
c
SYMBOL
A1
A
b
c
D
E
E1
e
L
MIN
0.05
0.36
5.13
7.75
5.13
0.51
NOM
0.250.19
1.27 BSC
MAX
0.25
2.03
0.48
5.33
8.26
5.38
0.76
θ
1 0°8°
For current Tape and Reel information, download the PDF le from:
http://www.catsemi.com/documents/tapeandreel.pdf
CAT24C256
13 Doc No. 1104, Rev. D
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ORDERING INFORMATION
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead nish is NiPdAu.
(3) The device used in the above example is a CAT24C256WI-GT3 (SOIC-JEDEC, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For SOIC, EIAJ (X) package the standard lead nish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT24C256XI-T2.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales ofce.
Prefix Device # Suffix
24C256 W I
Product
Number
CAT
Temperature Range
I = Industrial (-40°C to +85°C)
Company ID
Package
L: PDIP
W: SOIC, JEDEC
X: SOIC, EIAJ(4)
G—
Lead Finish
Blank: Matte-Tin
G: NiPdAu
T3
Tape & Reel
T: Tape & Reel
2: 2000/Reel(4)
3: 3000/Reel
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS
FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD
PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR
APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death
may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled “Advance
Information” or “Preliminary” and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor
applications and may not be complete.
Publication #: 1104
Revison: D
Issue date: 01/12/07
REVISION HISTORY
Date Revision Comments
10/07/05 A Initial Issue
11/16/05 BUpdate Ordering Information
Add Tape and Reel Specications
02/02/06 C Update Ordering Information
01/12/07 D
Update Package Outlines. Add SOIC, EIAJ Package Outlines
Update A.C. Characteristics. Add A.C. Test Conditions
Update Figures 1, 3 and 4
Delete Package Marking. Deleted Tape and Reel
Updated Ordering Information