Kinetis K24F Sub-Family Data
Sheet
120 MHz ARM® Cortex®-M4-based Microcontroller with FPU
The K24 product family members are optimized for cost-sensitive
applications requiring low-power, USB connectivity, and up to
256 KB of embedded SRAM. These devices share the
comprehensive enablement and scalability of the Kinetis family.
This product offers:
Run power consumption down to 250 μA/MHz. Static
power consumption down to 5.8 μA with full state retention
and 5 μs wakeup. Lowest Static mode down to 339 nA
USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
Vreg, with USB device crystal-less operation
Performance
Up to 120 MHz ARM® Cortex®-M4 core with DSP
instructions and floating point unit
Memories and memory interfaces
Up to 1 MB program flash memory and 256 KB RAM
FlexBus external bus interface
System peripherals
Multiple low-power modes, low-leakage wake-up unit
Memory protection unit with multi-master protection
16-channel DMA controller
External watchdog monitor and software watchdog
Security and integrity modules
Hardware CRC module
Hardware random-number generator
Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
128-bit unique identification (ID) number per chip
Analog modules
Two 16-bit SAR ADCs
Two 12-bit DACs
Three analog comparators (CMP)
Voltage reference
Communication interfaces
USB full-/low-speed On-the-Go controller
Controller Area Network (CAN) module
Three SPI modules
Three I2C modules. Support for up to 1 Mbit/s
Six UART modules
Secure Digital Host Controller (SDHC)
I2S module
Timers
Two 8-channel Flex-Timers (PWM/Motor control)
Two 2-channel FlexTimers (PWM/Quad decoder)
32-bit PITs and 16-bit low-power timers
Real-time clock
Programmable delay block
Clocks
3 to 32 MHz and 32 kHz crystal oscillator
PLL, FLL, and multiple internal oscillators
48 MHz Internal Reference Clock (IRC48M)
Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): –40 to 105°C
MK24FN1M0VLQ12
MK24FN1M0VLL12
MK24FN1M0VDC12
121 XFBGA
8 x 8 x 0.5 mm Pitch
0.65 mm
144 LQFP
20 x 20 x 1.6 mm Pitch
0.5 mm
100 QFP
14 x 14 x 1.7 mm Pitch 0.5 mm
NXP Semiconductors K24P144M120SF5
Data Sheet: Technical Data Rev. 7, 11/2016
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information 1
Part Number Memory Maximum number of I\O's
Flash (KB) SRAM (KB)
MK24FN1M0VLL12 1 MB 256 66
MK24FN1M0VDC12 1 MB 256 83
MK24FN1M0VLQ12 1 MB 256 100
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type Description Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K60PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K24P144M120SF5RM 1
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
K24P144M120SF51
Package
drawing
Package dimensions are provided in package drawings. 100-pin LQFP:
98ASS233081
XFBGA 121-pin:
98ASA00595D1
LQFP 144-pin:
98ASS23177W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
Memories and Memory Interfaces
Program
flash RAM
12-bit DAC
6-bit DAC
x3
CRC
Analog Timers Communication InterfacesSecurity
and Integrity
SPI
x3
Clocks
Frequency-
Core
Debug
interfaces DSP
Interrupt
controller
comparator
x3
Analog
Voltage
reference
Low power
timer
Human-Machine
Interface (HMI)
GPIO
System
DMA
Internal
watchdogs
and external
Low-leakage
wakeup
locked loop
Phase-
locked loop
reference
Internal
clocks
Programmable
delay block
timers
interrupt
Periodic
real-time
Independent
clock
oscillators
Low/high
frequency
UART
x6
®
Cortex™-M4ARM
FlexBus
Floating
point
Memory
Protection
SDHC
x1
CAN
x1
Serial
programming
interface
Kinetis K24 Family
USB charger
detect
USB voltage
regulator
USB OTG
LS/FS
USB LS/FS
transceiver
x1
IS
2
Hardware
encryption
number
Random
generator
x2
x3
IC
2
Timers
x2 (8ch)
x2 (2ch)
16-bit ADC
x2
Figure 1. K24 block diagram
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements.....6
2.2.2 LVD and POR operating requirements............. 8
2.2.3 Voltage and current operating behaviors.......... 8
2.2.4 Power mode transition operating behaviors......10
2.2.5 Power consumption operating behaviors.......... 11
2.2.6 EMC radiated emissions operating behaviors...16
2.2.7 Designing with radiated emissions in mind....... 17
2.2.8 Capacitance attributes...................................... 17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications............................... 17
2.3.2 General switching specifications....................... 18
2.4 Thermal specifications.....................................................19
2.4.1 Thermal operating requirements....................... 19
2.4.2 Thermal attributes............................................. 20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 Debug trace timing specifications..................... 21
3.1.2 JTAG electricals................................................ 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG specifications........................................... 25
3.3.2 IRC48M specifications...................................... 27
3.3.3 Oscillator electrical specifications..................... 28
3.3.4 32 kHz oscillator electrical characteristics.........30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash (FTFE) electrical specifications............... 31
3.4.2 EzPort switching specifications......................... 33
3.4.3 Flexbus switching specifications....................... 34
3.5 Security and integrity modules........................................ 37
3.6 Analog............................................................................. 37
3.6.1 ADC electrical specifications.............................38
3.6.2 CMP and 6-bit DAC electrical specifications.....42
3.6.3 12-bit DAC electrical characteristics................. 44
3.6.4 Voltage reference electrical specifications........ 47
3.7 Timers..............................................................................48
3.8 Communication interfaces............................................... 48
3.8.1 USB electrical specifications............................. 49
3.8.2 USB DCD electrical specifications.................... 49
3.8.3 USB VREG electrical specifications..................49
3.8.4 CAN switching specifications............................ 50
3.8.5 DSPI switching specifications (limited voltage
range)................................................................50
3.8.6 DSPI switching specifications (full voltage
range)................................................................52
3.8.7 Inter-Integrated Circuit Interface (I2C) timing....54
3.8.8 UART switching specifications.......................... 55
3.8.9 SDHC specifications......................................... 56
3.8.10 I2S switching specifications.............................. 56
4 Dimensions............................................................................. 62
4.1 Obtaining package dimensions....................................... 62
5 Pinout......................................................................................63
5.1 K24 Signal Multiplexing and Pin Assignments.................63
5.2 Unused analog interfaces................................................69
5.3 K24 Pinouts..................................................................... 70
6 Ordering parts......................................................................... 73
6.1 Determining valid orderable parts....................................73
7 Part identification.....................................................................74
7.1 Description.......................................................................74
7.2 Format............................................................................. 74
7.3 Fields............................................................................... 74
7.4 Example...........................................................................75
8 Terminology and guidelines.................................................... 75
8.1 Definitions........................................................................75
8.2 Examples.........................................................................76
8.3 Typical-value conditions.................................................. 76
8.4 Relationship between ratings and operating
requirements....................................................................77
8.5 Guidelines for ratings and operating requirements..........77
9 Revision History...................................................................... 78
4Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free 260 °C 2
Solder temperature, leaded 245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level 3 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
-500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Ratings
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 5
NXP Semiconductors
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current 185 mA
VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V
VDRTC_WAKEU
P
RTC Wakeup input voltage –0.3 VBAT + 0.3 V
VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB0_DP USB0_DP input voltage –0.3 3.63 V
VUSB0_DM USB0_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
General
6Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
V
V
VIL Input low voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD V
IICDIO Digital pin negative DC injection current — single pin
VIN < VSS-0.3V -5 mA
1
IICAIO Analog2, EXTAL, and XTAL pin DC injection current
— single pin
VIN < VSS-0.3V (Negative current injection)
VIN > VDD+0.3V (Positive current injection)
-5
+5
mA
3
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection
-25
+25
mA
VODPU Open drain pullup voltage level VDD VDD V4
VRAM VDD voltage required to retain RAM 1.2 V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT V
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-
VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative
injection currents.
4. Open drain outputs must be pulled to VDD.
General
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 7
NXP Semiconductors
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
80 mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
60 mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — high drive strength
Table continues on the next page...
General
8Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
V
V
Output high voltage — low drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
V
V
IOHT Output high current total for all ports 100 mA
VOH_RTC_WA
KEUP
Output high voltage — high drive strength
2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
VBAT – 0.5
VBAT – 0.5
V
V
Output high voltage — low drive strength
2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
VBAT – 0.5
VBAT – 0.5
V
V
IOH_RTC_WAK
EUP
Output high current total for RTC_WAKEUP pins 100 mA
VOL Output low voltage — high drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
0.5
0.5
V
V
Output low voltage — low drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
0.5
0.5
V
V
IOLT Output low current total for all ports 100 mA
VOL_RTC_WA
KEUP
Output low voltage — high drive strength
2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
0.5
0.5
V
V
Output low voltage — low drive strength
2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
0.5
0.5
V
V
IOL_RTC_WAK
EUP
Output low current total for RTC_WAKEUP pins 100 mA
IIN Input leakage current (per pin) for full temperature
range
1 μA 1
IIN Input leakage current (per pin) at 25°C 0.025 μA 1
IIN_RTC_WAK
EUP
Input leakage current (per RTC_WAKEUP pin) for full
temperature range
1 μA
IIN_RTC_WAK
EUP
Input leakage current (per RTC_WAKEUP pin) at
25°C
0.025 μA
Table continues on the next page...
General
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 9
NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
IOZ Hi-Z (off-state) leakage current (per pin) 0.25 μA
IOZ_RTC_WAK
EUP
Hi-Z (off-state) leakage current (per RTC_WAKEUP
pin)
0.25 μA
RPU Internal pullup resistors (except RTC_WAKEUP pins) 20 50 2
RPD Internal pulldown resistors (except RTC_WAKEUP
pins)
20 50 3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSxRUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
300 μs
VLLS0 RUN 156 μs
VLLS1 RUN 156 μs
VLLS2 RUN 78 μs
VLLS3 RUN 78 μs
LLS RUN 4.8 μs
VLPS RUN 4.5 μs
STOP RUN 4.5 μs
General
10 Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard
deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V
@ 3.0V
31.1
31
36.65
36.75
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
@ 3.0V
@ 25°C
@ 105°C
42.7
40
48.33
48.35
41.60
51.50
mA
mA
mA
3, 4
IDD_WAIT Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
17.9 mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
6.9 mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
1.0 mA 6
IDD_VLPR Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
1.7 mA 7
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
0.678 mA 8
IDD_STOP Stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.49
1.18
3.0
1.24
4.3
12.5
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
57
291
927.3
139.31
679.33
1869.85
μA
μA
μA
IDD_LLS Low leakage stop mode current at 3.0 V 9
Table continues on the next page...
General
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 11
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
@ –40 to 25°C
@ 70°C
@ 105°C
5.8
26.7
114.9
10.48
47.99
196.49
μA
μA
μA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
4.4
21
90.2
5.54
36.46
150.17
μA
μA
μA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
2.1
6.84
29.4
2.34
10.36
46.74
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.817
3.97
21.3
0.86
5.77
33.99
μA
μA
μA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
@ –40 to 25°C
@ 70°C
@ 105°C
0.52
3.67
21.20
0.62
5.7
34.9
μA
μA
μA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
@ –40 to 25°C
@ 70°C
@ 105°C
0.339
3.36
20.3
0.412
4.2
29.9
μA
μA
μA
IDD_VBAT Average current with RTC and 32 kHz disabled
@ 1.8 V
@ –40 to 25°C
@ 70°C
@ 105°C
@ 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.16
0.55
2.5
0.18
0.66
2.92
0.19
0.72
3.68
0.21
0.86
4.30
μA
μA
μA
μA
μA
μA
Table continues on the next page...
General
12 Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VBAT Average current when CPU is not accessing
RTC registers
@ 1.8 V
@ –40 to 25°C
@ 70°C
@ 105°C
@ 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.59
1.0
3.0
0.71
1.22
3.5
0.70
1.30
4.42
0.84
1.59
5.15
μA
μA
μA
μA
μA
μA
10
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 Mhz FlexBus clock, and 20 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus clock, 30 MHz Flexbus clock, and 20 MHz flash clock. MCG configured
for PEE mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Data reflects devices with 256 KB of RAM.
10. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 228 237 245 251 258 uA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
Table continues on the next page...
General
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 13
NXP Semiconductors
Table 7. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
VLPS
STOP
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
nA
I48MIRC 48 Mhz internal reference clock 350 350 350 350 350 350 µA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42 42 42 42 42 42 µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
General
14 Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
Run Mode Current Consumption vs Core Frequency
All Peripheral Clk Gates
ALLOFF
ALLON
Clk Ratio
Core-Bus-
Flaxbus-Flash
Core Freq (MHz)
Current Consumption on VDD (A)
40.00E-03
000.00E+00
10.00E-03
15.00E-03
20.00E-03
25.00E-03
30.00E-03
35.00E-03
5.00E-03
'1-1-1
1
'1-1-1
2
'1-1-1
4
'1-1-1
6.25
'1-1-1
12.5
'1-1-1
25
'1-2-3
75
'1-1-2
50
'1-2-4
100
'1-2-5
120
Figure 3. Run mode supply current vs. core frequency
General
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 15
NXP Semiconductors
Current Consumption on VDD (A)
All Peripheral Clk Gates
ALLOFF
ALLON
Clk Ratio
Core-Bus-Flash
Core Freq (MHz)
Very Low Power Run (VLPR) Current vs Core Frequency
1.40E-03
'1-1-1'1-1-2
1
'1-1-2'1-1-4'1-2-4
2
'1-1-4'1-2-4
4
000.00E+00
200.00E-06
400.00E-06
600.00E-06
800.00E-06
1.00E-03
1.20E-03
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol Description Frequency
band
(MHz)
Typ. Unit Notes
144 LQFP
VRE1 Radiated emissions voltage, band 1 0.15–50 16 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 22 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 21 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 16 dBμV
VRE_IEC IEC level 0.15–1000 L 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
General
16 Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins 7 pF
CIN_D Input capacitance: digital pins 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock 120 MHz
System and core clock when Full Speed USB in
operation
20 MHz
fBUS Bus clock 60 MHz
FB_CLK FlexBus clock 50 MHz
fFLASH Flash clock 25 MHz
fLPTMR LPTMR clock 25 MHz
VLPR mode1
fSYS System and core clock 4 MHz
Table continues on the next page...
General
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 17
NXP Semiconductors
Table 10. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fBUS Bus clock 4 MHz
FB_CLK FlexBus clock 4 MHz
fFLASH Flash clock 0.8 MHz
fERCLK External reference clock 16 MHz
fLPTMR_pin LPTMR clock 25 MHz
fLPTMR_ERCLK LPTMR external reference clock 16 MHz
fFlexCAN_ERCLK FlexCAN external reference clock 8 MHz
fI2S_MCLK I2S master clock 12.5 MHz
fI2S_BCLK I2S bit clock 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, timers, and I2C signals.
Table 11. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50 ns 3
External reset pulse width (digital glitch filter disabled) 100 ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 Bus clock
cycles
Port rise and fall time (high drive strength) - 3 V
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
8
6
18
12
ns
ns
ns
ns
4
Port rise and fall time (high drive strength) - 5 V
Slew disabled
4
Table continues on the next page...
General
18 Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
Table 11. General switching specifications (continued)
Symbol Description Min. Max. Unit Notes
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
6
4
24
14
ns
ns
ns
ns
Port rise and fall time (low drive strength) - 3 V
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
12
6
24
16
ns
ns
ns
ns
5
Port rise and fall time (low drive strength) - 5 V
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
17
10
36
20
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 25 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature1–40 105 °C
General
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016 19
NXP Semiconductors
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 13. Thermal attributes
Board type Symbol Description 144 LQFP 121 XFBGA 100 LQFP Unit Notes
Single-layer
(1s)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
51 33.3 51 °C/W 1
Four-layer
(2s2p)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
43 21.1 39 °C/W 1
Single-layer
(1s)
RθJMA Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
42 26.2 41 °C/W 1
Four-layer
(2s2p)
RθJMA Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
36 17.8 32 °C/W 1
RθJB Thermal
resistance,
junction to
board
30 16.3 24 °C/W 2
RθJC Thermal
resistance,
junction to
case
11 12 11 °C/W 3
ΨJT Thermal
characterizati
on parameter,
junction to
package top
outside center
(natural
convection)
2 0.2 2 °C/W 4
General
20 Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
NXP Semiconductors
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 14. Debug trace operating behaviors
Symbol Description Min. Max. Unit
Tcyc Clock period Frequency dependent MHz
Twl Low pulse width 2 ns
Twh High pulse width 2 ns
TrClock and data rise time 3 ns
TfClock and data fall time 3 ns
TsData setup 1.5 ns
ThData hold 1 ns
TRACECLK
Tr
Twh
Tf
Tcyc
Twl
Figure 5. TRACE_CLKOUT specifications
Peripheral operating requirements and behaviors
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