ACPM-7836-TR1 - Avago Technologies

Agilent ACPM-7836

CDMA1900 (PCS)

Power Amplifier Module

Data Sheet

Description

The ACPM-7836 is a fully matched

CDMA Power amplifier module.

Designed around Agilent Tech-

nologies’ new Enhancement Mode

pHEMT process, the ACPM-7836

offers premium performance in a

very small form factor. Fully

matched to 50 Ohms on the input

and output.

The amplifier has excellent ACPR

and efficiency performance at

max Pout and low quiescent

Features

• Operating frequency:

1850– 1910 MHz

• 28.5 dBm linear output power

@ 3.4V

• High efficiency: 40% PAE

• Dynamic bias control for low

midpower Idd

• Improved low power efficiency

with DC/DC converter

• Very low quiescent current with

single control voltage

• Internal 50 ohm matching networks

for both RF IN/OUT

• 3.2– 4.2 V linear operation

• cdma2000 1xRTT capable

• Only 3 SMT parts needed

• 4.0 x 4.0 x 1.1 mm SMT package

Applications

• CDMA handsets

• Datacards

• PDAs

Input

Vdd1

Power

Input

Match

On Chip

Inter-stage

Match

Bias Circuit

Passive

Output

Match

Vdd2

Vbias

Output

Vcntl

Single control bias setting for low Idq

and 40% PAE at Pout = 28.5 dBm

current with a single bias control

voltage. For even lower quiescent

current, a dynamic bias control

circuit can be used by varying

the voltage on the Vcntl pin

between 1.2V to 2.5V.

Designed in a surface mount RF

package, the ACPM-7836 is cost

and size competitive.

The ACPM-7836 is another key

component of the Agilent

CDMAdvantage RF chipset.

Maximum Ratings[1]

Parameter Min. Max.

Vdd Supply Voltage 6.0 V

Power Dissipation[2] 2.5 W

Bias Current 1.5 A

Control Voltage (Vcntl) 3.0 V

Amplifier Input RF Power 10 dBm

Junction Temperature +150°C

Storage Temperature (case temperature) -40°C +100°C

Notes:

1. Operation of this device in excess of any of these limits may cause permanent damage.

2. Tcase = 25°C

Thermal Resistance[2] θjc = 22.3°C/W

Recommended operating range of Vdd = 3.2 to

4.2 V, Ta = -30 to +85°C

Package Marking and Dimensions

Vdd2

(Pin 10)

Gnd

RFout

Gnd

1.1 mm

4.0 mm (sq)

Vdd1 (Pin 1)

RFin

Gnd

Vcntl

Vbias

Gnd

Agilent

ACPM-7836

YYWWDD

XXXX

0.400±0.076

0.850±0.076

2.000±0.076

3.80±0.076

4.000±0.076

3.400±0.076

2.000±0.076

4.000±0.076

1.100±0.076

Note:

YYWWDD: year – work week – day

XXXX: lot code

All units are in mm

Top View Side View Bottom View

Electrical Characterization Information

All tests are done in 50Ω system at Vdd1=Vdd2=Vbias = 3.4V, 25°C, unless noted otherwise.

Parameter Units Min Typ Max Comments

PCS CDMA

Frequency Range MHz 1850 1910

Gain (Fixed Cntl Voltage)

Pout = 28.5 dBm dB 25.5 27.5 29.5 Vcntl= 2.5V

Pout = 16 dBm 24 26 28 Vcntl= 1.8V

Power Added Efficiency

Pout = 28.5 dBm % 38 40 Vcntl= 2.5V

Pout = 16 dBm % 7.5 8.5 Vcntl= 1.8V

Total Supply Current mA 520 550 Pout = 28.5 dBm, Vcntl= 2.5V

mA 135 156 Pout =16 dBm, Vcntl= 1.8V

mA 31 Pout = -5 dBm, Vcntl = 1.2V

ACPR @ ± 1.25 MHz offset dBc/30 kHz -45 -48 Pout ≤ 28.5 dBm

ACPR @ ± 1.98 MHz offset dBc/30 kHz -53 -55 Pout ≤ 28.5 dBm

Quiescent Current mA 62 80 Pout ≤ 28.5 dBm, Vcntl= 2.5V

mA 47 60 Vcntl = 1.8V

mA 25 Vcntl = 1.2V

Vcntl Current mA 2.0 2.7 Vcntl = 2.5V

Input VSWR (Pout = 28.5 dBm) 2.0:1

Noise Figure dB 4.5

Noise Power @ 80 MHz offset in 1930–1990 MHz dBm/Hz -141 -138

Stability (Spurious): Load VSWR 5:1 dBc -50 All phases

Harmonic Suppression: 2Fo dBc -30 -38

Typical Performance, data measured in 50Ω system, Vdd1=Vdd2=Vbias = 3.4V, Vcntl = 2.5V, T = 25°C and Freq = 1880 MHz unless

noted otherwise.

Pout (dBm)

Figure 1. Gain vs. Pout.

GAIN (dB)

Vcntl (V)

Figure 2. Gain vs. Vcntl.

GAIN (dB)

Pout (dBm)

PAE (%)

Pout (dBm)

Figure 4. Idd vs. Output Power.

Idd (mA)

Pout (dBm)

Figure 5. Idd vs. Output Power.

Idd (mA)

Pout (dBm)

Figure 6. ACPR (1.25 MHz offset) vs. Pout.

ACPR1 (dBc)

Pout (dBm)

ACPR2 (dBc)

Pout (dBm)

Figure 8. 2nd/3rd Harmonics vs. Pout.

HARMONIC SUPPRESSION (dBc)

030105 15 2520

-50

-55

-60

-65

-70

-75

-80

-85

-90

2nd

3rd

030105152520

0 2.80.80.4 1.2 2.0 2.41.6

-20

-40

030105 15 2520

500

400

300

200

100

002010515

160

140

120

100

030105152520

-40

-45

-50

-55

-60

-65

10 302015 25

-30

-35

-40

-45

-50

Figure 3. PAE vs. Pout.

Figure 7. ACPR (1.98 MHz offset) vs. Pout.

Vcntl=2.5V

Vcntl=1.6V

Vcntl=1.2V

Vcntl=2.5V

Vcntl=1.6V

Vcntl=1.2V Vcntl=1.2V

Vcntl=1.6V

Vcntl=2.5V

Ordering Information

Part Number No. of Devices Container

ACPM-7836-BLK 10 Bulk

ACPM-7836-TR1 1000 7” Tape and Reel

Tape Dimensions and Orientation

φ1.55 ± 0.05

φ1.50 (MIN)

4.38 ± 0.10

1.80 ± 0.10

4.38 ± 0.10

8.00 ± 0.10 4.38 ± 0.10

2.00 ± 0.05

[1]

4.00 ± 0.10

[2]

5.50 ± 0.05

[3]

12.00 ± 0.3

1.75 ± 0.10

0.30 ± 0.05

Notes:

1. Measured from centerline of sprocket hole to centerline of pocket

2. Cumulative tolerance of 10 sprocket holes is ±0.2 mm

3. All dimensions in millimeters unless otherwise stated.

Agilent

ACPM-7836

YYWWDD

XXXX

Reel Drawing

NOTES:

1. Reel shall be labeled with the following

information (as a minimum).

a. manufacturers name or symbol

b. Agilent Technologies part number

c. purchase order number

d. date code

e. quantity of units

2. A certificate of compliance (c of c) shall

be issued and accompany each shipment

of product.

3. Reel must not be made with or contain

ozone depleting materials.

4. All dimensions in millimeters (mm)

50 min.

12.4 +2.0

–0.0

18.4 max.

min wide (ref)

Slot for carrier tape

insertion for attachment

to reel hub (2 places 180° apart)

BACK VIEW

FRONT VIEW

178

Shading indicates

thru slots

+0.4

–0.2

21.0±0.8

13.0±0.2

1.5 min.

Application Information

The following material is presented to assist in general design and use of the APCM-7836.

•Use of ACPM-7836 with a DC/DC converter

•3.0V Characterization, for use in Data Card Applications

•cdma2000 1XRTT Description and Characterization data

•Design tips on various methods to control the bias on Vcntl pin

•Description of ACPR measurement methods

•Description of Agilent evaluation demoboard for ACPM-7836

•IR Reflow Profile (applicable for all Agilent E-pHEMT PAs)

CDMA Power Amplifier Efficiency

Improvement with a DC-DC Converter

Efficiency of power amplifier for

wireless communication systems

is a critical requirement for

prolonging battery life. One

method to boost PA efficiency at

medium output power

(14~16 dBm Pout) is to use a

DC-DC Converter, which helps to

control the bias voltage of Power

Amplifier. This type of solution is

described below using the

Agilent ACPM-7836, 4x4 CDMA

PA, and commercially available

DC-DC converter.

ACPM-7836 Features

•4.0 x 4.0 x 1.1 mm SMT sized

1900 MHz(PCS) single band PA

•High efficiency: 40% PAE

•Dynamic bias control for low

medium power Idd

•CDMA2000 1xRTT capable

DC-DC Converter Features

•2.6V to 5.5V Input Voltage Range

•1 MHz Fixed Frequency PWM

Switching

•600 mA (min) Output Current

•Adjustable Output Voltages (Scaled

by a Reference Input Voltage to

supply output voltages from

0.75V to 3.4V)

•Low 0.1 µA (typ) Quiescent current

in shutdown mode

Reference voltage

BATT

=3.4V

Pout

Vcntl voltage

Vbias

Vcntl

Vdd1

Vdd2

ACPM-7836

BATTLX

OUT

REF

REFIN

DC/DC

Converter

4.7µH

2.2µF

Vout=1V ~3.2V, 600 mA

Test Setup Block Diagram

Figure 9. Test Setup with Agilent PA and DC-DC Converter.

Operational Instructions

1) Connect 3.4V supply to the VBATT pin on the DC/DC Converter.

2) Connect input to the reference voltage pin on DC/DC converter.

The input range on the reference voltage will determine the bias

levels on the PA, depending on scaling factor of DC/DC converter.

3) Connect 3.4V supply to the Vbias pin.

4) Set voltage on Vcntl pin (typically 2.5V for normal operation and

0V for shutdown).

5) Vdd1 and Vdd2 pins should be connected to the Vout pin from

DC-DC Converter.

6) Details for external component values associated with the DC/DC

converter can be obtained from the support material of DC/DC

vendor.

Figure 10. PAE and Vdd1_2 vs. Pout.

Pout (dBm)

PAE

(%)

Vdd1_2_Var

(V)

-20 25-15 -10 -5 0 5 10 15 20

4.5

3.5

2.5

1.5

0.5

Vdd1 & Vdd2

1880 MHz, -30°C

1880 MHz, +25°C

1880 MHz, +85°C

Figure 11. PAE and Vdd1_2 vs. Pout

(Low/Mid Values).

Pout (dBm)

PAE

(%)

0205 10 15

1.5

1.4

1.3

1.2

1.1

0.9

0.8

Vdd1_2_Var

(V)

Vdd1 & Vdd2

1880 MHz, -30°C

1880 MHz, +25°C

1880 MHz, +85°C

Figure 12. Gain and Vdd1_2 vs. Pout.

Pout (dBm)

GAIN

(dB)

-20 25-15 -10 -5 0 5 10 15 20

Vdd1_2_Var

(V)

Vdd1 & Vdd2

1880 MHz, -30°C

1880 MHz, +25°C

1880 MHz, +85°C

Figure 13. Idd and Vdd1_2 vs. Pout.

Pout (dBm)

Idd

(mA)

Vdd1_2

(V)

-20 25-15 -10 -5 0 5 10 15 20

500

450

400

350

300

250

200

150

100

Vdd1 & Vdd2

1880 MHz, -30°C

1880 MHz, +25°C

1880 MHz, +85°C

Vdd1_2

(V)

Figure 14. Idd and Vdd1_2 vs. Pout

(Low/Mid Values).

Pout (dBm)

Idd

(mA)

-20 20-15 -10 -5 0 5 10 15

120

100

2.0

1.8

1.6

1.4

1.2

1.0

0.8

Vdd1 & Vdd2

1880 MHz, -30°C

1880 MHz, +25°C

1880 MHz, +85°C

Vdd1_2_Var

(V)

Figure 15. ACPR1 (-885 kHz offset) and

Vdd1_2 vs. Pout.

Pout (dBm)

ACPR1

(

dBc

)

0 5 10 15 20 25

-40

-45

-50

-55

-60

-65

4.5

3.5

2.5

1.5

0.5

Vdd1 & Vdd2

1880 MHz, -30°C

1880 MHz, +25°C

1880 MHz, +85°C

Figure 16. ACPR2 (-1.98 MHz offset) and

Vdd1_2 vs. Pout.

Pout (dBm)

ACPR2

(

dBc

)

0 5 10 15 20 25

-50

-55

-60

-65

-70

-75

-80

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Vdd1_2_Var

(V)

Vdd1 & Vdd2

836.5 MHz, -30°C

836.5 MHz, +25°C

836.5 MHz, +85°C

Test Results: ACPM-7836 PCS band PA and DC-DC Converter

Test condition: Vdd1 = Vdd2 = 1.0V ~ 3.4V, 0.2Vstep

Vbias = 3.4V

Vcntl = 2.5V

Pout = -20 dBm ~ +28.5 dBm

Frequency = 1880 MHz

Temperature = +85°C, +25°C and -30°C

3.0 V Characterization, Data Card Applications

Electrical Data

All tests are done in 50Ω system at Vdd1=Vdd2=Vbias = 3.0V, 25°C, unless noted otherwise.

Parameter Units Min Typ Max Comments

1900 MHz CDMA

Frequency Range MHz 1850 1910

Gain (Fixed Cntl Voltage)

(Pout = 28.5 dBm) dB 26 Vcntl = 2.5V

(Pout = 13 dBm) dB 28 Vcntl = 2.5V

(Pout = -5 dBm) dB 28 Vcntl = 2.5V

Power Added Efficiency

Pout = 28.0 dBm % 42 Vcntl = 2.5V

Pout = 16 dBm % 8.5 Vcntl = 2.5V

Total Supply Current mA 500 Pout = 28.0 dBm, Vcntl= 2.5V

100 Pout = 13 dBm, Vcntl= 1.6V

30 Pout = -5 dBm, Vcntl= 1.2V

ACPR @ ± 1.25 MHz offset dBc/30 kHz -43 Pout ≤ 28.5 dBm

ACPR @ ± 1.98 MHz offset dBc/30 kHz -56 Pout ≤ 28.5 dBm

Quiescent Current mA 60 Pout ≤ 28.5 dBm, Vcntl = 2.5V

Input VSWR

(Pout = 28.5 dBm) 2.0:1

(Pout = 16 dBm) 2.5:1

Noise Figure dB 4.5

Noise Power @ 80 MHz offset in 1930 - 1990 MHz dBm/Hz -141

Stability (Spurious): Load VSWR 5:1 dBc -50 All phases

Harmonic Suppression

2Fo dBc -40

3Fo dBc -40

Typical Performance, data measured in 50Ω system, Vdd1=Vdd2=Vbias = 3.0V, Vcntl = 2.5V, T = 25°C and Freq =1880 MHz.

Figure 19. Idd vs. Pout.

Pout (dBm)

Figure 20. ACPR (1.25 MHz offset) vs. Pout.

ACPR1 (dBc)

Pout (dBm)

Figure 21. ACPR (1.98 MHz offset) vs. Pout.

ACPR2 (dBc)

Pout (dBm)

Figure 22. Harmonic Suppression vs. Pout.

HARMONIC SUPPRESSION (dBc)

Vcntl (V)

Figure 23. Gain vs. Vcntl.

GAIN (dB)

030105 15 2520

-50

-55

-60

-65

-70

-75

-80

-85

-90

Pout (dBm)

Figure 17. Gain vs. Pout.

GAIN (dB)

030105 15 2520

Pout (dBm)

Figure 18. PAE vs. Pout.

PAE (%)

030105 15 2520

Pout (dBm)

Idd (mA)

030105 15 2520

500

400

300

200

100

030105 15 2520

-40

-45

-50

-55

-60

-65

10 302015 25

-30

-35

-40

-45

-50

2nd

3rd

0 2.80.80.4 1.2 2.0 2.41.6

-20

-40

cdma 2000 1xRTT Characterization

System Description

CDMA2000 is the TIA’s standard

for third generation (3G) technol-

ogy and is an evolution of the IS-

95 CDMA format. CDMA2000

includes 1X RTT in the single-

carrier mode and 3X RTT in the

multi-carrier mode. This paper

describes the CDMA2000 1X RTT

approach and its performance

with Agilent 4x4 CDMA PAs,

ACPM-7836. CDMA2000 1X RTT,

being an extension of the IS-95

standard, has a chip rate of

1.2288Mchip/s. However, in

1xRTT, the reverse link transmits

more than one code channel to

accommodate the high data

rates. The minimum configura-

tion consists of a reverse pilot

(R-Pilot) channel for synchro-

nous detection by the Base

Transceiver System (BTS) and a

reverse fundamental channel

(R-FCH) for voice. Additional

channels such as the reverse

supplemental channels (R-SCHs)

and the reverse dedicated

channel (R-DCCH) are used to

send data or signaling informa-

tion. Channels can exist at

different rates and power levels.

Table 1 shows the transmitter

specification in CDMA2000

reverse link.

Typical channel configurations below are based on the transmitter test condition in the reverse link.

1) “Basic” Voice only configuration

–R-PICH @ -5.3 dB

–R-FCH @ -1.5 dB 9.6 kbps

2) Voice and Data configuration

–R-PICH @ -5.3 dB

–R-FCH @ -4.54 dB 9.6 kbps

–R-SCH1 @ -4.54 dB 9.6 kbps

Specification Spread Rate1

ERP at Maximum Output Power Lower limit +23 dBm

Upper limit +30 dBm

Minimum Controlled Output Power -50 dBm/1.23 MHz

Waveform Quality Factor and Frequency Accuracy >0.944

SR1, Band Class 0(Cellular band) SR1, Band Class1(PCS band)

885 kHz to 1.98 MHz 1.25 MHz to 1.98 MHz

Less stringent of -42 dBc/30 kHz Less stringent of -42 dBc/30 kHz

or -54 dBm/1.23 MHz or -54 dBm/1.23 MHz

1.98 MHz to 3.125 MHz 1.98 MHz to 2.25 MHz

Less stringent of -54 dBc/30 kHz Less stringent of -50 dBc/30 kHz

or -54 dBm/1.23 MHz or -54 dBm/1.23 MHz

3.125 MHz to 5.625 MHz 2.25 MHz to 6.25 MHz

-13 dBm/100 kHz -13 dBm/1 MHz

Spurious Emission at

Maximum RF output

power offset frequency

within the range

Table 1. Transmitter Specification in Reverse Link.

3) Voice and Control configuration

–R-PICH @ -5.3 dB

–R-FCH @ -3.85 dB 9.6 kbps

–R-DCCH @ -3.85 dB 9.6 kbps

4) Control channel only configuration

–R-PICH @ -5.3 dB

–R-DCCH @ -1.5 dB 9.6 kbps

Combinations of these channels

will increase the peak to average

power ratio for higher data rates.

The complementary cumulative

distribution function (CCDF)

measurement characterizes the

peak to average power statistics

of CDMA2000 reverse link. For

reference, the system specifica-

tions of peak to average power

ratio of IS-95 and CDMA2000 IX

RTT are 3.9 dB and 5.4 dB at

1% CCDF respectively.

Higher peak to average power

ratio requires a higher margin,

both in higher power gain and in

improved thermal stability for PA

linearity to meet the minimum

system specifications.

The test results below for the

ACPM-7836 show the compliance

to the system linearity specifica-

tions with 4 channel configura-

tions, representing a broad cross-

section of CDMA2000 1X RTT

environments.

Test result of ACPM-7836 using CDMA2000 1X RTT signal

Test condition - PA Evaluation board with Vdd1=Vdd2=Vbias = 3.4V, Vcntl = 2.5V, Frequency = 1880 MHz. Test result with each channel configuration.

1.25 MHz 1.25 MHz -1.98 MHz +1.98 MHz

Channel IVdd(mA) Pin(dBm) ACPR(dBc) ACPR(dBc) ACPR(dBc) ACPR(dBc) Pout(dBm)

Basic 451.0 -0.14 -52.6 -51.5 -60.2 -60 28

Voice+Data 435.0 0.52 -46.2 -45.7 -58.0 -58.3 28

Voice+Cntl 439.0 0.50 -45.5 -44.9 -60.1 -60 28

Cntl only 299.0 -2.56 -49.1 -48.8 -57.7 -57.5 25.5

Peak to average power ration (Pout = 16 dBm)

CCDF(%) Basic Voice + Data Voice + CNTL CNTL only

10 2.11 3.37 3.44 4.00

1 3.74 4.83 5.21 5.75

0.1 4.68 5.68 6.24 6.73

0.01 5.15 6.20 6.76 7.18

0.001 5.36 6.53 7.11 7.39

0.0001 5.48 6.63 7.17 7.45

EIA/TIA-98-D indicates a 2.5 dB allowed back off in power for control channel only configuration.

Design Tips to use Vcntl pin

Power Mode PA_ON Vcntl Power Range

Shut Down LOW 0V —

High Power HIGH 2.5V ≤ 28.5 dBm

To Duplexer

Battery

Vcntl

TxIC

Switch Circuit for PA

Baseband

PA_ON

Enable

Vdd1

Vdd2

Vbias

Vcntl

PMIC or LDO Note: PMIC: Power Management IC

LDO: Low Drop Output (Regulator)

Power Amplifier Control Using Vcntl

Pin on ACPM-7836

Power amplifier control scheme

in CDMA systems is one of the

important and challenging

aspects of CDMA-based handset

design. Handset designers must

balance maintaining adequate

linearity while optimizing

efficiency at high, medium and

low output power levels. The

primary method to achieve these

goals is to adjust the bias of the

PA as a function of output power.

Theoretically, the best efficiency

would be achieved when the bias

of the PA is continually adjusted

based on the output power

requirement of the PA. However,

implementing this type of circuit

can be complex and costly.

Therefore several different

approaches have been developed

to provide an acceptable trade-

off between optimum efficiency

and optimum manufacturability.

This application section reviews

four methods of controlling the

bias of a CDMA power amplifier:

fixed, step, logical and dynamic.

1. Fixed Bias Control

Using a fixed bias point on the

PA is the traditional method, and

it is the simplest. For example,

the recommended value of the

fixed control voltage on the Vcntl

pin for the ACPM-7836 is 2.5V.

The Vcntl pin on the PA is con-

trolled by PA_ON pin of the

baseband IC. When PA_ON is

HIGH, the output RF signal of the

PA is enabled, enabling the

subscriber unit to transmit the

required data. The switch circuit

also controls the on/off state of

the PA.

Below is an example of how to

control the the output of the PA

using PA_ON and Vcntl pins.

2. Step Bias Control and Dynamic

Bias Control (if controled PDM1)

The PDM1 output from the

baseband IC can be used to

create a software-programmable

voltage, to be used at the phone

designer’s discretion. To get high

efficiency and better ACPR, the

phone designers can change

control voltage of the PA by

adjusting PDM1 voltage accord-

ing to output power of PA. A

caution when using this

Power Mode PA_ON Vcntl Power Range

Shut Down LOW 0V —

Low Power HIGH 1.2V ~ -5 dBm

Mid Power HIGH 1.6V -5 dBm ~ 13 dBm

High Power HIGH 2.5V 13 dBm ~ 28.5 dBm

approach—careful consideration

must be made to to avoid an

abrupt discontinuity in the

output signal when the step bias

control voltage is applied.

The figure below is an example of

how to control the PA for

multiple bias points using the

PA_ON and Vcntl pins.

To Duplexer

Battery

Vdd1

Vdd2

Vcntl

TxIC

Switch Circuit for PA

Baseband

PA_ON

PDM1

Vbias

Enable

If PDM1 can be controlled then same circuit can be used for Dynamic bias control

3. Dynamic Bias Control Alternate

Implementation

Phone designers can use

TX_ADC_ADJ pin of the

baseband IC to get dynamic bias

control with Vcntl pin of PA.

TX_ADC_ADJ is a PDM output

pin produced by the TX AGC

subsystem and used to control

the gain of the Tx signal prior to

the PA. The variable output levels

from two inverting operational

amplifiers, generated and

compared by TX_ADC_ADJ,

provide dynamic control voltages

for the Vcntl of 1.0V ~ 2.7V with

a 0.1V step.

Av = -(V1/Vin) = -R3/R2,

V1 = -(R3/R2)Vin,

Vo = -(R5/R4)V1= [(R5*R3)/(R4*R2)]*Vin

The using of combination of two

pins, PDM1 and TX_ADC_ADJ, is

another method of realizing a

dynamic bias control scheme.

The two OP Amps control the

Vcntl voltage levels with com-

pared and integrated circuits.

To Duplexer

Battery

R2 Vin C1

PA_ON

TX_ADC_ADJ

Baseband IC

TxIC

Vcontrol

Switch Circuit

Enable

Vdd1

Vdd2

Vcntl

Vbias

To Duplexer

Battery

PA_ON

TX_ADC_ADJ

PDM1

Baseband IC

TxIC

Vcontrol

Switch Circuit

Enable

Vdd1

Vdd2

Vcntl

Vbias

ACPR Measurement Method

Adjacent-channel power ratio

(ACPR) is used to characterize

the distortion of power amplifiers

and other subsystems for their

tendency to cause interference

with neighboring radio channels

or systems. The ACPR measure-

ment often is specified as the

ratio of the power spectral

density (PSD) of the CDMA main

channel to the PSD measured at

Figure 24. CDMA Adjacent-Channel Power Ratio Measurement.

several offset frequencies. For the

Cellular band (824 ~ 849 MHz

transmitter channel), the two

offsets are at ±885 kHz and

±1.98 MHz and the measurement

resolution bandwidth specified is

30 kHz. These offsets are at

±1.25 MHz and ±1.98 MHz for the

PCS band (1850 ~ 1910 MHz

transmitter channel).

-10

-20

-30

-40

-50

-60

-70

-80

30 kHz

1.23 MHz

1st ACPR-U

1st ACPR-L

2nd ACPR-L

= 1.98 MHz

2nd ACPR-U

= 1.98 MHz

Offset frequency

1st ACPR (dBc)

2nd ACPR (dBc)

FREQUENCY (MHz)

ACPR Testing Diagram Test

PA Test Setup

Figure 25. ACPR test equipment setup.

Figure 26. ACPR measurement using VSA Transmitter tester.

ACPM-7836 Test Result using VSA Transmitter Tester

8593E

Spectrum

Analyzer

E4406A

VSA Transmitter

Tester

Power

Divider 20 dB

Attenuator

3 dB

Attenuator

CDMA PA

ACPM-7836

Vdd1

Vdd2

Vbias

Vcntl E4437B

CDMA Signal

Generator

DC Power Supply

CH1 CH2 CH3 CH4

ACPR Test Results using Spectrum Analyzer

The meaning of 16 dB

The accurate ACPR measurement

using Spectrum Analyzer needs

to consider the normalization

factor that is dependent on the

Resolution Bandwidth, RBW,

settings. The above figure (mea-

surement shown at 836 MHz for

general example) shows a com-

parison of the different ACPR

measurement results as a func-

tion of various RBW values. As

the RBW is reduced, less power is

captured during the measure-

ment and consequently the

channel power is recorded as a

Figure 27. Example ACPR measurement using Spectrum Analyzer.

smaller value. For example, if the

main channel power is measured

as 28 dBm in a 1.23 MHz band-

width, its power spectral density

is 28 dBm/1.23 MHz, which can

be normalized to 11.87 dBm/

30 kHz. The equation used to

calculate the normalization factor

of power spectral density is:

Normalization Factor =

10log[Normalization BW/Current BW

(Spectrum Analyzer RBW)]

= 10log[1.23X10

/30X10

]

= 16.13 dB

Since the ACPR in an IS95

system is specified in a 1.23 MHz

bandwidth, a channel power that

is measured using a different

RBW, can be normalized to

reflect the channel power as if it

was measured in a 1.23 MHz

bandwidth. The difference in

channel power measured in

30 kHz bandwidth and the

channel power measured in a

1.23 MHz bandwidth is 16 dB.

REF 42.8 dBm AT 30 dB

RBW = 1.0 MHz

RBW = 30 kHz

RBW = 300 kHz

Mkr 836 MHz

35.42 dBm

Center 836 MHz VBW 100 kHz Span 5.000 MHz

SWP 2.00 sec

ACPM-7836 Demoboard

Operation Instructions

1) Module Description

The ACPM-7836 is a fully matched

Power Amplifier. The sample

devices are provided on a demon-

stration PC Board with SMA

connectors for RF inputs and

outputs, and a DC connector for

all bias and control I/O’s. Please

refer to Figures 20 through 23 and

the Pin configuration table for I/O

descriptions and connections.

Figure 28. ACPM-7836 Evaluation Board Schematic and Layout.

Figure 29. Layer 1 – Top Metal & Solder Mask.

Vdd2 Vdd1

Vdd1

GND

RFin

Vbias

RFout

RF Out

GND

Vdd2

2.2 µF 4700 pF

RFin

Vcntl

GND

4700 pF

Vcntl

4700 pF

RF out

RF in

PCS

4x4 v2 C1 = 4700 pF

C2 = 4700 pF

C3 = 2.2 µF

C4 = 4700 pF

C5 = 4700 pF

GND

Vbias (f)

Vdd1 (f)

Vdd2 (f)

GND

Figure 30. Layer 2 – Ground.

Figure 31. Layer 3 – Bottom Metal & Solder Mask.

Top side Back side

1 GND 1b Vdd2 (s)

2 Vbias 2b GND

3 Vdd1 3b Vdd1 (s)

4 GND 4b Vcntl

5 Vdd2 5b Vbias (s)

PIN Configuration Table

2) Circuit Operation

The design of the power module

(PAM) provide bias control via

Vcntl to achieve optimal RF

performance and power control.

The control pin is labeled Vcntl.

Please refer to for the block

diagram of this PAM.

Typical Operation Conditions

(Vdd1=Vdd2=Vbias = 3.4V)

Parameter ACPM-7836

Frequency Range 1850 – 1910 MHz

Output Power 28.5 dBm

Vcntl 2.5 V

3) Maximum Ratings

Vdd 5.0V

Drain Current 1.5A

Vcntl 3V

RF input 10 dBm

Temperature -30 to 85°C

Please Note: Avoid Electrostatic Discharge

on all I/O’s.

4) Heat Sinking

The demonstration PC Board

provides an adequate heat sink.

Maximum device dissipation

should be kept below 2.5 Watts.

5) Testing

- Signal Source

The CDMA modulated signal for

the test is generated using an

Agilent ESG-D4000A (or ESG-

D3000A) Digital Signal Generator

with the following settings:

CDMA Setup : Reverse

Spreading: On

Bits/Symbol: 1

Data: PN15

Modulation: OQPSK

Chip Rate: 1.2288 Mcps

High Crest: On

Filter: Std

Phase Polarity: Invert

- ACPR Measurement

The ACPR (and channel power) is

measured using an Agilent 4406

VSA with corresponding ACPR

offsets for IS-98c and JSTD-8.

Averaging of 10 is used for ACPR

measurements.

- DC Connection

A DC connector is provided to

allow ease of connection to the

I/Os. Wires can be soldered to

the connector pins, or the

connector can be removed and

I/Os contacted via clip leads or

direct soldered connections. The

wiring of I/Os are listed in

Figures 20 through 23 and the

Pin configuration table. The Vdd

sense connections are provided

to allow the use of remote-

sensing power supplies of

compensation for PCB traces and

cable resistance.

- Device Operation

1) Connect RF Input and Output

for the band under test.

2) Terminate all unused RF

ports into 50 Ohms.

3) Connect Vdd1, Vdd2 and

Vdd3 supplies (including

remote sensing labeled

Vdd1 S, Vdd2 S and Vbias S

on the board). Nominal

voltage is 3.4V.

4) Connect Vcntl supply and set

reference voltage to the

voltage shown in the data

packet. Note that the Vcntl pin

is on the back side of the

demonstration board. Please

limit Vcntl to not exceed the

corresponding listed “DC

Biasing Condition” in the Data

Packet. Note that increasing

Vcntl over the corresponding

listed “DC Biasing Condition”

can result in power decrease

and current can exceed the

rated limit.

5) Apply RF input power accord-

ing to the values listed in

“Operation Data” in Data

Packet.

6) Power down in opposite

sequence.

Figure 32. Power Module Block Diagram.

Input

Vdd1

Passive

Input

Match

On Chip

Inter-stage

Match

Bias Circuit

Passive

Output

Match

Vdd2

Output

Vcntl

Single control bias setting for low Idq

and 40% PAE at Pout = 28.5 dBm

Vbias

IR Reflow Soldering

Figure 25 is a straight-line

representation of the recom-

mended nominal time-tempera-

ture profile from JESD22-A113-B

IR reflow.

Figure 33. Time-temperature Profile for IR Reflow Soldering Process.

Table 2. IR Reflow Process Zone.

Process Zone ∆Temperature ∆Temperature/∆Time

Preheat Zone 25°C to 100°C3°C/s MAX

Soak Zone 100°C to 150°C 0.5°C/s MAX (120s MAX)

Reflow Zone 150°C to 235°C (240°C MAX) 4.5°C/s TYP

235°C to 150°C -4.5°C/s TYP

Cooling Zone 150°C to 25°C-6°C/s MAX

Table 3. Classification Reflow Profiles.

Convection or IR/Convection

Average ramp-up rate (183°C to peak) 3°C/second max.

Preheat temperature 125 (± 25)°C 120 seconds max.

Temperature maintained above 183°C 60 – 150 seconds

Time within 5°C of actual peak temperature 10 – 20 seconds

Peak temperature range 220 +5/-0°C or 235 +5/-0°C

Ramp-down rate 6°C/second max.

Time 25°C to peak temperature 6 minutes max.

Note:

All temperatures measured refer to the package body surface.

TIME (seconds)

TEMPERATURE (°C)

150

100

200

183

235

60 9030 120 150 210180 270 300240

60 to 150s

above 183°C

Cooling

Zone

Reflow

Zone

Soak

Zone

Preheat

Zone

Zone 1 – Preheat Zone

The average heat up rate for

surface-mount component on

PCB shall be less than 3°C/

second to allow even heating for

both the component and PCB.

This ramp is maintained until it

reaches 100°C where flux

activation starts.

Zone 2 – Soak Zone

The flux is being activated here

to prepare for even and smooth

solder joint in subsequent zone.

The temperature ramp is kept

gradual to minimize thermal

mismatch between solder, PC

Board and components. Over-

ramp rate here can cause solder

splatter due to excessive oxida-

tion of paste.

Zone 3 – Reflow Zone

The third process zone is the

solder reflow zone. The tempera-

ture in this zone rises rapidly

from 183°C to peak temperature

of 235°C for the solder to trans-

form its phase from solid to

liquids. The dwell time at melting

point 183°C shall maintain at

between 60 to 150 seconds. Upon

the duration of 10-20 seconds at

peak temperature, it is then

cooled down rapidly to allow the

solder to freeze and form solid.

Extended duration above the

solder melting point can poten-

tially damage temperature

sensitive components and result

in excessive inter-metallic growth

that causes brittle solder joint,

weak and unreliable connections.

It can lead to unnecessary dam-

age to the PC Board and discol-

oration to component’s leads.

Zone 4 – Cooling Zone

The temperature ramp down rate

is 6°C/second maximum. It is

important to control the cooling

rate as fast as possible in order

to achieve the smaller grain size

for solder and increase fatigue

resistance of solder joint.

Solder Paste

The recommended solder paste is

type Sn6337A or Sn60Pb40A of

J-STD-006.

Note: Solder paste storage and shelf

life shall be in accordance with

manufacturer’s specifications.

Stencil or Screen

The solder paste may be depos-

ited onto PCB by either screen

printing, using a stencil or

syringe dispensing. The recom-

mended stencil thickness is in

accordance to JESD22-B102-C.

Nominal stencil thickness Component lead pitch

0.102 mm (0.004 in) Lead pitch less than 0.508 mm (0.020 in)

0.152 mm (0.006 in) 0.508 mm to 0.635 mm (0.02 in to 0.025 in)

0.203 mm (0.008 in) Lead pitch greater than 0.635 mm (0.025 in)

www.agilent.com/semiconductors

For product information and a complete list of

distributors, please go to our web site.

For technical assistance call:

Americas/Canada: +1 (800) 235-0312 or

(916) 788-6763

Europe: +49 (0) 6441 92460

China: 10800 650 0017

Hong Kong: (65) 6756 2394

India, Australia, New Zealand: (65) 6755 1939

Japan: (+81 3) 3335-8152(Domestic/International), or

0120-61-1280(Domestic Only)

Korea: (65) 6755 1989

Singapore, Malaysia, Vietnam, Thailand, Philippines,

Indonesia: (65) 6755 2044

Taiwan: (65) 6755 1843

Data subject to change.

November 16, 2004

5989-1895EN