NXP Semiconductors Data Sheet: Technical Data MC9S08PT16 Series Data Sheet Supports: MC9S08PT16(A) and MC9S08PT8(A) Key features * 8-Bit S08 central processor unit (CPU) - Up to 20 MHz bus at 2.7 V to 5.5 V across temperature range of -40 C to 105 C - Supporting up to 40 interrupt/reset sources - Supporting up to four-level nested interrupt - On-chip memory - Up to 16 KB flash read/program/erase over full operating voltage and temperature - Up to 256 byte EEPROM; 2-byte erase sector; program and erase while executing flash - Up to 2048 byte random-access memory (RAM) - Flash and RAM access protection * Power-saving modes - One low-power stop mode; reduced power wait mode - Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode * Clocks - Oscillator (XOSC) - loop-controlled Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz - Internal clock source (ICS) - containing a frequencylocked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allowing 1% deviation across temperature range of 0 C to 70 C and 2% deviation across the whole operating temperature; up to 20 MHz * System protection - Watchdog with independent clock source - Low-voltage detection with reset or interrupt; selectable trip points - Illegal opcode detection with reset - Illegal address detection with reset Document Number MC9S08PT16 Rev. 4, 03/2020 MC9S08PT16 MC9S08PT16A and MC9S08PT8A are recommended for new design * Development support - Single-wire background debug interface - Breakpoint capability to allow three breakpoints setting during in-circuit debugging - On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes * Peripherals - ACMP - one analog comparator with both positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering - ADC - 12-channel, 12-bit resolution; 2.5 s conversion time; data buffers with optional watermark; automatic compare function; internal bandgap reference channel; operation in stop mode; optional hardware trigger - CRC - programmable cyclic redundancy check module - FTM - two flex timer modulators modules including one 6-channel and one 2-channel ones; 16-bit counter; each channel can be configured for input capture, output compare, edge- or center-aligned PWM mode - IIC - One inter-integrated circuit module; up to 400 kbps; multi-master operation; programmable slave address; supporting broadcast mode and 10-bit addressing; supporting SMBUS and PMBUS - MTIM - One modulo timer with 8-bit prescaler and overflow interrupt - RTC - 16-bit real timer counter (RTC) - SCI - two serial communication interface (SCI/ UART) modules optional 13-bit break; full duplex non-return to zero (NRZ); LIN extension support - SPI - one 8-bit serial peripheral interface (SPI) modules; full-duplex or single-wire bidirectional; master or slave mode - TSI - supporting up to 16 external electrodes; configurable software or hardware scan trigger; fully support NXP touch sensing software library; capability to wake MCU from stop3 mode NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. * Input/Output - Up to 37 GPIOs including one output-only pin - One 8-bit keyboard interrupt module (KBI) - Two true open-drain output pins - Four, ultra-high current sink pins supporting 20 mA source/sink current * Package options - 44-pin LQFP - 32-pin LQFP - 20-pin SOIC; 20-pin TSSOP - 16-pin TSSOP MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 2 NXP Semiconductors Table of Contents 1 MCU block diagram...........................................................................4 6.2.2 Debug trace timing specifications................................18 2 Orderable part numbers......................................................................5 6.2.3 FTM module timing.....................................................19 3 Part identification............................................................................... 6 6.3 Thermal specifications...............................................................20 3.1 Description.................................................................................6 3.2 Format........................................................................................6 6.3.1 7 Thermal characteristics................................................ 20 Peripheral operating requirements and behaviors.............................. 21 3.3 Fields..........................................................................................6 7.1 External oscillator (XOSC) and ICS characteristics..................21 3.4 Example..................................................................................... 6 7.2 NVM specifications................................................................... 23 4 Parameter Classification.....................................................................7 7.3 Analog........................................................................................24 5 Ratings................................................................................................7 7.3.1 ADC characteristics..................................................... 24 5.1 Thermal handling ratings...........................................................7 7.3.2 Analog comparator (ACMP) electricals...................... 27 5.2 Moisture handling ratings.......................................................... 7 7.4 Communication interfaces......................................................... 27 5.3 ESD handling ratings.................................................................8 7.4.1 5.4 Voltage and current operating ratings........................................8 6 7.5 Human-machine interfaces (HMI).............................................31 General............................................................................................... 9 6.1 Nonswitching electrical specifications...................................... 9 SPI switching specifications........................................ 27 7.5.1 8 TSI electrical specifications.........................................31 Dimensions.........................................................................................31 6.1.1 DC characteristics........................................................ 9 6.1.2 Supply current characteristics...................................... 15 6.1.3 EMC performance........................................................17 9.1 Signal multiplexing and pin assignments.................................. 32 6.2 Switching specifications............................................................ 17 9.2 Device pin assignment...............................................................34 6.2.1 Control timing..............................................................17 8.1 Obtaining package dimensions.................................................. 31 9 Pinout................................................................................................. 32 10 Revision history................................................................................. 36 MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 3 MCU block diagram 1 MCU block diagram Port A Port B CPU PTB0/KBI0P4/RxD0/ADP4/TSI2 PTB1/KBI0P5/TxD0/ADP5/TSI3 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 PTB3/KBI0P7/MOSI0/ADP7/TSI5 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 3 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C HCS08 CORE PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 PTA2/KBI0P2/RxD0/SDA1 PTA3/KBI0P3/TxD0/SCL1 PTA4/ACMPO/BKGD/MS2 PTA5/IRQ/TCLK0/RESET PTA6/FTM2FAULT1/ADP2/TSI0 PTA7/FTM2FAULT2/ADP3/TSI1 PTC0/FTM2CH0/ADP8/TSI6 PTC1/FTM2CH1/ADP9/TSI7 PTC2/FTM2CH2/ADP10/TSI8 PTC3/FTM2CH3/ADP11/TSI9 PTC4/FTM0CH0/TSI10 PTC5/FTM0CH1/TSI11 PTC6/RxD1/TSI12 PTC7/TxD1/TSI13 Port D The block diagram below shows the structure of the MCUs. PTD0/FTM2CH23 PTD1/FTM2CH33 PTD2/TSI14 PTD3/TSI15 PTD4 PTD5 PTD6 PTD7 BDC SYSTEM INTEGRATION MODULE (SIM) WDG IRQ 1 kHz OSC LVD KEYBOARD INTERRUPT MODULE (KBI0 0) INTER-INTEGRATED CIRCUIT BUS (IIC) 8-BIT MODULO TIMER INTERRUPT PRIORITY (MTIM0 0) CONTROLLER(IPC) 2-CH FLEX TIMER ON-CHIP ICE AND DEBUG MODUE (DBG) MODULE (FTM0) 6-CH FLEX TIMER MODULE (FTM2) SERIAL COMMUNICATION INTERFACE (SCI0) USER EEPROM MC9S08PT16 = 256 bytes MC9S08PT8 = 256 bytes USER RAM MC9S08PT16 = 2,048 bytes MC9S08PT8 = 2,048 bytes 20 MHz INTERNAL CLOCK SOURCE (ICS) EXTAL XTAL VDD VSS VDD4 VSS4 VSS 4 VREFH VDDA VREFL VSSA EXTERNAL OSCILLATOR SOURCE (XOSC) SERIAL COMMUNICATION INTERFACE (SCI1) ANALOG COMPARATOR (ACMP) Port E USER FLASH MC9S08PT16 = 16,384 bytes MC9S08PT8 = 8,192 bytes REAL-TIME CLOCK (RTC) PTE0/SPSCK0 PTE1/MOSI0 PTE2/MISO0 PTE3/BUSOUT PTE4/TCLK2 SERIAL PERIPHERAL 0) INTERFACE (SPI0 TOUCH SENSE INTERFACE (TSI) POWER MANAGEMENT CONTROLLER (PMC) 12-CH 12-BIT ANALOG-TO-DIGITAL CONVERTER(ADC) CYCLIC REDUNDANCY CHECK (CRC) 1. PTA2 and PTA3 operate as true-open drain when working as output. 2. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin. 3. PTD0, PTD1, PTB4 and PTB5 can provide high sink/source current drive. 4. The secondary power pair of VDD and VSS (pin 11, 27 and 28 in 44-pin package) are not bonded in 32-pin, 20-pin or 16-pin packages. Figure 1. MCU block diagram MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 4 NXP Semiconductors Orderable part numbers 2 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document. Table 1. Ordering information Feature MC9S08PT16(A) MC9S08PT8(A) Part Number VLD VLC VWJ VTJ VTG VLD VLC VWJ VTJ VTG Max. frequency (MHz) 20 20 20 20 20 20 20 20 20 20 Flash memory (KB) 16 16 16 16 16 8 8 8 8 8 RAM (KB) 2 2 2 2 2 2 2 2 2 2 EEPROM (B) 256 256 256 256 256 256 256 256 256 256 12-bit ADC 12ch 12ch 10ch 10ch 6ch 12ch 12ch 10ch 10ch 6ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 2ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 2ch+2ch 8-bit Modulo timer 1 1 1 1 1 1 1 1 1 1 ACMP 1 1 1 1 1 1 1 1 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 8-bit SPI 1 1 1 1 1 1 1 1 1 1 I2C 1 1 1 1 1 1 1 1 1 1 SCI (LIN Capable) 2 2 1 1 1 2 2 1 1 1 Watchdog Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes CRC Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 20mA high-drive pins 4 4 2 2 2 4 4 2 2 2 TSI channels 16 16 8 8 4 16 16 8 8 4 KBI pins 8 8 8 8 8 8 8 8 8 8 GPIO 37 28 18 18 14 37 28 18 18 14 44-LQFP 32-LQFP 20-SOIC 20TSSOP 16TSSOP 44-LQFP 32-LQFP 20-SOIC 20TSSOP 16TSSOP 16-bit FlexTimer RTC Package MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 5 Part identification 3 Part identification 3.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 3.2 Format Part numbers for this device have the following format: MC 9 S08 PT AA (V) B CC 3.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values MC Qualification status * MC = fully qualified, general market flow 9 Memory * 9 = flash based S08 Core * S08 = 8-bit CPU PT Device family * PT AA Approximate flash size in KB * 16 = 16 KB * 8 = 8 KB (V) Mask set version * (blank) = Any version * A = Rev. 2 or later version, this is recommended for new design B Operating temperature range (C) * V = -40 to 105 CC Package designator * * * * * LD = 44-LQFP LC = 32-LQFP TJ = 20-TSSOP WJ = 20-SOIC TG = 16-TSSOP 3.4 Example This is an example part number: MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 6 NXP Semiconductors Parameter Classification MC9S08PT16VLD 4 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. 5 Ratings 5.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 7 Ratings 5.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -6000 +6000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105 C -100 +100 mA ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 5.4 Voltage and current operating ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in below table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Symbol Description Min. Max. Unit VDD Supply voltage -0.3 6.0 V IDD Maximum current into VDD -- 120 mA Digital input voltage (except RESET, EXTAL, XTAL, or true open drain pin PTA2 and PTA3) -0.3 VDD + 0.3 V Digital input voltage (true open drain pin PTA2 and PTA3) -0.3 6 V Analog1, -0.3 VDD + 0.3 V -25 25 mA VDD - 0.3 VDD + 0.3 V VDIO VAIO ID VDDA RESET, EXTAL, and XTAL input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage 1. All digital I/O pins, except open-drain pin PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 is only clamped to VSS. MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 8 NXP Semiconductors General 6 General 6.1 Nonswitching electrical specifications 6.1.1 DC characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 3. DC characteristics Symbol C -- -- VOH C Min Typical1 Max Unit -- 2.7 -- 5.5 V 5 V, Iload = -5 mA VDD - 0.8 -- -- V 3 V, Iload = -2.5 mA VDD - 0.8 -- -- V High current drive pins, high-drive strength2 5 V, Iload = -20 mA VDD - 0.8 -- -- V 3 V, Iload = -10 mA VDD - 0.8 -- -- V Max total IOH for all ports 5V -- -- -100 mA 3V -- -- -50 -- -- 0.8 V 3 V, Iload = 2.5 mA -- -- 0.8 V 5 V, Iload =20 mA -- -- 0.8 V 3 V, Iload = 10 mA -- -- 0.8 V -- -- 100 mA Descriptions Operating voltage Output high voltage All I/O pins, standarddrive strength C C C IOHT VOL D Output high current C Output low voltage All I/O pins, standard- 5 V, Iload = 5 drive strength mA C C High current drive pins, high-drive strength2 C IOLT D Output low current Max total IOL for all ports 5V 3V -- -- 50 VIH P Input high voltage All digital inputs VDD>4.5V 0.70 x VDD -- -- VDD>2.7V 0.75 x VDD -- -- Input low voltage All digital inputs VDD>4.5V -- -- 0.30 x VDD VDD>2.7V -- -- 0.35 x VDD C VIL P C V V Vhys C Input hysteresis All digital inputs -- 0.06 x VDD -- -- mV |IIn| P Input leakage current All input only pins (per pin) VIN = VDD or VSS -- 0.1 1 A Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 9 Nonswitching electrical specifications Table 3. DC characteristics (continued) Min Typical1 Max Unit VIN = VDD or VSS -- 0.1 1 A Total leakage All input only and I/O VIN = VDD or combined for VSS all inputs and Hi-Z pins -- -- 2 A -- 30.0 -- 50.0 k PTA2 and PTA3 pin -- 30.0 -- 60.0 k Single pin limit VIN < VSS, VIN > VDD -0.2 -- 2 mA -5 -- 25 Symbol C Descriptions |IOZ| P Hi-Z (offstate) leakage current |IOZTOT| C RPU P Pullup resistors All digital inputs, when enabled (all I/O pins other than PTA2 and PTA3) RPU3 P Pullup resistors IIC D DC injection current4, 5, 6 All input/output (per pin) Total MCU limit, includes sum of all stressed pins CIn C Input capacitance, all pins -- -- -- 7 pF VRAM C RAM retention voltage -- 2.0 -- -- V 1. Typical values are measured at 25 C. Characterized, not tested. 2. Only PTB4, PTB5, PTD0, PTD1 support ultra high current output. 3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin. 4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD. 5. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the large one. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is very low (which would reduce overall power consumption). Table 4. LVD and POR Specification Symbol C Description Min Typ Max Unit VPOR D POR re-arm voltage1, 2 1.5 1.75 2.0 V VLVDH C Falling low-voltage detect threshold - high range (LVDV = 1)3 4.2 4.3 4.4 V VLVW1H C Level 1 falling (LVWV = 00) 4.3 4.4 4.5 V VLVW2H C Level 2 falling (LVWV = 01) 4.5 4.5 4.6 V VLVW3H C Level 3 falling (LVWV = 10) 4.6 4.6 4.7 V VLVW4H C Level 4 falling (LVWV = 11) 4.7 4.7 4.8 V Falling lowvoltage warning threshold high range Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 10 NXP Semiconductors Nonswitching electrical specifications Table 4. LVD and POR Specification (continued) 1. 2. 3. 4. Symbol C Description Min Typ Max Unit VHYSH C High range low-voltage detect/warning hysteresis -- 100 -- mV VLVDL C Falling low-voltage detect threshold - low range (LVDV = 0) 2.56 2.61 2.66 V VLVDW1L C Level 1 falling (LVWV = 00) 2.62 2.7 2.78 V VLVDW2L C Level 2 falling (LVWV = 01) 2.72 2.8 2.88 V VLVDW3L C Level 3 falling (LVWV = 10) 2.82 2.9 2.98 V VLVDW4L C Level 4 falling (LVWV = 11) 2.92 3.0 3.08 V VHYSDL C Low range low-voltage detect hysteresis -- 40 -- mV VHYSWL C Low range low-voltage warning hysteresis -- 80 -- mV VBG P Buffered bandgap output 4 1.14 1.16 1.18 V Falling lowvoltage warning threshold low range Maximum is highest voltage that POR is guaranteed. POR ramp time must be longer than 20us/V to get a stable startup. Rising thresholds are falling threshold + hysteresis. Voltage factory trimmed at VDD = 5.0 V, Temp = 25 C VDD-VOH(V) IOH(mA) Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V) MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 11 Nonswitching electrical specifications VDD-VOH(V) IOH(mA) Figure 3. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V) VDD-VOH(V) IOH(mA) Figure 4. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V) MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 12 NXP Semiconductors Nonswitching electrical specifications VDD-VOH(V) IOH(mA) Figure 5. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V) VOL(V) IOL(mA) Figure 6. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V) MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 13 Nonswitching electrical specifications VOL(V) IOL(mA) Figure 7. Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V) VOL(V) IOL(mA) Figure 8. Typical IOL Vs. VOL (high drive strength) (VDD = 5 V) MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 14 NXP Semiconductors Nonswitching electrical specifications VOL(V) IOL(mA) Figure 9. Typical IOL Vs. VOL (high drive strength) (VDD = 3 V) 6.1.2 Supply current characteristics This section includes information about power supply current in various operating modes. Table 5. Supply current characteristics Num C Parameter 1 C Run supply current FEI mode, all modules on; run from flash C Symbol Bus Freq VDD (V) Typical1 Max Unit Temp RIDD 20 MHz 5 7.60 -- mA -40 to 105 C 10 MHz 4.65 -- 1 MHz 1.90 -- 7.05 -- 4.40 -- 1.85 -- 5.88 -- mA -40 to 105 C 10 MHz 3.70 -- 1 MHz 1.85 -- 5.35 -- mA -40 to 105 C C 20 MHz C 10 MHz 3 1 MHz 2 C C 3 Run supply current FEI mode, all modules off & gated; run from flash RIDD 20 MHz 5 C 20 MHz C 10 MHz 3.42 -- 1 MHz 1.80 -- 10.9 14.0 10 MHz 6.10 -- 1 MHz 1.69 -- P C Run supply current FBE mode, all modules on; run from RAM RIDD 20 MHz 3 5 Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 15 Nonswitching electrical specifications Table 5. Supply current characteristics (continued) Num C Parameter Symbol C 4 P C Run supply current FBE mode, all modules off & gated; run from RAM RIDD C Bus Freq VDD (V) Typical1 Max 20 MHz 3 8.18 -- 10 MHz 5.14 -- 1 MHz 1.44 -- 8.50 13.0 10 MHz 5.07 -- 1 MHz 1.59 -- 6.11 -- 4.10 -- 1.34 -- 5.95 -- 10 MHz 3.50 -- 1 MHz 1.24 -- 5.45 -- 10 MHz 3.25 -- 1 MHz 1.20 -- 20 MHz 20 MHz 5 3 10 MHz 1 MHz 5 C Wait mode current FEI mode, all modules on WIDD C 6 7 C 20 MHz 20 MHz C Stop3 mode supply current no clocks active (except 1kHz LPO clock)2, 3 C ADC adder to stop3 C ADLPC = 1 S3IDD -- 5 3 -- 5 1.35 -- -- 3 1.3 -- -- 5 40 -- 3 39 -- 5 121 -- 3 120 -- 5 128 -- 3 124 -- Unit Temp mA -40 to 105 C mA -40 to 105 C A -40 to 105 C -40 to 105 C A -40 to 105 C A -40 to 105 C A -40 to 105 C ADLSMP = 1 ADCO = 1 MODE = 10B ADICLK = 11B 8 C TSI adder to stop34 C PS = 010B -- -- NSCN = 0x0F EXTCHRG = 0 REFCHRG = 0 DVOLT = 01B 9 C C 1. 2. 3. 4. 5. LVD adder to stop35 -- -- Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value. RTC adder cause <1 A IDD increase typically, RTC clock source is 1kHz LPO clock. ACMP adder cause <10 A IDD increase typically. The current varies with TSI configuration and capacity of touch electrode. Please refer toTSI electrical specifications. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms. MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 16 NXP Semiconductors Switching specifications 6.1.3 EMC performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult NXP applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 6.1.3.1 EMC radiated emissions operating behaviors Table 6. EMC radiated emissions operating behaviors for 44-pin LQFP package Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15-50 8 dBV VRE2 Radiated emissions voltage, band 2 50-150 8 dBV VRE3 Radiated emissions voltage, band 3 150-500 8 dBV VRE4 Radiated emissions voltage, band 4 500-1000 5 dBV IEC level 0.15-1000 N -- VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 5.0 V, TA = 25 C, fOSC = 10 MHz (crystal), fSYS = 20 MHz, fBUS = 20 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method 6.2 Switching specifications 6.2.1 Control timing Table 7. Control timing Symbol Min Typical1 Max Unit Bus frequency (tcyc = 1/fBus) fBus DC -- 20 MHz Internal low power oscillator frequency fLPO -- 1.0 -- KHz textrst 1.5 x -- -- ns -- -- ns Num C Rating 1 P 2 C 3 D External reset pulse width2 tcyc 4 D Reset low drive trstdrv 34 x tcyc Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 17 Switching specifications Table 7. Control timing (continued) Num C 5 D 6 D 7 D Symbol Min Typical1 Max BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU 500 -- -- Unit ns BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes3 tMSH 100 -- -- ns Asynchronous path2 tILIH 100 -- -- ns Synchronous path4 tIHIL 1.5 x tcyc -- -- ns Asynchronous path2 tILIH 100 -- -- ns Synchronous path tIHIL 1.5 x tcyc -- -- ns Port rise and fall time standard drive strength (load = 50 pF)5 -- tRise -- 10.2 -- ns tFall -- 9.5 -- ns Port rise and fall time high drive strength (load = 50 pF)5 -- tRise -- 5.4 -- ns tFall -- 4.6 -- ns Rating IRQ pulse width D 8 D Keyboard interrupt pulse width D 9 C C C C 1. Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. 2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after VDD rises above VLVD. 4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5. Timing is shown with respect to 20% VDD and 80% VDD levels, across operating temperature range. textrst RESET PIN Figure 10. Reset timing tIHIL KBIPx IRQ/KBIPx tILIH Figure 11. IRQ/KBIPx timing 6.2.2 Debug trace timing specifications Table 8. Debug trace operating behaviors Symbol Description tcyc Clock period Min. Max. Unit Frequency dependent MHz Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 18 NXP Semiconductors Switching specifications Table 8. Debug trace operating behaviors (continued) Symbol Description Min. Max. Unit twl Low pulse width 2 -- ns twh High pulse width 2 -- ns tr Clock and data rise time -- 3 ns tf Clock and data fall time -- 3 ns ts Data setup 3 -- ns th Data hold 2 -- ns TRACECLK Tr Tf Twh Twl Tcyc Figure 12. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Ts Th Th TRACE_D[3:0] Figure 13. Trace data specifications 6.2.3 FTM module timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 9. FTM input timing No. C Function Symbol Min Max Unit 1 D External clock frequency fTCLK 0 fBus/4 Hz 2 D External clock period tTCLK 4 -- tcyc 3 D External clock high time tclkh 1.5 -- tcyc Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 19 Thermal specifications Table 9. FTM input timing (continued) No. C Function Symbol Min Max Unit 4 D External clock low time tclkl 1.5 -- tcyc 5 D Input capture pulse width tICPW 1.5 -- tcyc tTCLK tclkh TCLK tclkl Figure 14. Timer external clock tICPW FTMCHn FTMCHn tICPW Figure 15. Timer input capture pulse 6.3 Thermal specifications 6.3.1 Thermal characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 10. Thermal characteristics Rating Operating temperature range (packaged) Symbol TA1 Value TL to TH-40 to 105 Unit C Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 20 NXP Semiconductors Peripheral operating requirements and behaviors Table 10. Thermal characteristics (continued) Rating Junction temperature range Symbol TJ Value Unit -40 to 125 C Thermal resistance single-layer board 44-pin LQFP RJA 76 C/W 32-pin LQFP RJA 88 C/W 20-pin SOIC RJA 82 C/W 20-pin TSSOP RJA 116 C/W 16-pin TSSOP RJA 130 C/W Thermal resistance four-layer board 44-pin LQFP RJA 54 C/W 32-pin LQFP RJA 59 C/W 20-pin SOIC RJA 54 C/W 20-pin TSSOP RJA 76 C/W 16-pin TSSOP RJA 87 C/W 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + RJA x chip power dissipation. 7 Peripheral operating requirements and behaviors 7.1 External oscillator (XOSC) and ICS characteristics Table 11. XOSC and ICS specifications (temperature range = -40 to 105 C ambient) Num C 1 C Characteristic Min Typical1 Max Unit Low range (RANGE = 0) flo 31.25 32.768 39.0625 kHz High range (RANGE = 1) FEE or FBE mode2 fhi 4 -- 20 MHz C High range (RANGE = 1), high gain (HGO = 1), FBELP mode fhi 4 -- 20 MHz C High range (RANGE = 1), low power (HGO = 0), FBELP mode fhi 4 -- 20 MHz C 2 D 3 D Oscillator crystal or resonator Symbol Load capacitors Feedback resistor Low Frequency, Low-Power Mode4 See Note3 C1, C2 RF -- -- -- M Low Frequency, High-Gain Mode -- 10 -- M High Frequency, LowPower Mode -- 1 -- M Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 21 Peripheral operating requirements and behaviors Table 11. XOSC and ICS specifications (temperature range = -40 to 105 C ambient) (continued) Num C Characteristic Symbol High Frequency, High-Gain Mode Min Typical1 Max Unit -- 1 -- M -- -- -- k -- 200 -- k -- -- -- k 4 D Series resistor Low Frequency Low-Power Mode 4 5 D Series resistor High Frequency Low-Power Mode4 D Series resistor High Frequency, High-Gain Mode 4 MHz -- 0 -- k 8 MHz -- 0 -- k 16 MHz -- 0 -- k -- 1000 -- ms -- 800 -- ms -- 3 -- ms -- 1.5 -- ms tIRST -- 20 50 s fextal 0.03125 -- 5 MHz 0 -- 20 MHz D D 6 C C C C 7 8 T D D Crystal start-up time Low range = 32.768 kHz crystal; High range = 20 MHz crystal5, 6 High-Gain Mode Low range, low power RS tCSTL Low range, high power High range, low power tCSTH High range, high power Internal reference start-up time Square wave input clock frequency RS FEE or FBE mode2 FBELP mode 9 P Average internal reference frequency trimmed fint_t -- 31.25 -- kHz 10 P DCO output frequency range - trimmed fdco_t 16 -- 20 MHz 11 P fdco_t -- -- 2.0 %fdco C Total deviation of DCO output from trimmed frequency5 Over full voltage and temperature range Over fixed voltage and temperature range of 0 to 70 C 1.0 12 C FLL acquisition time5, 7 tAcquire -- -- 2 ms 13 C Long term jitter of DCO output clock (averaged over 2 ms interval)8 CJitter -- 0.02 0.2 %fdco 1. Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value. 2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3. See crystal or resonator manufacturer's recommendation. 4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 5. This parameter is characterized and not tested on each device. 6. Proper PC board layout procedures must be followed to achieve specifications. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 22 NXP Semiconductors Peripheral operating requirements and behaviors XOSC EXTAL XTAL RS RF C1 Crystal or Resonator C2 Figure 16. Typical crystal or resonator circuit 7.2 NVM specifications This section provides details about program/erase times and program/erase endurance for the flash and EEPROM memories. Table 12. Flash clock characteristics C Characteristic Symbol Min Typical Max Unit D Supply voltage for program/erase across the operating temperature range Vprog/erase 2.7 -- 5.5 V D Supply voltage for read operation VRead 2.7 -- 5.5 V D NVM Bus frequency fNVMBUS 1 -- 20 MHz D NVM operating frequency fNVMOP 0.8 1.0 1.05 MHz C FLASH Program/erase endurance TL to TH in the operating temperature range nFLPE 10 k 100 k -- Cycles C EEPROM Program/erase endurance TL to TH in the operating temperature range nFLPE 50 k 500 k -- Cycles C Data retention at an average junction temperature of TJavg = 85C after up to 10,000 program/erase cycles tD_ret 15 100 -- years All timing parameters are a function of the bus clock frequency, FNVMBUS. All program and erase times are also a function of the NVM operating frequency, fNVMOP. Each command timing is given by: tcommand=fNVMOP cycle x 1/fNVMOP + fNVMBUS cycle x 1/fNVMBUS MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 23 Peripheral operating requirements and behaviors Table 13. Flash timing characteristics C Characteristic Symbol fNVMOP cycle fNVMBUS cycle D Erase Verify All Blocks tVFYALL -- 5050 D Erase Verify Flash Block tRD1BLK -- 4631 D Erase Verify EEPROM Block tRD1BLK -- 810 D Erase Verify Flash Section tRD1SEC -- 494 D Erase Verify EEPROM Section tDRD1SEC -- 555 D Read Once tRDONCE -- 450 D Program Flash (2 word) tPGM2 68 1407 D Program Flash (4 word) tPGM4 122 2138 D Program Once tPGMONCE 122 2090 D Program EEPROM (1 Byte) tDPGM1 47 1371 D Program EEPROM (2 Byte) tDPGM2 94 2120 D Program EEPROM (3 Byte) tDPGM3 141 2869 D Program EEPROM (4 Byte) tDPGM4 188 3618 D Erase All Blocks tERSALL 100066 5455 D Erase Flash Block tERSBLK 100060 4954 D Erase Flash Sector tERSPG 20015 878 D Erase EEPROM Sector tDERSPG 5015 756 D Unsecure Flash tUNSECU 100066 5442 D Verify Backdoor Access Key tVFYKEY -- 464 D Set User Margin Level tMLOADU -- 413 Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. 7.3 Analog 7.3.1 ADC characteristics Table 14. 5 V 12-bit ADC operating conditions Characteri stic Conditions Symb Min Typ1 Max Unit Comment Supply voltage Absolute VDDA 2.7 -- 5.5 V -- Delta to VDD (VDD-VDDAD) VDDA -100 0 +100 mV Delta to VSS (VSS-VSSA)2 VSSA -100 0 +100 mV Ground voltage Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 24 NXP Semiconductors Peripheral operating requirements and behaviors Table 14. 5 V 12-bit ADC operating conditions (continued) Symb Min Typ1 Max Unit Input voltage VADIN VREFL -- VREFH V Input capacitance CADIN -- 4.5 5.5 pF Input resistance RADIN -- 3 5 k -- RAS -- -- 2 k External to MCU -- -- 5 -- -- 5 -- -- 10 -- -- 10 0.4 -- 8.0 MHz -- 0.4 -- 4.0 Characteri stic Analog source resistance Conditions * * 12-bit mode fADCK > 4 MHz fADCK < 4 MHz * * 10-bit mode fADCK > 4 MHz fADCK < 4 MHz 8-bit mode Comment (all valid fADCK) ADC conversion clock frequency High speed (ADLPC=0) fADCK Low power (ADLPC=1) 1. Typical values assume VDDA = 5.0 V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS R AS z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT R ADIN ADC SAR ENGINE v ADIN v AS C AS R ADIN INPUT PIN INPUT PIN R ADIN R ADIN INPUT PIN C ADIN Figure 17. ADC input impedance equivalency diagram MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 25 Peripheral operating requirements and behaviors Table 15. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Characteristic Conditions Supply current C Symb Min Typ1 Max Unit T IDDA -- 133 -- A T IDDA -- 218 -- A T IDDA -- 327 -- A T IDDAD -- 582 990 A ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 Supply current Stop, reset, module off T IDDA -- 0.011 1 A ADC asynchronous clock source High speed (ADLPC = 0) P fADACK 2 3.3 5 MHz 1.25 2 3.3 -- 20 -- -- 40 -- -- 3.5 -- -- 23.5 -- -- 5.0 -- Low power (ADLPC = 1) Conversion time (including sample time) Short sample (ADLSMP = 0) Sample time Short sample (ADLSMP = 0) T tADC Long sample (ADLSMP = 1) T tADS Long sample (ADLSMP = 1) Total unadjusted Error2 Differential NonLinearity 12-bit mode T ETUE 10-bit mode P -- 1.5 2.0 8-bit mode P -- 0.7 1.0 12-bit mode T -- 1.0 -- 10-bit mode4 DNL P -- 0.25 0.5 mode4 P -- 0.15 0.25 Integral Non-Linearity 12-bit mode T -- 1.0 -- 10-bit mode T -- 0.3 0.5 8-bit mode T -- 0.15 0.25 12-bit mode C -- 2.0 -- 10-bit mode P -- 0.25 1.0 8-bit Zero-scale error5 INL EZS ADCK cycles ADCK cycles LSB3 LSB3 LSB3 LSB3 Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 26 NXP Semiconductors Peripheral operating requirements and behaviors Table 15. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Min Typ1 Max -- 0.65 1.0 -- 2.5 -- T -- 0.5 1.0 8-bit mode T -- 0.5 1.0 Quantization error 12 bit modes D EQ -- -- 0.5 Input leakage error7 all modes D EIL Temp sensor slope -40C- 25C D m D VTEMP25 Characteristic Full-scale error6 Conditions C 8-bit mode P 12-bit mode T 10-bit mode Symb EFS LSB3 IIn * RAS 25C- 125C Temp sensor voltage 25C Unit LSB3 mV -- 3.266 -- -- 3.638 -- -- 1.396 -- mV/C V 1. Typical values assume VDDA = 5.0 V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. Includes quantization. 3. 1 LSB = (VREFH - VREFL)/2N 4. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 5. VADIN = VSSA 6. VADIN = VDDA 7. IIn = leakage current (refer to DC characteristics) 7.3.2 Analog comparator (ACMP) electricals Table 16. Comparator electrical specifications C Characteristic Symbol Min Typical Max D Supply voltage VDDA T Supply current (Operation mode) IDDA D Analog input voltage P Unit 2.7 -- 5.5 V -- 10 20 A VAIN VSS - 0.3 -- VDDA V Analog input offset voltage VAIO -- -- 40 mV C Analog comparator hysteresis (HYST=0) VH -- 15 20 mV C Analog comparator hysteresis (HYST=1) VH -- 20 30 mV T Supply current (Off mode) IDDAOFF -- 60 -- nA C Propagation Delay tD -- 0.4 1 s 7.4 Communication interfaces MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 27 Peripheral operating requirements and behaviors 7.4.1 SPI switching specifications The serial peripheral interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes high drive strength is enabled for SPI output pins. Table 17. SPI master mode timing Nu m. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 tHI 8 tv 9 10 11 Description Min. Max. Unit Comment fBus/2048 fBus/2 Hz fBus is the bus clock 2 x tBus 2048 x tBus ns tBus = 1/fBus Enable lead time 1/2 -- tSPSCK -- Enable lag time 1/2 -- tSPSCK -- tBus - 30 1024 x tBus ns -- Data setup time (inputs) 15 -- ns -- Data hold time (inputs) 0 -- ns -- Data valid (after SPSCK edge) -- 25 ns -- tHO Data hold time (outputs) 0 -- ns -- tRI Rise time input -- tBus - 25 ns -- tFI Fall time input tRO Rise time output -- 25 ns -- tFO Fall time output Frequency of operation SPSCK period Clock (SPSCK) high or low time MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 28 NXP Semiconductors Peripheral operating requirements and behaviors SS1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 10 11 10 11 4 5 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) MSB OUT2 9 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 18. SPI master mode timing (CPHA=0) SS1 (OUTPUT) 2 3 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 5 6 MISO (INPUT) 11 10 11 4 7 MSB IN2 BIT 6 . . . 1 LSB IN 9 8 MOSI (OUTPUT) 10 PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 19. SPI master mode timing (CPHA=1) Table 18. SPI slave mode timing Nu m. Symbol 1 fop 2 tSPSCK 3 tLead Description Frequency of operation SPSCK period Enable lead time Min. Max. Unit Comment 0 fBus/4 Hz fBus is the bus clock as defined in . 4 x tBus -- ns tBus = 1/fBus 1 -- tBus -- Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 29 Peripheral operating requirements and behaviors Table 18. SPI slave mode timing (continued) Nu m. Symbol 4 tLag 5 tWSPSCK 6 tSU 7 Min. Max. Unit Comment 1 -- tBus -- tBus - 30 -- ns -- Data setup time (inputs) 15 -- ns -- tHI Data hold time (inputs) 25 -- ns -- 8 ta Slave access time -- tBus ns Time to data active from high-impedance state 9 tdis Slave MISO disable time -- tBus ns Hold time to highimpedance state 10 tv Data valid (after SPSCK edge) -- 25 ns -- 11 tHO Data hold time (outputs) 0 -- ns -- 12 tRI Rise time input -- tBus - 25 ns -- tFI Fall time input tRO Rise time output -- 25 ns -- tFO Fall time output 13 Description Enable lag time Clock (SPSCK) high or low time SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 MISO (OUTPUT) see note SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 20. SPI slave mode timing (CPHA = 0) MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 30 NXP Semiconductors Dimensions SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 8 MOSI (INPUT) 13 12 13 11 10 see note MISO (OUTPUT) 12 SLAVE MSB OUT 6 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN NOTE: Not defined Figure 21. SPI slave mode timing (CPHA=1) 7.5 Human-machine interfaces (HMI) 7.5.1 TSI electrical specifications Table 19. TSI electrical specifications Symbol Description Min. Type Max Unit TSI_RUNF Fixed power consumption in run mode -- 100 -- A TSI_RUNV Variable power consumption in run mode (depends on oscillator's current selection) 1.0 -- 128 A TSI_EN Power consumption in enable mode -- 100 -- A TSI_DIS Power consumption in disable mode -- 1.2 -- A TSI_TEN TSI analog enable time -- 66 -- s TSI_CREF TSI reference capacitor -- 1.0 -- pF TSI_DVOLT Voltage variation of VP & VM around nominal values -10 -- 10 % 8 Dimensions 8.1 Obtaining package dimensions Package dimensions are provided in package drawings. MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 31 Pinout To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number: If you want the drawing for this package Then use this document number 16-pin TSSOP 98ASH70247A 20-pin SOIC 98ASB42343B 20-pin TSSOP 98ASH70169A 32-pin LQFP 98ASH70029A 44-pin LQFP 98ASS23225W 9 Pinout 9.1 Signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. Table 20. Pin availability by package pin-count Pin Number 44-LQFP 32-LQFP Lowest Priority <-- --> Highest 20-TSSOP 16-TSSOP Port Pin Alt 1 Alt 2 Alt 3 Alt 4 1 1 -- -- PTD11 -- FTM2CH3 -- -- 2 2 -- -- PTD01 -- FTM2CH2 -- -- 3 -- -- -- PTE4 -- TCLK2 -- -- 4 -- -- -- PTE3 -- BUSOUT -- -- 5 3 3 3 -- -- -- -- VDD 6 4 -- -- -- -- -- VDDA VREFH 7 5 -- -- -- -- -- VSSA VREFL 8 6 4 4 -- -- -- -- VSS 9 7 5 5 PTB7 -- -- SCL EXTAL 10 8 6 6 PTB6 -- -- SDA XTAL 11 -- -- -- -- -- -- -- Vss 7 PTB51 -- FTM2CH5 SS0 -- -- FTM2CH4 MISO0 -- 12 9 7 13 10 8 8 PTB41 14 11 9 -- PTC3 -- FTM2CH3 ADP11 TSI9 15 12 10 -- PTC2 -- FTM2CH2 ADP10 TSI8 16 -- -- -- PTD7 -- -- -- -- 17 -- -- -- PTD6 -- -- -- -- Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 32 NXP Semiconductors Pinout Table 20. Pin availability by package pin-count (continued) Pin Number Lowest Priority <-- --> Highest 44-LQFP 32-LQFP 20-TSSOP 16-TSSOP Port Pin Alt 1 Alt 2 Alt 3 Alt 4 18 -- -- -- PTD5 -- -- -- -- 19 13 11 -- PTC1 -- FTM2CH1 ADP9 TSI7 20 14 12 -- PTC0 -- FTM2CH0 ADP8 TSI6 21 15 13 9 PTB3 KBI0P7 MOSI0 ADP7 TSI5 22 16 14 10 PTB2 KBI0P6 SPSCK0 ADP6 TSI4 23 17 15 11 PTB1 KBI0P5 TXD0 ADP5 TSI3 24 18 16 12 PTB0 KBI0P4 RXD0 ADP4 TSI2 25 19 -- -- PTA7 -- FTM2FAULT2 ADP3 TSI1 26 20 -- -- PTA6 -- FTM2FAULT1 ADP2 TSI0 27 -- -- -- -- -- -- -- Vss 28 -- -- -- -- -- -- -- VDD 29 -- -- -- PTD4 -- -- -- -- 30 21 -- -- PTD3 -- -- -- TSI15 31 22 -- -- PTD2 -- -- -- TSI14 13 PTA32 KBI0P3 TXD0 SCL -- KBI0P2 RXD0 SDA -- 32 23 17 33 24 18 14 PTA22 34 25 19 15 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1 35 26 20 16 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0 36 27 -- -- PTC7 -- TxD1 -- TSI13 37 28 -- -- PTC6 -- RxD1 -- TSI12 38 -- -- -- PTE2 -- MISO0 -- -- 39 -- -- -- PTE1 -- MOSI0 -- -- 40 -- -- -- PTE0 -- SPSCK0 -- -- 41 29 -- -- PTC5 -- FTM0CH1 -- TSI11 42 30 -- -- PTC4 -- FTM0CH0 -- TSI10 43 31 1 1 PTA5 IRQ TCLK0 -- RESET 44 32 2 2 PTA4 -- ACMPO BKGD MS 1. This is a high current drive pin when operated as output. 2. This is a true open-drain pin when operated as output. Note When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software must clear any associated flags before interrupts are enabled. The table above illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 33 Pinout already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module. PTC6/RxD1/TSI12 PTC7/TxD1/TSI13 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 37 36 35 34 PTE1/MOSI0 PTE2/MISO0 38 PTE0/SPSCK0 40 39 42 41 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK0/RESET PTC4/FTM0CH0/TSI10 PTC5/FTM0CH1/TSI11 44 43 9.2 Device pin assignment 33 PTA2/KBI0P2/RxD0/SDA 2 32 PTA3/KBI0P3/TxD0/SCL 2 11 23 PTB1/KBI0P5/TxD0/ADP5/TSI3 21 PTB0/KBI0P4/RxD0/ADP4/TSI2 VSS 22 PTA7/FTM2FAULT2/ADP3/TSI1 24 PTB3/KBI0P7/MOSI0/ADP7/TSI5 25 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 9 10 19 PTB7/SCL/EXTAL PTB6/SDA/XTAL 20 VSS PTA6/FTM2FAULT1/ADP2/TSI0 PTC0/FTM2CH0/ADP8/TSI6 26 PTC1/FTM2CH1/ADP9/TSI7 27 8 18 7 VSS PTD5 VSSA /VREFL VDD 16 PTD4 28 17 29 6 PTD6 5 VDDA /VREFH PTD7 PTD3/TSI15 14 PTD2/TSI14 30 15 31 4 PTC3/FTM2CH3/ADP11/TSI9 3 PTC2/FTM2CH2/ADP10/TSI8 PTE4/TCLK2 PTE3/BUSOUT VDD 12 2 13 PTD0/FTM2CH21 PTB5/FTM2CH5/SS01 1 PTB4/FTM2CH4/MISO01 PTD1/FTM2CH31 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 22. MC9S08PT16 44-pin LQFP package MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 34 NXP Semiconductors PTC5/FTM0CH1/TSI11 PTC6/RxD1/TSI12 PTC7/TxD1/TSI13 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 29 27 26 25 PTA5/IRQ/TCLK0/RESET PTC4/FTM0CH0/TSI10 30 28 PTA4/ACMPO/BKGD/MS 32 31 Pinout 20 PTA6/FTM2FAULT1/ADP2/TSI0 6 19 PTA7/FTM2FAULT2/ADP3/TSI1 PTB7/SCL/EXTAL 7 18 PTB0/KBI0P4/RxD0/ADP4/TSI2 PTB6/SDA/XTAL 8 17 PTB1/KBI0P5/TxD0/ADP5/TSI3 14 16 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 PTA3/KBI0P3/TxD0/SCL2 15 PTA2/KBI0P2/RxD0/SDA 2 23 PTC0/FTM2CH0/ADP8/TSI6 24 PTB3/KBI0P7/MOSI0/ADP7/TSI5 13 5 VSS 12 VSSA/VREFL PTC1/FTM2CH1/ADP9/TSI7 PTD3/TSI15 PTC2/FTM2CH2/ADP10/TSI8 21 11 PTD2/TSI14 4 PTC3/FTM2CH3/ADP11/TSI9 22 VDDA/VREFH 9 VDD 3 10 2 PTB5/FTM2CH5/SS01 1 1 PTB4/FTM2CH4/MISO01 PTD1/FTM2CH31 PTD0/FTM2CH2 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 23. MC9S08PT16 32-pin LQFP package PTA5/IRQ/TCLK0/RESET 1 20 PTA4/ACMPO/BKGD/MS VDD VSS 2 19 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 3 18 PTA2/KBI0P2/RxD0/SDA 2 4 5 17 16 PTA3/KBI0P3/TxD0/SCL 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL 6 15 14 13 PTB1/KBI0P5/TxD0/ADP5/TSI3 12 PTC0/FTM2CH0/ADP8/TSI6 11 PTC1/FTM2CH1/ADP9/TSI7 PTB5/FTM2CH5/SS01 PTB4/FTM2CH4/MISO0 1 7 PTC3/FTM2CH3/ADP11/TSI9 8 9 PTC2/FTM2CH2/ADP10/TSI8 10 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTB0/KBI0P4/RxD0/ADP4/TSI2 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 PTB3/KBI0P7/MOSI0/ADP7/TSI5 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 24. MC9S08PT16 20-pin SOIC and TSSOP package MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 35 Revision history PTA5/IRQ/TCLK0/RESET 1 16 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA4/ACMPO/BKGD/MS VDD VSS 2 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 4 15 14 13 PTA3/KBI0P3/TxD0/SCL2 PTB7/SCL/EXTAL 5 12 PTB0/KBI0P4/RxD0/ADP4/TSI2 PTB6/SDA/XTAL 6 PTB1/KBI0P5/TxD0/ADP5/TSI3 7 11 10 8 9 PTB5/FTM2CH5/SS01 PTB4/FTM2CH4/MISO01 3 PTA2/KBI0P2/RxD0/SDA 2 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 PTB3/KBI0P7/MOSI0/ADP7/TSI5 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 25. MC9S08PT16 16-pin TSSOP package 10 Revision history The following table provides a revision history for this document. Table 21. Revision history Rev. No. Date Substantial Changes 1 7/2012 2 09/2014 Initial public release Updated VOH and VOL in DC characteristics Added footnote on the S3IDD in Supply current characteristics Added EMC radiated emissions operating behaviors Updated the typical of fint_t to 31.25 kHz and updated footnote to tAcquire in External oscillator (XOSC) and ICS characteristics * Updated the assumption for all the timing values in SPI switching specifications * Updated the rating descriptions for tRise and tFall in Control timing * Updated the part number format to add new field for new part numbers in Fields 3 06/2015 * Corrected the Min. of the textrst in Control timing * Updated Thermal characteristics to add footnote to the TA and removed redundant information.Updated the symbol of JA to RJA. 4 03/2020 * * * * * * * * * Added MCU block diagram. Added new section of Orderable part numbers Updated Tj in the Thermal characteristics. Updated flash characteristics in the NVM specifications Updated S3IDD values in the Supply current characteristics MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 36 NXP Semiconductors How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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