NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV Product Preview 2-Kb, 4-Kb, 8-Kb and 16-Kb Low Voltage Automotive I2C Serial EEPROM www.onsemi.com Description The NV24C02/04/08/16LV are 2-Kb, 4-Kb, 8-Kb and 16-Kb respectively CMOS Serial EEPROM devices that operate at a minimum 1.7 V supply voltage. They are organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. All devices support the Standard (100 kHz), Fast (400 kHz) and Fast-Plus (1 MHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non-volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight NV24C02, four NV24C04, two NV24C08 and one NV24C16 device on the same bus. Features * * * * * * * * * * * * * Automotive AEC-Q100 Grade 1 (-40C to +125C) Qualified Supports Standard, Fast and Fast-Plus I2C Protocol 1.7 V to 5.5 V Supply Voltage Range 16-Byte Page Write Buffer Fast Write Time (4 ms max) Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low power CMOS Technology More than 1,000,000 Program/Erase Cycles 100 Year Data Retention Automotive Grade 1 Temperature Range SOIC, TSSOP, US 8-Lead, TSOP-5 Lead and Wettable Flank UDFN 8-pad Packages These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant PIN CONFIGURATION (SOIC-8,US-8,UNFN-8 ,TSSOP-8) NV24C__ 16 / 08 / 04 / 02 NC / NC / NC / A0 NC / NC / A1 / A1 NC / A2 / A2 / A2 VSS US8 U SUFFIX CASE 493 TSOP-5 SN SUFFIX CASE 483 UDFN-8 MUW3 SUFFIX CASE 517DH SOIC8 DW SUFFIX CASE 751BD ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 14 of this data sheet. PIN CONFIGURATION (TSOP-5) 8 VCC SCL 1 2 7 WP VSS 2 3 6 SCL SDA 3 4 5 SDA 1 TSSOP-8 DT SUFFIX CASE 948AL 5 WP 4 VCC This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. (c) Semiconductor Components Industries, LLC, 2018 March, 2019 - Rev. P3 1 Publication Order Number: NV24C02LV/D NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV VCC Table 1. PIN FUNCTION Pin Name Function A0, A1, A2 SCL A2, A1, A0 NV24Cxx SDA WP Device Address Input SDA Serial Data Input/Output SCL Serial Clock Input WP Write Protect Input VCC Power Supply VSS Ground NC No Connect VSS Figure 1. Functional Symbol Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature -65 to +150 C Voltage on any pin with respect to Ground (Note 1) -0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. During input transitions, voltage undershoot on any pin should not exceed -1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2 and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute maximum ratings, irrespective of VCC. Table 3. RELIABILITY CHARACTERISTICS Symbol NEND (Note 2) TDR (Note 2) Parameter Endurance Data Retention Min Units 1,000,000 Write Cycles (Note 3) 100 Years 2. TA = 25C 3. A Write Cycle refers to writing a Byte or a Page. Table 4. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = -40C to +125C, unless otherwise specified.*) Symbol Parameter Test Conditions Min Max Units ICCR Read Current Read, fSCL = 1 MHz 0.3 mA ICCW Write Current Write 0.5 mA Standby Current All I/O Pins at GND or VCC TA = -40C to +85C 1 mA TA = -40C to +125C 2 ISB IL I/O Pin Leakage Pin at GND or VCC VIL1 Input Low Voltage 2.2 V VCC 5.5 V -0.5 2 mA 0.3 VCC V VIL2 Input Low Voltage 1.7 V VCC < 2.2 V -0.5 0.2 VCC V VIH1 Input High Voltage 2.2 V VCC 5.5 V 0.7 VCC VCC + 0.5 V VIH2 Input High Voltage 1.7 V VCC < 2.2 V 0.8 VCC VCC + 0.5 V VOL1 Output Low Voltage VCC 2.2 V, IOL = 6.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.2 V, IOL = 2.0 mA 0.2 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. *VCC(min) = 1.6 V for Read operations, TA = -20C to +85C. www.onsemi.com 2 NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV Table 5. PIN IMPEDANCE CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40C to +125C, unless otherwise specified.*) Parameter Symbol Conditions Max Units CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF WP Input Current, Address Input Current (A0, A1, A2) VIN < VIH, VCC = 5.5 V 50 mA VIN < VIH, VCC = 3.3 V 35 VIN < VIH, VCC = 1.7 V 25 VIN > VIH 2 IWP, IA (Note 5) 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. *VCC(min) = 1.6 V for Read operations, TA = -20C to +85C. Table 6. A.C. CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40C to +125C, unless otherwise specified.*) (Note 6) Standard Symbol FSCL tHD:STA Min Parameter Clock Frequency Fast Max Min 100 START Condition Hold Time Fast-Plus Max Min 400 Max Units 1,000 kHz 4 0.6 0.26 ms tLOW Low Period of SCL Clock 4.7 1.3 0.50 ms tHIGH High Period of SCL Clock 4 0.6 0.26 ms tSU:STA START Condition Setup Time 4.7 0.6 0.26 ms tHD:DAT Data In Hold Time 0 0 0 ms tSU:DAT Data In Setup Time 250 100 50 ns tR (Note 7) SDA and SCL Rise Time 1,000 300 120 ns tF (Note 7) SDA and SCL Fall Time 300 300 120 ns tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH (Note 7) Ti (Note 7) Data Out Hold Time 4 0.6 0.26 ms 4.7 1.3 0.5 ms 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs 0.9 100 50 0.45 50 50 ms ns 50 ns tSU:WP WP Setup Time 0 0 0 ms tHD:WP WP Hold Time 2.5 2.5 1 ms tWR tPU (Notes 7, 8) Write Cycle Time Power-up to Ready Mode 4 4 4 ms 0.35 0.35 0.35 ms 6. Test conditions according to "A.C. Test Conditions" table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. *VCC(min) = 1.6 V for Read operations, TA = -20C to +85C. Table 7. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC for VCC 2.2 V 0.15 x VCC to 0.85 x VCC for VCC < 2.2 V Input Rise and Fall Times 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.3 x VCC, 0.7 x VCC Output Load Current Source: IOL = 6 mA (VCC 2.2 V); IOL = 2 mA (VCC < 2.2 V); CL = 100 pF www.onsemi.com 3 NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV Power-On Reset (POR) Each NV24Cxx* incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. A NV24Cxx device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against `brown-out' failure following a temporary loss of power. *For common features, the NV24C02/04/08/16 will be referred to as NV24Cxx. During data transfer, the SDA line must remain stable while the SCL line is high. An SDA transition while SCL is high will be interpreted as a START or STOP condition (Figure 2). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a `wake-up' call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. NOTE: The I/O pins of NV24Cxx do not obstruct the SCL and SDA lines if the VCC supply is switched off. During power-up, the SCL and SDA pins (connected with pull-up resistors to VCC) will follow the VCC monotonically from VSS (0 V) to nominal VCC value, regardless of pull-up resistor value. The delta between the VCC and the instantaneous voltage levels during power ramping will be determined by the relation between bus time constant (determined by pull-up resistance and bus capacitance) and actual VCC ramp rate. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. For normal Read/Write operations, the first 4 bits of the Slave address are fixed at 1010 (Ah). The next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. The last bit of the slave address, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. The 3 address space extension bits are assigned as illustrated in Figure 3. A2, A1 and A0 must match the state of the external address pins, and a10, a9 and a8 are internal address bits. Functional Description The NV24Cxx supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The NV24Cxx acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 5. I2C Bus Protocol The I2C bus consists of two `wires', SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2-wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `1'. Data transfer may be initiated only when the bus is not busy (see AC Characteristics). www.onsemi.com 4 NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV SCL SDA START CONDITION STOP CONDITION Figure 2. Start/Stop Timing 1 0 1 0 A2 A1 A0 R/W NV24C0 2LV 1 0 1 0 A2 A1 a8 R/W N24C04 1 0 1 0 A2 a9 a8 R/W N24C08 1 0 1 0 a10 a9 a8 R/W N24C16 Figure 3. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACK SETUP (w tSU:DAT) ACK DELAY (v tAA) START Figure 4. Acknowledge Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tDH SDA OUT Figure 5. Bus Timing www.onsemi.com 5 tBUF NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV WRITE OPERATIONS Byte Write sixteen bytes are received and the STOP condition has been sent by the Master, the internal Write cycle begins. At this point all received data is written to the NV24Cxx in a single write cycle. In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the NV24Cxx. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The NV24Cxx device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 6). While this internal cycle is in progress (tWR), the SDA output will be tri-stated and the NV24Cxx will not respond to any request from the Master device (Figure 7). Acknowledge Polling The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the NV24Cxx initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NV24Cxx is still busy with the write operation, NoACK will be returned. If the NV24Cxx has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Page Write The NV24Cxx writes up to 16 bytes of data in a single write cycle, using the Page Write operation (Figure 8). The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the NV24Cxx will respond with an acknowledge and internally increments the four low order address bits. The high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter `wraps around' to the beginning of page and previously transmitted data will be overwritten. Once all BUS ACTIVITY: MASTER S T A R T Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the NV24Cxx. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the NV24Cxx will not acknowledge the data byte and the Write request will be rejected. Delivery State The NV24Cxx is shipped erased, i.e., all bytes are FFh. SLAVE ADDRESS ADDRESS BYTE DATA BYTE a7 - a 0 d7 - d 0 S T O P P S SLAVE A C K A C K Figure 6. Byte Write Sequence www.onsemi.com 6 A C K NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV SCL 8th Bit SDA ACK Byte n tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing BUS ACTIVITY: MASTER S T A R T DATA BYTE n ADDRESS BYTE SLAVE ADDRESS DATA BYTE n+1 S T O P DATA BYTE n+P S P A C K SLAVE n=1 P v 15 A C K A C K A C K Figure 8. Page Write Sequence ADDRESS BYTE DATA BYTE 1 8 9 a7 a0 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP Figure 9. WP Timing www.onsemi.com 7 A C K NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV READ OPERATIONS Immediate Read address of the location it wishes to read. After the NV24Cxx acknowledges the byte address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The NV24Cxx then responds with its acknowledge and sends the requested data byte. The Master device does not acknowledge the data (NoACK) but will generate a STOP condition (Figure 11). Upon receiving a Slave address with the R/W bit set to `1', the NV24Cxx will interpret this as a request for data residing at the current byte address in memory. The NV24Cxx will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the NV24Cxx returns to Standby mode. Sequential Read If during a Read session, the Master acknowledges the 1st data byte, then the NV24Cxx will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page). Selective Read Selective Read operations allow the Master device to select at random any memory location for a read operation. The Master device first performs a `dummy' write operation by sending the START condition, slave address and byte BUS ACTIVITY: MASTER N O S T A R T S AT CO KP SLAVE ADDRESS P S A C K SLAVE SCL D ATA BYTE 8 9 8th Bit SDA DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: MASTER S T A R T S T A R T ADDRESS BYTE SLAVE ADDRESS S N O S AT CO KP SLAVE ADDRESS P S A C K SLAVE A C K A C K D ATA BYTE Figure 11. Selective Read Sequence N O BUS ACTIVITY: MASTER A C K SLAVE ADDRESS A C K S AT CO KP A C K P SLAVE A C K D ATA BYTE n D ATA BYTE n+1 D ATA BYTE n+2 Figure 12. Sequential Read Sequence www.onsemi.com 8 D ATA BYTE n+x NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL-01 ISSUE O b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 0.15 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.90 e 0.65 BSC L 1.00 REF L1 0.50 0 0.60 1.05 0.75 8 e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. www.onsemi.com 9 NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD-01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 MAX c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 0 8 TOP VIEW D h A1 A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. www.onsemi.com 10 NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV PACKAGE DIMENSIONS UDFN8 2x3, 0.5P CASE 517DH ISSUE O B A D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL B ALTERNATE CONSTRUCTION IS NOT APPLICABLE. L L L1 DETAIL A ALTERNATE CONSTRUCTIONS E PIN ONE INDICATOR 0.05 C EXPOSED Cu A3 MOLD CMPD DIM A A1 A3 b D D2 E E2 e L L1 0.05 C TOP VIEW DETAIL B A 0.10 C 0.08 C NOTE 4 A1 A1 SIDE VIEW DETAIL A 1 D2 4 DETAIL B A3 C ALTERNATE CONSTRUCTIONS SEATING PLANE MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 2.00 BSC 1.30 1.50 3.00 BSC 1.30 1.50 0.50 BSC 0.30 0.50 --- 0.15 RECOMMENDED SOLDERING FOOTPRINT* L 1.56 E2 8 5 e BOTTOM VIEW 8X 0.68 1.55 3.40 8X b 0.10 M C A B 0.05 M C NOTE 3 1 8X 0.50 PITCH 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 11 NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV PACKAGE DIMENSIONS US8 CASE 493 ISSUE D X Y A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. MOLD FLASH. PROTRUSION AND GATE BURR SHALL NOT EXCEED 0.14MM (0.0055") PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL NOT EXCEED 0.14MM (0.0055") PER SIDE. 5. LEAD FINISH IS SOLDER PLATING WITH THICKNESS OF 0.0076-0.0203MM (0.003-0.008"). 6. ALL TOLERANCE UNLESS OTHERWISE SPECIFIED 0.0508MM (0.0002"). J 5 DETAIL E B L 1 4 R S G P U C SEATING PLANE T D H 0.10 (0.004) T K 0.10 (0.004) M N R 0.10 TYP T X Y V M F DETAIL E DIM A B C D F G H J K L M N P R S U V RECOMMENDED SOLDERING FOOTPRINT* 8X 0.30 8X 0.68 3.40 1 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 12 MILLIMETERS MIN MAX 1.90 2.10 2.20 2.40 0.60 0.90 0.17 0.25 0.20 0.35 0.50 BSC 0.40 REF 0.10 0.18 0.00 0.10 3.00 3.20 0_ 6_ 0_ 10 _ 0.23 0.34 0.23 0.33 0.37 0.47 0.60 0.80 0.12 BSC INCHES MIN MAX 0.075 0.083 0.087 0.094 0.024 0.035 0.007 0.010 0.008 0.014 0.020 BSC 0.016 REF 0.004 0.007 0.000 0.004 0.118 0.128 0_ 6_ 0_ 10 _ 0.010 0.013 0.009 0.013 0.015 0.019 0.024 0.031 0.005 BSC NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV PACKAGE DIMENSIONS TSOP-5 CASE 483 ISSUE M D 5X NOTE 5 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. 0.20 C A B 0.10 T M 2X 0.20 T B 5 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H SIDE VIEW C SEATING PLANE END VIEW MILLIMETERS MIN MAX 2.85 3.15 1.35 1.65 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 13 NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV Ordering Information Density (Kb) Package Type Device Specific Marking NV24C02UVLT2G 2 US-8 NV24C02MUW3VLTBG 2 NV24C02DWVLT3G OPN Temperature Range Shipping TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 2,000 Units / Reel UDFN-8 Wettable Flank TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel 2 SOIC-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C02DTVLT3G 2 TSSOP-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C02SNVLT3G 2 TSOP-5 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C04UVLT2G 4 US-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 2,000 Units / Reel NV24C04MUW3VLTBG 4 UDFN-8 Wettable Flank TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C04DWVLT3G 4 SOIC-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C04DTVLT3G 4 TSSOP-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C04SNVLT3G 4 TSOP-5 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C08UVLT2G 8 US-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 2,000 Units / Reel NV24C08MUW3VLTBG 8 UDFN-8 Wettable Flank TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C08DWVLT3G 8 SOIC-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C08DTVLT3G 8 TSSOP-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C08SNVLT3G 8 TSOP-5 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C16UVLT2G 16 US-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 2,000 Units / Reel NV24C16MUW3VLTBG 16 UDFN-8 Wettable Flank TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C16DWVLT3G 16 SOIC-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C16DTVLT3G 16 TSSOP-8 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel NV24C16SNVLT3G 16 TSOP-5 TBD V = Automotive Grade 1 (-40C to +125C) Tape & Reel, 3,000 Units / Reel 9. All packages are RoHS-compliant (Lead-free, Halogen-free). 10. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 14 NV24C02LV, NV24C04LV, NV24C08LV, NV24C16LV ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. 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ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 www.onsemi.com 15 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NV24C02LV/D