Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MOTOROLA MC68340 Integrated Processor with DMA User's Manual (c)MOTOROLA INC., 1992 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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The complete documentation package for the MC68340 consists of the MC68340UM/AD, MC68340 Integrated Processor with DMA User's Manual, M68000PM/AD, MC68000 Family Programmer's Reference Manual, and the MC68340P/D, MC68340 Integrated Processor with DMA Product Brief. The MC68340 Integrated with DMA Processor User's Manual describes the programming, capabilities, registers, and operation of the MC68340; the MC68000 Family Programmer's Reference Manual provides instruction details for the MC68340; and the MC68340 Integrated Processor with DMA Product Brief provides a brief description of the MC68340 capabilities. This user's manual is organized as follows: Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 Section 7 Device Overview Signal Descriptions Bus Operation System Integration Module CPU32 DMA Controller Module Serial Module Section 8 Section 9 Section 10 Section 11 Section 12 Timer Modules IEEE 1149.1 Test Access Port Applications Electrical Characteristics Ordering Information and Mechanical Data 68K FAX-IT FAX 512-891-8593 The Motorola High-End Technical Publication Department provides a FAX number for you to submit any questions and comments about this document. We welcome your suggestions for improving our documentation or any questions concerning our products. Please provide the part number and revision number (located in upper right-hand corner on the cover), and the title of the document when submitting. When referring to items in the manual please reference by the page number, paragraph number, figure number, table number, and line number if needed. Reference the line number from the top of the page. When we receive a FAX between the hours of 7:30 AM and 5:00 PM EST, Monday through Friday, we will respond within two hours. If the FAX is received after 5:00 PM or on the weekend, we will respond within two hours on the first working day following receipt of the FAX. When sending a FAX, please provide your name, company, FAX number, and voice number including area code (so we can talk to a real person if needed). For More Information On This Product, Go to: www.freescale.com 11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... Section 1 Device Overview 1.1 1.1.1 1.1.2 1.2 1.2.1 1.2.2 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 1.3.1.6 1.3.1.7 1.3.2 1.3.3 1.3.4 1.4 1.5 1.6 1.7 M68300 Family..................................................................................................1-2 Organization ..................................................................................................1-3 Advantages....................................................................................................1-3 Central Processor Unit..................................................................................... 1-3 CPU32 ............................................................................................................1-4 Background Debug Mode...........................................................................1-4 On-Chip Peripherals ........................................................................................1-5 System Integration Module.........................................................................1-5 External Bus Interface..............................................................................1-5 System Configuration and Protection...................................................1-6 Clock Synthesizer.....................................................................................1-6 Chip Select and Wait State Generation ...............................................1-6 Interrupt Handling.....................................................................................1-6 Discrete I/O Pins........................................................................................1-6 IEEE 1149.1 Test Access Port................................................................1-7 Direct Memory Access Module...................................................................1-7 Serial Module................................................................................................1-7 Timer Modules...............................................................................................1-8 Power Consumption Management................................................................1-8 Physical ..............................................................................................................1-9 Compact Disc-Interactive ................................................................................1-9 More Information...............................................................................................1-10 Section 2 Signal Descriptions 2.1 2.2 2.2.1 2.2.2 2.3 2.4 2.5 2.6 MOTOROLA Signal Index.......................................................................................................2-2 Address Bus.......................................................................................................2-4 Address Bus (A23-A0) ................................................................................2-4 Address Bus (A31-A24)..............................................................................2-4 Data Bus (D15-D0)..........................................................................................2-4 Function Codes (FC3-FC0)............................................................................2-5 Chip Selects (CS3-CS0) ................................................................................2-5 Interrupt Request Level (IRQ7, IRQ6, IRQ5, IRQ3) ...................................2-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com iii 11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.9 2.9.1 2.9.2 2.9.3 2.10 2.10.1 2.10.2 2.10.3 2.10.4 2.11 2.11.1 2.11.2 2.11.3 2.11.4 2.12 2.12.1 2.12.2 2.12.3 2.13 2.13.1 2.13.2 2.13.3 2.13.4 2.13.5 2.13.6 2.13.7 2.13.8 2.14 2.14.1 2.14.2 2.14.3 iv Title Page Number Bus Control Signals .........................................................................................2-6 Data and Size Acknowledge (DSACK1, DSACK0)................................2-6 Address Strobe (AS)....................................................................................2-6 Data Strobe (DS)...........................................................................................2-7 Transfer Size (SIZ1, SIZ0) ..........................................................................2-7 Read/Write (R/W)...........................................................................................2-7 Bus Arbitration Signals....................................................................................2-7 Bus Request (BR)..........................................................................................2-7 Bus Grant (BG)...............................................................................................2-7 Bus Grant Acknowledge (BGACK).............................................................2-7 Read-Modify-Write Cycle (RMC).................................................................2-8 Exception Control Signals ..............................................................................2-8 Reset (RESET)...............................................................................................2-8 Halt (HALT)....................................................................................................2-8 Bus Error (BERR)...........................................................................................2-8 Clock Signals ....................................................................................................2-8 System Clock (CLKOUT)............................................................................2-8 Crystal Oscillator (EXTAL, XTAL)...............................................................2-9 External Filter Capacitor (XFC) ..................................................................2-9 Clock Mode Select (MODCK).....................................................................2-9 Instrumentation and Emulation Signals .......................................................2-9 Instruction Fetch (IFETCH)..........................................................................2-9 Instruction Pipe (IPIPE)...............................................................................2-9 Breakpoint (BKPT)........................................................................................2-10 Freeze (FREEZE)..........................................................................................2-10 DMA Module Signals.......................................................................................2-10 DMA Request (DREQ2, DREQ1).................................................................2-10 DMA Acknowledge (DACK2, DACK1)......................................................2-10 DMA Done (DONE2, DONE1)......................................................................2-10 Serial Module Signals.....................................................................................2-11 Serial Crystal Oscillator (X2, X1) ...............................................................2-11 Serial External Clock Input (SCLK)...........................................................2-11 Receive Data (RxDA, RxDB).......................................................................2-11 Transmit Data (TxDA, TxDB).......................................................................2-11 Clear to Send (CTSA, CTSB).....................................................................2-11 Request to Send (RTSA, RTSB)................................................................2-11 Transmitter Ready (TRDYA).....................................................................2-11 Receiver Ready (RRDYA) .........................................................................2-12 Timer Signals ....................................................................................................2-12 Timer Gate (TGATE2, TGATE1)................................................................2-12 Timer Input (TIN2, TIN1) ..............................................................................2-12 Timer Output (TOUT2, TOUT1)...................................................................2-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA 11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Paragraph Number Freescale Semiconductor, Inc... 2.15 2.15.1 2.15.2 2.15.3 2.15.4 2.16 2.17 2.18 Title Page Number Test Signals.......................................................................................................2-13 Test Clock (TCK)...........................................................................................2-13 Test Mode Select (TMS)..............................................................................2-13 Test Data In (TDI)..........................................................................................2-13 Test Data Out (TDO).....................................................................................2-13 Synthesizer Power (VCCSYN)..........................................................................2-13 System Power and Ground (VCC and GND)................................................2-13 Signal Summary...............................................................................................2-13 Section 3 Bus Operation 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.7.1 3.1.7.2 3.1.7.3 3.2 3.2.1 3.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 3.2.3.4 3.2.3.5 3.2.3.6 3.2.3.7 3.2.4 3.2.5 3.2.6 3.3 3.3.1 3.3.2 3.3.3 MOTOROLA Bus Transfer Signals........................................................................................3-1 Bus Control Signals .....................................................................................3-2 Function Code Signals................................................................................3-3 Address Bus (A31-A0) ................................................................................3-4 Address Strobe (AS)....................................................................................3-4 Data Bus (D15-D0)......................................................................................3-4 Data Strobe (DS)...........................................................................................3-4 Bus Cycle Termination Signals..................................................................3-4 Data Transfer and Size Acknowledge Signals (DSACK1 and DSACK0).....................................................................3-4 Bus Error (BERR).......................................................................................3-5 Autovector (AVEC)....................................................................................3-5 Data Transfer Mechanism...............................................................................3-5 Dynamic Bus Sizing.....................................................................................3-5 Misaligned Operands...................................................................................3-7 Operand Transfer Cases.............................................................................3-7 Byte Operand to 8-Bit Port, Odd or Even (A0 = X) ..............................3-7 Byte Operand to 16-Bit Port, Even (A0 = 0)..........................................3-8 Byte Operand to 16-Bit Port, Odd (A0 = 1) ...........................................3-9 Word Operand to 8-Bit Port, Aligned.....................................................3-9 Word Operand to 16-Bit Port, Aligned...................................................3-10 Long-word Operand to 8-Bit Port, Aligned...........................................3-10 Long-Word Operand to 16-Bit Port, Aligned........................................3-12 Bus Operation................................................................................................3-14 Synchronous Operation with DSACK.....................................................3-14 Fast Termination Cycles..............................................................................3-15 Data Transfer Cycles........................................................................................3-16 Read Cycle.....................................................................................................3-16 Write Cycle.....................................................................................................3-18 Read-Modify-Write Cycle.............................................................................3-19 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com v 11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.4.1 3.4.4.2 3.4.4.3 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.7 Title Page Number CPU Space Cycles........................................................................................... 3-21 Breakpoint Acknowledge Cycle.................................................................3-22 LPSTOP Broadcast Cycle...........................................................................3-23 Module Base Address Register Access....................................................3-27 Interrupt Acknowledge Bus Cycles............................................................3-27 Interrupt Acknowledge Cycle--Terminated Normally........................3-27 Autovector Interrupt Acknowledge Cycle .............................................3-29 Spurious Interrupt Cycle..........................................................................3-30 Bus Exception Control Cycles........................................................................3-32 Bus Errors.......................................................................................................3-34 Retry Operation .............................................................................................3-36 Halt Operation ...............................................................................................3-38 Double Bus Fault ..........................................................................................3-39 Bus Arbitration...................................................................................................3-40 Bus Request...................................................................................................3-43 Bus Grant........................................................................................................3-43 Bus Grant Acknowledge..............................................................................3-43 Bus Arbitration Control.................................................................................3-44 Show Cycles..................................................................................................3-44 Reset Operation ................................................................................................3-46 Section 4 System Integration Module 4.1 4.2 4.2.1 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.2.4 4.2.2.5 4.2.2.6 4.2.2.6.1 4.2.2.6.2 4.2.2.7 4.2.3 4.2.3.1 4.2.3.2 4.2.3.3 4.2.4 4.2.4.1 vi Module Overview..............................................................................................4-1 Module Operation.............................................................................................4-2 Module Base Address Register Operation...............................................4-2 System Configuration and Protection Operation....................................4-3 System Configuration ..............................................................................4-5 Internal Bus Monitor .................................................................................4-6 Double Bus Fault Monitor........................................................................4-6 Spurious Interrupt Monitor ......................................................................4-6 Software Watchdog..................................................................................4-6 Periodic Interrupt Timer ...........................................................................4-7 Periodic Timer Period Calculation.....................................................4-8 Using the Periodic Timer as a Real-Time Clock .............................4-9 Simultaneous Interrupts by Sources in the SIM40.............................4-9 Clock Synthesizer Operation......................................................................4-9 Phase Comparator and Filter .................................................................4-11 Frequency Divider ....................................................................................4-12 Clock Control.............................................................................................4-13 Chip Select Operation .................................................................................4-13 Programmable Features..........................................................................4-14 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA 11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 4.2.4.2 4.2.5 4.2.5.1 4.2.5.2 4.2.6 4.2.7 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.3.3 4.3.4 4.3.4.1 4.3.4.2 4.3.4.3 4.3.5 4.3.5.1 4.3.5.2 4.3.5.3 4.3.5.4 4.3.5.5 4.3.5.6 4.3.5.7 4.4 4.4.1 4.4.2 4.4.3 Title Page Number Global Chip Select Operation ................................................................4-14 External Bus Interface Operation...............................................................4-15 Port A...........................................................................................................4-15 Port B...........................................................................................................4-16 Low-Power Stop ...........................................................................................4-17 Freeze.............................................................................................................4-17 Programming Model.........................................................................................4-18 Module Base Address Register (MBAR)...................................................4-20 System Configuration and Protection Registers.....................................4-21 Module Configuration Register (MCR)..................................................4-21 Autovector Register (AVR).......................................................................4-23 Reset Status Register (RSR)...................................................................4-23 Software Interrupt Vector Register (SWIV)...........................................4-24 System Protection Control Register (SYPCR).....................................4-24 Periodic Interrupt Control Register (PICR) ...........................................4-26 Periodic Interrupt Timer Register (PITR)...............................................4-27 Software Service Register (SWSR) ......................................................4-28 Clock Synthesizer Control Register (SYNCR) ........................................4-28 Chip Select Registers ..................................................................................4-29 Base Address Registers ..........................................................................4-30 Address Mask Registers..........................................................................4-31 Chip Select Registers Programming Example....................................4-33 External Bus Interface Control....................................................................4-33 Port A Pin Assignment Register 1 (PPARA1).......................................4-33 Port A Pin Assignment Register 2 (PPARA2).......................................4-34 Port A Data Direction Register (DDRA).................................................4-34 Port A Data Register (PORTA)................................................................4-34 Port B Pin Assignment Register (PPARB) ............................................4-35 Port B Data Direction Register (DDRB).................................................4-35 Port B Data Register (PORTB, PORTB1) ..............................................4-35 MC68340 Initialization Sequence.................................................................4-36 Startup ............................................................................................................4-36 SIM40 Module Configuration .....................................................................4-36 SIM40 Example Configuration Code........................................................4-38 Section 5 CPU32 5.1 5.1.1 5.1.2 5.1.3 MOTOROLA Overview.............................................................................................................5-1 Features..........................................................................................................5-2 Virtual Memory ..............................................................................................5-2 Loop Mode Instruction Execution ..............................................................5-3 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com vii 11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 5.1.4 5.1.5 5.1.6 5.1.7 5.1.7.1 5.1.7.2 5.1.8 5.1.9 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.1.1 5.3.1.1.1 5.3.1.1.2 5.3.1.2 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.3.3 5.3.3.4 5.3.3.5 5.3.3.6 5.3.3.7 5.3.3.8 5.3.3.9 5.3.3.10 5.3.4 5.3.4.1 5.3.4.2 5.3.4.3 5.3.4.4 5.3.4.5 5.3.5 5.3.6 5.4 5.4.1 5.4.2 5.4.2.1 5.4.2.2 viii Title Page Number Vector Base Register....................................................................................5-4 Exception Handling......................................................................................5-4 Addressing Modes........................................................................................5-5 Instruction Set................................................................................................5-5 Table Lookup and Interpolate Instructions...........................................5-7 Low-Power STOP Instruction .................................................................5-7 Processing States.........................................................................................5-7 Privilege States.............................................................................................5-7 Architecture Summary .....................................................................................5-8 Programming Model.....................................................................................5-8 Registers.........................................................................................................5-10 Instruction Set....................................................................................................5-11 M68000 Family Compatibility.....................................................................5-11 New Instructions........................................................................................5-11 Low-Power Stop (LPSTOP)................................................................5-11 Table Lookup and Interpolation (TBL)..............................................5-12 Unimplemented Instructions...................................................................5-12 Instruction Format and Notation.................................................................5-12 Instruction Summary ....................................................................................5-15 Condition Code Register.........................................................................5-20 Data Movement Instructions ...................................................................5-21 Integer Arithmetic Operations.................................................................5-22 Logic Instructions......................................................................................5-24 Shift and Rotate Instructions...................................................................5-24 Bit Manipulation Instructions...................................................................5-25 Binary-Coded Decimal (BCD) Instructions ..........................................5-26 Program Control Instructions..................................................................5-26 System Control Instructions....................................................................5-27 Condition Tests .........................................................................................5-29 Using the TBL Instructions ..........................................................................5-29 Table Example 1: Standard Usage.......................................................5-30 Table Example 2: Compressed Table ..................................................5-31 Table Example 3: 8-Bit Independent Variable ....................................5-32 Table Example 4: Maintaining Precision..............................................5-34 Table Example 5: Surface Interpolations.............................................5-36 Nested Subroutine Calls.............................................................................5-36 Pipeline Synchronization with the NOP Instruction................................5-36 Processing States.............................................................................................5-36 State Transitions...........................................................................................5-37 Privilege Levels.............................................................................................5-37 Supervisor Privilege Level......................................................................5-37 User Privilege Level.................................................................................5-39 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA 11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 5.4.2.3 5.5 5.5.1 5.5.1.1 5.5.1.2 5.5.1.3 5.5.1.4 5.5.2 5.5.2.1 5.5.2.2 5.5.2.3 5.5.2.4 5.5.2.5 5.5.2.6 5.5.2.7 5.5.2.8 5.5.2.9 5.5.2.10 5.5.2.11 5.5.2.12 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.1.2 5.5.3.1.3 5.5.3.1.4 5.5.3.2 5.5.3.2.1 5.5.3.2.2 5.5.3.2.3 5.5.3.2.4 5.5.3.2.5 5.5.3.2.6 5.5.3.2.7 5.5.4 5.5.4.1 5.5.4.2 5.5.4.3 5.6 5.6.1 5.6.1.1 5.6.1.2 MOTOROLA Title Page Number Changing Privilege Level........................................................................5-39 Exception Processing ......................................................................................5-39 Exception Vectors.........................................................................................5-40 Types of Exceptions .................................................................................5-41 Exception Processing Sequence ..........................................................5-41 Exception Stack Frame............................................................................5-42 Multiple Exceptions ..................................................................................5-42 Processing of Specific Exceptions ............................................................5-44 Reset ...........................................................................................................5-44 Bus Error.....................................................................................................5-46 Address Error.............................................................................................5-46 Instruction Traps........................................................................................5-47 Software Breakpoints...............................................................................5-47 Hardware Breakpoints.............................................................................5-48 Format Error...............................................................................................5-48 Illegal or Unimplemented Instructions ..................................................5-48 Privilege Violations...................................................................................5-49 Tracing........................................................................................................5-50 Interrupts.....................................................................................................5-51 Return from Exception..............................................................................5-52 Fault Recovery...............................................................................................5-53 Types of Faults ..........................................................................................5-55 Type I--Released Write Faults...........................................................5-55 Type II--Prefetch, Operand, RMW, and MOVEP Faults.................5-56 Type III--Faults During MOVEM Operand Transfer .......................5-57 Type IV--Faults During Exception Processing ...............................5-57 Correcting a Fault .....................................................................................5-57 Type I--Completing Released Writes via Software .......................5-57 Type I--Completing Released Writes via RTE................................5-57 Type II--Correcting Faults via RTE....................................................5-58 Type III--Correcting Faults via Software..........................................5-58 Type III--Correcting Faults by Conversion and Restart.................5-58 Type III--Correcting Faults via RTE...................................................5-59 Type IV--Correcting Faults via Software .........................................5-59 CPU32 Stack Frames ..................................................................................5-60 Four-Word Stack Frame ..........................................................................5-60 Six-Word Stack Frame.............................................................................5-60 Bus Error Stack Frame.............................................................................5-60 Development Support......................................................................................5-63 CPU32 Integrated Development Support................................................5-63 Background Debug Mode (BDM) Overview ........................................5-64 Deterministic Opcode Tracking Overview............................................5-64 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com ix 11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 5.6.1.3 5.6.2 5.6.2.1 5.6.2.2 5.6.2.2.1 5.6.2.2.2 5.6.2.2.3 5.6.2.3 5.6.2.4 5.6.2.5 5.6.2.5.1 5.6.2.5.2 5.6.2.5.3 5.6.2.6 5.6.2.7 5.6.2.7.1 5.6.2.7.2 5.6.2.8 5.6.2.8.1 5.6.2.8.2 5.6.2.8.3 5.6.2.8.4 5.6.2.8.5 5.6.2.8.6 5.6.2.8.7 5.6.2.8.8 5.6.2.8.9 5.6.2.8.10 5.6.2.8.11 5.6.2.8.12 5.6.2.8.13 5.6.2.8.14 5.6.2.8.15 5.6.2.8.16 5.6.3 5.6.3.1 5.6.3.2 5.6.3.3 5.7 5.7.1 5.7.1.1 5.7.1.2 x Title Page Number On-Chip Hardware Breakpoint Overview.............................................5-64 Background Debug Mode...........................................................................5-65 Enabling BDM ...........................................................................................5-65 BDM Sources ............................................................................................5-66 External BKPT Signal..........................................................................5-66 BGND Instruction ..................................................................................5-66 Double Bus Fault. .................................................................................5-66 Entering BDM ............................................................................................5-66 Command Execution................................................................................5-67 BDM Registers...........................................................................................5-67 Fault Address Register (FAR) .............................................................5-67 Return Program Counter (RPC) .........................................................5-67 Current Instruction Program Counter (PCC)....................................5-67 Returning from BDM.................................................................................5-68 Serial Interface..........................................................................................5-68 CPU Serial Logic..................................................................................5-69 Development System Serial Logic....................................................5-71 Command Set ...........................................................................................5-73 Command Format.................................................................................5-73 Command Sequence Diagram..........................................................5-74 Command Set Summary.....................................................................5-75 Read A/D Register (RAREG/RDREG)................................................5-76 Write A/D Register (WAREG/WDREG) ..............................................5-77 Read System Register (RSREG)........................................................5-77 Write System Register (WSREG).......................................................5-78 Read Memory Location (READ).........................................................5-79 Write Memory Location (WRITE)........................................................5-79 Dump Memory Block (DUMP). ...........................................................5-80 Fill Memory Block (FILL)......................................................................5-82 Resume Execution (GO)......................................................................5-83 Call User Code (CALL)........................................................................5-83 Reset Peripherals (RST)......................................................................5-85 No Operation (NOP).............................................................................5-85 Future Commands................................................................................5-86 Deterministic Opcode Tracking..................................................................5-86 Instruction Fetch (IFETCH)......................................................................5-86 Instruction Pipe (IPIPE)...........................................................................5-87 Opcode Tracking during Loop Mode ....................................................5-88 Instruction Execution Timing...........................................................................5-88 Resource Scheduling ..................................................................................5-88 Microsequencer ........................................................................................5-89 Instruction Pipeline...................................................................................5-89 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA 11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 5.7.1.3 5.7.1.3.1 5.7.1.3.2 5.7.1.3.3 5.7.1.4 5.7.1.5 5.7.1.6 5.7.1.7 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 5.7.3 5.7.3.1 5.7.3.2 5.7.3.3 5.7.3.4 5.7.3.5 5.7.3.6 5.7.3.7 5.7.3.8 5.7.3.9 5.7.3.10 5.7.3.11 5.7.3.12 5.7.3.13 5.7.3.14 Title Page Number Bus Controller Resources .......................................................................5-89 Prefetch Controller................................................................................5-90 Write Pending Buffer. ...........................................................................5-90 Microbus Controller..............................................................................5-91 Instruction Execution Overlap.................................................................5-91 Effects of Wait States................................................................................5-92 Instruction Execution Time Calculation ................................................5-92 Effects of Negative Tails ..........................................................................5-93 Instruction Stream Timing Examples ........................................................5-94 Timing Example 1--Execution Overlap................................................5-94 Timing Example 2--Branch Instructions ..............................................5-95 Timing Example 3--Negative Tails.......................................................5-96 Instruction Timing Tables ............................................................................5-97 Fetch Effective Address ...........................................................................5-99 Calculate Effective Address....................................................................5-100 MOVE Instruction ......................................................................................5-101 Special-Purpose MOVE Instruction.......................................................5-101 Arithmetic/Logic Instructions...................................................................5-102 Immediate Arithmetic/Logic Instructions...............................................5-105 Binary-Coded Decimal and Extended Instructions ............................5-106 Single Operand Instructions...................................................................5-107 Shift/Rotate Instructions...........................................................................5-108 Bit Manipulation Instructions...................................................................5-109 Conditional Branch Instructions.............................................................5-110 Control Instructions...................................................................................5-111 Exception-Related Instructions and Operations..................................5-111 Save and Restore Operations................................................................5-111 Section 6 DMA Controller Module 6.1 6.2 6.2.1 6.2.2 6.2.3 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.2 6.3.2.1 MOTOROLA DMA Module Overview....................................................................................6-2 DMA Module Signal Definitions.....................................................................6-4 DMA Request (DREQ)................................................................................6-4 DMA Acknowledge (DACK)......................................................................6-4 DMA Done (DONE).....................................................................................6-4 Transfer Request Generation .........................................................................6-4 Internal Request Generation.......................................................................6-4 Internal Request, Maximum Rate...........................................................6-5 Internal Request, Limited Rate ...............................................................6-5 External Request Generation .....................................................................6-5 External Burst Mode.................................................................................6-5 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xi 11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 6.3.2.2 6.4 6.4.1 6.4.1.1 6.4.1.2 6.4.2 6.4.2.1 6.4.2.2 6.5 6.6 6.6.1 6.6.2 6.6.2.1 6.6.2.2 6.6.3 6.6.3.1 6.6.3.2 6.6.3.3 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.7 6.7.8 6.8 6.9 6.9.1 6.9.1.1 6.9.1.2 6.9.2 Title Page Number External Cycle Steal Mode .....................................................................6-5 Data Transfer Modes........................................................................................6-6 Single-Address Mode..................................................................................6-6 Single-Address Read...............................................................................6-7 Single-Address Write...............................................................................6-9 Dual-Address Mode .....................................................................................6-12 Dual-Address Read..................................................................................6-12 Dual-Address Write ..................................................................................6-14 Bus Arbitration...................................................................................................6-18 DMA Channel Operation.................................................................................6-18 Channel Initialization and Startup.............................................................6-18 Data Transfers...............................................................................................6-19 Internal Request Transfers......................................................................6-19 External Request Transfers.....................................................................6-19 Channel Termination ...................................................................................6-20 Channel Termination ...............................................................................6-20 Interrupt Operation....................................................................................6-20 Fast Termination Option ..........................................................................6-20 Register Description.........................................................................................6-22 Module Configuration Register (MCR)......................................................6-23 Interrupt Register (INTR)..............................................................................6-26 Channel Control Register (CCR) ...............................................................6-26 Channel Status Register (CSR).................................................................6-30 Function Code Register (FCR) ...................................................................6-32 Source Address Register (SAR) ................................................................6-33 Destination Address Register (DAR).........................................................6-33 Byte Transfer Counter Register (BTC) ......................................................6-34 Data Packing .....................................................................................................6-35 DMA Channel Initialization Sequence .........................................................6-36 DMA Channel Configuration ......................................................................6-36 DMA Channel Operation in Single-Address Mode............................6-37 DMA Channel Operation in Dual-Address Mode ...............................6-37 DMA Channel Example Configuration Code ..........................................6-38 Section 7 Serial Module 7.1 7.1.1 7.1.2 7.1.3 7.1.4 xii Module Overview..............................................................................................7-2 Serial Communication Channels A and B...............................................7-3 Baud Rate Generator Logic ........................................................................7-3 Internal Channel Control Logic..................................................................7-3 Interrupt Control Logic .................................................................................7-3 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA 11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 7.1.5 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.8.1 7.2.8.2 7.2.9 7.2.9.1 7.2.9.2 7.2.10 7.2.11 7.2.12 7.2.12.1 7.2.12.2 7.2.13 7.2.13.1 7.2.13.2 7.2.13.3 7.3 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3 7.3.3 7.3.3.1 7.3.3.2 7.3.3.3 7.3.4 7.3.5 7.3.5.1 7.3.5.2 7.3.5.3 7.4 7.4.1 7.4.1.1 MOTOROLA Title Page Number Comparison of Serial Module to MC68681.............................................7-4 Serial Module Signal Definitions................................................................... 7-4 Crystal Input or External Clock (X1) ..........................................................7-5 Crystal Output (X2) .......................................................................................7-5 External Input (SCLK)..................................................................................7-6 Channel A Transmitter Serial Data Output (TxDA).................................7-6 Channel A Receiver Serial Data Input (RxDA)........................................7-6 Channel B Transmitter Serial Data Output (TxDB).................................7-6 Channel B Receiver Serial Data Input (RxDB)........................................7-6 Channel A Request-To-Send (RTSA) ......................................................7-6 RTSA...........................................................................................................7-6 OP0..............................................................................................................7-6 Channel B Request-To-Send (RTSB).......................................................7-6 RTSB ...........................................................................................................7-7 OP1..............................................................................................................7-7 Channel A Clear-To-Send (CTSA) ...........................................................7-7 Channel B Clear-To-Send (CTSB)............................................................7-7 Channel A Transmitter Ready (TRDYA).................................................7-7 TRDYA......................................................................................................7-7 OP6..............................................................................................................7-7 Channel A Receiver Ready (RRDYA).....................................................7-7 RRDYA......................................................................................................7-7 FFULLA.......................................................................................................7-7 OP4..............................................................................................................7-7 Operation............................................................................................................7-8 Baud Rate Generator ...................................................................................7-8 Transmitter and Receiver Operating Modes............................................7-8 Transmitter .................................................................................................7-10 Receiver......................................................................................................7-11 FIFO Stack..................................................................................................7-12 Looping Modes .............................................................................................7-14 Automatic Echo Mode..............................................................................7-14 Local Loopback Mode .............................................................................7-14 Remote Loopback Mode .........................................................................7-14 Multidrop Mode .............................................................................................7-15 Bus Operation................................................................................................7-17 Read Cycles...............................................................................................7-17 Write Cycles...............................................................................................7-17 Interrupt Acknowledge Cycles................................................................7-17 Register Description and Programming .......................................................7-17 Register Description.....................................................................................7-17 Module Configuration Register (MCR)..................................................7-19 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xiii 11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 7.4.1.2 7.4.1.3 7.4.1.4 7.4.1.5 7.4.1.6 7.4.1.7 7.4.1.8 7.4.1.9 7.4.1.10 7.4.1.11 7.4.1.12 7.4.1.13 7.4.1.14 7.4.1.15 7.4.1.16 7.4.1.17 7.4.2 7.4.2.1 7.4.2.2 7.4.2.3 7.5 7.5.1 7.5.2 Title Page Number Interrupt Level Register (ILR)..................................................................7-21 Interrupt Vector Register (IVR)................................................................7-21 Mode Register 1 (MR1)............................................................................7-22 Status Register (SR).................................................................................7-24 Clock-Select Register (CSR)..................................................................7-26 Command Register (CR) .........................................................................7-27 Receiver Buffer (RB).................................................................................7-30 Transmitter Buffer (TB).............................................................................7-30 Input Port Change Register (IPCR)........................................................7-31 Auxiliary Control Register (ACR)............................................................7-32 Interrupt Status Register (ISR)................................................................7-32 Interrupt Enable Register (IER)...............................................................7-34 Input Port (IP).............................................................................................7-35 Output Port Control Register (OPCR)....................................................7-35 Output Port Data Register (OP) ..............................................................7-37 Mode Register 2 (MR2)............................................................................7-37 Programming.................................................................................................7-40 Serial Module Initialization .....................................................................7-40 I/O Driver Example....................................................................................7-40 Interrupt Handling.....................................................................................7-40 Serial Module Initialization Sequence .........................................................7-46 Serial Module Configuration ......................................................................7-46 Serial Module Example Configuration Code ..........................................7-47 Section 8 Timer Modules 8.1 8.1.1 8.1.1.1 8.1.1.2 8.1.1.3 8.1.1.4 8.1.2 8.1.3 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.2 xiv Module Overview..............................................................................................8-1 Timer and Counter Functions.....................................................................8-2 Prescaler and Counter.............................................................................8-2 Timeout Detection.....................................................................................8-2 Comparator................................................................................................8-2 Clock Selection Logic..............................................................................8-3 Internal Control Logic...................................................................................8-3 Interrupt Control Logic .................................................................................8-4 Timer Modules Signal Definitions .................................................................8-4 Timer Input (TIN1, TIN2) ..............................................................................8-5 Timer Gate (TGATE1, TGATE2)................................................................8-6 Timer Output (TOUT1, TOUT2)...................................................................8-6 Operating Modes ..............................................................................................8-6 Input Capture/Output Compare..................................................................8-6 Square-Wave Generator.............................................................................8-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA 11/2/95 SECTION 1: OVERVIEW Freescale Semiconductor, Inc. UM Rev 1 TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.9.1 8.3.9.2 8.3.9.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.5 8.5.1 8.5.2 Title Page Number Variable Duty-Cycle Square-Wave Generator........................................8-9 Variable-Width Single-Shot Pulse Generator.........................................8-10 Pulse-Width Measurement..........................................................................8-12 Period Measurement....................................................................................8-13 Event Count ...................................................................................................8-14 Timer Bypass.................................................................................................8-16 Bus Operation................................................................................................8-17 Read Cycles...............................................................................................8-17 Write Cycles...............................................................................................8-17 Interrupt Acknowledge Cycles................................................................8-17 Register Description.........................................................................................8-17 Module Configuration Register (MCR)......................................................8-18 Interrupt Register (IR) ...................................................................................8-20 Control Register (CR)...................................................................................8-20 Status Register (SR).....................................................................................8-23 Counter Register (CNTR) ............................................................................8-25 Preload 1 Register (PREL1)........................................................................ 8-25 Preload 2 Register (PREL2)........................................................................ 8-26 Compare Register (COM)............................................................................8-26 Timer Module Initialization Sequence..........................................................8-27 Timer Module Configuration.......................................................................8-27 Timer Module Example Configuration Code...........................................8-28 Section 9 IEEE 1149.1 Test Access Port 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.5 9.6 Overview.............................................................................................................9-1 TAP Controller...................................................................................................9-2 Boundary Scan Register .................................................................................9-3 Instruction Register...........................................................................................9-9 EXTEST (000) ...............................................................................................9-10 SAMPLE/PRELOAD (001) ..........................................................................9-10 BYPASS (X1X, 101).....................................................................................9-11 HI-Z (100) .......................................................................................................9-11 MC68340 Restrictions......................................................................................9-11 Non-IEEE 1149.1 Operation...........................................................................9-12 Section 10 Applications 10.1 10.1.1 MOTOROLA Minimum System Configuration...................................................................10-1 Processor Clock Circuitry..........................................................................10-1 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xv 11/2/95 SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 TABLE OF CONTENTS (Concluded) Freescale Semiconductor, Inc... Paragraph Number 10.1.2 10.1.3 10.1.4 10.1.5 10.2 10.2.1 10.2.2 10.2.3 10.2.4 Title Page Number 10.3 10.3.1 10.3.2 Reset Circuitry .............................................................................................10-3 SRAM Interface ...........................................................................................10-3 ROM Interface..............................................................................................10-4 Serial Interface............................................................................................10-4 Memory Interface Information.......................................................................10-5 Using an 8-Bit Boot ROM...........................................................................10-5 Access Time Calculations.........................................................................10-6 Calculating Frequency-Adjusted Output ................................................10-7 Interfacing an 8-Bit Device to 16-Bit Memory Using Single-Address DMA Mode..................................................................10-10 Power Consumption Considerations..........................................................10-10 MC68340 Power Reduction at 5V ..........................................................10-11 MC68340V (3.3 V) .....................................................................................10-13 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 Section 11 Electrical Characteristics Maximum Rating .............................................................................................11-1 Thermal Characteristics.................................................................................11-1 Power Considerations ...................................................................................11-2 AC Electrical Specification Definitions .......................................................11-2 DC Electrical Specifications .........................................................................11-5 AC Electrical Specifications Control Timing..............................................11-6 AC Timing Specifications..............................................................................11-8 DMA Module AC Electrical Specifications.................................................11-19 Timer Module Electrical Specifications ......................................................11-20 Serial Module Electrical Specifications......................................................11-22 IEEE 1149.1 Electrical Specifications.........................................................11-25 Section 12 Ordering Information and Mechanical Data 12.1 12.2 12.2.1 12.2.2 12.3 12.3.1 12.3.2 Standard MC68340 Ordering Information .................................................12-1 Pin Assignment ...............................................................................................12-2 144-Lead Ceramic Quad Flat Pack (FE Suffix).....................................12-2 145-Lead Plastic Pin Grid Array (RP Suffix) ..........................................12-4 Package Dimensions.....................................................................................12-6 FE Suffix .......................................................................................................12-6 RP Suffix.......................................................................................................12-7 Index xvi MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA SECTION 1: OVERVIEW Freescale Semiconductor, Inc. 11/2/95 UM Rev 1 LIST OF ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number Title Page Number 1-1 Block Diagram.........................................................................................................1-1 2-1 Functional Signal Groups .....................................................................................2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 Input Sample Window............................................................................................3-2 MC68340 Interface to Various Port Sizes..........................................................3-7 Long-Word Operand Read Timing from 8-Bit Port............................................3-11 Long-Word Operand Write Timing to 8-Bit Port.................................................3-12 Long-Word and Word Read and Write Timing--16-Bit Port ...........................3-13 Fast Termination Timing........................................................................................3-15 Word Read Cycle Flowchart .................................................................................3-16 Word Write Cycle Flowchart..................................................................................3-18 Read-Modify-Write Cycle Timing .........................................................................3-19 CPU Space Address Encoding............................................................................3-21 Breakpoint Operation Flowchart ..........................................................................3-24 Breakpoint Acknowledge Cycle Timing (Opcode Returned)..........................3-25 Breakpoint Acknowledge Cycle Timing (Exception Signaled) ......................3-26 Interrupt Acknowledge Cycle Flowchart.............................................................3-28 Interrupt Acknowledge Cycle Timing ..................................................................3-29 Autovector Operation Timing................................................................................3-31 Bus Error without DSACK ...................................................................................3-35 Late Bus Error with DSACK ................................................................................3-36 Retry Sequence ......................................................................................................3-37 Late Retry Sequence .............................................................................................3-38 HALT Timing............................................................................................................3-39 Bus Arbitration Flowchart for Single Request....................................................3-41 Bus Arbitration Timing Diagram--Idle Bus Case..............................................3-42 Bus Arbitration Timing Diagram--Active Bus Case .........................................3-42 Bus Arbitration State Diagram..............................................................................3-45 Show Cycle Timing Diagram................................................................................3-46 Timing for External Devices Driving RESET ......................................................3-47 Power-Up Reset Timing Diagram........................................................................3-48 4-1 4-2 4-3 4-4 SIM40 Module Register Block..............................................................................4-3 System Configuration and Protection Function ................................................4-5 Software Watchdog Block Diagram ....................................................................4-7 Clock Block Diagram for Crystal Operation .......................................................4-10 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xvii SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 11/2/95 LIST OF ILLUSTRATIONS (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 4-5 4-6 4-7 4-8 MC68340 Crystal Oscillator..................................................................................4-10 Clock Block Diagram for External Oscillator Operation...................................4-11 Full Interrupt Request Multiplexer........................................................................4-16 SIM40 Programming Model..................................................................................4-19 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 CPU32 Block Diagram...........................................................................................5-3 Loop Mode Instruction Sequence .......................................................................5-3 User Programming Model.....................................................................................5-9 Supervisor Programming Model Supplement ..................................................5-9 Status Register........................................................................................................5-10 Instruction Word General Format.........................................................................5-12 Table Example 1.....................................................................................................5-30 Table Example 2.....................................................................................................5-31 Table Example 3.....................................................................................................5-33 Exception Stack Frame..........................................................................................5-42 Reset Operation Flowchart....................................................................................5-45 Format $0--Four-Word Stack Frame..................................................................5-60 Format $2--Six-Word Stack Frame ....................................................................5-60 Internal Transfer Count Register..........................................................................5-61 Format $C--BERR Stack for Prefetches and Operands..................................5-62 Format $C--BERR Stack on MOVEM Operand................................................5-62 Format $C--Four- and Six-Word BERR Stack..................................................5-63 In-Circuit Emulator Configuration ........................................................................5-64 Bus State Analyzer Configuration .......................................................................5-64 BDM Block Diagram...............................................................................................5-65 BDM Command Execution Flowchart.................................................................5-68 Debug Serial I/O Block Diagram..........................................................................5-70 Serial Interface Timing Diagram..........................................................................5-71 BKPT Timing for Single Bus Cycle......................................................................5-72 BKPT Timing for Forcing BDM .............................................................................5-72 BKPT/DSCLK Logic Diagram ..............................................................................5-72 Command-Sequence Diagram............................................................................5-75 Functional Model of Instruction Pipeline ............................................................5-87 Instruction Pipeline Timing Diagram...................................................................5-88 Block Diagram of Independent Resources ........................................................5-90 Simultaneous Instruction Execution....................................................................5-91 Attributed Instruction Times...................................................................................5-92 Example 1--Instruction Stream ...........................................................................5-95 Example 2--Branch Taken...................................................................................5-95 Example 2--Branch Not Taken............................................................................5-96 Example 3--Branch Negative Tail ......................................................................5-96 xviii MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA SECTION 1: OVERVIEW Freescale Semiconductor, Inc. 11/2/95 UM Rev 1 LIST OF ILLUSTRATIONS (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 DMA Block Diagram...............................................................................................6-1 Single-Address Transfers .....................................................................................6-3 Dual-Address Transfer...........................................................................................6-3 DMA External Connections to Serial Module....................................................6-6 Single-Address Read Timing (External Burst) ..................................................6-8 Single-Address Read Timing (Cycle Steal).......................................................6-9 Single-Address Write Timing (External Burst)...................................................6-10 Single-Address Write Timing (Cycle Steal).......................................................6-11 Dual-Address Read Timing (External Burst--Source Requesting)...............6-13 Dual-Address Read Timing (Cycle Steal--Source Requesting)...................6-14 Dual-Address Write Timing (External Burst--Destination Requesting)........6-16 Dual-Address Write Timing (Cycle Steal--Destination Requesting)............6-17 Fast Termination Option (Cycle Steal)................................................................6-21 Fast Termination Option (External Burst--Source Requesting) ....................6-22 DMA Module Programming Model......................................................................6-23 Packing and Unpacking of Operands.................................................................6-35 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 Simplified Block Diagram......................................................................................7-1 External and Internal Interface Signals ..............................................................7-5 Baud Rate Generator Block Diagram..................................................................7-8 Transmitter and Receiver Functional Diagram.................................................. 7-9 Transmitter Timing Diagram .................................................................................7-10 Receiver Timing Diagram......................................................................................7-12 Looping Modes Functional Diagram...................................................................7-15 Multidrop Mode Timing Diagram .........................................................................7-16 Serial Module Programming Model....................................................................7-19 Serial Module Programming Flowchart..............................................................7-41 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 Simplified Block Diagram......................................................................................8-1 Timer Functional Diagram.....................................................................................8-3 External and Internal Interface Signals ..............................................................8-5 Input Capture/Output Compare Mode.................................................................8-7 Square-Wave Generator Mode............................................................................8-8 Variable Duty-Cycle Square-Wave Generator Mode ......................................8-10 Variable-Width Single-Shot Pulse Generator Mode........................................8-11 Pulse-Width Measurement Mode ........................................................................8-12 Period Measurement Mode ..................................................................................8-14 Event Count Mode..................................................................................................8-15 Timer Module Programming Model.....................................................................8-18 9-1 9-2 Test Access Port Block Diagram..........................................................................9-2 TAP Controller State Machine..............................................................................9-3 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xix SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 11/2/95 LIST OF ILLUSTRATIONS (Continued) Figure Number Freescale Semiconductor, Inc... 9-3 9-4 9-5 9-6 9-7 9-8 9-9 Title Page Number Output Latch Cell (O.Latch)...................................................................................9-7 Input Pin Cell (I.Pin)................................................................................................9-7 Active-High Output Control Cell (IO.Ctl1)...........................................................9-8 Active-Low Output Control Cell (IO.Ctl0)............................................................9-8 Bidirectional Data Cell (IO.Cell)...........................................................................9-9 General Arrangement for Bidirectional Pins......................................................9-9 Bypass Register ......................................................................................................9-11 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 Minimum System Configuration Block Diagram.............................................10-1 Sample Crystal Circuit.........................................................................................10-2 Statek Corporation Crystal Circuit.....................................................................10-2 XFC and VCCSYN Capacitor Connections........................................................10-3 SRAM Interface .....................................................................................................10-3 ROM Interface........................................................................................................10-4 Serial Interface......................................................................................................10-5 External Circuitry for 8-Bit Boot ROM ................................................................10-5 8-Bit Boot ROM Timing.........................................................................................10-6 Access Time Computation Diagram..................................................................10-6 Signal Relationships to CLKOUT ......................................................................10-7 Signal Width Specifications................................................................................10-8 Skew between Two Outputs...............................................................................10-9 Circuitry for Interfacing 8-Bit Device to 16-Bit Memory in Single-Address DMA Mode..............................................................................10-10 10-15 MC68340 Current vs. Activity at 5 V..................................................................10-11 10-16 MC68340 Current vs. Voltage/Temperature....................................................10-12 10-17 MC68340 Current vs. Clock Frequency at 5 V................................................10-12 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 xx Drive Levels and Test Points for AC Specifications.......................................11-4 Read Cycle Timing Diagram...............................................................................11-11 Write Cycle Timing Diagram...............................................................................11-12 Fast Termination Read Cycle Timing Diagram ...............................................11-13 Fast Termination Write Cycle Timing Diagram................................................11-14 Bus Arbitation Timing--Active Bus Case .........................................................11-15 Bus Arbitration Timing--Idle Bus Case ............................................................11-16 Show Cycle Timing Diagram..............................................................................11-16 IACK Cycle Timing Diagram...............................................................................11-17 Background Debug Mode Serial Port Timing .................................................11-18 Background Debug Mode FREEZE Timing .....................................................11-18 DMA Signal Timing Diagram..............................................................................11-19 Timer Module Clock Signal Timing Diagram ..................................................11-20 Timer Module Signal Timing Diagram..............................................................11-21 Serial Module General Timing Diagram ..........................................................11-22 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA SECTION 1: OVERVIEW Freescale Semiconductor, Inc. 11/2/95 UM Rev 1 LIST OF ILLUSTRATIONS (Concluded) Figure Number Serial Module Asynchronous Mode Timing (X1)............................................11-23 Serial Module Asynchronous Mode Timing (SCLK-16X)............................11-23 Serial Module Synchronous Mode Timing Diagram .....................................11-23 Test Clock Input Timing Diagram.......................................................................11-25 Boundary Scan Timing Diagram .......................................................................11-26 Test Access Port Timing Diagram......................................................................11-26 Freescale Semiconductor, Inc... 11-16 11-17 11-18 11-19 11-20 11-21 Title Page Number MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xxi SECTION 1:Semiconductor, OVERVIEW Freescale Inc. UM Rev.1.0 11/2/95 LIST OF TABLES Freescale Semiconductor, Inc... Table Number Title Page Number 2-1 2-2 2-3 2-4 2-5 Signal Index.............................................................................................................2-2 Address Space Encoding .....................................................................................2-5 DSACK Encoding.................................................................................................2-6 SIZx Signal Encoding............................................................................................2-7 Signal Summary.....................................................................................................2-14 3-1 3-2 3-3 3-4 SIZx Signal Encoding............................................................................................3-3 Address Space Encoding .....................................................................................3-3 DSACK Encoding.................................................................................................3-5 DSACK, BERR, and HALT Assertion Results..................................................3-33 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 Clock Operating Modes.........................................................................................4-9 System Frequencies from 32.768-kHz Reference............................................4-13 Clock Control Signals............................................................................................4-13 Port A Pin Assignment Register ...........................................................................4-15 Port B Pin Assignment Register ...........................................................................4-16 SHENx Control Bits................................................................................................4-22 Deriving Software Watchdog Timeout................................................................4-25 BMTx Encoding.......................................................................................................4-26 PIRQL Encoding......................................................................................................4-26 DDx Encoding .........................................................................................................4-32 PSx Encoding..........................................................................................................4-32 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 Instruction Set..........................................................................................................5-6 Instruction Set Summary.......................................................................................5-16 Condition Code Computations.............................................................................5-20 Data Movement Operations..................................................................................5-21 Integer Arithmetic Operations...............................................................................5-23 Logic Operations.....................................................................................................5-24 Shift and Rotate Operations..................................................................................5-25 Bit Manipulation Operations .................................................................................5-25 Binary-Coded Decimal Operations .....................................................................5-26 Program Control Operations.................................................................................5-26 System Control Operations...................................................................................5-28 Condition Tests .......................................................................................................5-29 Standard Usage Entries........................................................................................5-30 Compressed Table Entries ...................................................................................5-32 xxii MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA SECTION 1: OVERVIEW Freescale Semiconductor, Inc. 11/2/95 UM Rev 1 LIST OF TABLES (Continued) Freescale Semiconductor, Inc... Table Number Title Page Number 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 8-Bit Independent Variable Entries .....................................................................5-33 Exception Vector Assignments.............................................................................5-40 Exception Priority Groups......................................................................................5-43 Tracing Control........................................................................................................5-50 BDM Source Summary..........................................................................................5-67 Polling the BDM Entry Source..............................................................................5-68 CPU Generated Message Encoding...................................................................5-70 Size Field Encoding...............................................................................................5-74 BDM Command Summary....................................................................................5-77 Register Field for RSREG and WSREG..............................................................5-79 6-1 6-2 6-3 6-4 6-5 6-6 FRZx Control Bits ....................................................................................................6-24 SSIZEx Encoding ...................................................................................................6-28 DSIZEx Encoding ...................................................................................................6-29 REQx Encoding.......................................................................................................6-29 BBx Encoding and Bus Bandwidth......................................................................6-29 Address Space Encoding .....................................................................................6-32 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 FRZx Control Bits ....................................................................................................7-20 PMx and PT Control Bits........................................................................................7-23 B/Cx Control Bits.....................................................................................................7-24 RCSx Control Bits...................................................................................................7-26 TCSx Control Bits ...................................................................................................7-27 MISCx Control Bits .................................................................................................7-28 TCx Control Bits ......................................................................................................7-29 RCx Control Bits......................................................................................................7-30 CMx Control Bits .....................................................................................................7-38 SBx Control Bits......................................................................................................7-39 8-1 8-2 8-3 8-4 8-5 8-6 OCx Encoding .........................................................................................................8-17 FRZx Control Bits ....................................................................................................8-19 IEx Encoding............................................................................................................8-21 POTx Encoding .......................................................................................................8-22 MODEx Encoding ...................................................................................................8-22 OCx Encoding .........................................................................................................8-22 9-1 9-2 9-3 Boundary Scan Control Bits .................................................................................9-4 Boundary Scan Bit Definitions .............................................................................9-5 Instructions...............................................................................................................9-10 10-1 10-2 Memory Access Times at 16.78 MHz................................................................10-7 Typical Electrical Characteristics.......................................................................10-13 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xxiii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 1 DEVICE OVERVIEW The MC68340 is a high-performance 32-bit integrated processor with direct memory access (DMA), combining an enhanced M68000-compatible processor, 32-bit DMA, and other peripheral subsystems on a single integrated circuit. The MC68340 CPU32 delivers 32-bit CISC processor performance from a lower cost 16-bit memory system. The combination of peripherals offered in the MC68340 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing. Systems requiring very high-speed block transfers of data can especially benefit from the MC68340. The MC68340's high level of functional integration results in significant reductions in component count, power consumption, board space, and cost while yielding much higher system reliability and shorter design time. The 3.3-V MC68340V is particularly attractive to applications requiring a very tight power budget. Complete code compatibility with the MC68000 and MC68010 affords the designer access to a broad base of established realtime kernels, operating systems, languages, applications, and development tools--many oriented towards embedded control. SYSTEM INTEGRATION MODULE (SIM40) SYSTEM PROTECTION TWOCHANNEL SERIAL I/O CPU32 68020- BASED PROCESSOR CHIP SELECTS AND WAIT STATES CLOCK SYNTHESIZER INTERMODULE BUS EXTERNAL BUS INTERFACE BUS ARBITRATION TWO-CHANNEL DMA CONTROLLER TIMER TIMER IEEE TEST Figure 1-1. Block Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. The primary features of the MC68340, illustrated in Figure 1-1, are as follows: * High Functional Integration on a Single Piece of Silicon * CPU32--MC68020-Derived 32-Bit Central Processor Unit -- Upward Object-Code Compatible with MC68000 and MC68010 -- Additional MC68020 Instructions and Addressing Modes -- Unique Embedded Control Instructions -- Fast Two-Clock Register Instructions--10,045 Dhrystones * Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers -- Single- or Dual-Address Transfers -- 32-Bit Addresses and Counters -- 8-, 16-, and 32-Bit Data Transfers -- 50 Mbyte/Sec Sustained Transfers (12.5 Mbyte/Sec Memory-to-Memory) * Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (USART) -- Baud Rate Generators -- Modem Control -- MC68681/MC2681 Compatible -- 9.8 Mbits/Sec Maximum Transfer Rate * Two Independent Counter/Timers -- 16-Bit Counter -- Up to 8-Bit Prescaler -- Multimode Operation -- 80-ns Resolution * System Integration Module Incorporates Many Functions Typically Relegated to External PALs, TTL, and ASIC, such as: -- System Configuration -- External Bus Interface -- System Protection -- Periodic Interrupt Timer -- Chip Select and Wait State Generation -- Interrupt Response -- Clock Generation -- Bus Arbitration -- Dynamic Bus Sizing -- IEEE 1149.1 Boundary Scan (JTAG) -- Up to 16 Discrete I/O Lines -- Power-On Reset * 32 Address Lines, 16 Data Lines * Power Consumption Control -- Static HCMOS Technology Reduces Power in Normal Operation -- Low Voltage Operation at 3.3 V 0.3 V (MC68340V only) -- Programmable Clock Generator Throttles Frequency -- Unused Peripherals Can Be Turned Off -- LPSTOP Provides an Idle State for Lowest Standby Current * 0-16.78 MHz or 0-25.16 MHz Operation * 144-Pin Ceramic Quad Flat Pack (CQFP) or 145-Pin Plastic Pin Grid Array (PGA) As a low voltage part, the MC68340V can operate with a 3.3-V power supply. MC68340 is used throughout this manual to refer to both the low voltage and standard 5-V parts since both are functionally equivalent. 1.1 M68300 FAMILY The MC68340 is one of a series of components in the M68300 family. Other members of the family include the MC68302, MC68330, MC68331, MC68332, and MC68333. 1-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 1.1.1 Organization Freescale Semiconductor, Inc... The M68300 family of integrated processors and controllers is built on an M68000 core processor, an on-chip bus, and a selection of intelligent peripherals appropriate for a set of applications. The CPU32 is a powerful central processor with nearly the performance of the MC68020. A system integration module incorporates the external bus interface and many of the smaller circuits that typically surround a microprocessor for address decoding, wait-state insertion, interrupt prioritization, clock generation, arbitration, watchdog timing, and power-on reset timing. Each member of the M68300 family is distinguished by its selection of peripherals. Peripherals are chosen to address specific applications but are often useful in a wide variety of applications. The peripherals may be highly sophisticated timing or protocol engines that have their own processors, or they may be more traditional peripheral functions, such as UARTs and timers. Since each major function is designed in a standalone module, each module might be found in many different M68300 family parts. Driver software written for a module on one M68300 part can be used to run the same module that appears on another part. 1.1.2 Advantages By incorporating so many major features into a single M68300 family chip, a system designer can realize significant savings in design time, power consumption, cost, board space, pin count, and programming. The equivalent functionality can easily require 20 separate components. Each component might have 16-64 pins, totaling over 350 connections. Most of these connections require interconnects or are duplications. Each connection is a candidate for a bad solder joint or misrouted trace. Each component is another part to qualify, purchase, inventory, and maintain. Each component requires a share of the printed circuit board. Each component draws power--often to drive large buffers to get the signal to another chip. The cumulative power consumption of all the components must be available from the power supply. The signals between the CPU and a peripheral might not be compatible nor run from the same clock, requiring time delays or other special design considerations. In a M68300 family component, the major functions and glue logic are all properly connected internally, timed with the same clock, fully tested, and uniformly documented. Power consumption stays well under a watt, and a special standby mode drops current well under a milliamp during idle periods. Only essential signals are brought out to pins. The primary package is the surface-mount quad flat pack for the smallest possible footprint; pin grid arrays are also available. 1.2 CENTRAL PROCESSOR UNIT The CPU32 is a powerful central processor that supervises system functions, makes decisions, manipulates data, and directs I/O. A special debugging mode simplifies processor emulation during system debug. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-3 Freescale Semiconductor, Inc. 1.2.1 CPU32 Freescale Semiconductor, Inc... The CPU32 is an M68000 family processor specially designed for use as a 32-bit core processor and for operation over the intermodule bus (IMB). Designers used the MC68020 as a model and included advances of the later M68000 family processors, resulting in an instruction execution performance of 4 MIPS (VAX-equivalent) at 25.16 MHz. The powerful and flexible M68000 architecture is the basis of the CPU32. MC68000 (including the MC68HC000 and the MC68EC000) and MC68010 user programs will run unmodified on the CPU32. The programmer can use any of the eight 32-bit data registers for fast manipulation of data and any of the eight 32-bit address registers for indexing data in memory. The CPU32 can operate on data types of single bits, binary-coded decimal (BCD) digits, and 8, 16, and 32 bits. Peripherals and data in memory can reside anywhere in the 4-Gbyte linear address space. A supervisor operating mode protects system-level resources from the more restricted user mode, allowing a true virtual environment to be developed. Flexible instructions for data movement, arithmetic functions, logical operations, shifts and rotates, bit set and clear, conditional and unconditional program branches, and overall system control are supported, including a fast 32 x 32 multiply and 32-bit conditional branches. New instructions, such as table lookup and interpolate and low power stop, support the specific requirements of embedded control applications. Many addressing modes complement these instructions, including predecrement and postincrement, which allow simple stack and queue maintenance and scaled indexed for efficient table accesses. Data types and addressing modes are supported orthogonally by all data operations and with all appropriate addressing modes. Position-independent code is easily written. The CPU32 is specially optimized to run with the MC68340's 16-bit data bus. Most instructions execute in one-half the number of clocks compared to the original MC68000, yielding an overall 1.6 times the performance of the same-speed MC68000 and measuring 10,045 Dhrystones/sec @ 25.16 MHz (6,742 Dhrystones/sec @ 16.78 MHz). Like all M68000 family processors, the CPU32 recognizes interrupts of seven different priority levels and allows the peripheral to vector the processor to the desired service routine. Internal trap exceptions ensure proper instruction execution with good addresses and data, allow operating system intervention in special situations, and permit instruction tracing. Hardware signals can either terminate or rerun bad memory accesses before instructions process data incorrectly. The CPU32 offers the programmer full 32-bit data processing performance with complete M68000 compatibility, yet with more compact code than is available with RISC processors. The CPU32 is identical in all CPU32-based M68300 family products. 1.2.2 Background Debug Mode A special operating mode is available in the CPU32 in which normal instruction execution is suspended while special on-chip microcode performs the functions of a debugger. 1-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Commands are received over a dedicated, high-speed, full-duplex serial interface. Commands allow the manual reading or writing of CPU32 registers, reading or writing of external memory locations, and diversion to user-specified patch code. This background debug mode permits a much simpler emulation environment while leaving the processor chip in the target system, running its own debugging operations. 1.3 ON-CHIP PERIPHERALS Freescale Semiconductor, Inc... To improve total system throughput and reduce part count, board size, and cost of system implementation, the M68300 family integrates on-chip, intelligent peripheral modules and typical glue logic. These functions on the MC68340 include the SIM40, a DMA controller, a serial module, and two timers. The processor communicates with these modules over the on-chip intermodule bus (IMB). This backbone of the chip is similar to traditional external buses with address, data, clock, interrupt, arbitration, and handshake signals. Because bus masters (like the CPU32 and DMA), peripherals, and the SIM40 are all on the chip, the IMB ensures that communication between these modules is fully synchronized and that arbitration and interrupts can be handled in parallel with data transfers, greatly improving system performance. Internal accesses across the IMB may be monitored from outside of the chip, if desired. Each module operates independently. No direct connections between peripheral modules are made inside the chip; however, external connections could, for instance, link a serial output to a DMA control line. Modules and their registers are accessed in the memory map of the CPU32 (and DMA) for easy access by general M68000 instructions and are relocatable. Each module may be assigned its own interrupt level, response vector, and arbitration priority. Since each module is a self-contained design and adheres to the IMB interface specifications, the modules may appear on other M68300 family products, retaining the investment in the software drivers for the module. 1.3.1 System Integration Module The MC68340 SIM40 provides the external bus interface for both the CPU32 and the DMA. It also eliminates much of the glue logic that typically supports the microprocessor and its interface with the peripheral and memory system. The SIM40 provides programmable circuits to perform address decoding and chip selects, wait-state insertion, interrupt handling, clock generation, bus arbitration, watchdog timing, discrete I/O, and power-on reset timing. A boundary scan test capability is also provided. 1.3.1.1 EXTERNAL BUS INTERFACE. The external bus interface (EBI) handles the transfer of information between the internal CPU32 or DMA controller and memory, peripherals, or other processing elements in the external address space. Based on the MC68030 bus, the external bus provides up to 32 address lines and 16 data lines. Address extensions identify each bus cycle as CPU32 or DMA initiated, supervisor or user privilege level, and instruction or data access. The data bus allows dynamic sizing for 8- or 16-bit bus accesses (plus 32 bits for DMA). Synchronous transfers from the CPU32 or the DMA can be made in as little as two clock cycles. Asynchronous transfers allow the MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-5 Freescale Semiconductor, Inc. memory system to signal the CPU32 or DMA when the transfer is complete and to note the number of bits in the transfer. An external master can arbitrate for the bus using a three-line handshaking interface. Freescale Semiconductor, Inc... 1.3.1.2 SYSTEM CONFIGURATION AND PROTECTION. The M68000 family of processors is designed with the concept of providing maximum system safeguards. System configuration and various monitors and timers are provided in the MC68340. Power-on reset circuitry is a part of the SIM40. A bus monitor ensures that the system does not lock up when there is no response to a memory access. The bus fault monitor can reset the processor when a catastrophic bus failure occurs. Spurious interrupts are detected and handled appropriately. A software watchdog can pull the processor out of an infinite loop. An interrupt can be sent to the CPU32 with programmable regularity for DRAM refresh, time-of-day clock, task switching, etc. 1.3.1.3 CLOCK SYNTHESIZER. The clock synthesizer generates the clock signals used by all internal operations as well as a clock output used by external devices. The clock synthesizer can operate with an inexpensive 32768-Hz watch crystal or an external oscillator for reference, using an internal phase-locked loop and voltage-controlled oscillator. At any time, software can select clock frequencies from 131 kHz to 16.78 MHz or 25.16 MHz, favoring either low power consumption or high performance. Alternately, an external clock can drive the clock signal directly at the operating frequency. With its fully static HCMOS design, it is possible to completely stop the system clock without losing the contents of the internal registers. 1.3.1.4 CHIP SELECT AND WAIT STATE GENERATION. Four programmable chip selects provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals with up to 175-ns access times with a 25-MHz system clock (265 ns @ 16.78 MHz). Each chip select signal has an associated base address and an address mask that determine the addressing characteristics of that chip select. Address space and write protection can be selected for each. The block size can be selected from 256 bytes up to 4 Gbytes in increments of 2 n. Accesses can be preselected for either 8- or 16-bit transfers. Fast synchronous termination or up to three wait states can be programmed, whether or not the chip select signals are used. External handshakes can also signal the end of a bus transfer. A system can boot from reset out of 8-bit-wide memory, if desired. 1.3.1.5 INTERRUPT HANDLING. Seven input signals are provided to trigger an external interrupt, one for each of the seven priority levels supported. Seven separate outputs can indicate the priority level of the interrupt being serviced. An input can direct the processor to a default service routine, if desired. Interrupts at each priority level can be preprogrammed to go to the default service routine. For maximum flexibility, interrupts can be vectored to the correct service routine by the interrupting device. 1.3.1.6 DISCRETE I/O PINS. When not used for other functions, 16 pins can be programmed as discrete input or output lines. Additionally, in other peripheral modules, pins for otherwise unused functions can often be used for general input/output. 1-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 1.3.1.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group). 1.3.2 Direct Memory Access Module Freescale Semiconductor, Inc... The most distinguishing MC68340 characteristic is the high-speed 32-bit DMA controller, used to quickly move large blocks of data between internal peripherals, external peripherals, or memory without processor intervention. The DMA module consists of two, independent, programmable channels. Each channel has separate request, acknowledge, and done signals. Each channel can operate in a single-address or a dual-address (flyby) mode. In single-address mode, only one (the source or the destination) address is provided, and a peripheral device such as a serial communications controller receives or supplies the data. An external request must start a single-address transfer. In this mode, each channel supports 32 bits of address and 8, 16, or 32 bits of data. In dual-address mode, two bus transfers occur, one from a source device and the other to a destination device. Dual-address transfers can be started by either an internal or external request. In this mode, each channel supports 32 bits of address and 8 or 16 bits of data (32 bits require external logic). The source and destination port size can be selected independently; when they are different, the data will be packed or unpacked. An 8-bit disk interface can be read twice before the concatenated 16-bit result is passed into memory. Byte, word, and long-word counts up to 32 bits can be transferred. All addresses and transfer counters are 32 bits. Addresses increment or remain constant, as programmed. The DMA channels support two external request modes, burst transfer and cycle steal. Internal requests can be programmed to occupy 25, 50, 75, or 100 percent of the data bus bandwidth. Interrupts can be programmed to postpone DMA completion. The DMA module can sustain a transfer rate of 12.5 Mbytes/sec in dual-address mode and nearly 50 Mbytes/sec in single-address mode @ 25.16 MHz (8.4 and 33.3 Mbytes/sec @ 16.78 MHz, respectively). The DMA controller arbitrates with the CPU32 for the bus in parallel with existing bus cycles and is fully synchronized with the CPU32, eliminating all delays normally associated with bus arbitration by allowing DMA bus cycles to butt seamlessly with CPU bus cycles. 1.3.3 Serial Module Most digital systems use serial I/O to communicate with host computers, operator terminals, or remote devices. The MC68340 contains a two-channel, full-duplex USART. An on-chip baud rate generator provides standard baud rates up to 76.8k baud independently to each channel's receiver and transmitter. The module is functionally equivalent to the MC68681/MC2681 DUART. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-7 Freescale Semiconductor, Inc. Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided on each channel. Full-duplex, autoecho loopback, local loopback, and remote loopback modes can be selected. Multidrop applications are supported. Freescale Semiconductor, Inc... A 3.6864-MHz crystal drives the baud rate generators. Each transmit and receive channel can be programmed for a different baud rate, or an external 1 x and 16x clock input can be selected. Full modem support is provided with separate request-to-send (RTS) and clearto-send (CTS) signals for each channel. One channel also provides service request signals. The two serial ports can sustain rates of 9.8 Mbps with a 25-MHz system clock in 1x mode, 612 kbps in 16x mode (6.5 Mbps and 410 kbps @ 16.78 MHz). 1.3.4 Timer Modules Timers and counters are used in a system to monitor elapsed time, generate waveforms, measure signals, keep time-of-day clocks, initiate DRAM refresh cycles, count events, and provide "time slices" to ensure that no task dominates the activity of the processor. A counter that counts clock pulses makes a timer, which is most useful when it causes certain actions to occur in response to reaching desired counts. The MC68340 has two, identical, versatile, on-chip counter/timers as well as a simple timer in the SIM40. These general-purpose counter/timers can be used for precisely timed events without the errors to which software-based counters and timers are susceptible-- e.g., errors caused by dynamic memory refreshing, DMA cycle steals, and interrupt servicing. The programmable timer operating modes are input capture, output compare, square-wave generation, variable duty-cycle square-wave generation, variable-width single-shot pulse generation, event counting, period measurement, and pulse-width measurement. Each timer consists of a 16-bit countdown counter with an 8-bit countdown prescaler for a composite 24-bit resolution. The two timers can be externally cascaded for a maximum count width of 48 bits. The counter/timer can be clocked by the internal system clock generated by the SIM40 (/2) or by an external clock input. Either the processor or external stimuli can trigger the starting and stopping of the counter. When a counter reaches a predetermined value, either an external output signal can be driven, or an interrupt can be made to the CPU32. The finest resolution of the timer is 80 ns with a 25-MHz system clock (125 ns @ 16.78 MHz). 1.4 POWER CONSUMPTION MANAGEMENT The MC68340 is very power efficient due to its advanced 0.8- HCMOS process technology and its static logic design. The resulting power consumption is typically 900 mW in full operation @ 25 MHz (650 mW @ 16.78 MHz)--far less than the comparable discrete component implementation the MC68340 can replace. For applications employing reduced voltage operation, selection of the MC68340V, which 1-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. requires only a 3.3-V power supply, reduces current consumption by 40-60% in all modes of operation (as well as reducing noise emissions). Freescale Semiconductor, Inc... The MC68340 has many additional methods of dynamically controlling power consumption during operation. The frequency of operation can be lowered under software control to reduce current consumption when performance is less critical. Idle internal peripheral modules can be turned off to save power (5-10% each). Running a special low power stop (LPSTOP) instruction shuts down the active circuits in the CPU and peripheral modules, halting instruction execution. Power consumption in this standby mode is reduced to about 350 W. Processing and power consumption can be resumed by resetting the part or by generating an interrupt with the SIM40's periodic interrupt timer. 1.5 PHYSICAL The MC68340 is available as 0-16.78 MHz and 0-25.16 MHz, 0C to +70C and -40C to +85C, and 5.0 V 5% and 3.3 V 0.3 supply voltages (reduced frequencies at 3.3 V) . Thirty-two power and ground leads minimize ground bounce and ensure proper isolation of different sections of the chip, including the clock oscillator. A 144 pins are used for signals and power. The MC68340 is available in a gull-wing ceramic quad flat pack (CQFP) with 25.6-mil (0.001-in) lead spacing or a 15 x 15 plastic pin grid array (PPGA) with 0.1-in pin spacing. 1.6 COMPACT DISC-INTERACTIVE The MC68340 was designed to meet the needs of many markets, including compact discinteractive (CD-I). CD-I is an emerging standard for a publishing medium that will bring multimedia to a broad general audience--the consumer. CD-I players combine television and stereo systems as output devices, with interactive control using a TV remote-controllike device to provide a multimedia experience selected from software "titles" contained in compressed form on standard compact discs. The highly integrated MC68340 is ideal as the central processor for CD-I players. It provides the M68000 microprocessor code compatibility and DMA functions required by the CD-I Green Book specification as well as many other useful on-chip functions for a very cost-effective solution. The extra demands of full-motion video CD-I systems make the best use of the MC68340 high performance. The MC68340 is CD-I compliant and has been CD-I qualified. With its low voltage operation, the MC68340V is the only practical choice for portable CD-I. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-9 Freescale Semiconductor, Inc. 1.7 MORE INFORMATION The following table lists available documentation related to the MC68340: Document Number BR1114/D MC68340/D MC68340UM/AD M68000PM/AD AN1063/D Freescale Semiconductor, Inc... M68300 Integrated Processor Family MC68340 Technical Summary MC68340 User's Manual M68000 Family Programmer's Reference Manual DRAM Controller for the MC68340 Software Implementation of SPI on the MC68340 AN453 1-10 Document Name BR573/D M68340 Evaluation System Product Brief BR729/D The 68K Source BR1407/D 3.3 Volt Logic and Interface Circuits MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTIONS SCLK X2 X1 BKPT/DSCLK FREEZE IPIPE/DSO IFETCH/DSI PORT A TCK TMS TDI TDO A31/PORT A7/IACK7 A30/PORT A6/IACK6 A29/PORT A5/IACK5 A28/PORT A4/IACK4 A27/PORT A3/IACK3 A26/PORT A2/IACK2 A25/PORT A1/IACK1 A24/PORT A0 TWO-CHANNEL SERIAL I/O CPU32 CORE TEST A23-A0 RxDA TxDA CTSA RxDB TxDB CTSB D15-D0 FC3-FC0 OUTPUT PORT SYSTEM INTEGRATION MODULE BUS ARBITRATION TIMER MODULE CLKOUT XFC XTAL TIMER MODULE TGATE2 TIN2 TOUT2 CLOCK TWO-CHANNEL DMA CONTROLLER PORT B DREQ1 DACK1 DONE1 DREQ2 DACK2 DONE2 IRQ7/PORT B7 IRQ6/PORT B6 IRQ5/PORT B5 IRQ3/PORT B3 CS3/IRQ4/PORT B4 CS2/IRQ2/PORT B2 CS1/IRQ1/PORT B1 CS0/AVEC MODCK/PORT B0 TxRDYA/OP6 RxRDYA/FFULLA/OP4 RTSB/OP1 RTSA/OP0 IMB TIN1 TOUT1 BR BG BGACK RMC EXTERNAL BUS INTERFACE TGATE1 RESET BERR HALT AS DS R/W SIZ1 SIZ0 DSACK1 DSACK0 EXTAL Freescale Semiconductor, Inc... This section contains brief descriptions of the MC68340 input and output signals in their functional groups as shown in Figure 2-1. Figure 2-1. Functional Signal Groups MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-1 Freescale Semiconductor, Inc. 2.1 SIGNAL INDEX The input and output signals for the MC68340 are listed in Table 2-1. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed in Table 2-1 can be found in Section 11 Electrical Characteristics. Table 2-1. Signal Index Signal Name Freescale Semiconductor, Inc... Address Bus Mnemonic Function A23-A0 Lower 24 bits of the address bus Input/ Output Out Address Bus/Port A7-A0/ Interrupt Acknowledge A31-A24 Upper eight bits of the address bus, parallel I/O port, or interrupt acknowledge lines Out/I/O/Out Data Bus D15-D0 The 16-bit data bus used to transfer byte or word data I/O Function Codes FC3-FC0 Identify the processor state and the address space of the current bus cycle Out Chip Select 3-1/ Interrupt Request Level/ Port B4, B2, B1 CS3-CS1 Enables peripherals at programmed addresses, interrupt priority level to the CPU32, or parallel I/O port Out/In/ I/O Chip Select 0/Autovector CS0 Enables peripherals at programmed addresses or requests an automatic vector Out/In Bus Request BR Indicates that an external device requires bus mastership Bus Grant BG Indicates that current bus cycle is complete and the MC68340 has relinquished the bus Out BGACK Indicates that an external device has assumed bus mastership In Provides asynchronous data transfers and dynamic bus sizing In Bus Grant Acknowledge Data and Size Acknowledge DSACK1, DSACK0 In RMC Identifies the bus cycle as part of an indivisible read modify-write operation Out Address Strobe AS Indicates that a valid address is on the address bus Out Data Strobe DS During a read cycle, DS indicates that an external device should place valid data on the data bus. During a write cycle, DS indicates that valid data is on the data bus. Out SIZ1, SIZ0 Indicates the number of bytes remaining to be transferred for this cycle Out R/ W Indicates the direction of data transfer on the bus Out IRQ7, IRQ6, IRQ5, IRQ3 Provides an interrupt priority level to the CPU32 or becomes a parallel I/O port In/I/O Read-Modify-Write Cycle Size Read/Write Interrupt Request Level/ Port B7, B6, B5, B3 RESET System reset I/O Halt HALT Suspends external bus activity I/O Bus Error BERR Indicates an invalid bus operation is being attempted In Reset System Clock Crystal Oscillator External Filter Capacitor 2-2 CLKOUT System clock out EXTAL, XTAL XFC Connections for an external crystal or oscillator to the internal oscillator circuit Connection pin for an external capacitor to filter the circuit of the phase-locked loop MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Out In, Out In MOTOROLA Freescale Semiconductor, Inc. Table 2-1. Signal Index (Continued) Signal Name Function MODCK Selects the source of the internal system clock upon reset or becomes a parallel I/O port In/I/O Instruction Fetch/ Development Serial In IFETCH/DSI Indicates when the CPU32 is performing an instruction word prefetch and when the instruction pipeline has been flushed or provides background debug mode serial in Out/In Instruction Pipe/ Development Serial Out IPIPE/DSO Used to track movement of words through the instruction pipeline or provides background debug mode serial out Out/Out Breakpoint/Development Serial Clock BKPT/DSCLK Signals a hardware breakpoint to the CPU32 or provides background debug mode serial clock In/-- FREEZE Indicates that the CPU32 has entered background debug mode Out Out Clock Mode Select/ Port B0 Freeze Freescale Semiconductor, Inc... Input/ Output Mnemonic Transmit Data TxDA, TxDB Transmitter serial data output from the serial module Clear-to-Send CTSA, CTSB Serial module clear-to-send inputs Request-to-Send/ OP1, OP0 RTSB, RTSA Channel request-to-send outputs or discrete outputs Serial Crystal Oscillator X1, X2 Connections for an external crystal to the serial module internal oscillator circuit Serial Clock SCLK External serial module clock input Transmitter Ready/OP6 TRDYA Indicates transmit buffer has a character or becomes a parallel output Receiver Ready/ FIFO Full/OP4 RRDYA Indicates receive buffer has a character, the receiver FIFO buffer is full or becomes a parallel output DMA Request DRE Input that starts a DMA process In Out/Out In Out/Out Out/Out/Out In Q2, DREQ1 DMA Acknowledge DACK2, DACK1 Output that signals an access during DMA Out DMA Done DONE2, DONE1 Bi-directional signal that indicates the last transfer I/O Timer Gate TGATE2, TGATE1 Counter enable input to timer In Timer Input TIN2, TIN1 Time reference input to timer In TOUT2, TOUT1 Output waveform from timer Out Timer Output Test Clock TCK Provides a clock for IEEE 1149.1 test logic In Test Mode Select TMS Controls test mode operations In Test Data In TDI Shifts in instructions and test data In Test Data Out TDO Shifts out instructions and test data Synchronizer Power System Power Supply and Ground MOTOROLA VCCSYN VCC , GND Out Quiet power supply to VCO; also used to control synthesizer mode after reset. -- Power supply and ground to the MC68340 -- MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-3 Freescale Semiconductor, Inc. NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 2.2 ADDRESS BUS Freescale Semiconductor, Inc... The address bus signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. The address bus consists of the following two groups. Refer to Section 3 Bus Operation for information on the address bus and its relationship to bus operation. 2.2.1 Address Bus (A23-A0) These three-state outputs (along with A31-A24) provide the address for the current bus cycle, except in the CPU address space. 2.2.2 Address Bus (A31-A24) These pins can be programmed as the most significant eight address bits, port A parallel I/O, or interrupt acknowledge signals. These pins can be used for more than one of their multiplexed functions as long as the external demultiplexing circuit properly resolves interaction between the different functions. A31-A24 These pins can function as the most significant eight address bits. Port A7-A0 These eight pins can serve as a dedicated parallel I/O port. See Section 4 System Integration Module for more information on programming these pins. IACK7- IACK1 The MC68340 asserts one of these pins to indicate the level of an external interrupt during an interrupt acknowledge cycle. Peripherals can use the IACK signals instead of monitoring the address bus and function codes to determine that an interrupt acknowledge cycle is in progress and to obtain the current interrupt level. 2.3 DATA BUS (D15-D0) This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the 2-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle. 2.4 FUNCTION CODES (FC3-FC0) Freescale Semiconductor, Inc... These signals are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either user or supervisor, program or data, and normal or direct memory access (DMA) spaces. One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles. The function code signals are valid while AS is asserted. See Table 2-2 for more information. Table 2-2. Address Space Encoding Function Code Bits 3 2 1 0 Address Spaces 0 0 0 0 Reserved (Motorola) 0 0 0 1 User Data Space 0 0 1 0 User Program Space 0 0 1 1 Reserved (User ) 0 1 0 0 Reserved (Motorola) 0 1 0 1 Supervisor Data Space 0 1 1 0 Supervisor Program Space 0 1 1 1 CPU Space 1 x x x DMA Space 2.5 CHIP SELECTS (CS3-CS0) These pins can be programmed to be chip select output signals, port B parallel I/O and autovector input, or additional interrupt request lines. Refer to Section 4 System Integration Module for more information on these signals. CS3- CS0 The chip select output signals enable peripherals at programmed addresses. These signals are inactive high (not high impedance) after reset. CS0 is the chip select for a boot ROM containing the reset vector and initialization program. It functions as the boot chip select immediately after reset. IRQ4, IRQ2, IRQ1 Interrupt request lines are external interrupt lines to the CPU32. These additional interrupt request lines are selected by the FIRQ bit in the module configuration register. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-5 Freescale Semiconductor, Inc. Port B4, B2, B1, AVEC This signal group functions as three bits of parallel I/O and the autovector input. AVEC requests an automatic vector during an interrupt acknowledge cycle. 2.6 INTERRUPT REQUEST LEVEL (IRQ7, IRQ6, IRQ5, IRQ3) These pins can be programmed to be either prioritized interrupt request lines or port B parallel I/O. Freescale Semiconductor, Inc... IRQ7, IRQ6, IRQ5, IRQ3 IRQ7 , the highest priority, is nonmaskable. IRQ6-IRQ1 are internally maskable interrupts. Refer to Section 5 CPU32 for more information on interrupt request lines. Port B7, B6, B5, B3 These pins can be used as port B parallel I/O. Refer to Section 4 System Integration Module for more information on parallel I/O signals. 2.7 BUS CONTROL SIGNALS These signals control the bus transfer operations of the MC68340. Refer to Section 3 Bus Operation for more information on these signals. 2.7.1 Data and Size Acknowledge ( DSACK1, DSACK0) These two active-low input signals allow asynchronous data transfers and dynamic data bus sizing between the MC68340 and external devices as listed in Table 2-3. During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. Table 2-3. DSACK Encoding DSACK 1 1 1 0 0 DSACK 0 1 0 1 0 Result Insert Wait States in Current Bus Cycle Complete Cycle--Data Bus Port Size Is 8 Bits Complete Cycle--Data Bus Port Size Is 16 Bits Reserved--Defaults to 16-Bit Port Size Can Be Used for 32-Bit DMA Cycles 2.7.2 Address Strobe ( AS) AS is an output timing signal that indicates the validity of both an address on the address bus and many control signals. AS is asserted approximately one-half clock cycle after the beginning of a bus cycle. 2-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 2.7.3 Data Strobe (DS) DS is an output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle. 2.7.4 Transfer Size (SIZ1, SIZ0) These output signals are driven by the bus master to indicate the number of operand bytes remaining to be transferred in the current bus cycle as noted in Table 2-4. Freescale Semiconductor, Inc... Table 2-4. SIZx Signal Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word 1 1 Three Byte 0 0 Long Word 2.7.5 Read/Write (R/ W) This active-high output signal is driven by the bus master to indicate the direction of a data transfer on the bus. A logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. 2.8 BUS ARBITRATION SIGNALS The following signals are the bus arbitration control signals used to determine the bus master. Refer to Section 3 Bus Operation for more information on these signals. 2.8.1 Bus Request (BR) This active-low input signal indicates that an external device needs to become the bus master. 2.8.2 Bus Grant (BG) Assertion of this active-low output signal indicates that the MC68340 has relinquished the bus. 2.8.3 Bus Grant Acknowledge (BGACK) Assertion of this active-low input indicates that an external device has become the bus master. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-7 Freescale Semiconductor, Inc. 2.8.4 Read-Modify-Write Cycle (RMC) This output signal identifies the bus cycle as part of an indivisible read-modify-write operation. It remains asserted during all bus cycles of the read-modify-write operation to indicate that bus ownership cannot be transferred. 2.9 EXCEPTION CONTROL SIGNALS These signals are used by the MC68340 to recover from an exception. Freescale Semiconductor, Inc... 2.9.1 Reset ( RESET) This active-low, open-drain, bidirectional signal is used to initiate a system reset. An external reset signal (as well as a reset from the SIM40) resets the MC68340 and all external devices. A reset signal from the CPU32 (asserted as part of the RESET instruction) resets external devices; the internal state of the CPU32 is not affected. The on-chip modules are reset, except for the SIM40. However, the module configuration register for each on-chip module is not altered. When asserted by the MC68340, this signal is guaranteed to be asserted for a minimum of 512 clock cycles. Refer to Section 3 Bus Operation for a description of bus reset operation and Section 5 CPU32 for information about the reset exception. 2.9.2 Halt (HALT) This active-low, open-drain, bidirectional signal is asserted to suspend external bus activity, to request a retry when used with BERR, or to perform a single-step operation. As an output, HALT indicates a double bus fault by the CPU32. Refer to Section 3 Bus Operation for a description of the effects of HALT on bus operation. 2.9.3 Bus Error (BERR) This active-low input signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor should retry the current cycle. Refer to Section 3 Bus Operation for a description of the effects of BERR on bus operation. 2.10 CLOCK SIGNALS These signals are used by the MC68340 for controlling or generating the system clocks. See Section 4 System Integration Module for more information on the various clocking methods and frequencies. 2.10.1 System Clock (CLKOUT) This output signal is the system clock output and is used as the bus timing reference by external devices. CLKOUT can be varied in frequency or slowed in low power stop mode to conserve power. 2-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 2.10.2 Crystal Oscillator (EXTAL, XTAL) These two pins are the connections for an external crystal to the internal oscillator circuit. If an external oscillator is used, it should be connected to EXTAL, with XTAL left open. 2.10.3 External Filter Capacitor (XFC) This pin is used to add an external capacitor to the filter circuit of the phase-locked loop. The capacitor should be connected between XFC and VCCSYN. 2.10.4 Clock Mode Select (MODCK) Freescale Semiconductor, Inc... This pin selects the source of the internal system clock during reset. After reset, it can be programmed to be port B parallel I/O. MODCK The state of this active-high input signal during reset selects the source of the internal system clock. If MODCK is high during reset, the internal voltage-controlled oscillator (VCO) furnishes the system clock in crystal mode. If MODCK is low during reset, an external clock source at the EXTAL pin furnishes the system clock output in external clock mode. Port B0 This pin can be used as a port B parallel I/O. 2.11 INSTRUMENTATION AND EMULATION SIGNALS These signals are used for test or software debugging. See Section 5 CPU32 for more information on these signals and background debug mode. 2.11.1 Instruction Fetch (IFETCH) This pin functions as IFETCH in normal operation and as DSI in background debug mode. IFETCH This active-low output signal indicates when the CPU32 is performing an instruction word prefetch and when the instruction pipeline has been flushed. DSI This development serial input signal helps to provide serial communications for background debug mode. 2.11.2 Instruction Pipe (IPIPE) This pin functions as IPIPE in normal operation and as DSO in background debug mode. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-9 Freescale Semiconductor, Inc. IPIPE This active-low output signal is used to track movement of words through the instruction pipeline. DSO This development serial output signal helps to provide serial communications for background debug mode. 2.11.3 Breakpoint (BKPT) Freescale Semiconductor, Inc... This pin functions as BKPT in normal operation and as DSCLK in background debug mode. BKPT This active-low input signal is used to signal a hardware breakpoint to the CPU32. DSCLK This development serial clock input helps to provide serial communications for background debug mode. 2.11.4 Freeze (FREEZE) Assertion of this active-high output signal indicates that the CPU32 has acknowledged a breakpoint and has initiated background mode operation. 2.12 DMA MODULE SIGNALS The following signals are used by the direct memory access (DMA) controller module to provide external handshake for either a source or destination. See Section 6 DMA Module for additional information on these signals. 2.12.1 DMA Request (DREQ2, DREQ1) This active-low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory. The assertion of DREQ starts the DMA process. The assertion level in external burst mode is level sensitive; in external cycle steal mode, it is falling-edge sensitive. 2.12.2 DMA Acknowledge (DACK2, DACK1) This active-low output is asserted by the DMA to signal to a peripheral that an operand is being transferred in response to a previous transfer request. 2.12.3 DMA Done (DONE2, DONE1) This active-low bidirectional signal is asserted by the DMA or a peripheral device during any DMA bus cycle to indicate that the last data transfer is being performed. DONE is an active input in any mode. As an output, it is only active in external request mode. An external pullup resistor is required even during operation in the internal request mode. 2-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 2.13 SERIAL MODULE SIGNALS The following signals are used by the serial module for data and clock signals. See Section 7 Serial Module for more information on these signals. 2.13.1 Serial Crystal Oscillator (X2, X1) These pins furnish the connection to a crystal or external clock, which must be supplied when using the baud rate generator. An external clock is connected to the X1 pin; X2 is left floating. Freescale Semiconductor, Inc... 2.13.2 Serial External Clock Input (SCLK) This input can be used as the external clock input for channel A or channel B, bypassing the baud rate generator. 2.13.3 Receive Data (RxDA, RxDB) These signals are the receiver serial data input for each channel. Data received on this signal is sampled on the rising edge of the clock source, with the least significant bit received first. 2.13.4 Transmit Data (TxDA, TxDB) These signals are the transmitter serial data output for each channel. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal at the falling edge of the clock source, with the least significant bit transmitted first. 2.13.5 Clear to Send (CTSA, CTSB) These active-low signals can be programmed as the clear-to-send inputs for each channel. 2.13.6 Request to Send (RTSA, RTSB) These active-low signals can be programmed as request-to-send outputs or used as discrete outputs. RTSB, RTSA When used for this function, these signals function as the request-to-send outputs. OP1, OP0 When used for this function, these outputs are controlled by the value of bit 1 and bit 0, respectively, in the output port data registers. 2.13.7 Transmitter Ready (TRDYA) This active-low output can be programmed as the channel A transmitter ready status indicator or used as a discrete output. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-11 Freescale Semiconductor, Inc. TRDYA When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character. OP6 When used for this function, this output is controlled by bit 6 in the output port data registers. 2.13.8 Receiver Ready (RRDYA) Freescale Semiconductor, Inc... This active-low output signal can be programmed as the channel A receiver ready, channel A FIFO full indicator, or a dedicated parallel output. RRDYA When used for this function, this signal reflects the complement of the status of bit 1 of the interrupt status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver contains a character. FFULLA When used for this function, this signal reflects the complement of the status of bit 1 of the interrupt status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full. OP4 When used for this function, this output is controlled by bit 4 in the output port data registers. 2.14 TIMER SIGNALS The following external signals are used by the timer modules. See Section 8 Timer Modules for additional information on these signals. 2.14.1 Timer Gate (TGATE2, TGATE1) These active-low inputs can be programmed to enable and disable the counters and prescalers. TGATE can also be programmed as a simple input. 2.14.2 Timer Input (TIN2, TIN1) These inputs can be programmed as clocks that cause events to occur in the counters and prescalers. 2.14.3 Timer Output (TOUT2, TOUT1) These outputs drive the various output waveforms generated by the timers. 2-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 2.15 TEST SIGNALS The following signals are used with the on-board test logic defined by the IEEE 1149.1 standard. See Section 9 IEEE 1149.1 Test Access Port for more information on the use of these signals. 2.15.1 Test Clock (TCK) This input provides a clock for on-board test logic defined by the IEEE 1149.1 standard. 2.15.2 Test Mode Select (TMS) Freescale Semiconductor, Inc... This input controls test mode operations for on-board test logic defined by the IEEE 1149.1 standard. 2.15.3 Test Data In (TDI) This input is used for serial test instructions and test data for on-board test logic defined by the IEEE 1149.1 standard. 2.15.4 Test Data Out (TDO) This output is used for serial test instructions and test data for on-board test logic defined by the IEEE 1149.1 standard. 2.16 SYNTHESIZER POWER (V CCSYN ) This pin supplies a quiet power source to the VCO to provide greater frequency stability. It is also used to control the synthesizer mode after reset. See Section 4 System Integration Module for more information. 2.17 SYSTEM POWER AND GROUND (V CC AND GND) These pins provide system power and ground to the MC68340. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. 2.18 SIGNAL SUMMARY Table 2-5 presents a summary of all the signals discussed in the preceding paragraphs. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-13 Freescale Semiconductor, Inc. Table 2-5. Signal Summary Signal Name Mnemonic Input/Output A23-A0 Out -- Yes Address Bus Port A7-A0/ Interrupt Acknowledge A31-A24 Out/I/O/Out --/--/Low Yes Data Bus D15-D0 I/O -- Yes Function Codes FC3-FC0 Out -- Yes Chip Select 3/Interrupt Request Level/Port B4, B2, B1 CS3-CS1 Out/In/I/O Low/Low/-- No CS0 Out/In Low/Low No Bus Request BR In Low -- Bus Grant BG Out Low No BGACK In Low -- DSACK1, DSACK0 In Low -- RMC Out Low Yes Address Strobe AS Out Low Yes Data Strobe DS Out Low Yes SIZ1, SIZ0 Out -- Yes R/ W Out High/Low Yes IRQ7, IRQ6, IRQ5, IRQ3 In/I/O Low/-- -- Reset RESET I/O Low No Halt HALT I/O Low No Bus Error BERR In Low -- CLKOUT Out -- No EXTAL, XTAL In, Out -- -- XFC In -- -- MODCK In/I/O --/-- -- Instruction Fetch/ Development Serial In IFETCH/DSI Out/In Low/-- No/-- Instruction Pipe/ Development Serial Out IPIPE/DSO Out/Out Low/-- No/-- BKPT/DSCLK In/In Low/-- --/-- FREEZE Out High No RxDA, RxDB In -- -- Address Bus Freescale Semiconductor, Inc... Chip Select 0/Autovector Bus Grant Acknowledge Data and Size Acknowledge Read-Modify-Write Cycle Size Read/Write Interrupt Request Level/ Port B7, B6, B5, B3 System Clock Crystal Oscillator External Filter Capacitor Clock Mode Select/Port B0 Breakpoint/ Development Serial Clock Freeze Receive Data 2-14 Active State MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Three-State MOTOROLA Freescale Semiconductor, Inc. Table 2-5. Signal Summary (Continued) Signal Name Mnemonic Input/Output Active State Three-State Transmit Data TxDA, TxDB Out -- No Clear-to-Send CTSA, CTSB In Low -- Request-to-Send/ OP1, OP0 RTSB, RTSA Out/Out Low/-- No SCLK In -- -- Transmitter Ready/OP6 TRDYA Out/Out Low/-- No Receiver Ready/ FIFO Full/OP4 RRDYA Out/Out/Out Low/Low/-- No DMA Request DREQ2, DREQ1 In Low -- DMA Acknowledge DACK2, DACK1 Out Low No DMA Done DONE2, DONE1 I/O Low No Timer Gate TGATE2, TGATE1 In Low -- Timer Input TIN2, TIN1 In -- -- TOUT2, TOUT1 Out -- Yes Test Clock TCK In -- -- Test Mode Select TMS In High -- TDI In High -- TDO Out High -- VCCSYN - -- -- VCC , GND - -- -- Freescale Semiconductor, Inc... Serial Clock Timer Output Test Data In Test Data Out Synchronizer Power System Power Supply and Return MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-15 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 3 BUS OPERATION This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the external bus is the same whether the MC68340 or an external device is the bus master; the names and descriptions of bus cycles are from the viewpoint of the bus master. For exact timing specifications, refer to Section 11 Electrical Characteristics. The MC68340 architecture supports byte, word, and long-word operands allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the SIZ1/SIZ0 outputs and DSACK1/DSACK0 inputs. The MC68340 requires word and longword operands to be located in memory on word boundaries. The only type of transfer that can be performed to an odd address is a single-byte transfer, referred to as an odd-byte transfer. For an 8-bit port, multiple bus cycles may be required for an operand transfer due to either misalignment or a word or long-word operand. 3.1 BUS TRANSFER SIGNALS The bus transfers information between the MC68340 and external memory or a peripheral device. External devices can accept or provide 8 bits or 16 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68340 contains an address bus that specifies the address for the transfer and a data bus that transfers the data. Control signals indicate the beginning and type of the cycle as well as the address space and size of the transfer. The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data. Both asynchronous and synchronous operation is possible for any port width. In asynchronous operation, the bus and control input signals are internally synchronized to the MC68340 clock, introducing a delay. This delay is the time required for the MC68340 to sample an input signal, synchronize the input to the internal clocks, and determine whether it is high or low. In synchronous mode, the bus and control input signals must be timed to setup and hold times. Since no synchronization is needed, bus cycles can be completed in three clock cycles in this mode. Additionally, using the fast-termination option of the chip select signals, two-clock operation is possible. Furthermore, for all inputs, the MC68340 latches the level of the input during a sample window around the falling edge of the clock signal. This window is illustrated in Figure 3-1, where t su and t h are the input setup and hold times, respectively. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-1 Freescale Semiconductor, Inc. the sample window. If an input makes a transition during the window time period, the level recognized by the MC68340 is not predictable; however, the MC68340 always resolves the latched level to either a logic high or low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section. t su th Freescale Semiconductor, Inc... CLKOUT EXT SAMPLE WINDOW Figure 3-1. Input Sample Window NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 3.1.1 Bus Control Signals The MC68340 initiates a bus cycle by driving the A31-A0, SIZx, FCx, and R/W outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with FC3-FC0. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles). Table 3-1 lists the encoding of the SIZx signal. These signals are valid while AS is asserted. The R/ W signal determines the direction of the transfer during a bus cycle. Driven at the beginning of a bus cycle, R/ W is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive write cycles. The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write operation and remains asserted until completion of the final bus cycle of the operation. 3-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table 3-1. SIZx Signal Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word 1 1 Three Bytes 0 0 Long Word Freescale Semiconductor, Inc... 3.1.2 Function Code Signals FC3-FC0 are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either user or supervisor, program or data, and normal or direct memory access (DMA) spaces. One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles. FC3-FC0 are valid while AS is asserted. Function codes (see Table 3-2) can be considered as extensions of the 32-bit address that can provide up to 16 different 4-Gbyte address spaces. Function codes are automatically generated by the CPU32 to select address spaces for data and program at both user and supervisor privilege levels, a CPU address space for processor functions, and an alternate master address space. User programs access only their own program and data areas to increase protection of system integrity and can be restricted from accessing other information. The S-bit in the CPU32 status register is set for supervisor accesses and cleared for user accesses to provide differentiation. Refer to 3.4 CPU Space Cycles for more information. Table 3-2. Address Space Encoding Function Code Bits MOTOROLA 3 2 1 0 Address Spaces 0 0 0 0 Reserved (Motorola) 0 0 0 1 User Data Space 0 0 1 0 User Program Space 0 0 1 1 Reserved (User ) 0 1 0 0 Reserved (Motorola) 0 1 0 1 Supervisor Data Space 0 1 1 0 Supervisor Program Space 0 1 1 1 CPU Space 1 x x x DMA Space MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-3 Freescale Semiconductor, Inc. 3.1.3 Address Bus (A31-A0) These signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. 3.1.4 Address Strobe ( AS) This output timing signal indicates the validity of many control signals and the address on the address bus. AS is asserted approximately one-half clock cycle after the beginning of a bus cycle. Freescale Semiconductor, Inc... 3.1.5 Data Bus (D15-D0) This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle. 3.1.6 Data Strobe (DS) DS is an output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle. 3.1.7 Bus Cycle Termination Signals The following signals can terminate a bus cycle. 3.1.7.1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS ( DSACK1 AND DSACK0). During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. These signals also indicate to the MC68340 the size of the port for the bus cycle just completed (see Table 3-3). Refer to 3.3.1 Read Cycle for timing relationships of DSACK1 and DSACK0. Additionally, the system integration module (SIM40) chip select address mask register can be programmed to internally generate DSACK1 and DSACK0 for external accesses, eliminating logic required to generate these signals. However, if external DSACK signals are returned earlier than indicated by the DD bits in the chip select address mask register, the cycle will terminate sooner than programmed. Refer to Section 4 System Integration Module for additional information. The SIM40 can alternatively be programmed to generate a fast termination cycle, providing a two-cycle external access. Refer to 3.2.6 Fast Termination Cycles for additional information on these cycles. 3-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 3.1.7.2 BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can be used in the absence of DSACK to indicate a bus error condition. BERR can also be asserted in conjunction with DSACK to indicate a bus error condition, provided it meets the appropriate timing described in this section and in Section 11 Electrical Characteristics. Additionally, BERR and HALT can be asserted together to indicate a retry termination. Refer to 3.5 Bus Exception Control Cycles for additional information on the use of these signals. Freescale Semiconductor, Inc... The internal bus monitor can be used to generate an internal bus error signal for internal and internal-to-external transfers. If the bus cycles of an external bus master are to be monitored, external BERR generation must be provided since the internal bus error monitor has no information about transfers initiated by an external bus master. 3.1.7.3 AUTOVECTOR (AVEC ).This signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68340 should internally generate a vector (autovector) number to locate an interrupt handler routine. AVEC can be generated either externally or internally by the SIM40 (see Section 4 System Integration Module for additional information). AVEC is ignored during all other bus cycles. 3.2 DATA TRANSFER MECHANISM The MC68340 supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by DSACK1 and DSACK0 . The MC68340 also supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of synchronous cycles controlled by the fast termination capability of the SIM40. 3.2.1 Dynamic Bus Sizing The MC68340 dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size (byte or word) and indicates completion of the bus cycle to the MC68340 through the use of the DSACK inputs. Refer to Table 3-3 for DSACK encoding. Table 3-3. DSACK Encoding MOTOROLA DSACK1 DSACK0 1 (Negated) 1 (Negated) Insert Wait States in Current Bus Cycle 1 (Negated) 0 (Asserted) Complete Cycle--Data Bus Port Size Is 8 Bits 0 (Asserted) 1 (Negated) Complete Cycle--Data Bus Port Size Is 16 Bits 0 (Asserted) 0 (Asserted) Reserved--Defaults to 16-Bit Port Size Can Be Used for 32-Bit DMA cycles Result MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-5 Freescale Semiconductor, Inc. For example, if the MC68340 is executing an instruction that reads a long-word operand from a 16-bit port, the MC68340 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires four read cycles. The addressed device uses DSACK to indicate the port width. For instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of whether the bus cycle is a byte or word operation). Freescale Semiconductor, Inc... Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on data bus bits 15-0, and an 8-bit port must reside on data bus bits 15-8. This requirement minimizes the number of bus cycles needed to transfer data to 8- and 16-bit ports and ensures that the MC68340 correctly transfers valid data. The MC68340 always attempts to transfer the maximum amount of data on all bus cycles; for a word operation, it always assumes that the port is 16 bits wide when beginning the bus cycle. The bytes of operands are designated as shown in Figure 3-2. The most significant byte of a long-word operand is OP0, and OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-length operand is OP0. These designations are used in the figures and descriptions that follow. Figure 3-2 shows the required organization of data ports on the MC68340 bus for both 8- and 16-bit devices. The four bytes shown in Figure 3-2 are connected through the internal data bus and data multiplexer to the external data bus. The data multiplexer establishes the necessary connections for different combinations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. The positioning of bytes is determined by the SIZ1/SIZ0 and A0 outputs. The SIZ1/SIZ0 outputs indicate the number of bytes to be transferred during the current bus cycle (see Table 3-1). The number of bytes transferred during a read or write bus cycle is equal to or less than the size indicated by the SIZ1/SIZ0 outputs, depending on port width. For example, during the first bus cycle of a long-word transfer to a word port, the size outputs indicate that four bytes are to be transferred although only two bytes are moved on that bus cycle. The address line A0 also affects the operation of the data multiplexer. During an operand transfer, A31-A1 indicate the word base address of that portion of the operand to be accessed, and A0 indicates the byte offset from the base (i.e., either odd or even byte). Figure 3-2 lists the bytes required on the data bus for read cycles. The entries shown as OPn are portions of the requested operand that are read or written during that bus cycle and are defined by SIZ1/SIZ0 and A0 for the bus cycle. 3-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. OPERAND OP0 OP1 OP0 31 OP3 OP2 OP1 OP0 OP2 OP1 OP0 23 15 7 Freescale Semiconductor, Inc... Case (a) (b) (c) (d) (e) (f) (g) Transfer Case Byte to Byte Byte to Word (Even) Byte to Word (Odd) Word to Byte (Aligned) Word to Word (Aligned) Long Word to Byte (Aligned) Long Word to Word (Aligned) SIZ1 0 0 0 1 1 0 0 SIZ0 1 1 1 0 0 0 0 A0 X 0 1 0 0 0 0 DSACK1 DSACK0 1 0 0 X 0 X 1 0 0 X 1 0 0 X 0 Data Bus D8 D7 D0 (OP0) OP0 (OP0) OP0 (OP0) OP0 (OP1) OP0 OP1 OP0 (OP1) OP0 OP0 OP1 D15 NOTES: 1. Operands in parentheses are ignored by the MC68340 during read cycles. 2. A 3-byte to byte transfer does occur as the second byte transfer of a long-word to byte port transfer. Figure 3-2. MC68340 Interface to Various Port Sizes 3.2.2 Misaligned Operands In this architecture, the basic operand size is 16 bits. Operand misalignment refers to whether an operand is aligned on a word boundary or overlaps the word boundary, determined by address line A0. When A0 is low, the address is even and is a word and byte boundary. When A0 is high, the address is odd and is a byte boundary only. A byte operand is properly aligned at any address; a word or long-word operand is misaligned at an odd address. At most, each bus cycle can transfer a word of data aligned on a word boundary. If the MC68340 transfers a long-word operand over a 16-bit port, the most significant operand word is transferred on the first bus cycle, and the least significant operand word is transferred on a following bus cycle. The CPU32 restricts all operands (both data and instructions) to be aligned. That is, word and long-word operands must be located on a word or long-word boundary, respectively. The only type of transfer that can be performed to an odd address is a single-byte transfer, referred to as an odd-byte transfer. If a misaligned access is attempted, the CPU32 generates an address error exception, and enters exception processing. Refer to Section 5 CPU32 for more information on exception processing. 3.2.3 Operand Transfer Cases The following cases are examples of the allowable alignments of operands to ports. 3.2.3.1 BYTE OPERAND TO 8-BIT PORT, ODD OR EVEN (A0 = X). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a singlebyte operand. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-7 Freescale Semiconductor, Inc. BYTE OPERAND OP0 0 7 DATA BUS CYCLE 1 D15 D8 D7 D0 OP0 (OP0) SIZ1 0 SIZ0 1 A0 X DSACK1 DSACK0 1 0 Freescale Semiconductor, Inc... For a read operation, the slave responds by placing data on bits 15-8 of the data bus, asserting DSACK0 and negating DSACK1 to indicate an 8-bit port. The MC68340 then reads the operand byte from bits 15-8 and ignores bits 7-0. For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read. The slave device reads the byte operand from bits 15-8 and places the operand in the specified location. The slave then asserts DSACK0 to terminate the bus cycle. 3.2.3.2 BYTE OPERAND TO 16-BIT PORT, EVEN (A0 = 0). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single-byte operand. BYTE OPERAND OP0 0 7 DATA BUS CYCLE 1 D15 OP0 D8 D7 D0 (OP0) SIZ1 0 SIZ0 1 A0 0 DSACK1 DSACK0 0 X For a read operation, the slave responds by placing data on bits 15-8 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 then reads the operand byte from bits 15-8 and ignores bits 7-0. For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read. The slave device reads the operand from bits 15-8 of the data bus and uses the address to place the operand in the specified location. The slave then asserts DSACK1 to terminate the bus cycle. 3-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 3.2.3.3 BYTE OPERAND TO 16-BIT PORT, ODD (A0 = 1). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single-byte operand. BYTE OPERAND OP0 0 7 DATA BUS CYCLE 1 D15 D8 D7 D0 (OP0) OP0 SIZ1 0 SIZ0 1 A0 1 DSACK1 DSACK0 0 X Freescale Semiconductor, Inc... For a read operation, the slave responds by placing data on bits 7-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 then reads the operand byte from bits 7-0 and ignores bits 15-8. For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read. The slave device reads the operand from bits 7-0 of the data bus and uses the address to place the operand in the specified location. The slave then asserts DSACK1 to terminate the bus cycle. 3.2.3.4 WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a word operand. WORD OPERAND OP0 15 OP1 87 0 DATA BUS D15 D8 D7 D0 (OP1) OP0 CYCLE 1 (OP1) OP1 CYCLE 2 SIZ1 1 0 SIZ0 0 1 A0 0 1 DSACK1 DSACK0 1 0 1 0 For a read operation, the slave responds by placing the most significant byte of the operand on bits 15-8 of the data bus and asserting DSACK0 to indicate an 8-bit port. The MC68340 reads the most significant byte of the operand from bits 15-8 and ignores bits 7-0. The MC68340 then decrements the transfer size counter, increments the address, and reads the least significant byte of the operand from bits 15-8 of the data bus. For a write operation, the MC68340 drives the word operand on bits 15-0 of the data bus. The slave device then reads the most significant byte of the operand from bits 15-8 of the data bus and asserts DSACK0 to indicate that it received the data but is an 8-bit port. The MC68340 then decrements the transfer size counter, increments the address, and writes the least significant byte of the operand to bits 15-8 of the data bus. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-9 Freescale Semiconductor, Inc. 3.2.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the size pins to indicate a word operand. WORD OPERAND OP0 OP1 15 0 D15 D8 D7 D0 DATA BUS CYCLE 1 OP0 OP1 SIZ1 1 SIZ0 0 A0 0 DSACK1 DSACK0 0 X Freescale Semiconductor, Inc... For a read operation, the slave responds by placing the data on bits 15-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the MC68340 reads the data on the data bus and terminates the cycle. For a write operation, the MC68340 drives the word operand on bits 15-0 of the data bus. The slave device then reads the entire operand from bits 15-0 of the data bus and asserts DSACK1 to terminate the bus cycle. 3.2.3.6 LONG-WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a long-word operand. OP0 LONG-WORD OPERAND 31 DATA BUS D15 CYCLE 1 CYCLE 2 CYCLE 3 CYCLE 4 OP1 23 OP0 OP1 OP2 OP3 D8 D7 D0 (OP1) (OP1) (OP3) (OP3) OP2 15 OP3 7 SIZ1 0 1 1 0 0 SIZ0 0 1 0 1 A0 0 1 0 1 DSACK1 DSACK0 1 0 1 0 1 0 1 0 For a read operation, shown in Figure 3-3, the slave responds by placing the most significant byte of the operand on bits 15-8 of the data bus and asserting DSACK0 to indicate an 8-bit port. The MC68340 reads the most significant byte of the operand (byte 0) from bits 15-8 and ignores bits 7-0. The MC68340 then decrements the transfer size counter, increments the address, initiates a new cycle, and reads byte 1 of the operand from bits 15-8 of the data bus. The MC68340 repeats the process of decrementing the transfer size counter, incrementing the address, initiating a new cycle, and reading a byte to transfer the remaining two bytes. For a write operation, shown in Figure 3-4, the MC68340 drives the two most significant bytes of the operand on bits 15-0 of the data bus. The slave device then reads only the most significant byte of the operand (byte 0) from bits 15-8 of the data bus and asserts DSACK0 to indicate reception and an 8-bit port. The MC68340 then decrements the transfer size counter, increments the address, and writes byte 1 of the operand to bits 15-8 of the data bus. The MC68340 continues to decrement the transfer size counter, increment the address, and write a byte to transfer the remaining two bytes to the slave device. 3-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 CLKOUT A31-A0 Freescale Semiconductor, Inc... FC3-FC0 R/W AS DS SIZ0 4 BYTES 3 BYTES 2 BYTES 1 BYTE SIZ1 DSACK0 DSACK1 OP0 D15-D8 OP1 OP3 OP2 D7-D0 BYTE READ BYTE BYTE READ READ LONG-WORD OPERAND READ FROM 8-BIT BUS BYTE READ Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-11 Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 CLKOUT A31-A0 FC3-FC0 R/W AS Freescale Semiconductor, Inc... DS SIZ0 3 BYTES 4 BYTES 1 BYTE 2 BYTES SIZ1 DSACK0 DSACK1 D15-D8 OP0 OP1 OP2 OP3 D7-D0 (OP1) (OP1) (OP3) (OP3) WRITE WRITE WRITE WRITE LONG-WORD OPERAND WRITE TO 8-BIT BUS Figure 3-4. Long-Word Operand Write Timing to 8-Bit Port 3.2.3.7 LONG-WORD OPERAND TO 16-BIT PORT, ALIGNED. Figure 3-5 shows both long-word and word read and write timing to a 16-bit port. LONG-WORD OPERAND OP0 31 D15 DATA BUS CYCLE 1 CYCLE 2 3-12 OP1 OP2 23 15 D8 D7 OP0 OP2 D0 OP1 OP3 OP3 7 0 SIZ1 0 1 SIZ0 0 0 A0 0 0 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com DSACK1 DSACK0 0 X 0 X MOTOROLA Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S4 S2 CLKOUT A31-A0 FC3-FC0 R/W AS Freescale Semiconductor, Inc... DS SIZ0 2 BYTES 4 BYTES 2 BYTES 4 BYTES 2 BYTES 2 BYTES SIZ1 DSACK0 DSACK1 D15-D8 OP0 OP2 OP0 OP0 OP2 OP0 D7-D0 OP1 OP3 OP1 OP1 OP3 OP1 LONG WORD READ FROM 16-BIT BUS WORD READ FROM 16-BIT BUS LONG WORD WRITE TO 16-BIT BUS WORD WRITE TO 16-BIT BUS Figure 3-5. Long-Word and Word Read and Write Timing--16-Bit Port The MC68340 drives the address bus with the desired address and drives the SIZx pins to indicate a long-word operand. For a read operation, the slave responds by placing the two most significant bytes of the operand on bits 15-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 reads the two most significant bytes of the operand (bytes 0 and 1) from bits 15-0. The MC68340 then decrements the transfer size counter by 2, increments the address by 2, initiates a new cycle, and reads bytes 2 and 3 of the operand from bits 15-0 of the data bus. For a write operation, the MC68340 drives the two most significant bytes of the operand on bits 15-0 of the data bus. The slave device then reads the two most significant bytes of the operand (bytes 0 and 1) from bits 15-0 of the data bus and asserts DSACK1 to indicate reception and a 16-bit port. The MC68340 then decrements the transfer size counter by 2, increments the address by 2, and writes bytes 2 and 3 of the operand to bits 15-0 of the data bus. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-13 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 3.2.4 Bus Operation The MC68340 bus is asynchronous, allowing external devices connected to the bus to operate at clock frequencies different from the clock for the MC68340. Bus operation uses the handshake lines (AS, DS, DSACK1/DSACK0, BERR, and HALT ) to control data transfers. AS signals a valid address on the address bus, and DS is used as a condition for valid data on a write cycle. Decoding the SIZx outputs and lower address line A0 provides strobes that select the active portion of the data bus. The slave device (memory or peripheral) responds by placing the requested data on the correct portion of the data bus for a read cycle or by latching the data on a write cycle; the slave asserts the DSACK1/DSACK0 combination that corresponds to the port size to terminate the cycle. Alternatively, the SIM40 can be programmed to assert the DSACK1/ DSACK0 combination internally and respond for the slave. If no slave responds or the access is invalid, external control logic may assert BERR to abort the bus cycle or BERR with HALT to retry the bus cycle. DSACK can be asserted before the data from a slave device is valid on a read cycle. The length of time that DSACK may precede data must not exceed a specified value in any asynchronous system to ensure that valid data is latched into the MC68340. (See Section 11 Electrical Characteristics for timing parameters.) Note that no maximum time is specified from the assertion of AS to the assertion of DSACK . Although the MC68340 can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK , the MC68340 inserts wait cycles in clock-period increments until DSACK is recognized. BERR and/or HALT can be asserted after DSACK is asserted. BERR and or HALT must be asserted within the time specified after DSACK is asserted in any asynchronous system. If this maximum delay time is violated, the MC68340 may exhibit erratic behavior. 3.2.5 Synchronous Operation with DSACK Although cycles terminated with DSACK are classified as asynchronous, cycles terminated with DSACK can also operate synchronously in that signals are interpreted relative to clock edges. The devices that use these cycles must synchronize the response to the MC68340 clock (CLKOUT) to be synchronous. Since the devices terminate bus cycles with DSACK, the dynamic bus sizing capabilities of the MC68340 are available. The minimum cycle time for these cycles is also three clocks. To support systems that use the system clock to generate DSACK and other asynchronous inputs, the asynchronous input setup time and the asynchronous input hold time are given. If the setup and hold times are met for the assertion or negation of a signal such as DSACK, the MC68340 is guaranteed to recognize that signal level on that specific falling edge of the system clock. If the assertion of DSACK is recognized on a particular falling edge of the clock, valid data is latched into the MC68340 (for a read cycle) on the next falling clock edge if the data meets the data setup time. In this case, the parameter for asynchronous operation can be ignored. The timing parameters are described in Section 11 Electrical Characteristics. 3-14 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. If a system asserts DSACK for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACK (and/or BERR/ HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles terminated with DSACK (three clocks per cycle). When BERR (or BERR and HALT) is asserted after DSACK, BERR (and HALT) must meet the appropriate setup time prior to the falling clock edge one clock cycle after DSACK is recognized. This setup time is critical, and the MC68340 may exhibit erratic behavior if it is violated. When operating synchronously, the data-in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to DS. Freescale Semiconductor, Inc... 3.2.6 Fast Termination Cycles With an external device that has a fast access time, the chip select circuit fast termination enable (FTE) can provide a two-clock external bus transfer. Since the chip select circuits are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock. Refer to Section 4 System Integration Module for more information on chip selects.When fast termination is selected, the DD bits of the corresponding address mask register are overridden. Fast termination can only be used with zero wait states. To use the fast termination option, an external device should be fast enough to have data ready, within the specified setup time, by the falling edge of S4. Figure 3-6 shows the DSACK timing for a read with two wait states, followed by a fast termination read and write. When using the fast termination option, DS is asserted only in a read cycle, not in a write cycle. S0 S1 S2 S3 SW SW* SW SW* S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 CLKOUT AS DS R/W DSACKx D15-D0 TWO WAIT STATES IN READ FAST TERMINATION READ FAST TERMINATION WRITE * DSACKx only internally asserted for fast termination cycles. Figure 3-6. Fast Termination Timing MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-15 Freescale Semiconductor, Inc. 3.3 DATA TRANSFER CYCLES The transfer of data between the MC68340 and other devices involves the following signals: * Address Bus A31-A0 * Data Bus D15-D0 Freescale Semiconductor, Inc... * Control Signals The address bus and data bus are parallel, nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the bus uses a handshake protocol to ensure correct movement of the data. In all bus cycles, the bus master is responsible for de-skewing all signals it issues at both the start and end of the cycle. In addition, the bus master is responsible for de-skewing the acknowledge and data signals from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations. Each bus cycle is defined as a succession of states that apply to the bus operation. These states are different from the MC68340 states described for the CPU32. The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states. 3.3.1 Read Cycle During a read cycle, the MC68340 receives data from a memory or peripheral device. If the instruction specifies a long-word or word operation, the MC68340 attempts to read two bytes at once. For a byte operation, the MC68340 reads one byte. The section of the data bus from which each byte is read depends on the operand size, address signal A0, and the port size. Refer to 3.2.1 Dynamic Bus Sizing and 3.2.2 Misaligned Operands for more information. Figure 3-7 is a flowchart of a word read cycle. SLAVE BUS MASTER ADDRESS DEVICE 1. 2. 3. 4. 5. SET R/W TO READ DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC3-FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS AND DS ACQUIRE DATA PRESENT DATA 1. DECODE ADDRESS 2. PLACE DATA ON D15-D0 3. DRIVE DSACKx SIGNALS 1. LATCH DATA 2. NEGATE AS AND DS START NEXT CYCLE TERMINATE CYCLE 1. REMOVE DATA FROM D15-D0 2. NEGATE DSACKx Figure 3-7. Word Read Cycle Flowchart 3-16 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. State 0--The read cycle starts in state 0 (S0). During S0, the MC68340 places a valid address on A31-A0 and valid function codes on FC3-FC0. The function codes select the address space for the cycle. The MC68340 drives R/ W high for a read cycle. SIZ1/SIZ0 become valid, indicating the number of bytes requested for transfer. State 1--One-half clock later, in state 1 (S1), the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during S1. The selected device uses R/ W, SIZ1 or SIZ0, A0, and DS to place its information on the data bus. One or both of the bytes (D15-D8 and D7-D0) are selected by SIZ1/SIZ0 and A0. Freescale Semiconductor, Inc... State 2--As long as at least one of the DSACK signals is recognized on the falling edge of S2 (meeting the asynchronous input setup time requirement), data is latched on the falling edge of S4, and the cycle terminates. State 3--If DSACK is not recognized by the start of state 3 (S3), the MC68340 inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized. State 4--At the falling edge of state 4 (S4), the MC68340 latches the incoming data and samples DSACK to get the port size. State 5--The MC68340 negates AS and DS during state 5 (S5). It holds the address valid during S5 to provide address hold time for memory systems. R/ W , SIZ1 and SIZ0, and FC3-FC0 also remain valid throughout S5. The external device keeps its data and DSACK signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK within approximately one clock period after sensing the negation of AS or DS . DSACK signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-17 Freescale Semiconductor, Inc. 3.3.2 Write Cycle During a write cycle, the MC68340 transfers data to memory or a peripheral device. Figure 3-8 is a flowchart of a word write cycle. BUS MASTER SLAVE ADDRESS DEVICE Freescale Semiconductor, Inc... 1. 2. 3. 4. 5. 6. 7. SET R/W TO WRITE DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC3-FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS PLACE DATA ON D15-D0 ASSERT DS TERMINATE OUTPUT TRANSFER ACCEPT DATA 1. DECODE ADDRESS 2. LATCH DATA FROM D15-D0 3. ASSERT DSACKx SIGNALS 1. NEGATE DS AND AS 2. REMOVE DATA FROM D15-D0 TERMINATE CYCLE 1. NEGATE DSACKx START NEXT CYCLE Figure 3-8. Word Write Cycle Flowchart State 0--The write cycle starts in S0. During S0, the MC68340 places a valid address on A31-A0 and valid function codes on FC3-FC0. The function codes select the address space for the cycle. The MC68340 drives R/W low for a write cycle. SIZ1/SIZ0 become valid, indicating the number of bytes to be transferred. State 1--One-half clock later during S1, the MC68340 asserts AS, indicating a valid address on the address bus. State 2--During S2, the MC68340 places the data to be written onto D15-D0, and samples DSACK at the end of S2. State 3--The MC68340 asserts DS during S3, indicating that data is stable on the data bus. As long as at least one of the DSACK signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK is not recognized by the start of S3, the MC68340 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized. The selected device uses R/W, SIZ1/SIZ0, and A0 to latch data from the appropriate byte(s) of D15-D8 and D7-D0. SIZ1/SIZ0 and A0 select the bytes of the data bus. If it has not already done so, the device asserts DSACK to signal that it has successfully stored the data. 3-18 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. State 4--The MC68340 issues no new control signals during S4. State 5--The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/ W, SIZ1/SIZ0, and FC3- FC0 also remain valid throughout S5. The external device must keep DSACK asserted until it detects the negation of AS or DS (whichever it detects first). The device must negate DSACK within approximately one clock period after sensing the negation of AS or DS . DSACK signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. Freescale Semiconductor, Inc... 3.3.3 Read-Modify-Write Cycle The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the MC68340, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the MC68340 asserts RMC to indicate that an indivisible operation is occurring. The MC68340 does not issue a BG signal in response to a BR signal during this operation. Figure 3-9 is an example of a functional timing diagram of a read-modify-write instruction specified in terms of clock periods. S0 S2 S0 S4 S2 S4 S0 CLK OUT A31-A30 FC3-FC0 SIZ1-SIZ0 R/W RMC AS DS DSACKx D15-D0 READ WRITE INDIVISIBLE CYCLE Figure 3-9. Read-Modify-Write Cycle Timing MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-19 Freescale Semiconductor, Inc. State 0--The MC68340 asserts RMC in S0 to identify a read-modify-write cycle. The MC68340 places a valid address on A31-A0 and valid function codes on FC3-FC0. The function codes select the address space for the operation. SIZ1/SIZ0 become valid in S0 to indicate the operand size. The MC68340 drives R/W high for the read cycle. State 1--One-half clock later during S1, the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during S1. Freescale Semiconductor, Inc... State 2--The selected device uses R/W, SIZ1/SIZ0, A0, and DS to place information on the data bus. Either or both of the bytes (D15-D8 and D7-D0) are selected by SIZ1/SIZ0 and A0. Concurrently, the selected device may assert DSACK. State 3--As long as at least one of the DSACK signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACK is not recognized by the start of S3, the MC68340 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample the DSACK signals on the falling edges of the clock until one is recognized. State 4--At the end of S4, the MC68340 latches the incoming data. State 5--The MC68340 negates AS and DS during S5. If more than one read cycle is required to read in the operand(s), S0-S5 are repeated for each read cycle. When finished reading, the MC68340 holds the address, R/W, and FC3-FC0 valid in preparation for the write portion of the cycle. The external device keeps its data and DSACK signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove the data and negate DSACK within approximately one clock period after sensing the negation of AS or DS. DSACK signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation. Idle States--The MC68340 does not assert any new control signals during the idle states, but it may internally begin the modify portion of the cycle at this time. S0-S5 are omitted if no write cycle is required. If a write cycle is required, R/W remains in the read mode until S0 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S2. State 0--The MC68340 drives R/ W low for a write cycle. Depending on the write operation to be performed, the address lines may change during S0. State 1--In S1, the MC68340 asserts AS, indicating a valid address on the address bus. State 2--During S2, the MC68340 places the data to be written onto D15-D0. State 3--The MC68340 asserts DS during S3, indicating stable data on the data bus. As long as at least one of the DSACK signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK is not recognized by the start of S3, the MC68340 inserts wait states instead of 3-20 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized. The selected device uses R/ W, DS, SIZ1/SIZ0, and A0 to latch data from the appropriate section(s) of D15-D8 and D7-D0. SIZ1/SIZ0 and A0 select the data bus sections. If it has not already done so, the device asserts DSACK when it has successfully stored the data. Freescale Semiconductor, Inc... State 4--The MC68340 issues no new control signals during S4. State 5--The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/ W and FC3-FC0 also remain valid throughout S5. If more than one write cycle is required, states S0-S5 are repeated for each write cycle. The external device keeps DSACK asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK within approximately one clock period after sensing the negation of AS or DS. 3.4 CPU SPACE CYCLES FC3-FC0 select user and supervisor program and data areas. The area selected by FC3- FC0 = $7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP broadcast, module base address register access, and interrupt acknowledge cycles described in the following paragraphs use CPU space. The CPU space type, which is encoded on A19-A16 during a CPU space operation, indicates the function that the MC68340 is performing. On the MC68340, four of the encodings are implemented as shown in Figure 3-10. All unused values are reserved by Motorola for additional CPU space types. CPU SPACE CYCLES FUNCTION CODE BREAKPOINT ACKNOWLEDGE LOW-POWER STOP BROADCAST MODULE BASE ADDRESS REGISTER ACCESS INTERRUPT ACKNOWLEDGE ADDRESS BUS 3 0 0 1 1 1 19 16 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# T 0 3 0 0 1 1 1 19 16 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 3 0 0 1 1 1 31 19 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 3 31 0 19 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1 0 0 1 1 1 CPU SPACE TYPE FIELD Figure 3-10. CPU Space Address Encoding MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-21 Freescale Semiconductor, Inc. 3.4.1 Breakpoint Acknowledge Cycle Freescale Semiconductor, Inc... The breakpoint acknowledge cycle allows external hardware to insert an instruction directly into the instruction pipeline as the program executes. The breakpoint acknowledge cycle is generated by the execution of a breakpoint instruction (BKPT) or the assertion of the BKPT pin. The T-bit state (shown in Figure 3-10) differentiates a software breakpoint cycle (T = 0) from a hardware breakpoint cycle (T = 1). When a BKPT instruction is executed (software breakpoint), the MC68340 performs a word read from CPU space, type 0, at an address corresponding to the breakpoint number (bits [2-0] of the BKPT opcode) on A4-A2, and the T-bit (A1) is cleared. If this bus cycle is terminated with BERR (i.e., no instruction word is available), the MC68340 then performs illegal instruction exception processing. If the bus cycle is terminated by DSACK , the MC68340 uses the data on D15-D0 (for 16-bit ports) or two reads from D15-D8 (for 8-bit ports) to replace the BKPT instruction in the internal instruction pipeline and then begins execution of that instruction. When the CPU32 acknowledges a BKPT pin assertion (hardware breakpoint) with background mode disabled, the CPU32 performs a word read from CPU space, type 0, at an address corresponding to all ones on A4-A2 (BKPT#7), and the T-bit (A1) is set. If this bus cycle is terminated by BERR, the MC68340 performs hardware breakpoint exception processing. If this bus cycle is terminated by DSACK, the MC68340 ignores data on the data bus and continues execution of the next instruction. NOTE The BKPT pin is sampled on the same clock phase as data and is latched with data as it enters the CPU32 pipeline. If BKPT is asserted for only one bus cycle and a pipeline flush occurs before BKPT is detected by the CPU32, BKPT is ignored. To ensure detection of BKPT by the CPU32, BKPT can be asserted until a breakpoint acknowledge cycle is recognized. The breakpoint operation flowchart is shown in Figure 3-11. Figures 3-12 and 3-13 show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes supplied on the cycle and with an exception signaled, respectively. 3-22 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 3.4.2 LPSTOP Broadcast Cycle Freescale Semiconductor, Inc... The low power stop (LPSTOP) broadcast cycle is generated by the CPU32 executing the LPSTOP instruction. Since the external bus interface must get a copy of the interrupt mask level from the CPU32, the CPU32 performs a CPU space type 3 write with the mask level encoded on the data bus, as shown in the following figure. The CPU space type 3 cycle waits for the bus to be available, and is shown externally to indicate to external devices that the MC68340 is going into LPSTOP mode. If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT. The SIM40 provides internal DSACK response to this cycle. For more information on how the SIM40 responds to LPSTOP mode, see Section 4 System Integration Module. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- I2 I1 I0 I2-I0--Interrupt Mask Level The interrupt mask level is encoded on bits 2-0 of the data bus during an LPSTOP broadcast. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-23 Freescale Semiconductor, Inc. BREAKPOINT OPERATION FLOW EXTERNAL DEVICE PROCESSOR ACKNOWLEDGE BREAKPOINT Freescale Semiconductor, Inc... IF BREAKPOINT INSTRUCTION EXECUTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19-A16 4. PLACE BREAKPOINT NUMBER ON A2-A4 5. CLEAR T-BIT (A1) 6. SET SIZE TO WORD 7. ASSERT AS AND DS IF BKPT PIN ASSERTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19-A16 4. PLACE ALL ONE'S ON A4-A2 5. SET T-BIT (A-1) TO ONE 6. SET SIZE TO WORD 7. ASSERT AS AND DS IF BREAKPOINT INSTRUCTION EXECUTED AND DSACKx IS ASSERTED: 1. LATCH DATA 2. NEGATE AS AND DS 3. GO TO (A) IF BKPT PIN ASSERTED AND DSACKx IS ASSERTED: 1. NEGATE AS AND DS 2. GO TO (A) IF BERR ASSERTED: 1. NEGATE AS AND DS 2. GO TO (B) (A) IF BREAKPOINT INSTRUCTION EXECUTED: 1. PLACE REPLACEMENT OPCODE ON DATA BUS 2. ASSERT DSACKx -OR1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKPT PIN ASSERTED: 1. ASSERT DSACKx -OR1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING (B) 1. NEGATE DSACKx or BERR IF BREAKPOINT INSTRUCTION EXECUTED: 1. PLACE LATCHED DATA IN INSTRUCTION PIPELINE 2. CONTINUE PROCESSING IF BKPT PIN ASSERTED: 1. CONTINUE PROCESSING IF BREAKPOINT INSTRUCTION EXECUTED: 1. INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED: 1. INITIATE HARDWARE BREAKPOINT PROCESSING Figure 3-11. Breakpoint Operation Flowchart 3-24 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 CLKOUT A31-A20 A19-A16 BREAKPOINT ENCODING (0000) A4-A1 BREAKPOINT NUMBER/T-BIT Freescale Semiconductor, Inc... A15-A5,A0 FC3-FC0 CPU SPACE SIZ0 SIZ1 AS DS R/W DSACKx D7-D0 D15-D8 BERR HALT BKPT BREAKPOINT OCCURS READ BREAKPOINT ACKNOWLEDGE INSTRUCTION WORD FETCH FETCHED INSTRUCTION EXECUTION Figure 3-12. Breakpoint Acknowledge Cycle Timing (Opcode Returned) MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-25 Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 CLKOUT A31-A20 BREAKPOINT ENCODING (0000) A19-A16 BREAKPOINT NUMBER/T-BIT A4-A1 Freescale Semiconductor, Inc... A15-A5, A0 FC3-FC0 CPU SPACE SIZ0 SIZ1 AS DS R/W DSACKx D7-D0 D15-D8 BERR HALT BKPT BREAKPOINT OCCURS READ BREAKPOINT ACKNOWLEDGE BUS ERROR ASSERTED EXCEPTION STACKING Figure 3-13. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 3-26 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 3.4.3 Module Base Address Register Access All internal module registers, including the SIM40, occupy a single 4-Kbyte block that is relocatable along 4-Kbyte boundaries. The location is fixed by writing the desired base address of the SIM40 block to the module base address register using the MOVES instruction. The module base address register is only accessible in CPU space at address $0003FF00. The SFC or DFC register must indicate CPU space (FC3-FC0 = $7), using the MOVEC instruction, before accessing the module base address register. Refer to Section 4 System Integration Module for additional information on the module base address register. Freescale Semiconductor, Inc... 3.4.4 Interrupt Acknowledge Bus Cycles The CPU32 makes an interrupt pending in three cases. The first case occurs when a peripheral device signals the CPU32 (with IRQ7-IRQ1) that the device requires service and the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register. The second case occurs when a transition has occurred in the case of a level 7 interrupt. A recognized level 7 interrupt must be removed for one clock cycle before a second level 7 can be recognized. The third case occurs if, upon returning from servicing a level 7 interrupt, the request level stays at 7 and the processor mask level changes from 7 to a lower level, a second level 7 is recognized. The CPU32 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the types of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing. 3.4.4.1 INTERRUPT ACKNOWLEDGE CYCLE--TERMINATED NORMALLY. When the CPU32 processes an interrupt exception, it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine. Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices that cannot supply a vector number will use the autovector cycle described in 3.4.4.2 Autovector Interrupt Acknowledge Cycle. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-27 Freescale Semiconductor, Inc. The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 3.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are as follows: 1. FC3-FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space. Freescale Semiconductor, Inc... 2. A3, A2, and A1 are set to the interrupt request level, and the IACK strobe corresponding to the current interrupt level is asserted. (Either the function codes and address signals or the IACK strobes can be monitored to determine that an interrupt acknowledge cycle is in progress and the current interrupt level.) 3. The CPU32 space type field (A19-A16) is set to $F (interrupt acknowledge). 4. Other address signals (A31-A20, A15-A4, and A0) are set to one. 5. The SIZ0/SIZ1 and R/ W signals are driven to indicate a single-byte read cycle. The responding device places the vector number on the least significant byte of its data port (for an 8-bit port, the vector number must be on D15-D8; for a 16-bit port, the vector must be on D7-D0) during the interrupt acknowledge cycle. The cycle is then terminated normally with DSACK. Figure 3-14 is a flowchart of the interrupt acknowledge cycle; Figure 3-15 shows the timing for an interrupt acknowledge cycle terminated with DSACK. INTERRUPTING DEVICE MC68340 REQUEST INTERRUPT GRANT INTERRUPT 1. SYNCHRONIZE IRQ7-IRQ1 2. COMPARE IRQ1-IRQ7 TO MASK LEVEL AND WAIT FOR INSTRUCTION TO COMPLETE 3. PLACE INTERRUPT LEVEL ON A3-A1; TYPE FIELD (A19-A16) = $F 4. SET R/W TO READ 5. SET FC3-FC0 TO 0111 6. DRIVE SIZE PINS TO INDICATE A ONE-BYTE TRANSFER 7. ASSERT AS AND DS 8. ASSERT THE CORRESPONDING IACKx STROBE. PROVIDE VECTOR NUMBER 1. PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA BUS 2. ASSERT DSACKx (OR AVEC IF NO VECTOR NUMBER) ACQUIRE VECTOR NUMBER RELEASE 1. LATCH VECTOR NUMBER 2. NEGATE DS AND AS 1. NEGATE DSACKx START NEXT CYCLE Figure 3-14. Interrupt Acknowledge Cycle Flowchart 3-28 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S2 S4 S0 0-2 CLOCKS* S1 S2 S4 S0 S2 CLKOUT A31-A4 A3-A1 INTERRUPT LEVEL A0 Freescale Semiconductor, Inc... FC3-FC0 CPU SPACE SIZ0 1 BYTE SIZ1 R/W AS DS VECTOR FROM 16-BIT PORT DSACKx VECTOR FROM 8-BIT PORT D7-D0 D15-D8 IRQ7-IRQ1 IACK7-IACK1 READ CYCLE WRITE STACK INTERNAL ARBITRATION IACK CYCLE *Internal Arbitration may take between 0-2 clock cycles. Figure 3-15. Interrupt Acknowledge Cycle Timing 3.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector (autovector). Instead of placing a vector number on the data bus and asserting DSACK, the device asserts AVEC to terminate the cycle. If the DSACK signals are asserted during an interrupt acknowledge cycle terminated by AVEC, the DSACK signals and MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-29 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... data will be ignored if AVEC is asserted before or at the same time as the DSACK signals. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK during an interrupt acknowledge cycle, the MC68340 ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)). AVEC is multiplexed with CS0. The FIRQ bit in the SIM40 module configuration register controls whether the AVEC /CS0 pin is used as an autovector input or as CS0 (refer to Section 4 System Integration Module for additional information). AVEC is only sampled during an interrupt acknowledge cycle. During all other cycles, AVEC is ignored. Additionally, AVEC can be internally generated for external devices by programming the autovector register. Seven distinct autovectors can be used, corresponding to the seven levels of interrupt available with signals IRQ7-IRQ1. Figure 3-16 shows the timing for an autovector operation. 3.4.4.3 SPURIOUS INTERRUPT CYCLE. Requested interrupts, whether internal or external, are arbitrated internally. When no internal module (including the SIM40, which responds for external requests) responds during an interrupt acknowledge cycle by arbitrating for the interrupt acknowledge cycle internally, the spurious interrupt monitor generates an internal bus error signal to terminate the vector acquisition. The MC68340 automatically generates the spurious interrupt vector number (24) instead of the interrupt vector number in this case. When an external device does not respond to an interrupt acknowledge cycle with AVEC or DSACK , a bus monitor must assert BERR , which results in the CPU32 taking the spurious interrupt vector. If HALT is also asserted, the MC68340 retries the interrupt acknowledge cycle instead of using the spurious interrupt vector. 3-30 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S2 S4 S0 0-2 CLOCKS* S1 S2 S4 S0 S2 CLKOUT A31-A4 A3-A1 INTERRUPT LEVEL Freescale Semiconductor, Inc... A0 FC3-FC0 CPU SPACE SIZ0 1 BYTE SIZ1 R/W AS DS DSACKx D15-D0 AVEC IRQ7-IRQ1 IACK7-IACK1 CYCLE READ WRITE STACK INTERNAL ARBITRATION IACK CYCLE * Internal Arbitration may take between 0-2 clocks. Figure 3-16. Autovector Operation Timing MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-31 Freescale Semiconductor, Inc. 3.5 BUS EXCEPTION CONTROL CYCLES The bus architecture requires assertion of DSACK from an external device to signal that a bus cycle is complete. Neither DSACK nor AVEC is asserted in the following cases: * DSACK/AVEC is programmed to respond internally. * The external device does not respond. Freescale Semiconductor, Inc... * Various other application-dependent errors occur. The MC68340 provides BERR when no device responds by asserting DSACK / AVEC within an appropriate period of time after the MC68340 asserts AS . This mechanism allows the cycle to terminate and the MC68340 to enter exception processing for the error condition. HALT is also used for bus exception control. This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation, or, in combination with BERR, a retry of a bus cycle in error. To properly control termination of a bus cycle for a retry or a bus error condition, DSACK, BERR, and HALT can be asserted and negated with the rising edge of the MC68340 clock. This assures that when two signals are asserted simultaneously, the required setup and hold time for both is met for the same falling edge of the MC68340 clock. This or an equivalent precaution should be designed into the external circuitry to provide these signals. Alternatively, the internal bus monitor could be used. The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACK assertion as follows (case numbers refer to Table 3-4): * Normal Termination: DSACK is asserted; BERR and HALT remain negated (case 1). * Halt Termination: HALT is asserted at the same time as or before DSACKx, and BERR remains negated (case 2). * Bus Error Termination: BERR is asserted in lieu of, at the same time as, or before DSACK (case 3) or after DSACK (case 4), and HALT remains negated; BERR is negated at the same time as or after DSACK. * Retry Termination: HALT and BERR are asserted in lieu of, at the same time as, or before DSACK (case 5) or after DSACK (case 6); BERR is negated at the same time as or after DSACK, and HALT may be negated at the same time as or after BERR. Table 3-4 lists various combinations of control signal sequences and the resulting bus cycle terminations. To ensure predictable operation, BERR and HALT should be negated according to the specifications given in Section 11 Electrical Characteristics. DSACK BERR, and HALT may be negated after AS. If DSACK or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3). 3-32 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACK until data is verified and assert BERR and HALT simultaneously to indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is valid, assert DSACK (case 1). 2. Delay DSACK until data is verified and assert BERR with or without DSACK if data is in error (case 3). This initiates exception processing for software handling of the condition. Freescale Semiconductor, Inc... 3. Return DSACK prior to data verification; if data is invalid, BERR is asserted on the next clock cycle (case 4). This initiates exception processing for software handling of the condition. 4. Return DSACK prior to data verification; if data is invalid, assert BERR and HALT on the next clock cycle (case 6). The memory controller can then correct the RAM prior to or during the automatic retry. Table 3-4. DSACK, BERR, and HALT Assertion Results Asserted on Rising Edge of State Case Num Control Signal N N+2 1 DSACK BERR HALT A NA NA S NA X Normal cycle terminate and continue. 2 DSACK BERR HALT A NA A/S S NA S Normal cycle terminate and halt; continue when HALT negated. 3 DSACK BERR HALT NA/A A NA X S X Terminate and take bus error exception, possibly deferred. 4 DSACK BERR HALT A NA NA X A NA Terminate and take bus error exception, possibly deferred. 5 DSACK BERR HALT NA/A A A/S X S S Terminate and retry when HALT negated. 6 DSACK BERR HALT A NA NA X A A Terminate and retry when HALT negated. NOTES: N -- A -- NA -- X -- S -- MOTOROLA Result Number of the current even bus state (e.g., S2, S4, etc.) Signal is asserted in this bus state Signal is not asserted in this state Don't care Signal was asserted in previous state and remains asserted in this state MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-33 Freescale Semiconductor, Inc. 3.5.1 Bus Errors Freescale Semiconductor, Inc... BERR can be used to abort the bus cycle and the instruction being executed. BERR takes precedence over DSACK provided it meets the timing constraints described in Section 11 Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredictable operation of the MC68340. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle. When BERR is issued to terminate a bus cycle, the MC68340 can enter exception processing immediately following the bus cycle, or it can defer processing the exception. The instruction prefetch mechanism requests instruction words from the bus controller before it is ready to execute them. If a bus error occurs on an instruction fetch, the MC68340 does not take the exception until it attempts to use that instruction word. Should an intervening instruction cause a branch or should a task switch occur, the bus error exception does not occur. The bus error condition is recognized during a bus cycle in any of the following cases: * DSACK and HALT are negated, and BERR is asserted. * HALT and BERR are negated, and DSACK is asserted. BERR is then asserted within one clock cycle ( HALT remains negated). * BERR and HALT are asserted simultaneously, indicating a retry. When the MC68340 recognizes a bus error condition, it terminates the current bus cycle in the normal way. Figure 3-17 shows the timing of a bus error for the case in which DSACK is not asserted. Figure 3-18 shows the timing for a bus error that is asserted after DSACK. Exceptions are taken in both cases. Refer to Section 5 CPU32 for details of bus error exception processing. In the second case, in which BERR is asserted after DSACK is asserted, BERR must be asserted within the time specified for purely asynchronous operation, or it must be asserted and remain stable during the sample window around the next falling edge of the clock after DSACK is recognized. If BERR is not stable at this time, the MC68340 may exhibit erratic behavior. BERR has priority over DSACK . In this case, data may be present on the bus, but it may not be valid. This sequence can be used by systems that have memory error detection and correction logic and by external cache memories. 3-34 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S2 SW SW S4 S0 S2 S4 CLKOUT Freescale Semiconductor, Inc... A31-A0 FC3-FC0 R/W AS DS DSACKx D15-D0 BERR READ CYCLE WITH BUS ERROR INTERNAL PROCESSING STACK WRITE Figure 3-17. Bus Error without DSACK MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-35 Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 CLKOUT A31-A0 FC3-FC0 R/W Freescale Semiconductor, Inc... AS DS DSACKx D15-D0 BERR WRITE CYCLE INTERNAL PROCESSING STACK WRITE Figure 3-18. Late Bus Error with DSACK 3.5.2 Retry Operation When both BERR and HALT are asserted by an external device during a bus cycle, the MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is similar to the delayed BERR signal described previously, can also occur (see Figure 3-20). The MC68340 terminates the bus cycle, places the control signals in their inactive state, and does not begin another bus cycle until the BERR and HALT signals are negated by external logic. After a synchronization delay, the MC68340 retries the previous cycle using the same access information (address, function code, size, etc.). BERR should be negated before S2 of the retried cycle to ensure correct operation of the retried cycle. 3-36 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S2 SW SW S4 S0 S2 S4 CLKOUT A31-A0 FC3-FC0 R/W Freescale Semiconductor, Inc... AS DS DSACKx D15-D0 DATA IGNORED BERR HALT READ CYCLE WITH RETRY HALT READ RERUN Figure 3-19. Retry Sequence The MC68340 retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. Asserting BR along with BERR and HALT provides a relinquish and retry operation. The MC68340 does not relinquish the bus during a read-modify-write operation. Any device that requires the MC68340 to give up the bus and retry a bus cycle during a read-modify-write cycle must assert only BERR and BR (HALT must not be included). The bus error handler software should examine the read-modify-write bit in the special status word (see Section 5 CPU32) and take the appropriate action to resolve this type of fault when it occurs. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-37 Freescale Semiconductor, Inc. S0 S2 S4 S0 S2 S4 CLKOUT A31-A0 FC3-FC0 R/W AS Freescale Semiconductor, Inc... DS DSACKx D15-D10 BERR HALT WRITE CYCLE HALT WRITE RERUN Figure 3-20. Late Retry Sequence 3.5.3 Halt Operation When HALT is asserted and BERR is not asserted, the MC68340 halts external bus activity at the next bus cycle boundary (see Figure 3-21). HALT by itself does not terminate a bus cycle. Negating and reasserting HALT in accordance with the correct timing requirements provides a single-step (bus cycle to bus cycle) operation. Since HALT affects external bus cycles only, a program that does not require use of the external bus may continue executing. The single-cycle mode allows the user to proceed through (and debug) external MC68340 operations, one bus cycle at a time. Since the occurrence of a bus error while HALT is asserted causes a retry operation, the user must anticipate retry cycles while debugging in the single-cycle mode. The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, single instructions, or changes in program flow. When the MC68340 completes a bus cycle with HALT asserted, D15-D0 is placed in the high-impedance state, and bus control signals are negated (not high-impedance state); the A31-A0, FCx, SIZx, and R/W signals remain in the same state. The halt operation has no effect on bus arbitration (see 3.6 Bus Arbitration). When bus arbitration occurs while the MC68340 is halted, the address and control signals are also placed in the highimpedance state. Once bus mastership is returned to the MC68340, if HALT is still 3-38 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. asserted, the A31-A0, FCx, SIZx, and R/ W signals are again driven to their previous states. The MC68340 does not service interrupt requests while it is halted. S0 S2 S0 S4 S2 S4 S0 CLKOUT A31-A0 FC3-FC0 Freescale Semiconductor, Inc... R/W AS DS DSACKx D15-D10 HALT BR BG BGACK READ HALT (ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) READ Figure 3-21. HALT Timing 3.5.4 Double Bus Fault A double bus fault results when a bus error or an address error occurs during the exception processing sequence for any of the following: * A previous bus error * A previous address error * A reset For example, the MC68340 attempts to stack several words containing information about the state of the machine while processing a bus error exception. If a bus error exception MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-39 Freescale Semiconductor, Inc. occurs during the stacking operation, the second error is considered a double bus fault. When a double bus fault occurs, the MC68340 halts and asserts HALT. Only a reset operation can restart a halted MC68340. However, bus arbitration can still occur (see 3.6 Bus Arbitration). A second bus error or address error that occurs after exception processing has completed (during the execution of the exception handler routine or later) does not cause a double bus fault. A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault. The MC68340 continues to retry the same bus cycle as long as the external hardware requests it. Reset can also be generated internally by the halt monitor (see Section 5 CPU32). Freescale Semiconductor, Inc... 3.6 BUS ARBITRATION The bus design of the MC68340 provides for a single bus master at any one time, either the MC68340 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the MC68340 internal bus. Bus arbitration is the protocol by which an external device becomes bus master; the bus controller in the MC68340 manages the bus arbitration signals so that the MC68340 has the lowest priority. External devices that need to obtain the bus must assert the bus arbitration signals in the sequences described in the following paragraphs. Systems having several devices that can become bus master require external circuitry to assign priorities to the devices so that, when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. The sequence of the protocol is as follows: 1. An external device asserts BR. 2. The MC68340 asserts BG to indicate that the bus is available. 3. The external device asserts BGACK to indicate that it has assumed bus mastership. NOTE The MC68340 does not place CS3-CS0 in a high-impedance state after reset or when the bus is granted to an external master. BR may be issued any time during a bus cycle or between cycles. BG is asserted in response to BR. To guarantee operand coherency, BG is only asserted at the end of an operand transfer. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal. When the requesting device receives BG and more than one external device can be bus master, the requesting device should begin whatever arbitration is required. When the external device assumes bus mastership, it asserts BGACK and maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: 1) it must have received BG through the arbitration process, and 2) BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. 3-40 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Figure 3-22 is a flowchart showing bus arbitration for a single device. This technique allows processing of bus requests during data transfer cycles. Refer to Figures 3-23 and 3-24 for bus arbitration timing diagrams. BR is negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the MC68340 and one device capable of bus mastership. In a system having a number of devices capable of bus mastership, BR from each device can be wireORed to the MC68340. In such a system, more than one bus request could be asserted simultaneously. BG is negated a few clock cycles after the transition of BGACK. However, if bus requests are still pending after the negation of BG, the MC68340 asserts another BG within a few clock cycles after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished using the bus. The following paragraphs provide additional information about the three steps in the arbitration process. Bus arbitration requests are recognized during normal processing, HALT assertion, and a CPU32 halt caused by a double bus fault. PROCESSOR REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION 1. ASSERT BR 1. ASSERT BG ACKNOWLEDGE BUS MASTERSHIP TERMINATE ARBITRATION 1. NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) 1. EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2. NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3. NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4. BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1. PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP RE-ARBITRATE OR RESUME PROCESSOR OPERATION 1. NEGATE BGACK Figure 3-22. Bus Arbitration Flowchart for Single Request MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-41 Freescale Semiconductor, Inc. CLKOUT A31-A0 D15-D0 AS BR Freescale Semiconductor, Inc... BG BGACK Figure 3-23. Bus Arbitration Timing Diagram--Idle Bus Case S0 S1 S2 S3 S4 S5 CLKOUT A31-A0 D15-D0 AS DS R/W DSACK0, DSACK1 BR BG BGACK Figure 3-24. Bus Arbitration Timing Diagram--Active Bus Case 3-42 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 3.6.1 Bus Request External devices capable of becoming bus masters request the bus by asserting BR. This signal can be wire-ORed to indicate to the MC68340 that some external device requires control of the bus. The MC68340 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started). If no BGACK is received while the BR is active, the MC68340 remains bus master once BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership. Freescale Semiconductor, Inc... 3.6.2 Bus Grant The MC68340 supports operand coherency; thus, if an operand transfer requires multiple bus cycles, the MC68340 does not release the bus until the entire transfer is complete. Therefore, assertion of BG is subject to the following constraints: * The minimum time for BG assertion after BR is asserted depends on internal synchronization (see Section 11 Electrical Characteristics). * During an external operand transfer, the MC68340 does not assert BG until after the last cycle of the transfer (determined by SIZx and DSACK). * During an external operand transfer, the MC68340 does not assert BG as long as RMC is asserted. * If the show cycle bits SHEN1-SHEN0 = 01, the MC68340 does not assert BG to an external master. Externally, the BG signal can be routed through a daisy-chained network or a priorityencoded network. The MC68340 is not affected by the method of arbitration as long as the protocol is obeyed. 3.6.3 Bus Grant Acknowledge An external device cannot request and be granted the external bus while another device is the active bus master. A device that asserts BGACK remains the bus master until it negates BGACK . BGACK should not be negated until all required bus cycles are completed. Bus mastership is terminated at the negation of BGACK. Once an external device receives the bus and asserts BGACK, it should negate BR. If BR remains asserted after BGACK is asserted, the MC68340 assumes that another device is requesting the bus and prepares to issue another BG. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-43 Freescale Semiconductor, Inc. 3.6.4 Bus Arbitration Control Freescale Semiconductor, Inc... The bus arbitration control unit in the MC68340 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68340 are internally synchronized in a maximum of two cycles of the clock. As shown in Figure 3-25 input signals labeled R and A are internally synchronized versions of B R and BGACK respectively. The BG output is labeled G, and the internal high-impedance control signal is labeled T. If T is true, the address, data, and control buses are placed in the highimpedance state after the next rising edge following the negation of AS and RMC . All signals are shown in positive logic (active high) regardless of their true active voltage level. The state machine shown in Figure 3-25 does not have a state 1 or state 4. State changes occur on the next rising edge of the clock after the internal signal is valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals (controlled by T) are driven by the MC68340 immediately following a state change, when bus mastership is returned to the MC68340. State 0, in which G and T are both negated, is the state of the bus arbiter while the MC68340 is bus master. R and A keep the arbiter in state 0 as long as they are both negated. The MC68340 does not allow arbitration of the external bus during the RMC sequence. For the duration of this sequence, the MC68340 ignores the BR input. If mastership of the bus is required during an RMC operation, BERR must be used to abort the RMC sequence. 3.6.5 Show Cycles The MC68340 can perform data transfers with its internal modules without using the external bus, but, when debugging, it is desirable to have address and data information appear on the external bus. These external bus cycles, called show cycles, are distinguished by the fact that AS is not asserted externally. DS is used to signal address strobe timing in show cycles. After reset, show cycles are disabled and must be enabled by writing to the SHEN bits in the module configuration register (see 4.3.2.1 Module Configuration Register (MCR)). When show cycles are disabled, the A31-A0, FCx, SIZx, and R/ W signals continue to reflect internal bus activity. However, AS and DS are not asserted externally, and the external data bus remains in a high-impedance state. When show cycles are enabled, DS indicates address strobe timing and the external data bus contains data. The following paragraphs are a state-by-state description of show cycles, and Figure 3-26 illustrates a show cycle timing diagram. Refer to Section 11 Electrical Characteristics for specific timing information. 3-44 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. RA + B GTV AB STATE 0 RA Freescale Semiconductor, Inc... RAB RA G TV RA STATE 3 R+A G TV STATE 2 R A +A G TV R R STATE 5 RA G TV RA STATE 6 RA R - BUS REQUEST A - BUS GRANT ACKNOWLEDGE B - BUS CYCLE IN PROGRESS G - BUS GRANT T - THREE-STATE SIGNAL TO BUS CONTROL V - BUS AVAILABLE TO BUS CONTROL Figure 3-25. Bus Arbitration State Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-45 Freescale Semiconductor, Inc. State 0--During state 0, the A31-A0 and FCx become valid, R/ W is driven to indicate a show read or write cycle, and the SIZx pins indicate the number of bytes to transfer. During a read, the addressed peripheral is driving the data bus, and the user must take care to avoid bus conflicts. State 41--One-half clock cycle later, DS (rather than AS ) is asserted to indicate that address information is valid. Freescale Semiconductor, Inc... State 42--No action occurs in state 42. The bus controller remains in state 42 (wait states will be inserted) until the internal read cycle is complete. State 43--When DS is negated, show data is valid on the next falling edge of the system clock. The external data bus drivers are enabled so that data becomes valid on the external bus as soon as it is available on the internal bus. State 0--The A31-A0, FCx, R/W , and SIZx pins change to begin the next cycle. Data from the preceding cycle is valid through state 0. S0 S41 S42 S43 S0 S1 S2 CLKOUT A31-A0, FC2-FC0, SIZ1-SIZ0 R/W AS, CS DS D15-D0 BKPT SHOW CYCLE START OF EXTERNAL CYCLE Figure 3-26. Show Cycle Timing Diagram 3.7 RESET OPERATION The MC68340 has reset control logic to determine the cause of reset, synchronize it if necessary, and assert the appropriate reset lines. The reset control logic can independently drive three different lines: 1. EXTRST (external reset) drives the external RESET pin. 2. CLKRST (clock reset) resets the clock module. 3-46 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 3. INTRST (internal reset) goes to all other internal circuits. Synchronous reset sources are not asserted until the end of the current bus cycle, whether or not RMC is asserted. The internal bus monitor is automatically enabled for synchronous resets; therefore, if the current bus cycle does not terminate normally, the bus monitor terminates it. Only single-byte or word transfers are guaranteed valid for synchronous resets. An external or clock reset is a synchronous reset source. Freescale Semiconductor, Inc... Asynchronous reset sources indicate a catastrophic failure, and the reset controller logic immediately resets the system. Resetting the MC68340 causes any bus cycle in progress to terminate as if DSACK or BERR had been asserted. In addition, the MC68340 appropriately initializes registers for a reset exception. Asynchronous reset sources include power-up, software watchdog, double bus fault resets, and execution of the RESET instruction. If an external device drives RESET low, RESET should be asserted for at least 590 clock periods to ensure that the MC68340 resets. The reset control logic holds reset asserted internally until the external RESET is released. When the reset control logic detects that external RESET is no longer being driven, it drives both internal and external reset low for an additional 512 cycles to guarantee this length of reset to the entire system. Figure 3-27 shows the RESET timing. 1 CLOCK RESET 590 CLOCK 512 CLOCK PULLED EXTERNAL DRIVEN BY MC68340 Figure 3-27. Timing for External Devices Driving RESET If reset is asserted from any other source, the reset control logic asserts RESET for 328 input clock periods plus 512 output clock periods, and until the source of reset is negated. After any internal reset occurs, a 14-cycle rise time is allowed before testing for the presence of an external reset. If no external reset is detected, the CPU32 begins its vector fetch. Figure 3-28 is a timing diagram of the power-up reset operation, showing the relationships between RESET, V CC , and bus signals. During the reset period, the entire bus threestates except for non-three-statable signals, which are driven to their inactive state. Once RESET negates, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for RESET exception processing begins. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-47 Freescale Semiconductor, Inc. CLKOUT VCO LOCK VCC 328 x TCLKIN 512 x TCLKOUT 14 CLOCKS RESET BUS CYCLES ADDRESS AND CONTROL SIGNALS THREE-STATED Freescale Semiconductor, Inc... BUS STATE UNKNOWN 1 2 3 4 NOTES: 1. Internal start-up time. 2. SSP read here. 3. PC read here. 4. First instruction fetched here. Figure 3-28. Power-Up Reset Timing Diagram When a RESET instruction is executed, the MC68340 drives the RESET signal for 512 clock cycles. The SIM40 registers and the module control registers in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction. 3-48 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 4 SYSTEM INTEGRATION MODULE Freescale Semiconductor, Inc... The MC68340 system integration module (SIM40) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. It also provides the IEEE 1149.1 boundary scan capabilities. The SIM40 includes the following functions: * System Configuration and Protection * Clock Synthesizer * Chip Selects and Wait States * External Bus Interface * Bus Arbitration * Dynamic Bus Sizing * IEEE 1149.1 Test Access Port 4.1 MODULE OVERVIEW The SIM40 is essentially identical to the SIM implemented in the MC68330. The SIM40 has similar features to the SIM in the MC68331, MC68332, and MC68333. The periodic interrupt timer, double bus fault monitor, software watchdog, internal bus monitor, and spurious interrupt monitor are identical. However, many of the other features in the SIM's differ in their use and details. The system configuration and protection function controls system configuration and provides various monitors and timers, including the internal bus monitor, double bus fault monitor, spurious interrupt monitor, software watchdog timer, and the periodic interrupt timer. The clock synthesizer generates the clock signals used by the SIM40 and the other onchip modules, as well as CLKOUT used by external devices. The programmable chip select function provides four chip select signals that can enable external memory and peripheral circuits, providing all handshaking and timing signals. Each chip select signal has an associated base address register and an address mask register that contain the programmable characteristics of that chip select. Up to three wait states can be programmed by setting bits in the address mask register. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-1 Freescale Semiconductor, Inc. The external bus interface (EBI) handles the transfer of information between the internal CPU32 and memory, peripherals, or other processing elements in the external address space. See Section 3 Bus Operation for further information. Freescale Semiconductor, Inc... The MC68340 dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports. The device signals its port size and indicates completion of the bus cycle through the use of the DSACK inputs. Dynamic bus sizing allows a programmer to write code that is not buswidth specific. For a discussion on dynamic bus sizing, see Section 3 Bus Operation. The MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture . Problems associated with testing high-density circuit boards have led to the development of this standard under the sponsorship of the IEEE Test Technology Committee and Joint Test Action Group (JTAG). The MC68340 implementation supports circuit-board test strategies based on this standard. Refer to Section 9 IEEE 1149.1 Test Access Port for additional information. 4.2 MODULE OPERATION The following paragraphs describe the operation of the module base address register, system configuration and protection, clock synthesizer, chip select functions, and the external bus interface. NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 4.2.1 Module Base Address Register Operation The module base address register (MBAR) controls the location of all internal module registers (see 4.3.1 Module Base Address Register (MBAR)). The address stored in this register is the base address (starting location) for all internal registers. All internal module registers are contained in a single 4-Kbyte block (see Figure 4-1) that is relocatable along 4-Kbyte boundaries. The location of the internal registers is fixed by writing the desired base address of the 4-Kbyte block to the MBAR using the MOVES instruction to address $0003FF00 in CPU space. The source function code (SFC) and destination function code (DFC) registers contain the address space values (FC3-FC0) for the read or write operand of the MOVES instruction (see Section 5 CPU32 or M68000PM/AD, Programmer's Reference Manual ). Therefore, the SFC or DFC register must indicate CPU space (FC3-FC0 = $7), using the MOVEC instruction, before accessing MBAR. The offset from the base address is shown above each register diagram. 4-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. $FFFFFFFF $XXXXXFFF MC68340 RELOCATABLE MODULE BLOCK $FFF $7BF DMA $780 $721 $XXXXX000 SERIAL PORTS $700 . $67F TIMER MODULES $600 Freescale Semiconductor, Inc... $07F SIM 40 $000 MBAR ($0003FF00 FC=0111) RAM (TYPICAL) $00000000 NOTE: $XXXXX is the value contained in the MBAR bits BA31-BA12. Figure 4-1. SIM40 Module Register Block 4.2.2 System Configuration and Protection Operation The SIM40 allows the user to control certain features of system configuration by writing bits in the module configuration register (MCR). This register also contains read-only status bits that show the state of the SIM40. All M68000 family members are designed to provide maximum system safeguards. As an extension of the family, the MC68340 promotes the same basic concepts of safeguarded design present in all M68000 members. In addition, many functions that normally must be provided by external circuits are incorporated in this device. The following features are provided in the system configuration and protection function: SIM40 Module Configuration The SIM40 allows the user to configure the system to the particular requirements. The functions include control of FREEZE and show cycle operation, the function of the CS signals, the access privilege of the supervisor/user registers, the level of interrupt arbitration, and automatic vectoring for external interrupts. Reset Status The reset status register provides the user with information on the cause of the most recent reset. The possible causes of reset include: external, power-up, software watchdog, double bus fault, loss of clock, and RESET instruction. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Internal Bus Monitor The SIM40 provides an internal bus monitor to monitor the DSACK response time for all internal bus accesses. An option allows the monitoring of external bus accesses. For external bus accesses, four selectable response times are provided to allow for variations in response speed of memory and peripherals used in the system. A bus error signal is asserted internally if the DSACK response limit is exceeded. BERR is not asserted externally. This monitor can be disabled for external bus cycles only. Double Bus Fault Monitor The double bus fault monitor causes a reset to occur if the internal HALT is asserted by the CPU32, indicating a double bus fault. A double bus fault results when a bus or address error occurs during the exception processing sequence for a previous bus or address error, a reset, or while the CPU32 is loading information from a bus error stack frame during an RTE instruction. This function can be disabled. See Section 3 Bus Operation for more information. Spurious Interrupt Monitor If no interrupt arbitration occurs during an interrupt acknowledge (IACK) cycle, the bus error signal is asserted internally. This function cannot be disabled. Software Watchdog The software watchdog asserts reset or a level 7 interrupt (as selected by the system protection and control register) if the software fails to service the software watchdog for a designated period of time (i.e., because it is trapped in a loop or lost). There are eight selectable timeout periods. This function can be disabled. Periodic Interrupt Timer The SIM40 provides a timer to generate periodic interrupts. The periodic interrupt time period can vary from 122 s to 15.94 s (with a 32.768-kHz crystal used to generate the system clock). This function can be disabled. Figure 4-2 shows a block diagram of the system configuration and protection function. 4-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MODULE CONFIGURATION RESET STATUS DOUBLE BUS FAULT MONITOR Freescale Semiconductor, Inc... BUS MONITOR HALT RESET REQUEST BERR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG CLOCK 29 PRESCALER PERIODIC INTERRUPT TIMER SOFTWARE RESET REQUEST or IRQ7 IRQ7-IRQ1 Figure 4-2. System Configuration and Protection Function 4.2.2.1 SYSTEM CONFIGURATION. Aspects of the system configuration are controlled by the MCR and the autovector register (AVR). The configuration of port B is controlled by the combination of the FIRQ bit in the MCR and the port B pin assignment register (PPARB). Port B pins can function as dedicated I/O lines, chip selects, interrupts, or autovector input. For debug purposes, internal bus accesses can be shown on the external bus. This function is called show cycles. The SHEN1, SHEN0 bits in the MCR control show cycles. Bus arbitration can be either enabled or disabled during show cycles. Arbitration for servicing interrupts is controlled by the value programmed into the interrupt arbitration (IARB) field of the MCR. Each module that generates interrupts, including the SIM40, has an IARB field. The value of the IARB field allows arbitration during an IACK cycle among modules that simultaneously generate the same interrupt level. No two modules should share the same IARB value. The IARB must contain a value other than $0 for all modules that can generate interrupts; interrupts with IARB = 0 are discarded as extraneous. The SIM40 arbitrates for both its own interrupts and externally generated interrupts. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-5 Freescale Semiconductor, Inc. There are eight arbitration levels for access to the intermodule bus (IMB). The SIM40 is fixed at the highest level (above the programmable level 7), and the CPU32 is fixed at the lowest level (below level 0). The direct memory access (DMA) module is the only other module that can become bus master and arbitrate for the bus. It must be initialized with a level other than 0 or 7. Freescale Semiconductor, Inc... The AVR contains bits that correspond to external interrupt levels that require an autovector response. The SIM40 supports up to seven discrete external interrupt requests. If the bit corresponding to an interrupt level is set in the AVR, the SIM40 returns an autovector in response to the IACK cycle servicing that external interrupt request. Otherwise, external circuitry must either return an interrupt vector or assert the external AVEC signal. 4.2.2.2 INTERNAL BUS MONITOR. The internal bus monitor continually checks for the bus cycle termination response time by checking the DSACK, BERR, and HALT status or the AVEC status during an IACK cycle. The monitor initiates a bus error if the response time is excessive. The bus monitor feature cannot be disabled for internal accesses to an internal module. The internal bus monitor cannot check the DSACK response on the external bus unless the MC68340 is the bus master. The BME bit in the system protection control register (SYPCR) enables the internal bus monitor for internal-to-external bus cycles. If the system contains external bus masters whose bus cycles must be monitored, an external bus monitor must be implemented. In this case, the internal-to-external bus monitor option must be disabled. The bus cycle termination response time is measured in clock cycles, and the maximumallowable response time is programmable. The bus monitor response time period ranges from 8 to 64 system clocks (see Table 4-8). These options are provided to allow for different response times of peripherals that might be used in the system. 4.2.2.3 DOUBLE BUS FAULT MONITOR. A double bus fault is caused by a bus error or address error during the exception processing sequence. The double bus fault monitor responds to an assertion of HALT on the internal bus. Refer to Section 3 Bus Operation for more information. The DBF bit in the reset status register (RSR) indicates that the last reset was caused by the double bus fault monitor. The double bus fault monitor reset can be enabled by the DBFE bit in the SYPCR. 4.2.2.4 SPURIOUS INTERRUPT MONITOR. The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an IACK cycle. Normally, during an IACK cycle, one or more internal modules recognize that the CPU32 is responding to interrupt request(s) and arbitrate for the privilege of returning a vector or asserting AVEC . (The SIM40 reports and arbitrates for externally generated interrupts.) This feature cannot be disabled. 4.2.2.5 SOFTWARE WATCHDOG. The SIM40 provides a software watchdog option to prevent system lock-up in case the software becomes trapped in loops with no controlled exit. Once enabled by the SWE bit in the SYPCR, the software watchdog requires a special service sequence to be executed on a periodic basis. If this periodic servicing action does not occur, the software watchdog times out and issues a reset or a level 7 4-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. interrupt (as programmed by the SWRI bit in the SYPCR). The address of the interrupt service routine for the software watchdog interrupt is stored in the software interrupt vector register (SWIV). Figure 4-3 shows a block diagram of the software watchdog as well as the clock control circuits for the periodic interrupt timer. The watchdog clock rate is determined by the SWP bit in the periodic interrupt timer register (PITR) and the SWT bits in the SYPCR. See Table 4-7 for a list of watchdog timeout periods. Freescale Semiconductor, Inc... The software watchdog service sequence consists of the following steps: 1) write $55 to the software service register (SWSR) and 2) write $AA to the SWSR. Both writes must occur in the order listed prior to the watchdog timeout, but any number of instructions or accesses to the SWSR can be executed between the two writes. PITR SWP PTP FREEZE EXTAL CLOCK DISABLE PRESCALER (2 9 ) CLOCK MUX PITCLK . .4 PIT INTERRUPT MODULUS COUNTER PRECLK RESET SWCLK 15 STAGE DIVIDER CHAIN (215 ) LPSTOP 29 2 11 213 215 Figure 4-3. Software Watchdog Block Diagram 4.2.2.6 PERIODIC INTERRUPT TIMER. The periodic interrupt timer consists of an 8-bit modulus counter that is loaded with the value contained in the PITR (see Figure 4-3). The modulus counter is clocked by a signal derived from the EXTAL input pin unless an external frequency source is used. When an external frequency source is used (MODCK low during reset), the default state of the prescaler control bits (SWP and PTP) in the PITR is changed to enable both prescalers. Either clock source (EXTAL or EXTAL / 512) is divided by 4 before driving the modulus counter (PITCLK). When the modulus counter value reaches zero, an interrupt is generated. The level of the generated interrupt is programmed into the PIRQL bits in the periodic interrupt control register (PICR). During the IACK cycle, the SIM40 places the periodic interrupt vector, programmed into the PIV bits in the PICR, onto the internal bus. The value of bits 7-0 in the PITR is then loaded again into the modulus counter, and the counting process starts over. If a new value is written to the PITR, this value is loaded into the modulus counter when the current count is completed. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-7 Freescale Semiconductor, Inc. 4.2.2.6.1 Periodic Timer Period Calculation. The period of the periodic timer can be calculated using the following equation: periodic interrupt timer period = PITR count value EXTAL frequency/prescaler value 22 Freescale Semiconductor, Inc... Solving the equation using a crystal frequency of 32.768-kHz with the prescaler disabled gives: periodic interrupt timer period = periodic interrupt timer period = PITR count value 32768/1 22 PITR count value 8192 This gives a range from 122 s, with a PITR value of $01 (00000001 binary), to 31.128 ms, with a PITR value of $FF (11111111 binary). Solving the equation with the prescaler enabled (PTP=1 in the PITR) gives the following values: periodic interrupt timer period = periodic interrupt timer period = PITR count value 32768/512 22 PITR count value 16 This gives a range from 62.5 ms, with a PITR value of $01, to 15.94 s, with a PITR value of $FF. For fast calculation of periodic timer period using a 32.768-kHz crystal, the following equations can be used: With prescaler disabled: programmable interrupt timer period = PITR (122 s) = PITR (62.5 ms) With prescaler enabled: programmable interrupt timer period 4-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock. The periodic interrupt timer can be used as a real-time clock interrupt by setting it up to generate an interrupt with a one-second period. Rearranging the periodic timer period equation to solve for the desired count value: PITR count value = (PIT period) (EXTAL frequency) (Prescaler value) (2 2) PITR count value = (1) (32768) (512) (2 2) PITR count value = 16 (decimal) Therefore, when using a 32.768-kHz crystal, the PITR should be loaded with a value of $10 with the prescaler enabled to generate interrupts at a one-second rate. 4.2.2.7 SIMULTANEOUS INTERRUPTS BY SOURCES IN THE SIM40. If multiple interrupt sources at the same interrupt level are simultaneously asserted in the SIM40, it will prioritize and service the interrupts in the following order: 1) software watchdog, 2) periodic interrupt timer, and 3) external interrupts. 4.2.3 Clock Synthesizer Operation The clock synthesizer can operate with either an external crystal or an external oscillator for reference, using the internal phase-locked loop (PLL) and voltage-controlled oscillator (VCO), or an external clock can directly drive the clock signal at the operating frequency. The four modes of clock operation are listed in Table 4-1. Table 4-1. Clock Operating Modes Mode Description MODCK Reset Value VCCSYN Operating Value Crystal Mode External crystal or oscillator used with the on-chip PLL and VCO to generate a system clock and CLKOUT of programmable rates. 5V 5V External Clock Mode without PLL The desired operating frequency is driven into EXTAL resulting in a system clock and CLKOUT of the same frequency, not tightly coupled. 0V 0V External Clock Mode with PLL The desired operating frequency is driven into EXTAL, resulting in a system clock and CLKOUT of the same frequency, with a tight skew between input and output signals. 0V 5V Limp Mode Upon input signal loss for either clock mode using the PLL, operation continues at approximately one-half operating speed (affected by the value of the X-bit in the SYNCR). X 5V In crystal mode (see Figure 4-4), the clock synthesizer can operate from the on-chip PLL and VCO, using a parallel resonant crystal connected between the EXTAL and XTAL pins, or an external oscillator connected to EXTAL as a reference frequency source. The oscillator circuit is shown in Figure 4-5. A 32.768-kHz watch crystal provides an inexpensive reference, but the reference crystal or external oscillator frequency can be any frequency in the range specified in Section 11 Electrical Characteristics. When MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-9 Freescale Semiconductor, Inc. using crystal mode, the system clock frequency is programmable (using the W, X, and Y bits in the SYNCR) over the range specified in Section 11 Electrical Characteristics (see Table 4-2.). VDDSYN XFC 1 330 K 20 pF 20 pF 0.1 F 20 M EXTAL XTAL Freescale Semiconductor, Inc... CRYSTAL OSCILLATOR 0.1 F V DDSYN XFC PIN LOW-PASS FILTER PHASE COMPARATOR 0.01 F MUX 1 VCO CLKOUT /2 /64 MUX 1 MODULUS DIVIDER 0 SEL 0 /4 /8 0 X SEL 6 0 $3F FEEDBACK DIVIDER Y W NOTE 1: Must be low-leakage capacitor. Figure 4-4. Clock Block Diagram for Crystal Operation 60 k XTAL EXTAL . 60 k Figure 4-5. MC68340 Crystal Oscillator A separate power pin (VCCSYN ) is used to allow the clock circuits to run with the rest of the device powered down and to provide increased noise immunity for the clock circuits. The source for VCCSYN should be a quiet power supply with adequate external bypass capacitors placed as close as possible to the VCCSYN pin to ensure a stable operating frequency. Figure 4-4 shows typical values for the bypass and PLL external capacitors. The crystal manufacturer's documentation should be consulted for specific recommendations for external components. 4-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. To use an external clock source (see Figure 4-6), the operating clock frequency can be driven directly into the EXTAL pin (the XTAL pin must be left floating for this case). This approach results in a system clock and CLKOUT that are the same as the input signal frequency, but not tightly coupled to it. To enable this mode, MODCK must be held low during reset, and VCCSYN held at 0 V while the chip is in operation. VCCSYN XFC 1 0.1 F EXTERNAL CLOCK Freescale Semiconductor, Inc... EXTAL XTAL CRYSTAL OSCILLATOR XFC PIN PHASE COMPARATOR VCCSYN LOW-PASS FILTER .01 F VCO FEEDBACK DIVIDER 2 CLKOUT CLOCK CONTROL SYSTEM CLOCK NOTES: 1. Must be low-leakage capacitor. 2. External mode uses this path only. Figure 4-6. Clock Block Diagram for External Oscillator Operation Alternatively, an external clock signal can be directly driven into EXTAL (with XTAL left floating) using the on-chip PLL. This configuration results in an internal clock and CLKOUT signal of the same frequency as the input signal, with a tight skew between the external clock and the internal clock and CLKOUT signals. To enable this mode, MODCK must be held low during reset, and V CCSYN should be connected to a quiet 5-V source. If an input signal loss for either of the clock modes utilizing the PLL occurs, chip operation can continue in limp mode with the VCO running at approximately one-half the operating speed (affected by the value of the X-bit in the SYNCR), using an internal voltage reference. The SLIMP bit in the SYNCR indicates that a loss of input signal reference has been detected. The RSTEN bit in the SYNCR controls whether an input signal loss causes a system reset or causes the device to operate in limp mode. The SLOCK bit in the SYNCR indicates when the VCO has locked onto the desired frequency or if an external clock is being used. 4.2.3.1 PHASE COMPARATOR AND FILTER. The phase comparator takes the output of the frequency divider and compares it to an external input signal reference. The result of MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-11 Freescale Semiconductor, Inc. this compare is low-pass filtered and used to control the VCO. The comparator also detects when the external crystal or oscillator stops running to initiate the limp mode for the system clock. Freescale Semiconductor, Inc... The PLL requires an external low-leakage filter capacitor, typically in the range from 0.01 to 0.1 F, connected between the XFC and VCCSYN pins. The XFC capacitor should provide 50-M insulation but should not be electrolytic. Smaller values of the external filter capacitor provide a faster response time for the PLL, and larger values provide greater frequency stability. For external clock mode without PLL, the XFC pin can be left open. 4.2.3.2 FREQUENCY DIVIDER. The frequency divider circuits divide the VCO frequency down to the reference frequency for the phase comparator. The frequency divider consists of 1) a 2-bit prescaler controlled by the W-bit in the SYNCR and 2) a 6-bit modulo downcounter controlled by the Y-bits in the SYNCR. Several factors are important to the design of the system clock. The resulting system clock frequency must be within the limits specified for the device. The frequency of the system clock is given by the following equation: FSYSTEM = FCRYSTAL [2(2+2W+X) ] x (Y+1) The maximum VCO frequency limit must also be observed. The VCO frequency is given by the following equation: FVCO = FSYSTEM [2(2-X)] Since clearing the X-bit causes the VCO to run at twice the system frequency, the VCO upper frequency limit must be considered when programming the SYNCR. Both the system clock and VCO frequency limits are given in Section 11 Electrical Characteristics. Table 4-2 lists some frequencies available from various combinations of SYNCR bits with a reference frequency of 32.768-KHz. 4-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 4-2. System Frequencies from 32.768-kHz Reference Y W = 0; X = 0 W = 0; X = 1 W = 1; X = 0 W = 1; X = 1 000000 131 262 524 1049 000101 786 1573 3146 6291 001010 1442 2884 5767 11534 001111 2097 4194 8389 16777 010100 2753 5505 11010 22020 011001 3408 6816 13631 - 011111 4194 8389 16777 - 100011 4719 9437 18874 - 101000 5374 10748 21496 - 101101 6029 12059 24117 - 110010 6685 13369 - - 110111 7340 14680 - - 111100 7995 15991 - - 111111 8389 16777 - - NOTE: System frequencies are in kHz. 4.2.3.3 CLOCK CONTROL. The clock control circuits determine the source used for both internal and external clocks during special circumstances, such as low-power stop (LPSTOP) execution. Table 4-3 summarizes the clock activity during LPSTOP in crystal mode operation. Any clock in the off state is held low. The STEXT and STSIM bits in the SYNCR control clock activity during LPSTOP. Refer to 4.2.6 Low-Power Stop for additional information. Table 4-3. Clock Control Signals Control Bits Clock Outputs STSIM STEXT SIMCLK CLKOUT 0 0 EXTAL Off 0 1 EXTAL EXTAL 1 0 VCO Off 1 1 VCO VCO NOTE: SIMCLK runs the periodic interrupt RESET and IRQ pin synchronizers in LPSTOP mode. 4.2.4 Chip Select Operation Typical microprocessor systems require external hardware to provide select signals to external memory and peripherals. The MC68340 integrates these functions on chip to provide the cost, speed, and reliability benefits of a higher level of integration. The chip select function contains register pairs for each external chip select signal. The pair consists of a base address register and an address mask register that define the characteristics of a single chip select. The register pair provides flexibility for a wide variety of chip select functions. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-13 Freescale Semiconductor, Inc. 4.2.4.1 PROGRAMMABLE FEATURES. The chip select function supports the following programmable features: Freescale Semiconductor, Inc... Four Programmable Chip Select Circuits All four chip select circuits are independently programmable from the same list of selectable features. Each chip select circuit has an individual base address register and address mask register that contain the programmed characteristics of that chip select. The base address register selects the starting address for the address block in 256-byte increments. The address mask register specifies the size of the address block range. The base address register V-bit indicates that the register information for that chip select is valid. A global chip select ( CS0) allows address decode for a boot ROM before system initialization occurs. Variable Block Sizes The block size, starting from the specified base address, can vary in size from 256 bytes up to 4 Gbytes in 2n increments. The specified base address must be on a multiple of the the block size. The block size is specified in the address mask register. Both 8- and 16-Bit Ports Supported The 8-bit ports are accessible on both odd and even addresses when connected to data bus bits 15-8; the 16-bit ports can be accessed as odd bytes, even bytes, or even words. The port size is specified by the PS bits in the address mask register. Write Protect Capability The WP bit in each base address register can restrict write access to its range of addresses. Fast Termination Option Programming the FTE bit in the base address register for the fast termination option causes the chip select to terminate the cycle by asserting the internal DSACK early, providing a two-cycle external access. Internal DSACK Generation for External Accesses with Programmable Wait States DSACK can be generated internally with up to three wait states for a particular device using the DD bits in the address mask register. Full 32-Bit Address Decode with Address Space Checking The FC bits in the base address register and FCM bits in the address mask register are used to select address spaces for which the chip selects will be asserted. 4.2.4.2 GLOBAL CHIP SELECT OPERATION. Global chip select operation allows address decode for a boot ROM before system initialization occurs. CS0 is the global chip select output, and its operation differs from the other external chip select outputs following reset. When the CPU32 begins fetching after reset, CS0 is asserted for every address until the V-bit is set in the CS0 base address register. 4-14 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. NOTE Freescale Semiconductor, Inc... If an access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not. Global chip select provides a 16-bit port with three wait states, which allows a boot ROM to be located in any address space and still provide the stack pointer and program counter values at $00000000 and $00000004, respectively. Global chip select does not provide write protection and responds to all function codes. While CS0 is a global chip select, no other chip select (CS1, CS2, CS3 ) can be used. CS0 operates in this manner until the V-bit is set in the CS0 base address register, which will then allow the use of CS3-CS1. Provided the desired address range is first loaded into the CS0 base address register, CS0 can be programmed to continue decode for a range of addresses after the V-bit is set, After the V-bit is set for CS0, global chip select can only be restarted with a system reset. A system can use an 8-bit boot ROM if an external 8-bit DSACK that responds in two or less wait states is generated. The 8-bit DSACK must respond in two or less wait states so that the global chip select, which responds with three wait states, will not be used. See Section 10 Applications for a detailed discussion. 4.2.5 External Bus Interface Operation This section describes port A and port B functions. Refer to Section 3 Bus Operation for more information about the EBI. 4.2.5.1 PORT A. Port A pins can be independently programmed to function as either addresses A31-A24, discrete I/O pins, or IACKx pins. The port A pin assignment registers (PPARA1 and PPARA2) control the function of the port A pins as listed in Table 4-4. Upon reset, port A is configured as input pins. If the system uses these signals as addresses, pulldowns should be put on these signals to avoid indeterminate values until the port A registers can be programmed. Table 4-4. Port A Pin Assignment Register Pin Function Signal MOTOROLA PPARA1 = 0 PPARA1 = 1 PPARA1 = 0 PPARA2 = 0 PPARA2 = X PPARA2 = 1 A31 A31 PORT A7 IACK7 A30 A30 PORT A6 IACK6 A29 A29 PORT A5 IACK5 A28 A28 PORT A4 IACK4 A27 A27 PORT A3 IACK3 A26 A26 PORT A2 IACK2 A25 A25 PORT A1 IACK1 A24 A24 PORT A0 -- MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-15 Freescale Semiconductor, Inc. 4.2.5.2 PORT B. Port B pins can be independently programmed to function as chip selects, IRQ and MODCK pins, or discrete I/O pins. These pins are multiplexed as shown in Figure 4-7. Selection of a pin function is accomplished by a combination of the port B pin assignment register (PPARB) and the FIRQ bit of the MCR. See Table 4-5 for port B combinations. By changing the value of the FIRQ bit and the corresponding bits in the PPARB for a particular signal, the port B pins can be configured for different pin functions. Upon reset, port B is configured as MODCK, IRQ7, IRQ6, IRQ5, IRQ3, and CS3-CS0. Freescale Semiconductor, Inc... INTERRUPT PORT LOGIC MODCK/PORT B0 IRQ7/PORT B7 IRQ6/PORT B6 IRQ5/PORT B5 IRQ3/PORT B3 IRQ4/PORT B4 IRQ2/PORT B2 IRQ1/PORT B1 CS3/IRQ4/PORT B4 CS2/IRQ2/PORT B2 AVEC FULL IRQ MUX CHIPSELECT MODULE CS1/IRQ1/PORT B1 CS0/AVEC CS3 CS2 CS1 CS0 FIRQ Figure 4-7. Full Interrupt Request Multiplexer Table 4-5. Port B Pin Assignment Register Pin Function Signal FIRQ = 0 FIRQ = 0 FIRQ = 1 FIRQ = 1 PPARB = 0 PPARB = 1 PPARB = 0 PPARB = 1 IRQ7 PORTB7 IRQ7 PORTB7 IRQ7 IRQ6 PORTB6 IRQ6 PORTB6 IRQ6 IRQ5 PORTB5 IRQ5 PORTB5 IRQ5 IRQ3 PORTB3 IRQ3 PORTB3 IRQ3 CS3 CS3 CS3 PORTB4 IRQ4 CS2 CS2 CS2 PORTB2 IRQ2 CS1 CS1 CS1 PORTB1 IRQ1 CS0 CS0 CS0 AVEC AVEC MODCK PORTB0 MODCK PORTB0 MODCK NOTE: MODCK has no function after reset. 4-16 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The number of wait states programmed into the internal wait state generation logic by a chip select can be used even though the pin is not used as a C S signal. The programmed number of wait states in the CS signal applies to the port B pins configured as IRQ or I/O pins. This is done by programming the chip select with the number of wait states to be added, as though it were to be used. The DD1/DD0 and PS1/PS0 bits in the chip select address mask register must be set to add the desired number of wait states (the V-bit in the module base address register should be set). Freescale Semiconductor, Inc... 4.2.6 Low-Power Stop Executing the LPSTOP instruction provides reduced power consumption when the MC68340 is idle; only the SIM40 remains active. Operation of the SIM40 clock and CLKOUT during LPSTOP is controlled by the STSIM and STEXT bits in the SYNCR (see Table 4-3). LPSTOP disables the clock to the software watchdog in the low state. The software watchdog remains stopped until the LPSTOP mode ends; it begins to run again on the next rising clock edge. NOTE When the CPU32 executes the STOP instruction (as opposed to LPSTOP), the software watchdog continues to run. If the software watchdog is enabled, it issues a reset or interrupt when timeout occurs. The periodic interrupt timer does not respond to an LPSTOP instruction; thus, it can be used to exit LPSTOP as long as the interrupt request level is higher than the CPU32 interrupt mask level. To stop the periodic interrupt timer while in LPSTOP, the PITR must be loaded with a zero value before LPSTOP is executed. The bus monitor, double bus fault monitor, and spurious interrupt monitor are all inactive during LPSTOP. The STP bit in the MCR of each on-chip module (DMA, timers, and serial modules) should be set prior to executing the LPSTOP instruction. Setting the STP bit stops all clocks within each of the modules, except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR of each module. The system clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or until reset. For more information, see the description of the MCR STP bit for each module. If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT (see 3.4.2 LPSTOP Broadcast Cycle ). 4.2.7 Freeze FREEZE is asserted by the CPU32 if a breakpoint is encountered with background mode enabled. Refer to Section 5 CPU32 for more information on the background mode. When FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor continue to operate normally. However, the software watchdog, the periodic interrupt timer and the internal bus monitor will be affected. When FREEZE is asserted, setting the FRZ1 bit in MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-17 Freescale Semiconductor, Inc. the MCR disables the software watchdog and periodic interrupt timer, and setting the FRZ0 bit in the MCR disables the bus monitor. 4.3 PROGRAMMING MODEL Freescale Semiconductor, Inc... Figure 4-8 is a programming model (register map) of all registers in the SIM40. For more information about a particular register, refer to the description of the module or function indicated in the right column. The ADDR (address) column indicates the offset of the register from the address stored in the module base address register. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U). For the registers discussed in the following pages, the number in the upper right-hand corner indicates the offset of the register from the address stored in the module base address register. The numbers on the top line of the register represent the bit position in the register. The second line contains the mnemonic for the bit. The numbers below the register represent the bit values after a hardware reset. The access privilege is indicated in the lower right-hand corner. NOTE: A CPU32 RESET instruction will not affect any of the SIM40 registers. 4-18 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. ADDR FC 000 S 15 8 7 0 MODULE CONFIGURATION REGISTER (MCR) SYSTEM PROTECTION 004 S 006 S CLOCK SYNTHESIZER CONTROL REGISTER (SYNCR) AUTOVECTOR REGISTER (AVR) RESET STATUS REGISTER (RSR) CLOCK SYSTEM Freescale Semiconductor, Inc... PROTECTION 010 S/U 012 S/U 014 S 016 S 018 RESERVED PORT A DATA (PORTA) EBI RESERVED PORT A DATA DIRECTION (DDRA) EBI RESERVED PORT A PIN ASSIGNMENT 1 (PPRA1) EBI RESERVED PORT A PIN ASSIGNMENT 2 (PPRA2) EBI S/U RESERVED PORT B DATA (PORTB) EBI 01A S/U RESERVED PORT B DATA (PORTB1) EBI 01C S/U RESERVED PORT B DATA DIRECTION (DDRB) EBI 01E S RESERVED PORT B PIN ASSIGNMENT (PPARB) EBI 020 S SW INTERRUPT VECTOR (SWIV) SYSTEM PROTECTION CONTROL (SYPCR) PROTECTION SYSTEM 022 S PERIODIC INTERRUPT CONTROL REGISTER (PICR) SYSTEM PROTECTION 024 S PERIODIC INTERRUPT TIMING REGISTER (PITR) SYSTEM PROTECTION 026 S RESERVED SOFTWARE SERVICE (SWSR) SYSTEM PROTECTION 040 S ADDRESS MASK 1 CS0 CHIP SELECT 042 S ADDRESS MASK 2 CS0 CHIP SELECT 044 S BASE ADDRESS 1 CS0 CHIP SELECT 046 S BASE ADDRESS 2 CS0 CHIP SELECT 048 S ADDRESS MASK 1 CS1 CHIP SELECT 04A S ADDRESS MASK 2 CS1 CHIP SELECT 04C S BASE ADDRESS 1 CS1 CHIP SELECT 04E S BASE ADDRESS 2 CS1 CHIP SELECT 050 S ADDRESS MASK 1 CS2 CHIP SELECT 052 S ADDRESS MASK 2 CS2 CHIP SELECT 054 S BASE ADDRESS 1 CS2 CHIP SELECT 056 S BASE ADDRESS 2 CS2 CHIP SELECT 058 S ADDRESS MASK 1 CS3 CHIP SELECT 05A S ADDRESS MASK 2 CS3 CHIP SELECT 05C S BASE ADDRESS 1 CS3 CHIP SELECT 05E S BASE ADDRESS 2 CS3 CHIP SELECT Figure 4-8. SIM40 Programming Model MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-19 Freescale Semiconductor, Inc. 4.3.1 Module Base Address Register (MBAR) MBAR 1 $0003FF00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 IBA18 BA17 BA16 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU Space Only Freescale Semiconductor, Inc... MBAR 2 $0003FF02 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA15 BA14 BA13 BA12 0 0 AS8 AS7 AS6 AS5 AS4 AS3 AS2 AS1 AS0 V RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU Space Only BA31-BA12--Base Address Bits 31-12 The base address field is the upper 20 bits of the MBAR that provides for block starting locations in increments of 4-Kbytes. Bits 11, 10--Reserved AS8-AS0--Address Space Bits 8-0 The address space field allows particular address spaces to be masked, placing the 4K module block into a particular address space(s). If an address space is masked, an access to the register block location in that address space becomes an external access. The module block is not accessed. The address space bits are as follows: AS8--mask DMA Space address space (FC3-FC0 = 1xxx) AS7--mask CPU Space address space (FC3-FC0 = 0111) AS6--mask Supervisor Program address space (FC3-FC0 = 0110) AS5--mask Supervisor Data address space (FC3-FC0 = 0101) AS4--mask Reserved [Motorola] address space (FC3-FC0 = 0100) AS3--mask Reserved [User] address space (FC3-FC0 = 0011) AS2--mask User Program address space (FC3-FC0 = 0010) AS1--mask User Data address space (FC3-FC0 = 0001) AS0--mask Reserved [Motorola] address space (FC3-FC0 = 0000) For each address space bit: 1 = Mask this address space from the internal module selection. The bus cycle goes external. 0 = Decode for the internal module block. V--Valid Bit This bit indicates when the contents of the MBAR are valid. The base address value is not used; therefore, all internal module registers are not accessible until the V-bit is set. 1 = Contents are valid. 0 = Contents are not valid. 4-20 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. NOTE An access to this register does not affect external space since the cycle is not run externally. Example code for accessing the MBAR is as follows: Register D0 will contain the value of MBAR. MBAR can be read using the following code: Freescale Semiconductor, Inc... MOVE.L MOVEC.L LEA.L MOVES.L #7,D0 D0,SFC $0003FF00,A0 (A0),D0 load D0 with the CPU space function code load SFC to indicate CPU space load A0 with the address of MBAR load D0 with the contents of MBAR Address $0003FF00 in CPU space (MBAR) will be loaded with the value $FFFFF001. This value will set the base address of the internal registers to $FFFFF. MBAR can be written to using the following code: MOVE.L MOVEC.L LEA.L MOVE.L MOVES.L #7,D0 D0,DFC $0003FF00,A0 #$FFFFF001,D0 D0,(A0) load D0 with the CPU space function code load DFC to indicate CPU space load A0 with the address of MBAR load D0 with the value to be written into MBAR write the value contained in D0 into MBAR 4.3.2 System Configuration and Protection Registers The following paragraphs provide descriptions of the system configuration and protection registers. 4.3.2.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the SIM40 configuration, can be read or written at any time. MCR $000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FRZ1 FRZ0 FIRQ 0 0 SHEN1 SHEN0 SUPV 0 0 0 IARB3 IARB2 IARB1 IARB0 RESET: 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 Supervisor Only Bits 15, 11, 10, 6-4--Reserved FRZ1--Freeze Software Enable 1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts from occurring during software debug. 0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run. See 4.2.7 Freeze for more information. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-21 Freescale Semiconductor, Inc. FRZ0--Freeze Bus Monitor Enable 1 = When FREEZE is asserted, the bus monitor is disabled. 0 = When FREEZE is asserted, the bus monitor continues to operate as programmed. Freescale Semiconductor, Inc... FIRQ--Full Interrupt Request Mode 1 = Configures port B for seven interrupt request lines, autovector, and no external chip selects. 0 = Configures port B for four interrupt request lines and four external chip selects. See Table 4-5 for pin function selection. SHEN1, SHEN0--Show Cycle Enable These two control bits determine what the EBI does with the external bus during internal transfer operations (see Table 4-6). A show cycle allows internal transfers to be externally monitored. The address, data, and control signals (except for AS) are driven externally. DS is used to signal address strobe timing for show cycles. Data is valid on the next falling clock edge after DS is negated. However, data is not driven externally, and AS and DS are not asserted externally for internal accesses unless show cycles are enabled. If external bus arbitration is disabled, the EBI will not recognize an external bus request until arbitration is enabled again. To prevent bus conflicts, external peripherals must not attempt to initiate cycles during show cycles with arbitration disabled. Table 4-6. SHENx Control Bits SHEN1 SHEN0 ACTION 0 0 Show cycles disabled, external arbitration enabled 0 1 Show cycles enabled, external arbitration disabled 1 X Show cycles enabled, external arbitration enabled SUPV--Supervisor/User Data Space The SUPV bit defines the SIM40 registers as either supervisor data space or user (unrestricted) data space. 1 = The SIM40 registers defined as supervisor/user are restricted to supervisor data access (FC3-FC0 = $5). An attempted user-space write is ignored and returns BERR. 0 = The SIM40 registers defined as supervisor/user data are unrestricted (FC2 is a don't care). IARB3-IARB0--Interrupt Arbitration Bits 3-0 These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. The reset value of IARB is $F, allowing the SIM40 to arbitrate during an IACK cycle immediately after reset. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). A 4-22 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. value of $0 prevents arbitration and causes all SIM40 interrupts, including external interrupts, to be discarded as extraneous. 4.3.2.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to external interrupt levels that require an autovector response. Setting a bit allows the SIM40 to assert an internal AVEC during the IACK cycle in response to the specified interrupt request level. This register can be read and written at any time. Freescale Semiconductor, Inc... AVR $006 7 6 5 4 3 2 1 0 AV7 AV6 AV5 AV4 AV3 AV2 AV1 0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only NOTE: The IARB field in the MCR must contain a value other than $0 for the SIM40 to autovector for external interrupts. 4.3.2.3 RESET STATUS REGISTER (RSR). The RSR contains a bit for each reset source to the SIM40. A set bit indicates the last type of reset that occurred, and only one bit can be set in the register. The RSR is updated by the reset control logic when the SIM40 comes out of reset. This register can be read at any time; a write has no effect. For more information, see Section 3 Bus Operation. RSR $007 7 6 5 4 3 2 1 0 EXT POW SW DBF 0 LOC SYS 0 Supervisor Only EXT--External Reset 1 = The last reset was caused by an external signal driving RESET. POW--Power-Up Reset 1 = The last reset was caused by the power-up reset circuit. SW--Software Watchdog Reset 1 = The last reset was caused by the software watchdog circuit. DBF--Double Bus Fault Monitor Reset 1 = The last reset was caused by the double bus fault monitor. Bits 3, 0--Reserved MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-23 Freescale Semiconductor, Inc. LOC--Loss of Clock Reset 1 = The last reset was caused by a loss of frequency reference to the clock synthesizer. This reset can only occur if the RSTEN bit in the SYNCR is set and the VCO is enabled. Freescale Semiconductor, Inc... SYS--System Reset 1 = The last reset was caused by the CPU32 executing a RESET instruction. The system reset does not load a reset vector or affect any internal CPU32 registers, SIM40 configuration registers, or the MCR in each internal peripheral module (DMA, timers, and serial modules). It will, however, reset external devices and all other registers in the peripheral modules. 4.3.2.4 SOFTWARE INTERRUPT VECTOR REGISTER (SWIV). The SWIV contains the 8-bit vector that is returned by the SIM40 during an IACK cycle in response to an interrupt generated by the software watchdog. This register can be read or written at any time. This register is set to the uninitialized vector, $0F, at reset. SWIV $020 7 6 5 4 3 2 1 0 SWIV7 SWIV6 SWIV5 SWIV4 SWIV3 SWIV2 SWIV1 SWIV0 RESET: 0 0 0 0 1 1 1 1 Supervisor Only 4.3.2.5 SYSTEM PROTECTION CONTROL REGISTER (SYPCR). The SYPCR controls the system monitors, the prescaler for the software watchdog, and the bus monitor timing. This register can be read at any time, but can be written only once after reset. SYPCR $021 7 6 5 4 3 2 1 0 SWE SWRI SWT1 SWT0 DBFE BME BMT1 BMT0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only SWE--Software Watchdog Enable 1 = Software watchdog is enabled. 0 = Software watchdog is disabled. See 4.2.2.5 Software Watchdog for more information. SWRI--Software Watchdog Reset/Interrupt Select 1 = Software watchdog causes a system reset. 0 = Software watchdog causes a level 7 interrupt to the CPU32. 4-24 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SWT1, SWT0--Software Watchdog Timing These bits, along with the SWP bit in the PITR, control the divide ratio used to establish the timeout period for the software watchdog. The software watchdog timeout period is given by the following formula: divide count EXTAL frequency The software watchdog timeout period, listed in Table 4-7, gives the formula to derive the software watchdog timeout for any clock frequency. The timeout periods are listed for a 32.768-kHz crystal used with the VCO and for a 16.777-MHz external oscillator. Freescale Semiconductor, Inc... Table 4-7. Deriving Software Watchdog Timeout SWP SWT1 SWT0 Software Timeout Period 32.768-kHz Crystal Period 16.777-MHz External Clock Period 0 0 0 29/EXTAL Input Frequency 15.6 ms 30 s 62.5 ms 122 s 0 0 1 211 /EXTAL Input Frequency 0 1 0 213 /EXTAL Input Frequency 250 ms 488 s 0 1 1 215 /EXTAL Input Frequency 1s 1.95 ms 0 218 /EXTAL Input Frequency 8s 15.6 ms 32 s 62.5 ms 1 0 1 0 1 220 /EXTAL Input Frequency 1 1 0 222 /EXTAL Input Frequency 128 s 250 ms 1 1 1 224 /EXTAL Input Frequency 512 s 1s NOTE: When the SWP and SWT bits are modified to select a software timeout other than the default, the software service sequence ($55 followed by $AA written to the software service register) must be performed before the new timeout period takes effect. Refer to 4.2.2.5 Software Watchdog for more information. DBFE--Double Bus Fault Monitor Enable 1 = Enable double bus fault monitor function. 0 = Disable double bus fault monitor function. For more information, see 4.2.2.3 Double Bus Fault Monitor and Section 5 CPU32. BME--Bus Monitor External Enable 1 = Enable bus monitor function for an internal-to-external bus cycle. 0 = Disable bus monitor function for an internal-to-external bus cycle. For more information see 4.2.2.2 Internal Bus Monitor. BMT1, BMT0--Bus Monitor Timing These bits select the timeout period for the bus monitor (see Table 4-8). Upon reset, the bus monitor is set to 64 system clocks. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-25 Freescale Semiconductor, Inc. Table 4-8. BMTx Encoding BMT1 BMT0 0 0 64 system clocks (CLKOUT) Bus Monitor Timeout Period 0 1 32 system clocks 1 0 16 system clocks 1 1 8 system clocks Freescale Semiconductor, Inc... 4.3.2.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the interrupt level and the vector number for the periodic interrupt request. This register can be read or written at any time. Bits 15-11 are unimplemented and always return zero; a write to these bits has no effect. PICR $022 15 14 13 12 11 0 0 0 0 0 RESET: 0 0 0 0 0 10 9 8 PIRQL2 PIRQL1 PIRQL0 0 0 0 7 6 5 4 3 2 1 0 PIV7 PIV6 PIV5 PIV4 PIV3 PIV2 PIV1 PIV0 0 0 0 0 1 1 1 1 Supervisor Only Bits 15-11--Reserved PIRQL2-PIRQL0--Periodic Interrupt Request Level These bits contain the periodic interrupt request level. Table 4-9 lists which interrupt request level is asserted during an IACK cycle when a periodic interrupt is generated. The periodic timer continues to run when the interrupt is disabled. Table 4-9. PIRQL Encoding PIRQL2 PIRQL1 PIRQL0 Interrupt Request Level 0 0 0 Periodic Interrupt Disabled 0 0 1 Interrupt Request Level 1 0 1 0 Interrupt Request Level 2 0 1 1 Interrupt Request Level 3 1 0 0 Interrupt Request Level 4 1 0 1 Interrupt Request Level 5 1 1 0 Interrupt Request Level 6 1 1 1 Interrupt Request Level 7 NOTE: Use caution with a level 7 interrupt encoding due to the SIM40's interrupt servicing order. See 4.2.2.7 Simultaneous Interrupts by Sources in the SIM40 for the servicing order. 4-26 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. PIV7-PIV0--Periodic Interrupt Vector Bits 7-0 These bits contain the value of the vector generated during an IACK cycle in response to an interrupt from the periodic timer. When the SIM40 responds to the IACK cycle, the periodic interrupt vector from the PICR is placed on the bus. This vector number is multiplied by four to form the vector offset, which is added to the vector base register to obtain the address of the vector. 4.3.2.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for prescaling the software watchdog and periodic timer as well as the count value for the periodic timer. This register can be read or written at any time. Bits 15-10 are not implemented and always return zero when read. A write does not affect these bits. Freescale Semiconductor, Inc... PITR $024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SWP PTP PITR7 PITR6 PITR5 PITR4 PITR3 PITR2 PITR1 PITR0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET: 0 MODCK MODCK Supervisor Only Bits 15-10--Reserved SWP--Software Watchdog Prescale This bit controls the software watchdog clock source as shown in 4.3.2.5 System Protection Control Register (SYPCR). 1 = Software watchdog clock prescaled by a value of 512. 0 = Software watchdog clock not prescaled. The SWP reset value is the inverse of the MODCK bit state on the rising edge of reset. PTP--Periodic Timer Prescaler Control This bit contains the prescaler control for the periodic timer. 1 = Periodic timer clock prescaled by a value of 512. 0 = Periodic timer clock not prescaled. The PTP reset value is the inverse of the MODCK bit state on the rising edge of reset. PITR7-PITR0--Periodic Interrupt Timer Register Bits 7-0 The remaining bits of the PITR contain the count value for the periodic timer. A zero value turns off the periodic timer. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-27 Freescale Semiconductor, Inc. 4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which the software watchdog servicing sequence is written. The software watchdog can be enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time, but returns all zeros when read. SWSR 7 $027 6 5 4 3 2 1 0 SWSR7 SWSR6 SWSR5 SWSR4 SWSR3 SWSR2 SWSR1 SWSR0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only Freescale Semiconductor, Inc... 4.3.3 Clock Synthesizer Control Register (SYNCR) The SYNCR can be read or written only in supervisor mode. The reset state of SYNCR produces an operating frequency of 8.39 MHz when the PLL is referenced to a 32.768kHz reference signal. The system frequency is controlled by the frequency control bits in the upper byte of the SYNCR as follows: FSYSTEM = FCRYSTAL [2(2+2W+X) ] x (Y+1) SYNCR $004 15 14 13 12 11 10 9 8 7 6 5 W X Y5 Y4 Y3 Y2 Y1 Y0 RSVD 0 0 RESET: 0 0 1 1 1 1 1 1 0 0 0 4 3 SLIMP SLOCK U U = Unaffected by reset U 2 1 0 RSTEN STSIM STEXT 0 0 0 Supervisor Only W--Frequency Control Bit This bit controls the prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO speed by a factor of 4, requiring a time delay for the VCO to relock (see equation for determining system frequency). X--Frequency Control Bit This bit controls a divide-by-two prescaler, which is not in the synthesizer feedback loop. Setting the bit doubles the system clock speed without changing the VCO speed, as specified in the equation for determining system frequency; therefore, no delay is incurred to relock the VCO. Y5-Y0--Frequency Control Bits The Y-bits, with a value from 0-63, control the modulus downcounter in the synthesizer feedback loop, causing it to divide by the value of Y+1 (see the equation for determining system frequency). Changing these bits requires a time delay for the VCO to relock. Bits 7-5--Reserved Bit 7 is reserved for factory testing. 4-28 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SLIMP--Limp Mode 1 = A loss of input signal reference has been detected, and the VCO is running at approximately one-half the maximum speed (affected by the X-bit ), determined from an internal voltage reference. 0 = External input signal frequency is at VCO reference. Freescale Semiconductor, Inc... SLOCK--Synthesizer Lock 1 = VCO has locked onto the desired frequency (or system clock is driven externally). 0 = VCO is enabled, but has not yet locked. RSTEN--Reset Enable 1 = Loss of input signal causes a system reset. 0 = Loss of input signal causes the VCO to operate at a nominal speed without external reference (limp mode), and the device continues to operate at that speed. STSIM--Stop Mode System Integration Clock 1 = When LPSTOP is executed, the SIM40 clock is driven from the VCO. 0 = When LPSTOP is executed, the SIM40 clock is driven from an external crystal or oscillator, and the VCO is turned off to conserve power. STEXT--Stop Mode External Clock 1 = When the LPSTOP instruction is executed, the external clock pin (CLKOUT) is driven from the SIM40 clock as determined by the STSIM bit. 0 = When the LPSTOP instruction is executed, the external clock (CLKOUT) is held low to conserve power. No external clock will be driven in LPSTOP mode. 4.3.4 Chip Select Registers The following paragraphs provide descriptions of the registers in the chip select function, and an example of how to program the registers. The chip select registers cannot be used until the V-bit in the MBAR is set. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-29 Freescale Semiconductor, Inc. 4.3.4.1 BASE ADDRESS REGISTERS. There are four 32-bit base address registers in the chip select function, one for each chip select signal. Base Address 1 $044, $04C, $054, $05C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 RESET: U U U U U U U U U U U U U U U U Supervisor Only Freescale Semiconductor, Inc... Base Address 2 $046, $04E, $056, $05E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BFC3 BFC2 BFC1 BFC0 WP FTE NCS V RESET: U U U U U U U U U U U U U U 0 0 U = Unaffected by reset Supervisor Only BA31-BA8--Base Address Bits 31-8 The base address field, the upper 24 bits of each base address register, selects the starting address for the chip select. The specified base address must be on a multiple of the selected block size. The corresponding bits, AM31-AM8, in the address mask register define the size of the block for the chip select. The base address field (and the base function code field) is compared to the address on the address bus to determine if a chip select should be generated. BFC3-BFC0--Base Function Code Bits 3-0 The value programmed into this field causes a chip select to be asserted for a certain address space type. There are nine function code address spaces (see Section 3 Bus Operation) specified as either user or supervisor, program or data, CPU, and DMA. These bits should be used to allow access to one type of address space. If access to more than one type of address space is desired, the FCMx bits should be used in addition to the BFCx bits. To prevent access to CPU space, set the NCS bit. WP--Write Protect This bit can restrict write accesses to the address range in a base address register. An attempt to write to the range of addresses specified in a base address register that has this bit set returns BERR. 1 = Only read accesses are allowed. 0 = Either read or write accesses are allowed. FTE--Fast-Termination Enable This bit causes the cycle to terminate early with an internal DSACK, giving a fast twoclock external access. When clear, all external cycles are at least three clocks. If fast termination is enabled, the DD bits of the corresponding address mask register are overridden (see Section 3 Bus Operation). 1 = Fast termination cycle enabled (termination determined by PS bits). 0 = Fast termination cycle disabled (termination determined by DD and PS bits). 4-30 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NCS--No CPU Space This bit specifies whether or not a chip select will assert on a CPU space access cycle (FC3-FC0 = $7 or $F). If both supervisor data and program accesses are desired, while ignoring CPU space accesses, then this bit should be set. The NCS bit is cleared at reset. 1 = Suppress the chip select on a CPU space access. 0 = Assert the chip select on a CPU space access. V--Valid Bit This bit indicates that the contents of its base address register and address mask register pair are valid. The programmed chip selects do not assert until the V-bit is set. A reset clears the V-bit in each base address register, but does not change any other bits in the base address and address mask registers ( CS0 is a special case, see 4.2.4.2 Global Chip Select Operation). 1 = Contents are valid. 0 = Contents are not valid. 4.3.4.2 ADDRESS MASK REGISTERS. There are four 32-bit address mask registers in the chip select function, one for each chip select signal. Address Mask 1 $040, $048, $050, $058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AM31 AM30 AM29 AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 AM20 AM19 AM18 AM17 AM16 RESET: U U U U U U U U U U U U U U U U Supervisor Only Address Mask 2 $042, $04A, $052, $05A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AM15 AM14 AM13 AM12 AM11 AM10 AM9 AM8 FCM3 FCM2 FCM1 FCM0 DD1 DD0 PS1 PS0 RESET: U U U U U U U U U U U U U U U U U = Unaffected by reset Supervisor Only AM31-AM8--Address Mask Bits 31-8 The address mask field, the upper 24 bits of each address mask register, defines the chip select block size. The block size is equal to 2n , where n = (number of bits set in the address mask field) + 8. Any set bit masks the corresponding base address register bit (the base address register bit becomes a don't care). By masking the address bits independently, external devices of different size address ranges can be used. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at any time. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-31 Freescale Semiconductor, Inc. FCM3-FCM0--Function Code Mask Bits 3-0 This field can be used to mask certain function code bits, allowing more than one address space type to be assigned to a chip select. Any set bit masks the corresponding function code bit. DD1, DD0--DSACK Delay Bits 1 and 0 This field determines the number of wait states added before an internal DSACK is returned for that entry. Table 4-10 lists the encoding for the DD bits. Freescale Semiconductor, Inc... NOTE: The port size field must be programmed for an internal DSACK response and the FTE bit in the base address register must be cleared for the DDx bits to have significance. If external DSACK signals are returned earlier than indicated by the DDx bits, the cycle will terminate sooner than programmed. See 4.2.5.2 PORT B for a discussion on using the internal DSACK generation without using the CS signal. Table 4-10. DDx Encoding DD1 DD0 Response 0 0 Zero Wait State 0 1 One Wait State 1 0 Two Wait States 1 1 Three Wait States PS1, PS0--Port Size Bits 1 and 0 This field determines whether a given chip select responds with DSACK and, if so, what port size is returned. Table 4-11 lists the encoding for the PSx bits. Table 4-11. PSx Encoding PS1 PS0 Mode 0 0 Reserved* 0 1 16-Bit Port 1 0 8-Bit Port 1 1 External DSACK Response *Use only for 32-bit DMA transfers. To use the external DSACK response, PS1-PS0 = 11 should be selected to suppress internal DSACK generation. The DDx bits then have no significance. 4-32 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 4.3.4.3 CHIP SELECT REGISTERS PROGRAMMING EXAMPLE. The following listing is an example of programming a chip select at starting address $00040000, for a block size of 256 Kbytes, accessing supervisor and user data spaces with a 16-bit port requiring two wait states. There will be no write protection, no fast termination, and no CPU space accesses. base address 1 = $0004 base address 2 = $0013 address mask 1 = $0003 address mask 2 = $FF49 Freescale Semiconductor, Inc... NOTE If an access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not. 4.3.5 External Bus Interface Control The following paragraphs describe the registers that control the I/O pins used with the EBI. Refer to the Section 3 Bus Operation for more information about the EBI. For a list of pin numbers used with port A and port B, see the pinout diagram in Section 12 Ordering Information and Mechanical Data. Section 2 Signal Descriptions shows a block diagram of the port control circuits. 4.3.5.1 PORT A PIN ASSIGNMENT REGISTER 1 (PPARA1). PPARA1 selects between an address and discrete I/O function for the port A pins. Any set bit defines the corresponding pin to be an I/O pin, controlled by the port A data and data direction registers. Any cleared bit defines the corresponding pin to be an address bit as defined in the following register diagram. Bits set in this register override the configuration setting of PPARA2. The $FF reset value of PPARA1 configures it as an input port. This register can be read or written at any time. PPARA1 $015 7 6 5 4 3 2 1 0 PRTA7 (A31) PRTA6 (A30) PRTA5 (A29) PRTA4 (A28) PRTA3 (A27) PRTA2 (A26) PRTA1 (A25) PRTA0 (A24) RESET: 1 1 1 1 1 1 1 1 Supervisor Only MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-33 Freescale Semiconductor, Inc. 4.3.5.2 PORT A PIN ASSIGNMENT REGISTER 2 (PPARA2). PPARA2 selects between an address and IACK function for the port A pins. Any set bit defines the corresponding pin to be an IACK output pin. Any cleared bit defines the corresponding pin to be an address bit as defined in the register diagram. Any set bits in PPARA1 override the configuration set in PPARA2. Bit 0 has no function in this register because there is no level 0 interrupt. This register can be read or written at any time. Freescale Semiconductor, Inc... PPARA2 $017 7 6 5 4 3 2 1 0 IACK7 (A31) IACK6 (A30) IACK5 (A29) IACK4 (A28) IACK3 (A27) IACK2 (A26) IACK1 (A25) 0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only The IACK signals are asserted if a bit in PPARA2 is set and the CPU32 services an external interrupt at the corresponding level. IACK signals have the same timing as address strobes. NOTE: Upon reset, port A is configured as an input port. 4.3.5.3 PORT A DATA DIRECTION REGISTER (DDRA). DDRA controls the direction of the pin drivers when the pins are configured as I/O. Any set bit configures the corresponding pin as an output. Any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O. This register can be read or written at any time. DDRA $013 7 6 5 4 3 2 1 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 RESET: 0 0 0 0 0 0 0 0 Supervisor/User 4.3.5.4 PORT A DATA REGISTER (PORTA). PORTA affects only pins configured as discrete I/O. A write to PORTA is stored in the internal data latch, and if any port A pin is configured as an output, the value stored for that bit is driven on the pin. A read of PORTA returns the value at the pin only if the pin is configured as discrete input. Otherwise, the value read is the value stored in the internal data latch. This register can be read or written at any time. PORTA $011 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 RESET: U U U U U U U U Supervisor/User 4-34 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 4.3.5.5 PORT B PIN ASSIGNMENT REGISTER (PPARB). PPARB controls the function of each port B pin. Any set bit defines the corresponding pin to be an IRQ input or CS as defined in Table 4-5. Any cleared bit defines the corresponding pin to be a discrete I/O pin (or CS if the FIRQ bit of the MCR is zero) controlled by the port B data and data direction registers. The MODCK signal has no function after reset. PPARB is configured to all ones at reset to provide for MODCK, IRQ7, IRQ6, IRQ5, IRQ3, and CS3- CS0. This register can be read or written at any time. Freescale Semiconductor, Inc... PPARB $01F 7 6 5 4 3 2 1 0 PPARB7 (IRQ7) PPARB6 (IRQ6) PPARB5 (IRQ5) PPARB4 (IRQ4) PPARB3 (IRQ3) PPARB2 (IRQ2) PPARB1 (IRQ1) PPARB0 (MODCK) RESET: 1 1 1 1 1 1 1 1 Supervisor Only 4.3.5.6 PORT B DATA DIRECTION REGISTER (DDRB). DDRB controls the direction of the pin drivers when the pins are configured as I/O. Any set bit configures the corresponding pin as an output; any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O. This register can be read or written at any time. DDRB $01D 7 6 5 4 3 2 1 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 RESET: 0 0 0 0 0 0 0 0 Supervisor/User 4.3.5.7 PORT B DATA REGISTER (PORTB, PORTB1). This is a single register that can be accessed at two different addresses. This register affects only those pins configured as discrete I/O. A write is stored in the internal data latch, and if any port B pin is configured as an output, the value stored for that bit is driven on the pin. A read of this register returns the value stored in the register only if the pin is configured as a discrete output. Otherwise, the value read is the value of the pin. This register can be read or written at any time. PORTB, PORTB1 $019, 01B 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 RESET: U U U U U U U U Supervisor/User MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-35 Freescale Semiconductor, Inc. 4.4 MC68340 INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the MC68340 after power-up. Freescale Semiconductor, Inc... 4.4.1 Startup RESET is asserted by the MC68340 during the time in which V CC is ramping up, the VCO is locking onto the frequency, and the MC68340 is going through the reset operation. After RESET is negated, four bus cycles are run, with global CS0 being asserted to fetch the 32-bit supervisor stack pointer (SSP) and the 32-bit program counter (PC) from the boot ROM. Until programmed differently, CS0 is a global, 16-bit-wide, three-wait-state chip select. CS0 can be programmed to continue decode for a range of addresses after the V-bit is set, provided the desired address range is first loaded into the CS0 base address register. After the V-bit is set for CS0 , global chip select can only be restarted with a system reset. After the SSP and the PC are fetched, the module base address register (MBAR) should be initialized, and the MBAR V-bit should be set (CPU space address $0003FF00) with the desired base address for the internal modules. 4.4.2 SIM40 Module Configuration The order of the following SIM40 register initializations is not important; however, time can be saved by initializing the SYNCR first to quickly increase to the desired processor operating frequency. The module base address register must be initialized prior to any of following steps. Clock Synthesizer Control Register (SYNCR): * Set frequency control bits (W, X, Y) to specify frequency. * Select action taken during loss of crystal (RSTEN bit): activate a system reset or operate in limp mode. * Select system clock and CLKOUT during LPSTOP (STSIM and STEXT bits). Module Configuration Register (MCR) * If using the software watchdog, periodic interrupt timer, and/or the bus monitor, select action taken when FREEZE is asserted (FRZx bits). * Select port B configuration (FIRQ bit). Note that this bit is used in combination with the bits in the PPARB to program the function of the port B pins. * Select the access privilege for the supervisor/user registers (SUPV bit). * Select the interrupt arbitration level for the SIM40 (IARBx bits). Autovector Register (AVR) * Select the desired external interrupt levels for internal autovectoring. 4-36 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. System Protection Control Register (SYPCR) (Note that this register can only be written once after reset.) * Enable the software watchdog, if desired (SWE bit). * If the watchdog is enabled, select whether a system reset or a level 7 interrupt is desired at timeout (SWRI bit). * If the watchdog is enabled, select the timeout period (SWTx bits). * Enable the double bus fault monitor, if desired (DBFE bit). * Enable the external bus monitor, if desired (BME bit). * Select timeout period for bus monitor (BMTx bits). Freescale Semiconductor, Inc... Software Watchdog Interrupt Vector Register (SWIV) * If using the software watchdog, program the vector number for a software watchdog interrupt. Periodic Interrupt Timer Register (PITR) * If using the software watchdog, select whether or not to prescale (SWP bit). * If using the periodic interrupt timer, select whether or not to prescale (PTP bit). * Program the count value for the periodic timer, or program a zero value to turn off the periodic timer (PITRx bits). Periodic Interrupt Control Register (PICR) * If using the periodic timer, program the desired interrupt level for the periodic interrupt timer (PIRQLx bits). * If using the periodic timer, program the vector number for a periodic timer interrupt. Chip Select Base Address and Address Mask Registers * Initialize and set the V-bits in the necessary chip select base address and address mask registers. Following this step, other system resources requiring the CS signals can be accessed. Care must be exercised when changing the address for CS0. The address of the instruction following the MOVE instruction to the CS0 base address register must match the value of the PC at that time. CS0 must be taken out of global chip select mode by setting the V-bit in the base address register before CS3-CS1 can be used. Port A and B Registers * Program the desired function of the port A signals (PPARA1 and PPARA2 registers). * Program the desired function of the port B signals (PPARB register). MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-37 Freescale Semiconductor, Inc. 4.4.3 SIM40 Example Configuration Code Freescale Semiconductor, Inc... The following code is an example configuration sequence for the SIM40 module. *************************************************************************** * MC68340 basic SIM40 register initialization example code: * This code is used to initialize the MC68340's internal SIM40 registers, * providing basic functions for operation. * It includes chip select programming for external devices. * This code would be programmed beginning at offset $0 into ROM which is * relocated to address $60000 by the initialization code. * The SSP_VEC and RST_VEC vectors used to initialize the system stack * pointer and initial PC, respectively, are located at offset $0 after * reset. *************************************************************************** * equates *************************************************************************** SSP_INIT EQU $10000 Stack pointer initial value - top of RAM MBAR EQU $0003FF00 Address of Module Base Address Reg. MODBASE EQU $FFFFF000 Default Module Base address value **************************************** * SIM40 register offsets from MBAR base address MCR EQU $00 SYNCR EQU $04 SYPCR EQU $21 CSAM0 EQU $40 CSBAR0 EQU $44 CSAM1 EQU $48 CSBAR1 EQU $4c CSAM2 EQU $50 CSBAR2 EQU $54 CSAM3 EQU $58 CSBAR3 EQU $5c *************************************************************************** * Reset vectors * These two vectors should be located at addresses $0 and $4 after a processor * hardware reset. *************************************************************************** ORG $60000 SSP_VEC DC.L SSP_INIT Supervisor stack pointer - initial value RST_VEC DC.L INIT340 Reset vector pointing to initialization code 4-38 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. *************************************************************************** * Initialization code *************************************************************************** * Start Chip Select Initialization: INIT340 MOVE.W #$2700,SR Init SR - interrupts masked Freescale Semiconductor, Inc... *************************************************************************** * Set up default module base address value MOVEQ.L #7,D0 MBAR is in CPU space MOVEC.L D0,DFC load DFC to indicate CPU space MOVE.L #MODBASE+1,D0 Set address/valid bit MOVES.L D0,MBAR write to MBAR *************************************************************************** * Set up system protection register: * Software watchdog disabled, double bus fault monitor disabled, bus * monitor BERR after 16 clocks. MOVE.B #6,SYPCR+MODBASE *************************************************************************** * Clock synthesizer control register: * Switch from 8.3 to 16.7 MHZ MOVE.W #$7F00,SYNCR+MODBASE X-bit doubles the default speed *************************************************************************** * Module configuration register: * When FREEZE is asserted, software watchdog and periodic interrupt timer * are disabled, bus monitor is enabled. Port B = 4 IRQs, 4 chip selects. * Show Cycles enabled, external arbitration enabled. Supervisor/user * SIM registers unrestricted, Interrupt Arbitration at priority $F MOVE.W #$420F,MCR+MODBASE *************************************************************************** * Now, set up Address masks and base addresses for the chip selects: LEA CSAM0+MODBASE,A0 Point to CS0 addr. mask location. MOVEQ #7,D Set up a loop counter. LEA CSAM0$,A1 Point to addr mask memory location. LOOP MOVE.L (A1)+,(A0)+ Init. addr mask and base addr reg DBRA D0,LOOP MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-39 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... *************************************************************************** * Data table for chip select initialization *************************************************************************** * CS0 - EPROM - 00060000-0007ffff, 3-wait states, 16-bit term., write protect CSAM0$ DC.L $0001FFFD CSBAR0$ DC.L $00060009 * CS1 - RAM - 00000000-0000ffff, fast termination CSAM1$ DC.L $0000FFF0 CSBAR1$ DC.L $00000005 * CS2 - external device - 00FFE8xx, external termination CSAM2$ DC.L $000000F3 CSBAR2$ DC.L $00FFE801 * CS3 - secondary memory - 00000000-0003ffff, 3-wait states, 16-bit term. CSAM3$ DC.L $0003FFFD CSBAR3$ DC.L $00000001 *************************************************************************** END 4-40 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 5 CPU32 The CPU32, the first-generation instruction processing module of the M68300 family, is based on the industry-standard MC68000 core processor. It has many features of the MC68010 and MC68020 as well as unique features suited for high-performance processor applications. The CPU32 provides a significant performance increase over the MC68000 CPU, yet maintains source-code and binary-code compatibility with the M68000 family. 5.1 OVERVIEW The CPU32 is designed to interface to the intermodule bus (IMB), allowing interaction with other IMB submodules. In this manner, integrated processors can be developed that contain useful peripherals on chip. This integration provides high-speed accesses among the IMB submodules, increasing system performance. Another advantage of the CPU32 is low power consumption. The CPU32 is implemented in high-speed complementary metal-oxide semiconductor (HCMOS) technology, providing low power use during normal operation. During periods of inactivity, the LPSTOP instruction can be executed, shutting down the CPU32 and other IMB modules, greatly reducing power consumption. Ease of programming is an important consideration when using an integrated processor. The CPU32 instruction format reflects a predominate register-memory interaction philosophy. All data resources are available to all operations that require them. The programming model includes eight multifunction data registers and seven general-purpose addressing registers. The data registers readily support 8-bit (byte), 16-bit (word), and 32bit (long-word) operand lengths for all operations. Address manipulation is supported by word and long-word operations. Although the program counter (PC) and stack pointers (SP) are special-purpose registers, they are also available for most data addressing activities. Ease of program checking and diagnosis is enhanced by trace and trap capabilities at the instruction level. As processor applications become more complex and programs become larger, high-level language (HLL) will become the system designer's choice in programming languages. HLL aids in the rapid development of complex algorithms with less error and is readily portable. The CPU32 instruction set will efficiently support HLL. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-1 Freescale Semiconductor, Inc. 5.1.1 Features Features of the CPU32 are as follows: * Fully Upward Object-Code Compatible with M68000 Family * Virtual Memory Implementation * Loop Mode of Instruction Execution * Fast Multiply, Divide, and Shift Instructions * Fast Bus Interface with Dynamic Bus Port Sizing * Improved Exception Handling for Embedded Control Applications Freescale Semiconductor, Inc... * Additional Addressing Modes -- Scaled Index -- Address Register Indirect with Base Displacement and Index -- Expanded PC Relative Modes -- 32-Bit Branch Displacements * Instruction Set Additions -- High-Precision Multiply and Divide -- Trap On Condition Codes -- Upper and Lower Bounds Checking * Enhanced Breakpoint Instruction * Trace on Change of Flow * Table Lookup and Interpolate Instruction * LPSTOP Instruction * Hardware BKPT Signal, Background Mode * Fully Static Implementation A block diagram of the CPU32 is shown in Figure 5-1. The major blocks depicted operate in a highly independent fashion that maximizes concurrences of operation while managing the essential synchronization of instruction execution and bus operation. The bus controller loads instructions from the data bus into the decode unit. The sequencer and control unit provide overall chip control, managing the internal buses, registers, and functions of the execution unit. 5.1.2 Virtual Memory A system that supports virtual memory has a limited amount of high-speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device. When the processor attempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The 5-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. CPU32 uses instruction restart, which requires that only a small portion of the internal machine state be saved. After correcting the page fault, the machine state is restored, and the instruction is refetched and restarted. This process is completely transparent to the application program. SEQUENCER Freescale Semiconductor, Inc... CONTROL UNIT DATA BUS ADDRESS BUS INSTRUCTION PREFETCH AND DECODE 16 BUS CONTROL EXECUTION UNIT BUS CONTROL 32 Figure 5-1. CPU32 Block Diagram 5.1.3 Loop Mode Instruction Execution The CPU32 has several features that provide efficient execution of program loops. One of these features is the DBcc looping primitive instruction. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode is used by any single-word instruction that does not change the program flow. Loop mode is implemented in conjunction with the DBcc instruction. Figure 5-2 shows the required form of an instruction loop for the processor to enter loop mode. ONE-WORD INSTRUCTION DBcc DBcc DISPLACEMENT $FFFC = 4 Figure 5-2. Loop Mode Instruction Sequence The loop mode is entered when the DBcc instruction is executed and the loop displacement is -4. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-3 Freescale Semiconductor, Inc. condition and count are checked after each execution of the data operations of the looped instruction. The CPU32 automatically exits the loop mode on interrupts or other exceptions. Freescale Semiconductor, Inc... 5.1.4 Vector Base Register The vector base register (VBR) contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors. Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing. These routines perform a series of operations appropriate for the corresponding exceptions. Because the exception vectors contain memory addresses, each consists of one long word, except for the reset vector. The reset vector consists of two long words: the address used to initialize the supervisor stack pointer (SSP) and the address used to initialize the PC. The address of an interrupt exception vector is derived from an 8-bit vector number and the VBR. The vector numbers for some exceptions are obtained from an external device; other numbers are supplied automatically by the processor. The processor multiplies the vector number by 4 to calculate the vector offset, which is added to the VBR. The sum is the memory address of the vector. All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map; once initialization is complete, there are no fixed assignments. Since the VBR provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Refer to 5.5 Exception Processing for additional details. 31 0 VECTOR BASE REGISTER (VBR) 5.1.5 Exception Handling The processing of an exception occurs in four steps, with variations for different exception causes. During the first step, a temporary internal copy of the status register (SR) is made, and the SR is set for exception processing. During the second step, the exception vector is determined. During the third step, the current processor context is saved. During the fourth step, a new context is obtained, and the processor then proceeds with instruction processing. Exception processing saves the most volatile portion of the current context by pushing it on the supervisor stack. This context is organized in a format called the exception stack frame. This information always includes the SR and PC context of the processor when the exception occurred. To support generic handlers, the processor places the vector offset in the exception stack frame. The processor also marks the frame with a frame format. The format field allows the return-from-exception (RTE) instruction to identify what information is on the stack so that it may be properly restored. 5-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.1.6 Addressing Modes Addressing in the CPU32 is register oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory; this flexibility eliminates the need for extra instructions to store register contents in memory. The seven basic addressing modes are as follows: * Register Direct * Register Indirect * Register Indirect with Index * Program Counter Indirect with Displacement Freescale Semiconductor, Inc... * Program Counter Indirect with Index * Absolute * Immediate Included in the register indirect addressing modes are the capabilities to postincrement, predecrement, and offset. The PC relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the SR, SP and/or PC. Addressing is explained fully in the M68000PM/AD, M68000 Family Programmer's Reference Manual . 5.1.7 Instruction Set The instruction set of the CPU32 is very similar to that of the MC68020 (see Table 5-1). Two new instructions have been added to facilitate embedded control applications: LPSTOP and table lookup and interpolate (TBL). The following M68020 instructions are not implemented on the CPU32: BFxxx -- Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST) CALLM, RTM -- Call Module, Return Module CAS, CAS2 -- Compare and Set (Read-Modify-Write Instructions) cpxxx -- Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc) PACK, UNPK -- Pack, Unpack BCD Instructions The CPU32 traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to define specialpurpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-5 Freescale Semiconductor, Inc. Table 5-1. Instruction Set Freescale Semiconductor, Inc... Mnemonic ABCD ADD ADDA ADDI ADDQ AND ANDI ASL ASR Bcc BCHG BCLR BGND BKPT BRA BSET BSR BTST CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB ILLEGAL JMP JSR LEA LINK LPSTOP LSL, LSR MOVE 5-6 Description Mnemonic Add Decimal with Extend Add Add Address Add Immediate Add Quick Logical AND Logical AND Immediate Arithmetic Shift Left Arithmetic Shift Right Branch Conditionally (16 Tests) Bit Test and Change Bit Test and Clear Enter Background Mode Breakpoint Branch Always Bit Test and Set Branch to Subroutine Bit Test Check Register against Bounds Check Register against Upper and Lower Bounds Clear Operand Compare Compare Address Compare Immediate Compare Memory Compare Register against Upper and Lower Bounds Test Condition, Decrement and Branch (16 Tests) Signed Divide Unsigned Divide Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend Take Illegal Instruction Trap Jump Jump to Subroutine Load Effective Address Link and Allocate Low-Power Stop Logical Shift Left and Right Move MOVEA MOVE CCR MOVE SR MOVE USP MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU NBCD NEG NEGX NOP NOT OR ORI PEA RESET ROL, ROR ROXL, ROXR RTD RTE RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TBLS, TBLSN Description Move Address Move Condition Code Register Move to/from Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Data Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Ones Complement Logical Inclusive OR Logical Inclusive OR Immediate Push Effective Address Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and Deallocate Return from Exception Return and Restore Return from Subroutine Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Data Register Halves Test and Set Operand Table Lookup and Interpolate, Signed TBLU, TBLUN Table Lookup and Interpolate, Unsigned TRAPcc Trap Conditionally (16 Tests) TRAPV Trap on Overflow TST Test UNLK Unlink MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.1.7.1 TABLE LOOKUP AND INTERPOLATE INSTRUCTIONS. To maximize throughput for real-time applications, reference data is often "particulated" and stored in memory for quick access. The storage of each data point would require an inordinate amount of memory. The table instruction requires only a sample of data points stored in the array, thus reducing memory requirements. Intermediate values are recovered with this instruction via linear interpolation. The results may be rounded by a round-to-nearest algorithm. Freescale Semiconductor, Inc... 5.1.7.2 LOW-POWER STOP INSTRUCTION. In applications where power consumption is a consideration, the CPU32 forces the device into a low-power standby mode when immediate processing is not required. The low-power stop mode is entered by executing the LPSTOP instruction. The processor will remain in this mode until a user-specified (or higher) interrupt level or reset occurs. 5.1.8 Processing States The processor is always in one of four processing states: normal, exception, halted, or background. The normal processing state is that associated with instruction execution; the bus is used to fetch instructions and operands and to store results. The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally generated explicitly by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, a bus error, or a reset. The halted processing state is an indication of catastrophic hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. The background processing state is initiated by breakpoints, execution of special instructions, or a double bus fault. Background processing allows interactive debugging of the system via a simple serial interface. Refer to 5.4 Processing States for details. 5.1.9 Privilege States The processor operates at one of two levels of privilege--supervisor or user. The supervisor level has higher privileges than the user level. Not all instructions are permitted to execute in the lower privileged user level, but all instructions are available at the supervisor level. This scheme allows the supervisor to protect system resources from uncontrolled access. The processor uses the privilege level indicated by the S-bit in the SR to select either the user or supervisor privilege level and either the user stack pointer (USP) or SSP for stack operations. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-7 Freescale Semiconductor, Inc. 5.2 ARCHITECTURE SUMMARY The CPU32 is upward source- and object-code compatible with the MC68000 and MC68010. It is downward source- and object-code compatible with the MC68020. Within the M68000 family, architectural differences are limited to the supervisory operating state. User state programs can be executed unchanged on upward-compatible devices. The major CPU32 features are as follows: * 32-Bit Internal Data Path and Arithmetic Hardware * 32-Bit Address Bus Supported by 32-Bit Calculations Freescale Semiconductor, Inc... * Rich Instruction Set * Eight 32-Bit General-Purpose Data Registers * Seven 32-Bit General-Purpose Address Registers * Separate User and Supervisor Stack Pointers * Separate User and Supervisor State Address Spaces * Separate Program and Data Address Spaces * Many Data Types * Flexible Addressing Modes * Full Interrupt Processing * Expansion Capability 5.2.1 Programming Model The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. User programs can only use the registers of the user model. The supervisor programming model, which supplements the user programming model, is used by CPU32 system programmers who wish to protect sensitive operating system functions. The supervisor model is identical to that of MC68010 and later processors. The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit PC, separate 32-bit SSP and USP, a 16-bit SR, two alternate function code registers, and a 32-bit VBR (see Figures 5-3 and 5-4). 5-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 31 16 15 8 7 0 D0 D1 D2 D3 DATA REGISTERS D4 D5 D6 D7 31 16 15 Freescale Semiconductor, Inc... A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 31 16 15 0 A7 (USP) 31 USER STACK POINTER 0 15 8 7 PC PROGRAM COUNTER CCR CONDITION CODE REGISTER 0 0 Figure 5-3. User Programming Model 31 16 15 15 0 8 7 SUPERVISOR STACK POINTER SR STATUS REGISTER PC PROGRAM COUNTER SFC ALTERNATE FUNCTION CODE REGISTERS 0 (CCR) 31 31 A7' (SSP) 0 3 2 0 DFC Figure 5-4. Supervisor Programming Model Supplement MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-9 Freescale Semiconductor, Inc. 5.2.2 Registers Registers D7-D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-bit) operations. Registers A6 to A0 and the USP and SSP are address registers that may be used as software SPs or base address registers. Register A7 (shown as A7 and A7' in Figures 5-3 and 5-4) is a register designation that applies to the USP in the user privilege level and to the SSP in the supervisor privilege level. In addition, address registers may be used for word and long-word operations. All of the 16 general-purpose registers (D7-D0, A7-A0) may be used as index registers. Freescale Semiconductor, Inc... The PC contains the address of the next instruction to be executed by the CPU32. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. The SR (see Figure 5-5) contains condition codes, an interrupt priority mask (three bits), and three control bits. Condition codes reflect the results of a previous operation. The codes are contained in the low byte (CCR) of the SR. The interrupt priority mask determines the level of priority an interrupt must have to be acknowledged. The control bits determine trace mode and privilege level. At user privilege level, only the CCR is available. At supervisor privilege level, software can access the full SR. The VBR contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. Alternate source and destination function code registers (SFC and DFC) contain 3-bit function codes. The CPU32 generates a function code each time it accesses an address. Specific codes are assigned to each type of access. The codes can be used to select eight dedicated 4-Gbyte address spaces. The MOVEC instruction can use registers SFC and DFC to specify the function code of a memory address. USER BYTE (CONDITION CODE REGISTER) SYSTEM BYTE 15 T1 14 T0 13 S 12 0 TRACE ENABLE 11 0 10 I2 9 I1 8 I0 7 0 6 0 5 0 INTERRUPT PRIORITY MASK 4 X 3 N 2 Z 1 V 0 C EXTEND NEGATIVE ZERO SUPERVISOR/USER STATE OVERFLOW CARRY Figure 5-5. Status Register 5-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.3 INSTRUCTION SET The following paragaphs describe the set of instructions provided in the CPU32 and demonstrate their use. Descriptions of the instruction format and the operands used by instructions are included. After a summary of the instructions by category, a detailed description of each instruction is listed in alphabetical order. Complete programming information is provided, as well as a description of condition code computation and an instruction format summary. The CPU32 instructions include machine functions for all the following operations: * Data Movement Freescale Semiconductor, Inc... * Arithmetic Operations * Logical Operations * Shifts and Rotates * Bit Manipulation * Conditionals and Branches * System Control The large instruction set encompasses a complete range of capabilities and, combined with the enhanced addressing modes, provides a flexible base for program development. 5.3.1 M68000 Family Compatibility It is the philosophy of the M68000 Family that all user-mode programs can execute unchanged on a more advanced processor and that supervisor-mode programs and exception handlers should require only minimal alteration. The CPU32 can be thought of as an intermediate member of the M68000 family. Object code from an MC68000 or MC68010 may be executed on the CPU32, and many of the instruction and addressing mode extensions of the MC68020 are also supported. 5.3.1.1 NEW INSTRUCTIONS. Two instructions have been added to the M68000 instruction set for use in embedded control applications: LPSTOP and table lookup and interpolation (TBL). 5.3.1.1.1 Low-Power Stop (LPSTOP). In applications where power consumption is a consideration, the CPU32 can force the device into a low-power standby mode when immediate processing is not required. The low-power mode is entered by executing the LPSTOP instruction. The processor remains in this mode until a user-specified or higher level interrupt or a reset occurs. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-11 Freescale Semiconductor, Inc. 5.3.1.1.2 Table Lookup and Interpolation (TBL). To maximize throughput for real-time applications, reference data is often precalculated and stored in memory for quick access. The storage of sufficient data points can require an inordinate amount of memory. The TBL instruction uses linear interpolation to recover intermediate values from a sample of data points, and thus conserves memory. Freescale Semiconductor, Inc... When the TBL instruction is executed, the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them. Byte, word, and longword operand sizes are supported. The result can be rounded according to a round-tonearest algorithm or returned unrounded along with the fractional portion of the calculated result (byte and word results only). This extra precision can be used to reduce cumulative error in complex calculations. See 5.3.4 Using the TBL Instructions for examples. 5.3.1.2 UNIMPLEMENTED INSTRUCTIONS. The ability to trap on unimplemented instructions allows user-supplied code to emulate unimplemented capabilities or to define special-purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements. See 5.5.2.8 Illegal or Unimplemented Instructions for more details. 5.3.2 Instruction Format and Notation All instructions consist of at least one word. Some instructions can have as many as seven words, as shown in Figure 5-6. The first word of the instruction, called the operation word, specifies instruction length and the operation to be performed. The remaining words, called extension words, further specify the instruction and operands. These words may be immediate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number, special register specifications, trap operands, or argument counts. 15 0 OPERATION WORD (ONE WORD, SPECIFIES OPERATION AND MODES) SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) IMMEDIATE OPERAND OR SOURCE ADDRESS EXTENSION (IF ANY, ONE TO THREE WORDS) DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO THREE WORDS) Figure 5-6. Instruction Word General Format 5-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways: * Register Specification A register field of the instruction contains the number of the register. * Effective Address An effective address field of the instruction contains address mode information. * Implicit Reference The definition of an instruction implies the use of specific registers. The register field within an instruction specifies the register to be used. Other fields within the instruction specify whether the register is an address or data register and how it is to be used. The M68000PM/AD, M68000 Family Programmer's Reference Manual , contains detailed register information. Except where noted, the following notation is used in this section: Data Immediate data from an instruction Destination Destination contents Source Source contents Vector Location of exception vector An Any address register (A7-A0) Ax, Ay Address registers used in computation Dn Any data register (D7-D0) Rc Control register (VBR, SFC, DFC) Rn Any address or data register Dh, Dl Data registers, high- and low-order 32 bits of product Dr, Dq Data registers, division remainder, division quotient Dx, Dy Data registers, used in computation Dym, Dyn Data registers, table interpolation values Xn Index register [An] Address extension cc Condition code d# Displacement Example: d16 is a 16-bit displacement ea Effective address #data Immediate data; a literal integer label Assembly program label list List of registers Example: D3-D0 [...] Bits of an operand Examples: [7] is bit 7; [31:24] are bits 31-24 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-13 Freescale Semiconductor, Inc. (...) Freescale Semiconductor, Inc... CCR PC SP SR SSP USP FC DFC SFC + - / x = > < V ~ BCD LSW MSW {R/W} Contents of a referenced location Example: (Rn) refers to the contents of Rn Condition code register (lower byte of SR) X--extend bit N--negative bit Z--zero bit V--overflow bit C--carry bit Program counter Active stack pointer Status register Supervisor stack pointer User stack pointer Function code Destination function code register Source function code register Arithmetic addition or postincrement Arithmetic subtraction or predecrement Arithmetic division or conjunction symbol Arithmetic multiplication Equal to Not equal to Greater than Greater than or equal to Less than Less than or equal to Logical AND Logical OR Logical exclusive OR Invert; operand is logically complemented Binary-coded decimal, indicated by subscript Example: Source10 is a BCD source operand. Least significant word Most significant word Read/write indicator In a description of an operation, a destination operand is placed to the right of source operands and is indicated by an arrow (). 5-14 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.3.3 Instruction Summary The instructions form a set of tools to perform the following operations: Data movement Bit manipulation Integer arithmetic Binary-coded decimal arithmetic Logic Program control Shift and rotate System control Freescale Semiconductor, Inc... The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development. All CPU32 instructions are summarized in Table 5-2. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-15 Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary Opcode Freescale Semiconductor, Inc... Syntax Source 10 + Destination10 + X Destination ABCD Dy,Dx ABCD -(Ay),-(Ax) ADD Source + Destination Destination ADD ea,Dn ADD Dn,ea ADDA Source + Destination Destination ADDA ea,An ADDI Immediate Data + Destination Destination ADDI #data, ea ADDQ Immediate Data + Destination Destination ADDQ # data ,ea ADDX Source + Destination + X Destination ADDX Dy,Dx ADDX -(Ay),-(Ax) AND Source Destination Destination AND ea, Dn AND Dn,ea ANDI Immediate Data Destination Destination ANDI #data, ea Source CCR CCR ANDI #data,CCR If supervisor state the Source SR SR else TRAP ANDI #data,SR Destination Shifted by count Destination ASd Dx,Dy ASd # data ,Dy ASd ea If (condition true) then PC + d PC Bcc label BCHG ~(number of Destination) Z; ~(number of Destination) bit number of Destination BCHG Dn,ea BCHG # data ,ea BCLR ~(number of Destination) Z; 0 bit number of Destination BCLR Dn, ea BCLR # data ,ea BGND If (background mode enabled) then enter background mode else Format/Vector offset -(SSP) PC -(SSP) SR -(SSP) (Vector) PC BGND BKPT Run breakpoint acknowledge cycle; TRAP as illegal instruction BKPT # data BRA PC + d PC BRA label BSET ~(number of Destination) Z; 1 bit number of Destination BSET Dn, ea BSET # data, ea BSR SP - 4 SP; PC (SP); PC + d PC BSR label BTST - (number of Destination) Z; BTST Dn, ea BTST # data ,ea CHK If Dn < 0 or Dn > Source then TRAP CHK ea,Dn CHK2 If Rn < lower bound or If Rn > upper bound then TRAP CHK2 ea,Rn 0 Destination CLR ea ABCD ANDI to CCR ANDI to SR ASL,ASR Bcc CLR Destination -- Source cc CMP ea,Dn CMPA Destination -- Source CMPA ea,An CMPI Destination -- Immediate Data CMPI # data, ea Destination -- Source cc CMPM (Ay)+,(Ax)+ CMP CMPM 5-16 Operation MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Continued) Freescale Semiconductor, Inc... Opcode Operation Syntax CMP2 Compare Rn < lower-bound or Rn > upper-bound and Set Condition Codes CMP2 ea,Rn DBcc If condition false then (Dn - 1 Dn; If Dn -1 then PC + d PC) DBcc Dn, label DIVS DIVSL Destination/Source Destination DIVS.W ea,Dn DIVS.L ea,Dq DIVS.L ea,Dr:Dq DIVSL.L ea,Dr:Dq 32/16 16r:16q 32/32 32q 64/32 32r:32q 32/32 32r:32q DIVU DIVUL Destination/Source Destination DIVU.W ea,Dn DIVU.L ea,Dq DIVU.L ea,Dr:Dq DIVUL.L ea,Dr:Dq 32/16 16r:16q 32/32 32q 64/32 32r:32q 32/32 32r:32q EOR Source Destination Destination EOR Dn, ea EORI Immediate Data Destination Destination EORI # data ,ea Source CCR CCR EORI # data ,CCR EORI to SR If supervisor state the Source SR SR else TRAP EORI # data ,SR EXG Rx Ry EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx EXT EXTB Destination Sign-Extended Destination EXT.W Dn EXT.L Dn EXTB.L Dn LLEGAL SSP - 2 SSP; Vector Offset (SSP); SSP - 4 SSP; PC (SSP); SSp - 2 SSP; SR (SSP); Illegal Instruction Vector Address PC ILLEGAL EORI to CCR JMP Destination Address PC JMP ea JSR SP-4 SP; PC (SP) Destination Address PC JSR ea extend byte to word extend word to long word extend byte to long word LEA ea An LEA ea,An LINK SP - 4 SP; An (SP) SP An, SP + d SP LINK An,# displacement LPSTOP If supervisor state Immediate Data SR Interrupt Mask External Bus Interface (EBI) STOP else TRAP LPSTOP # data LSL,LSR Destination Shifted by count Destination LSd1 Dx,Dy LSd1 # data ,Dy LSd1 ea MOVE Source Destination MOVE ea,ea MOVEA Source Destination MOVEA ea,An CCR Destination MOVE CCR, ea MOVE from CCR MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-17 Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Continued) Opcode Operation Syntax Source CCR MOVE ea,CCR MOVE from SR If supervisor state then SR Destination else TRAP MOVE SR, ea MOVE to SR If supervisor state then Source SR else TRAP MOVE ea,SR MOVE USP If supervisor state then USP An or An USP else TRAP MOVE USP,An MOVE An,USP MOVEC If supervisor state then Rc Rn or Rn Rc else TRAP MOVEC Rc,Rn MOVEC Rn,Rc MOVEM Registers Destination Source Registers MOVEM register list, ea MOVEM ea,register list MOVEP Source Destination MOVEP Dx,(d,Ay) MOVEP (d,Ay),Dx Freescale Semiconductor, Inc... MOVE to CCR MOVEQ Immediate Data Destination MOVEQ # data,Dn MOVES If supervisor state then Rn Destination [DFC] or Source [SFC] Rn else TRAP MOVES Rn, ea MOVES ea,Rn MULS Source x Destination Destination MULS.W ea,Dn MULS.L ea,Dl MULS.L ea,Dh:Dl 16 x 16 32 32 x 32 32 32 x 32 64 MULU Source x Destination Destination MULU.W ea,Dn MULU.L ea,Dl MULU.L ea,Dh:Dl 16 x 16 32 32 x 32 32 32 x 32 64 NBCD 0 - (Destination10) - X Destination NBCD ea 0 - (Destination) Destination NEG ea NEG 0 - (Destination) - X Destination NEGX ea NOP None NOP NOT ~Destination Destination NOT ea OR Source V Destination Destination OR ea,Dn OR Dn, ea ORI Immediate Data V Destination Destination ORI # data ,ea Source V CCR CCR ORI # data ,CCR ORI to SR If supervisor state then Source V SR SR else TRAP ORI # data ,SR PEA Sp - 4 SP; ea (SP) PEA ea If supervisor state then Assert RESET else TRAP RESET Destination Rotated by count Destination ROd 1 Rx,Dy ROd 1 # data ,Dy ROd 1 ea NEGX ORI to CCR RESET ROL,ROR 5-18 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Concluded) Opcode Freescale Semiconductor, Inc... ROXL,ROXR Operation Syntax Destination Rotated with X by count Destination ROXd 1 Rx,Dy ROXd 1 # data ,Dy ROXd 1 ea RTD (SP) PC; SP + 4 + d SP RTD # displacement RTE If supervisor state the (SP) SR; SP + 2 SP; (SP) PC; SP + 4 SP; restore state and deallocate stack according to (SP) else TRAP RTE RTR (SP) CCR; SP + 2 SP; (SP) PC; SP + 4 SP RTR RTS (SP) PC; SP + 4 SP RTS Destination10 - Source 10 - X Destination SBCD Dx,Dy SBCD -(Ax),-(Ay) If Condition True then 1s Destination else 0s Destination Scc ea STOP If supervisor state then Immediate Data SR; STOP else TRAP STOP # data SUB Destination - Source Destination SUB ea,Dn SUB Dn, ea SBCD Scc SUBA Destination - Source Destination SUBA ea,An SUBI Destination - Immediate Data Destination SUBI # data ,ea SUBQ Destination - Immediate Data Destination SUBQ # data,ea SUBX Destination - Source - X Destination SUBX Dx,Dy SUBX -(Ax),-(Ay) SWAP Register [31:16] Register [15:0] SWAP Dn Destination Tested Condition Codes; 1 bit 7 of Destination TAS ea ENTRY(n) + {(ENTRY(n + 1) - ENTRY(n)) * Dx[7:0]} / 256 Dx TBLS.size ea, Dx TBLS.size Dym:Dyn, Dx ENTRY(n) x 256 + {(ENTRY(n + 1) - ENTRY(n)) * Dx [7:0]} Dx TBLSN. size ea,Dx TBLSN. size Dym:Dyn, Dx ENTRY(n) + {(ENTRY(n + 1) - ENTRY(n)) * Dx[7:0]} / 256 Dx TBLU. size ea,Dx TBLU. size Dym:Dyn, Dx TBLUN ENTRY(n) * 256 + {(ENTRY(n + 1) - ENTRY(n)) * Dx[7:0]} Dx TBLUN. size ea,Dx TBLUN. size Dym:Dyn,Dx TRAP SSP - 2 SSP; Format/Offset (SSP); SSP - 4 SSP; PC (SSP); SSP - 2 SSP; SR (SSP); Vector Address PC TRAP # vector TRAPcc If cc then TRAP TRAPcc TRAPcc.W # data TRAPcc.L # data TRAPV If V then TRAP TRAPV Destination Tested Condition Codes TST ea TAS TBLS TBLSN TBLU TST UNLK An SP; (SP) An; SP + 4 SP NOTE 1: d is direction, L or R. MOTOROLA UNLK An MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-19 Freescale Semiconductor, Inc. 5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that indicate the result of a processor operation. Table 5-3 lists the effect of each instruction on these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them. Refer to Table 5-7 as an example. Table 5-3. Condition Code Computations Freescale Semiconductor, Inc... Operations 5-20 X N Z V C ABCD * U ? U ? C = Decimal Carry Z = Z R ... R0 ADD, ADDI, ADDQ * * * ? ? V = Sm Dm R V S D Rm C = Sm Dm V R Dm V Sm R ADDX * * ? ? ? V = Sm Dm R V S D Rm C = Sm Dm V R Dm V Sm R Z = Z R ... R0 AND, ANDI, EOR, EORI, MOVEQ, MOVE, OR, ORI, CLR, EXT, NOT, TAS, TST -- * * 0 0 CHK -- * U U U CHK2, CMP2 -- U ? U ? Z = (R = LB) V (R = UB) C = (LB < UB) (IR < LB) V (R > UB) V (UB < LB) (R > UB) (R < LB) SUB, SUBI, SUBQ * * * ? ? V = S Dm R V Sm D Rm C = Sm D V Rm D V Sm Rm SUBX * * ? ? ? V = S Dm R V Sm D Rm C = Sm D V Rm D V Sm Rm Z = Z R ... R0 CMP, CMPI, CMPM -- * * ? ? V = S Dm R V Sm D Rm C = Sm D V Rm D V Sm Rm DIVS, DIVU -- * * ? 0 V = Division Overflow MULS, MULU -- * * ? 0 V = Multiplication Overflow SBCD, NBCD * U ? U ? C = Decimal Borrow Z = Z R ... R0 NEG * * * ? ? V = Dm Rm C = Dm V Rm NEGX * * ? ? ? V = Dm Rm C = Dm V Rm Z = Z R ... R0 ASL * * * ? ? V = Dm (D - 1 V ... V D - r ) V D (Dm-1 V ... + Dm - r) C = D - r + 1 ASL (r = 0) -- * * 0 0 LSL, ROXL * * * 0 ? LSR (r = 0) -- * * 0 0 ROXL (r = 0) -- * * 0 ? C=X C = Dm - r + 1 ROL -- * * 0 ? ROL (r = 0) -- * * 0 0 ASR, LSR, ROXR * * * 0 ? ASR, LSR (r = 0) -- * * 0 0 ROXR (r = 0) -- * * 0 ? Special Definition C = Dm - r + 1 C = Dr - 1 C=X MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table 5-3. Condition Code Computations (Continued) X N Z V C ROR Operations -- 0 ? ROR (r = 0) -- 0 0 Special Definition C = Dr - 1 Freescale Semiconductor, Inc... NOTE : The following notations apply to this table only. -- = Not affected Sm = Source operand MSB U = Undefined Dm = Destination operand MSB ? = See special definition Rm = Result operand MSB = General case R = Register tested X = C n = Bit Number N = Rm r = Shift count Z = LB = Lower bound = Upper bound = UB Rm = V Rm ... R0 Boolean AND Boolean OR = NOT Rm 5.3.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction is the basic means of transferring and storing address and data. MOVE instructions transfer byte, word, and long-word operands from memory to memory, memory to register, register to memory, and register to register. Address movement instructions (MOVE or MOVEA) transfer word and long-word operands and ensure that only valid address manipulations are executed. In addition to the general MOVE instructions, there are several special data movement instructions--move multiple registers (MOVEM), move peripheral data (MOVEP), move quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), and unlink stack (UNLK). Table 5-4 is a summary of the data movement operations. Table 5-4. Data Movement Operations Instruction Operand Syntax Operand Size EXG Rn, Rn 32 Rn Rn LEA ea, An 32 ea An LINK An, #d 16, 32 Operation SP - 4 SP, An (SP); SP An, SP + d SP MOVE ea, ea 8, 16, 32 Source Destination MOVEA ea, An 16, 32 32 Source Destination MOVEM list, ea ea, list 16, 32 16, 32 32 Listed registers Destination Source Listed registers MOVEP Dn, (d16, An) 16, 32 Dn [31:24] (An + d); Dn [23:16] (An + d + 2); Dn [15:8] (An + d + 4); Dn [7:0] (An + d + 6) (An + d) Dn [31:24]; (An + d + 2) Dn [23:16]; (An + d + 4) Dn [15:8]; (An + d + 6) Dn [7:0] Immediate Data Destination (d 16, An), Dn MOVEQ #data, Dn 8 32 PEA ea 32 SP - 4 SP; ea SP UNLK An 32 An SP; (SP) An, SP + 4 SP MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-21 Freescale Semiconductor, Inc. 5.3.3.3 INTEGER ARITHMETIC OPERATIONS. The arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations. Address operands consist of 16 or 32 bits. The clear and negate instructions apply to all sizes of data operands. Signed and unsigned MUL and DIV instructions include: * Word multiply to produce a long-word product * Long-word multiply to produce a long-word or quad-word product Freescale Semiconductor, Inc... * Division of a long-word dividend by a word divisor (word quotient and word remainder) * Division of a long-word or quad-word dividend by a long-word divisor (long-word quotient and long-word remainder) A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arithmetic operations. 5-22 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table 5-5. Integer Arithmetic Operations Operand Syntax Operand Size ADD Dn, ea ea, Dn 8, 16, 32 8, 16, 32 Source + Destination Destination ADDA ea, An 16, 32 Source + Destination Destination ADDI #data, ea 8, 16, 32 Immediate Data + Destination Destination ADDQ #data, ea 8, 16, 32 Immediate Data + Destination Destination ADDX Dn, Dn - (An), - (An) 8, 16, 32 8, 16, 32 Source + Destination + X Destination Freescale Semiconductor, Inc... Instruction Operation CLR ea 8, 16, 32 0 Destination CMP ea, Dn 8, 16, 32 (Destination - Source), CCR shows results CMPA ea, An 16, 32 (Destination - Source), CCR shows results CMPI #data, ea 8, 16, 32 CMPM (An) +, (An) + 8, 16, 32 (Destination - Source), CCR shows results CMP2 ea, Rn 8, 16, 32 Lower bound Rn Upper Bound, CCR shows results DIVS/DIVU ea, Dn ea, Dr:Dq ea, Dq ea, Dr:Dq 32/16 16:16 64/32 32:32 32/32 32 32/32 32:32 EXT Dn Dn 8 16 16 32 Sign Extended Destination Destination EXTB Dn 8 32 Sign Extended Destination Destination MULS/MULU ea, Dn ea, Dl ea, Dh:Dl 16 x 16 32 32 x 32 32 32 x 32 64 DIVSL/DIVUL (Destination - Immediate Data), CCR shows results Destination/Source Destination (signed or unsigned) Source x Destination Destination (signed or unsigned) NEG ea 8, 16, 32 0 - Destination Destination NEGX ea 8, 16, 32 0 - Destination - X Destination SUB ea, Dn Dn, ea 8, 16, 32 Destination - Source Destination SUBA ea, An 16, 32 Destination - Source Destination SUBI #data, ea 8, 16, 32 Destination - Immediate Data Destination SUBQ #data, ea 8, 16, 32 Destination - Immediate Data Destination SUBX Dn, Dn - (An), - (An) 8, 16, 32 8, 16, 32 Destination - Source - X Destination TBLS/TBLU ea, Dn Dym:Dyn, Dn 8, 16, 32 Dyn - Dym Temp (Temp x Dn [7:0]) Temp (Dym x 256) + Temp Dn TBLSN/TBLUN ea, Dn Dym:Dyn, Dn 8, 16, 32 Dyn - Dym Temp (Temp x Dn [7:0]) / 256 Temp Dym + Temp Dn MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-23 Freescale Semiconductor, Inc. 5.3.3.4 LOGIC INSTRUCTIONS. The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The test (TST) instruction arithmetically compares the operand with zero, placing the result in the CCR. Table 5-6 summarizes the logical operations. Table 5-6. Logic Operations Operand Syntax Operand Size AND ea, Dn Dn, ea 8, 16, 32 8, 16, 32 Source Destination Destination ANDI #data, ea 8, 16, 32 Immediate Data Destination Destination EOR Dn, ea 8, 16, 32 Source Destination Destination EORI #data, ea 8, 16, 32 Immediate Data Destination Destination NOT ea 8, 16, 32 Destination Destination OR ea, Dn Dn, ea 8, 16, 32 8, 16, 32 Source V Destination Destination ORI #data, ea 8, 16, 32 Immediate Data V Destination Destination TST ea 8, 16, 32 Source - 0, to set condition codes Freescale Semiconductor, Inc... Instruction Operation 5.3.3.5 SHIFT AND ROTATE INSTRUCTIONS. The arithmetic shift instructions, ASR and ASL, and logical shift instructions, LSR and LSL, provide shift operations in both directions. The ROR, ROL, ROXR, and ROXL instructions perform rotate (circular shift) operations, with and without the extend bit. All shift and rotate operations can be performed on either registers or memory. Register shift and rotate operations shift all operand sizes. The shift count may be specified in the instruction operation word (to shift from 1 to 8 places) or in a register (modulo 64 shift count). Memory shift and rotate operations shift word-length operands one bit position only. The SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping. Table 5-7 is a summary of the shift and rotate operations. 5-24 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table 5-7. Shift and Rotate Operations Instruction ASL ASR LSL Freescale Semiconductor, Inc... LSR ROL ROR ROXL ROXR SWAP Operand Syntax Operand Size Dn, Dn #data, Dn ea 8, 16, 32 8, 16, 32 16 Dn, Dn #data, Dn ea 8, 16, 32 8, 16, 32 16 Dn, Dn #data, Dn ea 8, 16, 32 8, 16, 32 16 Dn, Dn #data, Dn ea 8, 16, 32 8, 16, 32 16 Dn, Dn #data, Dn ea 8, 16, 32 8, 16, 32 16 Dn, Dn #data, Dn ea 8, 16, 32 8, 16, 32 16 Dn, Dn #data, Dn ea 8, 16, 32 8, 16, 32 16 Dn, Dn #data, Dn ea 8, 16, 32 8, 16, 32 16 Dn 16 Operation X/C 0 X/C 0 X/C 0 X/C C C C X X C MSW LSW 5.3.3.6 BIT MANIPULATION INSTRUCTIONS. Bit manipulation operations are accomplished using the following instructions: bit test (BTST), bit test and set (BSET), bit test and clear (BCLR), and bit test and change (BCHG). All bit manipulation operations can be performed on either registers or memory. The bit number is specified as immediate data or in a data register. Register operands are 32 bits long, and memory operands are 8 bits long. Table 5-8 is a summary of bit manipulation instructions. Table 5-8. Bit Manipulation Operations Operand Syntax Operand Size BCHG Dn, ea #data, ea 8, 32 8, 32 ~(bit number of destination) Z bit of destination BCLR Dn, ea #data, ea 8, 32 8, 32 ~(bit number of destination) Z; 0 bit of destination BSET Dn, ea #data, ea 8, 32 8, 32 ~(bit number of destination) Z; 1 bit of destination BTST Dn, ea #data, ea 8, 32 8, 32 ~( bit number of destination) Z Instruction MOTOROLA Operation MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-25 Freescale Semiconductor, Inc. 5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five instructions support operations on BCD numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD). Table 5-9 is a summary of the BCD operations. Table 5-9. Binary-Coded Decimal Operations Operand Syntax Operand Size ABCD Dn, Dn - (An), - (An) 8 8 Source 10 + Destination10 + X Destination NBCD ea 8 8 0 - Destination10 - X Destination SBCD Dn, Dn - (An), - (An) 8 8 Destination10 - Source10 - X Destination Freescale Semiconductor, Inc... Instruction Operation 5.3.3.8 PROGRAM CONTROL INSTRUCTIONS. A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations. Table 5-10 summarizes these instructions. Table 5-10. Program Control Operations Instruction Operand Syntax Operand Size Bcc label 8, 16, 32 If condition true, then PC + d PC DBcc Dn , label 16 If condition false, then Dn - 1 PC; if Dn (- 1), then PC + d PC Scc ea 8 If condition true, then destination bits are set to 1; else destination bits are cleared to 0 BRA label 8, 16, 32 PC + d PC BSR label 8, 16, 32 SP - 4 SP; PC (SP); PC + d PC JMP ea none Destination PC JSR ea none SP - 4 SP; PC (SP); destination PC NOP none none PC + 2 PC Operation Conditional Unconditional Returns 5-26 (SP) PC; SP + 4 + d SP RTD #d 16 RTR none none (SP) CCR; SP + 2 SP; (SP) PC; SP + 4 SP RTS none none (SP) PC; SP + 4 SP MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... To specify conditions for change in program control, condition codes must be substituted for the letters "cc" in conditional program control opcodes. Condition test mnemonics are given below. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. CC -- Carry clear LS -- Low or same CS -- Carry set LT -- Less than EQ -- Equal MI -- Minus F False* NE -- Not equal GE -- Greater or equal PL -- Plus GT -- Greater than T True HI High VC -- Overflow clear Less or equal VS -- Overflow set -- -- LE -- -- *Not applicable to the Bcc instruction 5.3.3.9 SYSTEM CONTROL INSTRUCTIONS. Privileged instructions, trapping instructions, and instructions that use or modify the CCR provide system control operations. All of these instructions cause the processor to flush the instruction pipeline. Table 5-11 summarizes the instructions. The preceding list of condition tests also applies to the TRAPcc instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-27 Freescale Semiconductor, Inc. Table 5-11. System Control Operations Instruction Operand Syntax Operand Size Operation Freescale Semiconductor, Inc... Privileged ANDI #data, SR 16 Immediate Data SR SR EORI #data, SR 16 Immediate Data SR SR MOVE ea, SR SR, ea 16 16 Source SR SR Destination MOVEA USP, An An, USP 32 32 USP An An USP MOVEC Rc, Rn Rn, Rc 32 32 Rc Rn Rn Rc MOVES Rn, ea ea, Rn 8, 16, 32 Rn Destination using DFC Source using SFC Rn ORI #data, SR 16 Immediate Data V SR SR RESET none none Assert RESET line RTE none none (SP) SR; SP + 2 SP; (SP) PC; SP + 4 SP; restore stack according to format STOP #data 16 LPSTOP #data none Immediate Data SR; STOP Immediate Data SR; interrupt mask EBI; STOP Trap Generating BKPT #data none If breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction. BGND none none If background mode enabled, then enter background mode, else format/vector offset - (SSP); PC - (SSP); SR - (SSP); (vector) PC CHK ea, Dn 16, 32 CHK2 ea, Rn 8, 16, 32 ILLEGAL none none SSP - 2 SSP; vector offset (SSP); SSP - 4 SSP; PC (SSP); SSP - 2 SSP; SR (SSP); llegal instruction vector address PC TRAP #data none SSP - 2 SSP; format/vector offset (SSP); SSP - 4 SSP; PC (SSP); SR (SSP); vector address PC TRAPcc none #data none 16, 32 TRAPV none none If Dn < 0 or Dn < (ea), then CHK exception If Rn < lower bound or Rn > upper bound, then CHK exception If cc true, then TRAP exception If V set, then overflow TRAP exception Condition Code Register 5-28 ANDI #data, CCR 8 Immediate Data CCR CCR EORI #data, CCR 8 Immediate Data CCR CCR MOVE ea, CCR CCR, ea 16 16 Source CCR CCR Destination ORI #data, CCR 8 Immediate Data V CCR CCR MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.3.3.10 CONDITION TESTS. Conditional program control instructions and the TRAPcc instruction execute on the basis of condition tests. A condition test is the evaluation of a logical expression related to the state of the CCR bits. If the result is 1, the condition is true. If the result is 0, the condition is false. For example, the T condition is always true, and the EQ condition is true only if the Z-bit condition code is true. Table 5-12 lists each condition test. Freescale Semiconductor, Inc... Table 5-12. Condition Tests Mnemonic Condition Encoding Test T True 0000 1 F* False 0001 0 HI High 0010 C*Z LS Low or Same 0011 C+Z CC Carry Clear 0100 C CS Carry Set 0101 C NE Not Equal 0110 Z EQ Equal 0111 Z VC Overflow Clear 1000 V VS Overflow Set 1001 V PL Plus 1010 N MI Minus 1011 N GE Greater or Equal 1100 N * V + N* V LT Less Than 1101 N * V+ N*V GT Greater Than 1110 N * V * Z+ N * V * Z LE Less or Equal * Not available for the Bcc instruction. * = Boolean AND + = Boolean OR N = Boolean NOT 1111 Z + N * V+ N * V 5.3.4 Using the TBL Instructions There are four TBL instructions. TBLS returns a signed, rounded byte, word, or long-word result. TBLSN returns a signed, unrounded byte, word, or long-word result. TBLU returns an unsigned, rounded byte, word, or long-word result. TBLUN returns an unsigned, unrounded byte, word, or long-word result. All four instructions support two types of interpolation data: an n-element table stored in memory and a two-element range stored in a pair of data registers. The latter form provides a means of performing surface (3D) interpolation between two previously calculated linear interpolations. The following examples show how to compress tables and use fewer interpolation levels between table entries. Example 1 (see Figure 5-7) demonstrates TBL for a 257-entry table, allowing up to 256 interpolation levels between entries. Example 2 (see Figure 5-8) reduces table length for the same data to four entries. Example 3 (see Figure 5-9) demonstrates use of an 8-bit independent variable with an instruction. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-29 Freescale Semiconductor, Inc. Two additional examples show how TBLSN can reduce cumulative error when multiple table lookup and interpolation operations are used in a calculation. Example 4 demonstrates addition of the results of three table interpolations. Example 5 illustrates use of TBLSN in surface interpolation. 5.3.4.1 TABLE EXAMPLE 1: STANDARD USAGE. The table consists of 257 word entries. As shown in Figure 5-7, the function is linear within the range 32768 X 49152. Table entries within this range are as given in Table 5-13 . Freescale Semiconductor, Inc... Table 5-13. Standard Usage Entries Entry Number X Value Y Value 128* 32768 1311 162 41472 1659 163 41728 1669 164 41984 1679 165 42240 1690 192* 49152 1966 *These values are the end points of the range. All entries between these points fall on the line. DEPENDENT VARIABLE Y 16384 32768 49152 65536 X INDEPENDENT VARIABLE Figure 5-7. Table Example 1 5-30 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The table instruction is executed with the following bit pattern in Dx: 31 16 NOT USED 15 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 Table Entry Offset Dx [8:15] = $A3 = 163 Interpolation Fraction Dx [0:7] = $80 = 128 Using this information, the table instruction calculates dependent variable Y: 5.3.4.2 TABLE EXAMPLE 2: COMPRESSED TABLE. In Example 2 (see Figure 5-8), the data from Example 1 has been compressed by limiting the maximum value of the independent variable. Instead of the range 0 X = 65535, X is limited to 0 X 1023. The table has been compressed to only five entries, but up to 256 levels of interpolation are allowed between entries. Y DEPENDENT VARIABLE Freescale Semiconductor, Inc... Y = 1669 + (128 (1679 - 1669)) / 256 = 1674 256 512 786 1024 X INDEPENDENT VARIABLE Figure 5-8. Table Example 2 NOTE Extreme table compression with many levels of interpolation is possible only with highly linear functions. The table entries within the range of interest are listed in Table 5-14. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-31 Freescale Semiconductor, Inc. Table 5-14. Compressed Table Entries Entry Number X Value Y Value 2 512 1311 3 786 1966 Since the table is reduced from 257 to 5 entries, independent variable X must be scaled appropriately. In this case the scaling factor is 64, and the scaling is done by a single instruction: LSR.W #6,Dx Thus, Dx now contains the following bit pattern: Freescale Semiconductor, Inc... 31 16 NOT USED 15 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 Table Entry Offset Dx [8:15] = $02 = 2 Interpolation Fraction Dx [0:7] = $8E = 142 Using this information, the table instruction calculates dependent variable Y: Y = 1331 + (142 (1966 - 1311)) / 256 = 1674 The function chosen for Examples 1 and 2 is linear between data points. If another function had been been used, interpolated values might not have been identical. 5.3.4.3 TABLE EXAMPLE 3: 8-BIT INDEPENDENT VARIABLE. This example shows how to use a table instruction within an interpolation subroutine. Independent variable X is calculated as an 8-bit value, allowing 16 levels of interpolation on a 17-entry table. X is passed to the subroutine, which returns an 8-bit result. The subroutine uses the data listed in Table 5-15, based on the function shown in Figure 5-9. 5-32 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... INDEPENDENT VARIABLE Freescale Semiconductor, Inc. Y 2048 1024 4096 3072 X INDEPENDENT VARIABLE Figure 5-9. Table Example 3 Table 5-15. 8-Bit Independent Variable Entries X (Subroutine) X (Instruction) Y 0 0 0 1 256 16 2 512 32 3 768 48 4 1024 64 5 1280 80 6 1536 96 7 1792 112 8 2048 128 9 2304 112 10 2560 96 11 2816 80 12 3072 64 13 3328 48 14 3584 32 15 3840 16 16 4096 0 The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column is the result returned by the subroutine. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-33 Freescale Semiconductor, Inc. The following value has been calculated for independent variable X: 31 16 NOT USED 15 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 Since X is an 8-bit value, the upper four bits are used as a table offset and the lower four bits are used as an interpolation fraction. The following results are obtained from the subroutine: Table Entry Offset Dx [4:7] = $B = 11 Interpolation Fraction Dx [0:3] = $D = 13 Freescale Semiconductor, Inc... Thus, Y is calculated as follows: Y = 80 + (13 (64 - 80)) / 16 = 67 If the 8-bit value for X were used directly by the table instruction, interpolation would be incorrectly performed between entries 0 and 1. Data must be shifted to the left four places before use: LSL.W #4, Dx The new range for X is 0 X 4096; however, since a left shift fills the least significant digits of the word with zeros, the interpolation fraction can only have one of 16 values. After the shift operation, Dx contains the following value: 31 16 NOT USED 15 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 Execution of the table instruction using the new value in Dx yields: Table Entry Offset Dx [8:15] = $0B = 11 Interpolation Fraction Dx [0:7] = $D0 = 208 Thus, Y is calculated as follows: Y = 80 + (208 (64 - 80)) / 256 = 67 5.3.4.4 TABLE EXAMPLE 4: MAINTAINING PRECISION. In this example, three TBL operations are performed and the results are summed. The calculation is done once with the result of each TBL rounded before addition and once with only the final result rounded. Assume that the result of the three interpolations are as follows (a ".'' indicates the binary radix point). 5-34 TBL # 1 0010 0000 . 0111 0000 TBL# 2 0011 1111 . 0111 0000 TBL # 3 0000 0001 . 0111 0000 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. First, the results of each TBL are rounded with the TBLS round-to-nearest-even algorithm. The following values would be returned by TBLS: TBL # 1 TBL # 2 TBL # 3 0010 0000 . 0011 1111 . 0000 0001 . Summing, the following result is obtained: Freescale Semiconductor, Inc... 0010 0011 0000 0110 0000 . 1111 . 0001 . 0000 . Now, using the same TBL results, the sum is first calculated and then rounded according to the same algorithm: 0010 0011 0000 0110 0000 . 0111 1111 . 0111 0001 . 0111 0001 . 0101 0000 0000 0000 0000 Rounding yields: 0110 0001 . The second result is preferred. The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the intermediate results: L0: TBLSN.B TBLSN.B TBLSN.B ADD.L ADD.L ASR.L BCC.B ADDQ.B L1: . . . MOTOROLA ea, Dx ea, Dx ea, Dl Dx, Dm Dm, Dl #8, Dl L1 #1, Dl Long addition avoids problems with carry Move radix point Fraction MSB in carry MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-35 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 5.3.4.5 Table Example 5: Surface Interpolations. The various forms of table can be used to perform surface (3D) TBLs. However, since the calculation must be split into a series of 2D TBLs, the possibility of losing precision in the intermediate results is possible. The following code sequence, incorporating both TBLS and TBLSN, eliminates this possibility. L0: MOVE.W TBLSN.B TBLSN.B TBLS.W ASR.L BCC.B ADDQ.B L1: . . . Dx, Dl ea, Dx ea, Dl Dx:Dl, Dm #8, Dm L1 #1, Dl Copy entry number and fraction number Surface interpolation, with round Read just the result No round necessary Half round up Before execution of this code sequence, Dx must contain fraction and entry numbers for the two TBL, and Dm must contain the fraction for surface interpolation. The ea fields in the TBLSN instructions point to consecutive columns in a 3D table. The TBLS size parameter must be word if the TBLSN size parameter is byte, and must be long word if TBLSN is word. Increased size is necessary because a larger number of significant digits is needed to accommodate the scaled fractional results of the 2D TBL. 5.3.5 Nested Subroutine Calls The LINK instruction pushes an address onto the stack, saves the stack address at which the address is stored, and reserves an area of the stack for use. Using this instruction in a series of subroutine calls will generate a linked list of stack frames. The UNLK instruction removes a stack frame from the end of the list by loading an address into the SP and pulling the value at that address from the stack. When the instruction operand is the address of the link address at the bottom of a stack frame, the effect is to remove the stack frame from both the stack and the linked list. 5.3.6 Pipeline Synchronization with the NOP Instruction Although the no operation (NOP) instruction performs no visible operation, it does force synchronization of the instruction pipeline, since all previous instructions must complete execution before the NOP begins. 5.4 PROCESSING STATES This section describes the processing states of the CPU32. It includes a functional description of the bits in the supervisor portion of the SR and an overview of actions taken by the processor in response to exception conditions. 5-36 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.4.1 State Transitions The processor is in normal, background, or exception state unless halted. When the processor fetches instructions and operands or executes instructions, it is in the normal processing state. The stopped condition, which the processor enters when a STOP or LPSTOP instruction is executed, is a variation of the normal state in which no further bus cycles are generated. Freescale Semiconductor, Inc... Background state is an alternate operational mode used for system debugging. Refer to 5.6 Development Support for more information. Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines, interrupt routines, and other exception handlers. Exception processing includes the stack operations, the exception vector fetch, and the filling of the instruction pipeline caused by an exception. Exception processing ends when execution of an exception handler routine begins. Refer to 5.5 Exception Processing for comprehensive information. A catastrophic system failure occurs if the processor detects a bus error or generates an address error while in the exception processing state. This type of failure halts the processor. For example, if a bus error occurs during exception processing caused by a bus error, the CPU32 assumes that the system is not operational and halts. The halted condition should not be confused with the stopped condition. After the processor executes a STOP or LPSTOP instruction, execution of instructions can resume when a trace, interrupt, or reset exception occurs. 5.4.2 Privilege Levels To protect system resources, the processor can operate with either of two levels of access--user or supervisor. Supervisor level is more privileged than user level. All instructions are available at the supervisor level, but execution of some instructions is not permitted at the user level. There are separate SPs for each level. The S-bit in the SR indicates privilege level and determines which SP is used for stack operations. The processor identifies each bus access (supervisor or user mode) via function codes to enforce supervisor and user access levels. In a typical system, most programs execute at the user level. User programs can access only their own code and data areas and are restricted from accessing other information. The operating system executes at the supervisor privilege level, has access to all resources, performs the overhead tasks for the user level programs, and coordinates their activities. 5.4.2.1 SUPERVISOR PRIVILEGE LEVEL. If the S-bit in the SR is set, supervisor privilege level applies, and all instructions are executable. The bus cycles generated for instructions executed in supervisor level are normally classified as supervisor references, and the values of the function codes on FC2-FC0 refer to supervisor address spaces. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-37 Freescale Semiconductor, Inc. All exception processing is performed at the supervisor level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the SSP. Freescale Semiconductor, Inc... Instructions that have important system effects can only be executed at supervisor level. For instance, user programs are not permitted to execute STOP, LPSTOP, or RESET instructions. To prevent a user program from gaining privileged access, except in a controlled manner, instructions that can alter the S-bit in the SR are privileged. The TRAP #n instruction provides controlled user access to operating system services. 5.4.2.2 USER PRIVILEGE LEVEL. If the S-bit in the SR is cleared, the processor executes instructions at the user privilege level. The bus cycles for an instruction executed at the user privilege level are classified as user references, and the values of the function codes on FC2-FC0 specify user address spaces. While the processor is at the user level, implicit references to the system SP and explicit references to address register seven (A7) refer to the USP. 5.4.2.3 CHANGING PRIVILEGE LEVEL. To change from user privilege level to supervisor privilege level, a condition that causes exception processing must occur. When exception processing begins, the current values in the SR, including the S-bit, are saved on the supervisor stack, and then the S-bit is set to enable supervisory access. Execution continues at supervisor privilege level until exception processing is complete. To return to user access level, a system routine must execute one of the following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These instructions execute only at supervisor privilege level and can modify the S-bit of the SR. After these instructions execute, the instruction pipeline is flushed, then refilled from the appropriate address space. The RTE instruction causes a return to a program that was executing when an exception occurred. When RTE is executed, the exception stack frame saved on the supervisor stack can be restored in either of two ways. If the frame was generated by an interrupt, breakpoint, trap, or instruction exception, the SR and PC are restored to the values saved on the supervisor stack, and execution resumes at the restored PC address, with access level determined by the S-bit of the restored SR. If the frame was generated by a bus error or an address error exception, the entire processor state is restored from the stack. 5.5 EXCEPTION PROCESSING An exception is a special condition that preempts normal processing. Exception processing is the transition from normal mode program execution to execution of a routine that deals with an exception. The following paragraphs discuss system resources related to exception handling, exception processing sequence, and specific features of individual exception processing routines. 5-38 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.5.1 Exception Vectors An exception vector is the address of a routine that handles an exception. The VBR contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. Sixty-four vectors are defined by the processor, and 192 vectors are reserved for user definition as interrupt vectors. Except for the reset vector which is two long words, each vector in the table is one long word. Refer to Table 5-16 for information on vector assignment. Table 5-16. Exception Vector Assignments Vector Offset Freescale Semiconductor, Inc... Vector Number Dec Hex Space Assignment 0 0 000 SP Reset: Initial Stack Pointer 1 4 004 SP Reset: Initial Program Counter 2 8 008 SD Bus Error 3 12 00C SD Address Error 4 16 010 SD Illegal Instruction 5 20 014 SD Zero Division 6 24 018 SD CHK, CHK2 Instructions 7 28 01C SD TRAPcc, TRAPV Instructions 8 32 020 SD Privilege Violation 9 36 024 SD Trace 10 40 028 SD Line 1010 Emulator 11 44 02C SD Line 1111 Emulator 12 48 030 SD Hardware Breakpoint 13 52 034 SD (Reserved for Coprocessor Protocol Violation) 14 56 038 SD Format Error 15 60 03C SD Uninitialized Interrupt 16-23 64 92 040 05C SD (Unassigned, Reserved) -- 24 96 060 SD Spurious Interrupt 25 100 064 SD Level 1 Interrupt Autovector 26 104 068 SD Level 2 Interrupt Autovector 27 108 06C SD Level 3 Interrupt Autovector 28 112 070 SD Level 4 Interrupt Autovector 29 116 074 SD Level 5 Interrupt Autovector 30 120 078 SD Level 6 Interrupt Autovector 31 124 07C SD Level 7 Interrupt Autovector 32-47 128 188 080 0BC SD Trap Instruction Vectors (0-15) -- 48-58 192 232 0C0 0E8 SD (Reserved for Coprocessor) -- 59-63 236 252 0EC 0FC SD (Unassigned, Reserved) 256 1020 100 3FC SD 64-255 MOTOROLA -- User-Defined Vectors (192) MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-39 Freescale Semiconductor, Inc. CAUTION Because there is no protection on the 64 processor-defined vectors, external devices can access vectors reserved for internal purposes. This practice is strongly discouraged. Freescale Semiconductor, Inc... All exception vectors, except the reset vector, are located in supervisor data space. The reset vector is located in supervisor program space. Only the initial reset vector is fixed in the processor memory map. When initialization is complete, there are no fixed assignments. Since the VBR stores the vector table base address, the table can be located anywhere in memory. It can also be dynamically relocated for each task executed by an operating system. Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained from an external device; others are supplied by the processor. The processor multiplies the vector number by 4 to calculate vector offset, then adds the offset to the contents of the VBR. The sum is the memory address of the vector. 5.5.1.1 TYPES OF EXCEPTIONS. An exception can be caused by internal or external events. An internal exception can be generated by an instruction or by an error. The TRAP, TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions during normal execution. Illegal instructions, instruction fetches from odd addresses, word or long-word operand accesses from odd addresses, and privilege violations also cause internal exceptions. Sources of external exception include interrupts, breakpoints, bus errors, and reset requests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access control and processor restart. 5.5.1.2 EXCEPTION PROCESSING SEQUENCE. For all exceptions other than a reset exception, exception processing occurs in the following sequence. Refer to 5.5.2.1 Reset for details of reset processing. As exception processing begins, the processor makes an internal copy of the SR. After the copy is made, the processor state bits in the SR are changed--the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority mask is also updated. Next, the exception number is obtained. For interrupts, the number is fetched from CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal logic provides a vector number. Next, current processor status is saved. An exception stack frame is created and placed on the supervisor stack. All stack frames contain copies of the SR and the PC for use by RTE. The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame. 5-40 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Finally, the processor prepares to resume normal execution of instructions. The exception vector offset is determined by multiplying the vector number by 4, and the offset is added to the contents of the VBR to determine displacement into the exception vector table. The exception vector is loaded into the PC. If no other exception is pending, the processor will resume normal execution at the new address in the PC. The exception stack frame always includes the contents of SR and PC at the time the exception occurred. To support generic handlers, the processor also places the vector offset in the exception stack frame and marks the frame with a format code. The format field allows an RTE instruction to identify stack information so that it can be properly restored. The general form of the exception stack frame is illustrated in Figure 5-10. Although some formats are peculiar to a particular M68000 Family processor, format 0000 is always legal and always indicates that only the first four words of a frame are present. See 5.5.4 CPU32 Stack Frames for a complete discussion of exception stack frames. 15 0 SP STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW FORMAT VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION, DEPENDING ON EXCEPTION (0, 2, OR 8 WORDS) STACKING ORDER HIGHER ADDRESSES Freescale Semiconductor, Inc... 5.5.1.3 EXCEPTION STACK FRAME. During exception processing, the most volatile portion of the current context is saved on the top of the supervisor stack. This context is organized in a format called the exception stack frame. Figure 5-10. Exception Stack Frame 5.5.1.4 MULTIPLE EXCEPTIONS. Each exception has been assigned a priority based on its relative importance to system operation. Priority assignments are shown in Table 5-17. Group 0 exceptions have the highest priorities; group 4 exceptions have the lowest priorities. Exception processing for exceptions that occur simultaneously is done by priority, from highest to lowest. It is important to be aware of the difference between exception processing mode and execution of an exception handler. Each exception has an assigned vector that points to an associated handler routine. Exception processing includes steps described in 5.5.1.2 Exception Processing Sequence, but does not include execution of handler routines, which is done in normal mode. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-41 Freescale Semiconductor, Inc. When the CPU32 completes exception processing, it is ready to begin either exception processing for a pending exception or execution of a handler routine. Priority assignment governs the order in which exception processing occurs, not the order in which exception handlers are executed. Table 5-17. Exception Priority Groups Group/ Priority 0 Characteristics Reset Aborts all processing (instruction or exception); does not save old context. Address Error Bus Error Suspends processing (instruction or exception); saves internal context. 2 BKPT#n, CHK, CHK2, Division by Zero, RTE, TRAP#n, TRAPcc, TRAPV Exception processing is a part of instruction execution. 3 Illegal Instruction, Line A, Unimplemented Line F, Privilege Violation Exception processing begins before instruction execution. Trace Hardware Breakpoint Interrupt Exception processing begins when current instruction or previous exception processing is complete. 1.1 1.2 Freescale Semiconductor, Inc... Exception and Relative Priority 4.1 4.2 4.3 As a general rule, when simultaneous exceptions occur, the handler routines for lower priority exceptions are executed before the handler routines for higher priority exceptions. For example, consider the arrival of an interrupt during execution of a TRAP instruction, while tracing is enabled. Trap exception processing (2) is done first, followed immediately by exception processing for the trace (4.1), and then by exception processing for the interrupt (4.3). Each exception places a new context on the stack. When the processor resumes normal instruction execution, it is vectored to the interrupt handler, which returns to the trace handler that returns to the trap handler. There are special cases to which the general rule does not apply. The reset exception will always be the first exception handled since reset clears all other exceptions. It is also possible for high-priority exception processing to begin before low-priority exception processing is complete. For example, if a bus error occurs during trace exception processing, the bus error will be processed and handled before trace exception processing is completed. 5-42 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.5.2 Processing of Specific Exceptions Freescale Semiconductor, Inc... The following paragraphs provide details concerning sources of specific exceptions, how each arises, and how each is processed. 5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception. The reset exception has the highest priority of any exception. Reset is used for system initialization and for recovery from catastrophic failure. The reset exception aborts any processing in progress when it is recognized, and that processing cannot be recovered. Reset performs the following operations: 1. Clears T0 and T1 in the SR to disable tracing 2. Sets the S-bit in the SR to establish supervisor privilege 3. Sets the interrupt priority mask to the highest priority level (%111) 4. Initializes the VBR to zero ($00000000) 5. 6. 7. 8. Generates a vector number to reference the reset exception vector Loads the first long word of the vector into the interrupt SP Loads the second long word of the vector into the PC Fetches and initiates decode of the first instruction to be executed Figure 5-11 is a flowchart of the reset exception After initial instruction prefetches, normal program execution begins at the address in the PC. The reset exception does not save the value of either the PC or the SR. If a bus error or address error occurs during reset exception processing sequence, a double bus fault occurs, the processor halts, and the HALT signal is asserted to indicate the halted condition. Execution of the RESET instruction does not cause a reset exception nor does it affect any internal CPU register. The SIM40 registers and the MCR in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other internal peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-43 Freescale Semiconductor, Inc. ENTRY Freescale Semiconductor, Inc... 1 0 $7 $0 S T0,T1 I2:I0 VBR . FETCH VECTOR # 0 OTHERWISE SP (VECTOR # 0) BUS ERROR FETCH VECTOR # 1 OTHERWISE PC BUS ERROR (VECTOR # 1) PREFETCH 3 WORDS OTHERWISE BEGIN INSTRUCTION EXECUTION BUS ERROR/ ADDRESS ERROR (DOUBLE BUS FAULT) ASSERT HALT EXIT EXIT Figure 5-11. Reset Operation Flowchart 5-44 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.5.2.2 BUS ERROR. A bus error exception occurs when an assertion of the BERR signal is acknowledged. The BERR signal can be asserted by one of three sources: 1. External logic by assertion of the BERR input pin 2. Direct assertion of the internal BERR signal by an internal module 3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog after detecting a no-response condition Freescale Semiconductor, Inc... Bus error exception processing begins when the processor attempts to use information from an aborted bus cycle. When the aborted bus cycle is an instruction prefetch, the processor will not initiate exception processing unless the prefetched information is used. For example, if a branch instruction flushes an aborted prefetch, that word is not accessed, and no exception occurs. When the aborted bus cycle is a data access, the processor initiates exception processing immediately, except in the case of released operand writes. Released write bus errors are delayed until the next instruction boundary or until another operand access is attempted. Exception processing for bus error exceptions follows the regular sequence, but context preservation is more involved than for other exceptions because a bus exception can be initiated while an instruction is executing. Several bus error stack format organizations are utilized to provide additional information regarding the nature of the fault. First, any register altered by a faulted-instruction EA calculation is restored to its initial value. Then a special status word (SSW) is placed on the stack. The SSW contains specific information about the aborted access--size, type of access (read or write), bus cycle type, and function code. Finally, fault address, bus error exception vector number, PC value, and a copy of the SR are saved. If a bus error occurs during exception processing for a bus error, an address error, a reset, or while the processor is loading stack information during RTE execution, the processor halts. This simplifies isolation of catastrophic system failure by preventing processor interaction with stacks and memory. Only assertion of RESET can restart a halted processor. 5.5.2.3 ADDRESS ERROR. Address error exceptions occur when the processor attempts to access an instruction, word operand, or long-word operand at an odd address. The effect is much the same as an internally generated bus error. The exception processing sequence is the same as that for bus error, except that the vector number refers to the address error exception vector. Address error exception processing begins when the processor attempts to use information from the aborted bus cycle. If the aborted cycle is a data space access, exception processing begins when the processor attempts to use the data, except in the MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-45 Freescale Semiconductor, Inc. case of a released operand write. Released write exceptions are delayed until the next instruction boundary or attempted operand access. An address exception on a branch to an odd address is delayed until the PC is changed. No exception occurs if the branch is not taken. In this case, the fault address and return PC value placed in the exception stack frame are the odd address, and the current instruction PC points to the instruction that caused the exception. Freescale Semiconductor, Inc... If an address error occurs during exception processing for a bus error, another address error, or a reset, the processor halts. 5.5.2.4 INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise from either processor recognition of abnormal conditions during instruction execution or from use of specific trapping instructions. Traps are generally used to handle abnormal conditions that arise in control routines. The TRAP instruction, which always forces an exception, is useful for implementing system calls for user programs. The TRAPcc, TRAPV, CHK, and CHK2 instructions force exceptions when a program detects a run-time error. The DIVS and DIVU instructions force an exception if a division operation is attempted with a divisor of zero. Exception processing for traps follows the regular sequence. If tracing is enabled when an instruction that causes a trap begins execution, a trace exception will be generated by the instruction, but the trap handler routine will not be traced (the trap exception will be processed first, then the trace exception). The vector number for the TRAP instruction is internally generated--part of the number comes from the instruction itself. The trap vector number, PC value, and a copy of the SR are saved on the supervisor stack. The saved PC value is the address of the instruction that follows the instruction that generated the trap. For all instruction traps other than TRAP, a pointer to the instruction causing the trap is also saved in the fifth and sixth words of the exception stack frame. 5.5.2.5 SOFTWARE BREAKPOINTS. To support hardware emulation, the CPU32 must provide a means of inserting breakpoints into target code and of announcing when a breakpoint is reached. The MC68000 and MC68008 can detect an illegal instruction inserted at a breakpoint when the processor fetches from the illegal instruction exception vector location. Since the VBR on the CPU32 allows relocation of exception vectors, the exception vector address is not a reliable indication of a breakpoint. CPU32 breakpoint support is provided by extending the function of a set of illegal instructions ($4848-$484F). When a breakpoint instruction is executed, the CPU32 performs a read from CPU space $0, at a location corresponding to the breakpoint number. If this bus cycle is terminated by BERR, the processor performs illegal instruction exception processing. If the bus cycle is terminated by DSACK, the processor uses the data returned to replace the breakpoint in the instruction pipeline and begins execution of that instruction. See Section 3 Bus Operation for a description of CPU space operations. 5-46 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.5.2.6 HARDWARE BREAKPOINTS. The CPU32 recognizes hardware breakpoint requests. Hardware breakpoint requests do not force immediate exception processing, but are left pending. An instruction breakpoint is not made pending until the instruction corresponding to the request is executed. A pending breakpoint can be acknowledged between instructions or at the end of exception processing. To acknowledge a breakpoint, the CPU performs a read from CPU space $0 at location $1E (see Section 3 Bus Operation). Freescale Semiconductor, Inc... If the bus cycle terminates normally, instruction execution continues with the next instruction, as if no breakpoint request occurred. If the bus cycle is terminated by BERR, the CPU begins exception processing. Data returned during this bus cycle is ignored. Exception processing follows the regular sequence. Vector number 12 (offset $30) is internally generated. The PC of the currently executing instruction, the PC of the next instruction to execute, and a copy of the SR are saved on the supervisor stack. 5.5.2.7 FORMAT ERROR. The processor checks certain data values for control operations. The validity of the stack format code and, in the case of a bus cycle fault format, the version number of the processor that generated the frame are checked during execution of the RTE instruction. This check ensures that the program does not make erroneous assumptions about information in the stack frame. If the format of the control data is improper, the processor generates a format error exception. This exception saves a four-word format exception frame and then vectors through vector table entry number 14. The stacked PC is the address of the RTE instruction that discovered the format error. 5.5.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS. An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal CPU32 instruction, if it is a MOVEC instruction that contains an undefined register specification field in the first extension word, or if it contains an indexed addressing mode extension word with bits 5-4 = 00 or bits 3-0 0000. If an illegal instruction is fetched during instruction execution, an illegal instruction exception occurs. This facility allows the operating system to detect program errors or to emulate instructions in software. Word patterns with bits 15-12 = 1010 (referred to as A-line opcodes) are unimplemented instructions. A separate exception vector (vector 10, offset $28) is given to unimplemented instructions to permit efficient emulation. Word patterns with bits 15-12 = 1111 (referred to as F-line opcodes) are used for M68000 family instruction set extensions. They can generate an unimplemented instruction exception caused by the first extension word of the instruction or by the addressing mode extension word. A separate F-line emulation vector (vector 11, offset $2C) is used for the exception vector. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-47 Freescale Semiconductor, Inc. All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 family members. Those customers requiring the use of an unimplemented opcode for synthesis of "custom instructions," operating system calls, etc., should use this opcode. Freescale Semiconductor, Inc... Exception processing for illegal and unimplemented instructions is similar to that for traps. The instruction is fetched and decoding is attempted. When the processor determines that execution of an illegal instruction is being attempted, exception processing begins. No registers are altered. Exception processing follows the regular sequence. The vector number is generated to refer to the illegal instruction vector or in the case of an unimplemented instruction, to the corresponding emulation vector. The illegal instruction vector number, current PC, and a copy of the SR are saved on the supervisor stack, with the saved value of the PC being the address of the illegal or unimplemented instruction. 5.5.2.9 PRIVILEGE VIOLATIONS. To provide system security, certain instructions can be executed only at the supervisor access level. An attempt to execute one of these instructions at the user level will cause an exception. The privileged exceptions are as follows: * AND Immediate to SR * EOR Immediate to SR * LPSTOP * MOVE from SR * MOVE to SR * MOVE USP * MOVEC * MOVES * OR Immediate to SR * RESET * RTE * STOP Exception processing for privilege violations is nearly identical to that for illegal instructions. The instruction is fetched and decoded. If the processor determines that a privilege violation has occurred, exception processing begins before instruction execution. Exception processing follows the regular sequence. The vector number (8) is generated to reference the privilege violation vector. Privilege violation vector offset, current PC, and SR are saved on the supervisor stack. The saved PC value is the address of the first word of the instruction causing the privilege violation. 5-48 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility to allow tracing of instruction execution. CPU32 tracing also has the ability to trap on changes in program flow. In trace mode, a trace exception is generated after each instruction executes, allowing a debugging program to monitor the execution of a program under test. The T1 and T0 bits in the supervisor portion of the SR are used to control tracing. When T1-T0 = 00, tracing is disabled, and instruction execution proceeds normally (see Table 5-18). Freescale Semiconductor, Inc... Table 5-18. Tracing Control T1 T0 0 0 Tracing Function No tracing 0 1 Trace on change of flow 1 0 Trace on instruction execution 1 1 Undefined; reserved When T1-T0 = 01 at the beginning of instruction execution, a trace exception will be generated if the PC changes sequence during execution. All branches, jumps, subroutine calls, returns, and SR manipulations can be traced in this way. No exception occurs if a branch is not taken. When T1-T0 = 10 at the beginning of instruction execution, a trace exception will be generated when execution is complete. If the instruction is not executed, either because an interrupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception is not generated. At the present time, T1-T0 = 11 is an undefined condition. It is reserved by Motorola for future use. Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction. Exception processing follows the regular sequence; tracing is disabled so that the trace exception itself is not traced. A vector number is generated to reference the trace exception vector. The address of the instruction that caused the trace exception, the trace exception vector offset, the current PC, and a copy of the SR are saved on the supervisor stack. The saved value of the PC is the address of the next instruction to be executed. A trace exception can be viewed as an extension to the function of any instruction. If a trace exception is generated by an instruction, the execution of that instruction is not complete until the trace exception processing associated with it is also complete. If an instruction is aborted by a bus error or address error exception, trace exception processing is deferred until the suspended instruction is restarted and completed normally. An RTE from a bus error or address error will not be traced because of the possibility of continuing the instruction from the fault. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-49 Freescale Semiconductor, Inc. If an instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception. If an instruction forces an exception, the forced exception is processed before the trace exception. Freescale Semiconductor, Inc... If an instruction is executed and a breakpoint is pending upon completion of the instruction, the trace exception is processed before the breakpoint. If an attempt is made to execute an illegal, unimplemented, or privileged instruction while tracing is enabled, no trace exception will occur because the instruction is not executed. This is particularly important to an emulation routine that performs an instruction function, adjusts the stacked PC to beyond the unimplemented instruction, and then returns. The SR on the stack must be checked to determine if tracing is on before the return is executed. If tracing is on, trace exception processing must be emulated so that the trace exception handler can account for the emulated instruction. Tracing also affects normal operation of the STOP and LPSTOP instructions. If either instruction begins execution with T1 set, a trace exception will be taken after the instruction loads the SR. Upon return from the trace handler routine, execution will continue with the instruction following STOP (LPSTOP), and the processor will not enter the stopped condition. 5.5.2.11 INTERRUPTS. There are seven levels of interrupt priority and 192 assignable interrupt vectors within each exception vector table. Careful use of multiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the processor. Interrupt recognition and subsequent processing are based on internal interrupt request signals ( IRQ7 - IRQ1 ) and the current priority set in SR priority mask I2-I0. Interrupt request level zero (IRQ7- IRQ1 negated) indicates that no service is requested. When an interrupt of level one through six is requested via IRQ6- IRQ1, the processor compares the request level with the interrupt mask to determine whether the interrupt should be processed. Interrupt requests are inhibited for all priority levels less than or equal to the current priority. Level seven interrupts are nonmaskable. IRQ7- IRQ1 are synchronized and debounced by input circuitry on consecutive rising edges of the processor clock. To be valid, an interrupt request must be held constant for at least two consecutive clock periods. Interrupt requests do not force immediate exception processing, but are left pending. A pending interrupt is detected between instructions or at the end of exception processing-- all interrupt requests must be held asserted until they are acknowledged by the CPU. If the priority of the interrupt is greater than the current priority level, exception processing begins. Exception processing occurs as follows. First, the processor makes an internal copy of the SR. After the copy is made, the processor state bits in the SR are changed--the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling 5-50 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. tracing. Priority level is then set to the level of the interrupt, and the processor fetches a vector number from the interrupting device (CPU space $F). The fetch bus cycle is classified as an interrupt acknowledge, and the encoded level number of the interrupt is placed on the address bus. If an interrupting device requests automatic vectoring, the processor generates a vector number (25 to 31) determined by the interrupt level number. Freescale Semiconductor, Inc... If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is taken to be spurious, and the spurious interrupt vector number (24) is generated. The exception vector number, PC, and SR are saved on the supervisor stack. The saved value of the PC is the address of the instruction that would have executed if the interrupt had not occurred. Priority level 7 interrupt is a special case. Level 7 interrupts are nonmaskable interrupts (NMI). Level 7 requests are transition sensitive to eliminate redundant servicing and resultant stack overflow. Transition sensitive means that the level 7 input must change state before the CPU will detect an interrupt. An NMI is generated each time the interrupt request level changes to level 7 (regardless of priority mask value), and each time the priority mask changes from 7 to a lower number while the request level remains at 7. Many M68000 peripherals provide for programmable interrupt vector numbers to be used in the system interrupt request/acknowledge mechanism. If the vector number is not initialized after reset and if the peripheral must acknowledge an interrupt request, the peripheral should return the uninitialized interrupt vector number (15). See Section 3 Bus Operation for detailed information on interrupt acknowledge cycles. 5.5.2.12 RETURN FROM EXCEPTION. When exception stacking operations for all pending exceptions are complete, the processor begins execution of the handler for the last exception processed. After the exception handler has executed, the processor must restore the system context in existence prior to the exception. The RTE instruction is designed to accomplish this task. When RTE is executed, the processor examines the stack frame on top of the supervisor stack to determine if it is valid and determines what type of context restoration must be performed. See 5.5.4 CPU32 Stack Frames for a description of stack frames. For a normal four-word frame, the processor updates the SR and PC with data pulled from the stack, increments the SSP by 8, and resumes normal instruction execution. For a sixword frame, the SR and PC are updated from the stack, the active SSP is incremented by 12, and normal instruction execution resumes. For a bus fault frame, the format value on the stack is first checked for validity. In addition, the version number on the stack must match the version number of the processor that is MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-51 Freescale Semiconductor, Inc. attempting to read the stack frame. The version number is located in the most significant byte (bits 15-8) of the internal register word at location SP + $14 in the stack frame. The validity check ensures that stack frame data will be properly interpreted in multiprocessor systems. Freescale Semiconductor, Inc... If a frame is invalid, a format error exception is taken. If it is inaccessible, a bus error exception is taken. Otherwise, the processor reads the entire frame into the proper internal registers, de-allocates the stack (12 words), and resumes normal processing. Bus error frames for faults during exception processing require the RTE instruction to rewrite the faulted stack frame. If an error occurs during any of the bus cycles required by rewrite, the processor halts. If a format error occurs during RTE execution, the processor creates a normal four-word fault stack frame below the frame that it was attempting to use. If a bus error occurs, a bus-error stack frame will be created. The faulty stack frame remains intact, so that it may be examined and repaired by an exception handler or used by a different type of processor (e.g., MC68010, MC68020, or future M68000 processor) in a multiprocessor system. 5.5.3 Fault Recovery There are four phases of recovery from a fault: recognizing the fault, saving the processor state, repairing the fault (if possible), and restoring the processor state. Saving and restoring the processor state are described in the following paragraphs. The stack contents are identified by the special status word (SSW). In addition to identifying the fault type represented by the stack frame, the SSW contains the internal processor state corresponding to the fault. 15 14 13 12 11 10 9 8 7 6 5 TP MV 0 TR B1 B0 RR RM IN RW LG 4 3 SIZ 2 1 0 FUNC TP--BERR frame type MV--MOVEM in progress TR--Trace pending B1--Breakpoint channel 1 pending B0--Breakpoint channel 0 pending RR--Rerun write cycle after RTE RM--Faulted cycle was read-modify-write IN--Instruction/other RW--Read/write of faulted bus cycle LG--Original operand size was long word SIZ--Remaining size of faulted bus cycle FUNC--Function code of faulted bus cycle 5-52 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The TP field defines the class of the faulted bus operation. Two bus error exception frame types are defined. One is for faults on prefetch and operand accesses, and the other is for faults during exception frame stacking: 0 = Operand or prefetch bus fault 1 = Exception processing bus fault Freescale Semiconductor, Inc... MV is set when the operand transfer portion of the MOVEM instruction is in progress at the time of a bus fault. If a prefetch bus fault occurs while prefetching the MOVEM opcode and extension word, both the MV and IN bits will be set. 0 = MOVEM was not in progress when fault occurred 1 = MOVEM was in progress when fault occurred TR indicates that a trace exception was pending when a bus error exception was processed. The instruction that generated the trace will not be restarted upon return from the exception handler. This includes MOVEM and released write bus errors indicated by the assertion of either MV or RR in the SSW. 0 = Trace not pending 1 = Trace pending B1 indicates that a breakpoint exception was pending on channel 1 (external breakpoint source) when a bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception. 0 = Breakpoint not pending 1 = Breakpoint pending B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint source) when the bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception. 0 = Breakpoint not pending 1 = Breakpoint pending RR will be set if the faulted bus cycle was a released write. A released write is one that is overlapped. If the write is completed (rerun) in the exception handler, the RR bit should be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set upon return from the exception handler. 0 = Faulted cycle was read, RMW, or unreleased write 1 = Faulted cycle was a released write Faulted RMW bus cycles set the RM bit. RM is ignored during unstacking. 0 = Faulted cycle was non-RMW cycle 1 = Faulted cycle was either the read or write of an RMW cycle Instruction prefetch faults are distinguished from operand (both read and write) faults by the IN bit. If IN is cleared, the error was on an operand cycle; if IN is set, the error was on an instruction prefetch. IN is ignored during unstacking. 0 = Operand 1 = Prefetch MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-53 Freescale Semiconductor, Inc. Read and write bus cycles are distinguished by the RW bit. Read bus cycles will set this bit, and write bus cycles will clear it. RW is reloaded into the bus controller if the RR bit is set during unstacking. 0 = Faulted cycle was an operand write 1 = Faulted cycle was a prefetch or operand read Freescale Semiconductor, Inc... The LG bit indicates an original operand size of long word. LG is cleared if the original operand was a byte or word--SIZ will indicate original (and remaining) size. LG is set if the original was a long word--SIZ will indicate the remaining size at the time of fault. LG is ignored during unstacking. 0 = Original operand size was byte or word 1 = Original operand size was long word The SSW SIZ field shows operand size remaining when a fault was detected. This field does not indicate the initial size of the operand, nor does it necessarily indicate the proper status of a dynamically sized bus cycle. Dynamic sizing occurs on the external bus and is transparent to the CPU. Byte size is shown only when the original operand was a byte. The field is reloaded into the bus controller if the RR bit is set during unstacking. The SIZ field is encoded as follows: 00--Long word 01--Byte 10--Word 11--Unused, reserved The function code for the faulted cycle is stacked in the FUNC field of the SSW, which is a copy of FC2-FC0 for the faulted bus cycle. This field is reloaded into the bus controller if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored during unstacking. Further discussion of the SSW is included in 5.5.3.1 Types of Faults. 5.5.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that faults on some bus cycles be treated differently than faults on other bus cycles. The CPU32 defines four fault types: released write faults, faults during exception processing, faults during MOVEM operand transfer, and faults on any other bus cycle. 5.5.3.1.1 Type I--Released Write Faults. CPU32 instruction pipelining can cause a final instruction write to overlap the execution of a following instruction. A write that is overlapped is called a released write. A released write fault occurs when a bus error or some other fault occurs on the released write. Released write faults are taken at the next instruction boundary. The stacked PC is that of the next unexecuted instruction. If a subsequent instruction attempts an operand access while a released write fault is pending, the instruction is aborted and the write fault is acknowledged. This action prevents stale data from being used by the instruction. 5-54 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The SSW for a released write fault contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 0 0 0 TR B1 B0 1 0 0 0 LG 4 3 2 SIZ 0 FUNC Freescale Semiconductor, Inc... TR, B1, and B0 are set if the corresponding exception is pending when the bus error exception is taken. Status regarding the faulted bus cycle is reflected in the LG, SIZ, and FUNC fields. The remainder of the stack contains the PC of the next unexecuted instruction, the current SR, the address of the faulted memory location, and the contents of the data buffer that was to be written to memory. This data is written on the stack in the format depicted in Figure 5-15. When a released write fault exception handler executes, the machine will complete the faulted write and then continue executing instructions wherever the PC indicates. 5.5.3.1.2 Type II--Prefetch, Operand, RMW, and MOVEP Faults. The majority of bus error exceptions are included in this category--all instruction prefetches, all operand reads, all RMW cycles, and all operand accesses resulting from execution of MOVEP (except the last write of a MOVEP Rn,ea or the last write of MOVEM, which are type I faults). The TAS, MOVEP, and MOVEM instructions account for all operand writes not considered released. All type II faults cause an immediate exception that aborts the current instruction. Any registers that were altered as the result of an EA calculation (i.e., postincrement or predecrement) are restored prior to processing the bus cycle fault. The SSW for faults in this category contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0 B1 B0 0 RM IN RW LG 4 3 SIZ 2 0 FUNC The trace pending bit is always cleared, since the instruction will be restarted upon return from the handler. Saving a pending exception on the stack causes a trace exception to be taken prior to restarting the instruction. If the exception handler does not alter the stacked SR trace bits, the trace is requeued when the instruction is started. The breakpoint pending bits are stacked in the SSW, even though the instruction is restarted upon return from the handler. This avoids problems with bus state analyzer equipment that has been programmed to breakpoint only the first access to a specific location or to count accesses to that location. If this response is not desired, the exception handler can clear the bits before return. The RM, IN, RW, LG, FUNC, and SIZ fields all reflect the type of bus cycle that caused the fault. If the bus cycle was an RMW, the RM bit will be set, and the RW bit will show whether the fault was on a read or write. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-55 Freescale Semiconductor, Inc. 5.5.3.1.3 Type III--Faults During MOVEM Operand Transfer. Bus faults that occur as a result of MOVEM operand transfer are classified as type III faults. MOVEM instruction prefetch faults are type II faults. Type III faults cause an immediate exception that aborts the current instruction. None of the registers altered during execution of the faulted instruction are restored prior to execution of the fault handler. This includes any register predecremented as a result of the effective address calculation or any register overwritten during instruction execution. Since postincremented registers are not updated until the end of an instruction, the register retains its pre-instruction value unless overwritten by operand movement. Freescale Semiconductor, Inc... The SSW for faults in this category contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 0 1 0 TR B1 B0 RR 0 IN RW LG 4 3 2 SIZ 0 FUNC MV is set, indicating that MOVEM should be continued from the point where the fault occurred upon return from the exception handler. TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception is taken. IN is set if a bus fault occurs while prefetching an opcode or an extension word during instruction restart. RW, LG, SIZ, and FUNC all reflect the type of bus cycle that caused the fault. All write faults have the RR bit set to indicate that the write should be rerun upon return from the exception handler. The remainder of the stack frame contains sufficient information to continue MOVEM with operand transfer following a faulted transfer. The address of the next operand to be transferred, incremented or decremented by operand size, is stored in the faulted address location ($08). The stacked transfer counter is set to 16 minus the number of transfers attempted (including the faulted cycle). Refer to Figure 5-12 for the stacking format. 5.5.3.1.4 Type IV--Faults During Exception Processing. The fourth type of fault occurs during exception processing. If this exception is a second address or bus error, the machine halts in the double bus fault condition. However, if the exception is one that causes a four- or six-word stack frame to be written, a bus cycle fault frame is written below the faulted exception stack frame. The SSW for a fault within an exception contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 1 0 0 TR B1 B0 0 0 0 1 LG 4 3 SIZ 2 0 FUNC TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception is taken. The contents of the faulted exception stack frame are included in the bus fault stack frame. The pre-exception SR and the format/vector word of the faulted frame are stacked. The type of exception can be determined from the format/vector word. If the faulted exception stack frame contains six words, the PC of the instruction that caused the initial 5-56 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. exception is also stacked. This data is placed on the stack in the format shown in Figure 5-13. The return address from the initial exception is stacked for RTE . 5.5.3.2 CORRECTING A FAULT. There are two ways to complete a faulted released write bus cycle. The first is to use a software handler. The second is to rerun the bus cycle via RTE. Type II fault handlers must terminate with RTE, but specific requirements must also be met before an instruction is restarted. Freescale Semiconductor, Inc... There are three varieties of type III operand fault recovery. The first is completion of an instruction in software. The second is conversion to type II with restart via RTE. The third is continuation from the fault via RTE. 5.5.3.2.1 Type I--Completing Released Writes via Software. To complete a bus cycle in software, a handler must first read the SSW function code field to determine the appropriate address space, access the fault address pointer on the stack, and then transfer data from the stacked image of the output buffer to the fault address. Because the CPU32 has a 16-bit internal data bus, long operands require two bus accesses. A fault during the second access of a long operand causes the LG bit in the SSW to be set. The SIZ field indicates remaining operand size. If operand coherency is important, the complete operand must be rewritten. After a long operand is rewritten, the RR bit must be cleared. Failure to clear the RR bit can cause the RTE instruction to rerun the bus cycle. Following rewrite, it is not necessary to adjust the PC (or other stack contents) before executing RTE. 5.5.3.2.2 Type I--Completing Released Writes via RTE. An exception handler can use the RTE instruction to complete a faulted bus cycle. When RTE executes, the fault address, data output buffer, PC, and SR are restored from the stack. Any pending breakpoint or trace exceptions, as indicated by TR, B1, and B0 in the stacked SSW, are requeued during SSW restoration. The RR bit in the SSW is checked during the unstacking operation; if it is set, the RW, FUNC, and SIZ fields are restored and the released write cycle is rerun. To maintain long-word operand coherence, stack contents must be adjusted prior to RTE execution. The fault address must be decremented by 2 if LG is set and SIZ indicates a remaining byte or word. SIZ must be set to long. All other fields should be left unchanged. The bus controller uses the modified fault address and SIZ field to rerun the complete released write cycle. Manipulating the stacked SSW can cause unpredictable results because RTE checks only the RR bit to determine if a bus cycle must be rerun. Inadvertent alteration of the control bits could cause the bus cycle to be a read instead of a write or could cause access to a different address space than the original bus cycle. If the rerun bus cycle is a read, returned data will be ignored. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-57 Freescale Semiconductor, Inc. 5.5.3.2.3 Type II--Correcting Faults via RTE. Instructions aborted because of a type II fault are restarted upon return from the exception handler. A fault handler must establish safe restart conditions. If a fault is caused by a nonresident page in a demand-paged virtual memory configuration, the fault address must be read from the stack, and the appropriate page retrieved. An RTE instruction terminates the exception handler. After unstacking the machine state, the instruction is refetched and restarted. 5.5.3.2.4 Type III--Correcting Faults via Software. Sufficient information is contained in the stack frame to complete MOVEM in software. After the cause of the fault is corrected, the faulted bus cycle must be rerun. Perform the following procedures to complete an instruction through software: Freescale Semiconductor, Inc... A. Setup for Rerun Read the MOVEM opcode and extension from locations pointed to by stackframe PC and PC + 2. The EA need not be recalculated since the next operand address is saved in the stack frame. However, the opcode EA field must be examined to determine how to update the address register and PC when the instruction is complete. Adjust the mask to account for operands already transferred. Subtract the stacked operand transfer count from 16 to obtain the number of operands transferred. Scan the mask using this count value. Each time a set bit is found, clear it and decrement the counter. When the count is zero, the mask is ready for use. Adjust the operand address. If the predecrement addressing mode is in effect, subtract the operand size from the stacked value; otherwise, add the operand size to the stacked value. B. Rerun Instruction Scan the mask for set bits. Read/write the selected register from/to the operand address as each bit is found. As each operand is transferred, clear the mask bit and increment (decrement) the operand address. When all bits in the mask are cleared, all operands have been transferred. If the addressing mode is predecrement or postincrement, update the register to complete the execution of the instruction. If TR is set in the stacked SSW, create a six-word stack frame and execute the trace handler. If either B1 or B0 is set in the SSW, create another six-word stack frame and execute the hardware breakpoint handler. De-allocate the stack and return control to the faulted program. 5.5.3.2.5 Type III--Correcting Faults by Conversion and Restart. In some situations it may be necessary to rerun all the operand transfers for a faulted instruction rather than continue from a faulted operand. Clearing the MV bit in the stacked SSW converts a type III fault into a type II fault. Consequently, MOVEM, like all other type II 5-58 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. exceptions, will be restarted upon return from the exception handler. When a fault occurs after an operand has transferred, that transfer is not "undone". However, these memory locations are accessed a second time when the instruction is restarted. If a register used in an EA calculation is overwritten before a fault occurs, an incorrect EA is calculated upon instruction restart. 5.5.3.2.6 Type III--Correcting Faults via RTE. The preferred method of MOVEM bus fault recovery is to correct the cause of the fault and then execute an RTE instruction without altering the stack contents. Freescale Semiconductor, Inc... The RTE recognizes that MOVEM was in progress when a fault occurred, restores the appropriate machine state, refetches the instruction, repeats the faulted transfer, and continues the instruction. MOVEM is the only instruction continued upon return from an exception handler. Although the instruction is refetched, the EA is not recalculated, and the mask is rescanned the same number of times as before the fault; modifying the code prior to RTE can cause unexpected results. 5.5.3.2.7 Type IV--Correcting Faults via Software. Bus error exceptions can occur during exception processing while the processor is fetching an exception vector or while it is stacking. The same stack frame and SSW are used in both cases, but each has a distinct fault address. The stacked faulted exception format/vector word identifies the type of faulted exception and the contents of the remainder of the frame. A fault address corresponding to the vector specified in the stacked format/vector word indicates that the processor could not obtain the address of the exception handler. A bus error exception handler should execute RTE after correcting a fault. RTE restores the internal machine state, fetches the address of the original exception handler, recreates the original exception stack frame, and resumes execution at the exception handler address. If the fault is intractable, the exception handler should rewrite the faulted exception stack frame at SP + $14 + $06 and then jump directly to the original exception handler. The stack frame can be generated from the information in the bus error frame: the preexception SR (SP + $0C), the format/vector word (SP + $0E), and, if the frame being written is a six-word frame, the PC of the instruction causing the exception (SP + $10). The return PC value is available at SP + $02. A stacked fault address equal to the current SP may indicate that, although the first exception received a bus error while stacking, the bus error exception stacking successfully completed. This occurrence is extremely improbable, but the CPU32 supports recovery from it. Once the exception handler determines that the fault has been corrected, recovery can proceed as described previously. If the fault cannot be corrected, move the supervisor stack to another area of memory, copy all valid stack frames to the new stack, create a faulted exception frame on top of the stack, and resume execution at the exception handler address. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-59 Freescale Semiconductor, Inc. 5.5.4 CPU32 Stack Frames The CPU32 generates three different stack frames: four-word frames, six-word frames, and twelve-word bus error frames. 5.5.4.1 FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation exceptions. Depending on the exception type, the PC value is either the address of the next instruction to be executed or the address of the instruction that caused the exception (see Figure 5-12). Freescale Semiconductor, Inc... 15 0 SP STATUS REGISTER +$02 PROGRAM COUNTER HIGH PROGRAM COUNTER LOW +$06 0 0 0 0 VECTOR OFFSET Figure 5-12. Format $0--Four-Word Stack Frame 5.5.4.2 SIX-WORD STACK FRAME. This stack frame (see Figure 5-13) is created by instruction-related traps, which include CHK, CHK2, TRAPcc, TRAPV, and divide-by-zero, and by trace exceptions. The faulted instruction PC value is the address of the instruction that caused the exception. The next PC value (the address to which RTE returns) is the address of the next instruction to be executed. 15 0 SP STATUS REGISTER +$02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW +$06 +$08 0 0 1 0 VECTOR OFFSET FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW Figure 5-13. Format $2--Six-Word Stack Frame Hardware breakpoints also utilize this format. The faulted instruction PC value is the address of the instruction executing when the breakpoint was sensed. Usually this is the address of the instruction that caused the breakpoint, but, because released writes can overlap following instructions, the faulted instruction PC may point to an instruction following the instruction that caused the breakpoint. The address to which RTE returns is the address of the next instruction to be executed. 5.5.4.3 BUS ERROR STACK FRAME. This stack frame is created when a bus cycle fault is detected. The CPU32 bus error stack frame differs significantly from the equivalent stack frames of other M68000 Family members. The only internal machine state required in the CPU32 stack frame is the bus controller state at the time of the error and a single register. 5-60 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Bus operation in progress at the time of a fault is conveyed by the SSW. 15 14 13 12 11 10 9 8 7 6 5 4 TP MV 0 TR B1 B0 RR RM IN RW LG 3 SIZ 2 1 0 FUNC The bus error stack frame is 12 words in length. There are three variations of the frame, each distinguished by different values in the SSW TP and MV fields. An internal transfer count register appears at location SP + $14 in all bus error stack frames. The register contains an 8-bit microcode revision number, and, for type III faults, an 8-bit transfer count. Register format is shown in Figure 5-14. Freescale Semiconductor, Inc... 15 8 7 MICROCODE REVISION NUMBER 0 TRANSFER COUNT Figure 5-14. Internal Transfer Count Register The microcode revision number is checked before a bus error stack frame is restored via RTE. In a multiprocessor system, this check ensures that a processor using stacked information is at the same revision level as the processor that created it. The transfer count is ignored unless the MV bit in the stacked SSW is set. If the MV bit is set, the least significant byte of the internal register is reloaded into the MOVEM transfer counter during RTE execution. For faults occurring during normal instruction execution (both prefetches and non-MOVEM operand accesses) SSW TP, MV = 00. Stack frame format is shown in Figure 5-15. Faults that occur during the operand portion of the MOVEM instruction are identified by SSW TP, MV = 01. Stack frame format is shown in Figure 5-16. When a bus error occurs during exception processing, SSW TP, MV = 10. The frame shown in Figure 5-17 is written below the faulting frame. Stacking begins at the address pointed to by SP - 6 (SP value is the value before initial stacking on the faulted frame). The frame can have either four or six words, depending on the type of error. Four-word stack frames do not include the faulted instruction PC (the internal transfer count register is located at SP + $10 and the SSW is located at SP + $12). The fault address of a dynamically sized bus cycle is the address of the upper byte, regardless of the byte that caused the error. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-61 Freescale Semiconductor, Inc. 15 0 SP STATUS REGISTER +$02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW +$06 1 1 0 0 +$08 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C DBUF HIGH Freescale Semiconductor, Inc... DBUF LOW +$10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW +$14 +$16 INTERNAL TRANSFER COUNT REGISTER 0 0 SPECIAL STATUS WORD Figure 5-15. Format $C--BERR Stack for Prefetches and Operands 15 0 SP STATUS REGISTER +$02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW +$06 1 1 +$08 0 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C DBUF HIGH DBUF LOW +$10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW +$14 +$16 INTERNAL TRANSFER COUNT REGISTER 0 1 SPECIAL STATUS WORD Figure 5-16. Format $C--BERR Stack on MOVEM Operand 5-62 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 15 0 SP STATUS REGISTER +$02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW +$06 1 1 0 0 VECTOR OFFSET +$08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C PRE-EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT/VECTOR WORD +$10 FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY) FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY) Freescale Semiconductor, Inc... +$14 +$16 INTERNAL TRANSFER COUNT REGISTER 1 0 SPECIAL STATUS WORD Figure 5-17. Format $C--Four- and Six-Word BERR Stack 5.6 DEVELOPMENT SUPPORT All M68000 family members have the following special features that facilitate applications development. Trace on Instruction Execution--All M68000 processors include an instruction-byinstruction tracing facility to aid in program development. The MC68020, MC68030, and CPU32 can also trace those instructions that change program flow. In trace mode, an exception is generated after each instruction is executed, allowing a debugger program to monitor execution of a program under test. See 5.5.2.10 Tracing for more information. Breakpoint Instruction--An emulator can insert software breakpoints into target code to indicate when a breakpoint occurs. On the MC68010, MC68020, MC68030, and CPU32, this function is provided via illegal instructions ($4848-$484F) that serve as breakpoint instructions. See 5.5.2.5 Software Breakpoints for more information. Unimplemented Instruction Emulation--When an attempt is made to execute an illegal instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, Aline) utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software. See 5.5.2.8 Illegal or Unimplemented Instructions for more information. 5.6.1 CPU32 Integrated Development Support In addition to standard MC68000 family capabilities, the CPU32 has features to support advanced integrated system development. These features include background debug mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in a single-chip environment. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-63 Freescale Semiconductor, Inc. 5.6.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW. Microprocessor systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The BDM on the CPU32 is unique because the debugger is implemented in CPU microcode. BDM incorporates a full set of debug options--registers can be viewed and/or altered, memory can be read or written, and test features can be invoked. Freescale Semiconductor, Inc... A resident debugger simplifies implementation of an in-circuit emulator. In a common setup (see Figure 5-18), emulator hardware replaces the target system processor. A complex, expensive pod-and-cable interface provides a communication path between target system and emulator. IN-CIRCUIT EMULATOR TARGET SYSTEM TARGET MCU .. . Figure 5-18. In-Circuit Emulator Configuration By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for incircuit emulation. The processor remains in the target system (see Figure 5-19), and the interface is simplified. The BSA monitors target processor operation and the on-chip debugger controls the operating environment. Emulation is much closer to target hardware; thus, many interfacing problems (i.e., limitations on high-frequency operation, AC and DC parametric mismatches, and restrictions on cable length) are minimized. TARGET SYSTEM TARGET MCU BUS STATE ANALYZER . Figure 5-19. Bus State Analyzer Configuration 5.6.1.2 DETERMINISTIC OPCODE TRACKING OVERVIEW. CPU32 function code outputs are augmented by two supplementary signals that monitor the instruction pipeline. The IFETCH output signal identifies bus cycles in which data is loaded into the pipeline and signals pipeline flushes. The IPIPE output signal indicates when each mid-instruction pipeline advance occurs and when instruction execution begins. These signals allow a BSA to synchronize with instruction stream activity. Refer to 5.6.3 Deterministic Opcode Tracking for complete information. 5.6.1.3 ON-CHIP HARDWARE BREAKPOINT OVERVIEW. An external breakpoint input and an on-chip hardware breakpoint capability permit breakpoint trap on any 5-64 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. memory access. Off-chip address comparators will not detect breakpoints on internal accesses unless show cycles are enabled. Breakpoints on prefetched instructions, which are flushed from the pipeline before execution, are not acknowledged, but operand breakpoints are always acknowledged. Acknowledged breakpoints can initiate either exception processing or BDM. See 5.5.2.6 Hardware Breakpoints for more information. 5.6.2 Background Debug Mode Freescale Semiconductor, Inc... BDM is an alternate CPU32 operating mode. During BDM, normal instruction execution is suspended, and special microcode performs debugging functions under external control. Figure 5-20 is a BDM block diagram. BDM can be initiated in several ways--by externally generated breakpoints, by internal peripheral breakpoints, by the background instruction (BGND), or by catastrophic exception conditions. While in BDM, the CPU32 ceases to fetch instructions via the parallel bus and communicates with the development system via a dedicated, high-speed, SPI-type serial command interface. SERIAL INTERFACE IPIPE/DSO MICROCODE SEQUENCER IFETCH/DSI IRC IRB IR BERR BERR BERR BKPT BKPT BKPT BKPT/DSCLK BUS CONTROL DATA BUS BERR FREEZE . . ... EXECUTION UNIT ADDRESS BUS Figure 5-20. BDM Block Diagram 5.6.2.1 ENABLING BDM. Accidentally entering BDM in a nondevelopment environment could lock up the CPU32 since the serial command interface would probably not be available. For this reason, BDM is enabled during reset via the BKPT signal. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-65 Freescale Semiconductor, Inc. BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET. BDM remains enabled until the next system reset. A high BKPT on the trailing edge of RESET disables BDM. BKPT is relatched on each rising transition of RESET . BKPT is synchronized internally and must be held low for at least two clock cycles prior to negation of RESET. Freescale Semiconductor, Inc... BDM enable logic must be designed with special care. If hold time on BKPT (after the trailing edge of RESET) extends into the first bus cycle following reset, this bus cycle could be tagged with a breakpoint. Refer to Section 3 Bus Operation for timing information. 5.6.2.2 BDM SOURCES. When BDM is enabled, any of several sources can cause the transition from normal mode to BDM. These sources include external BKPT hardware, the BGND instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not enabled when an exception condition occurs, the exception is processed normally. Table 5-19 summarizes the processing of each source for both enabled and disabled cases. As depicted in the table, the BKPT instruction never causes a transition into BDM. Table 5-19. BDM Source Summary Source BDM Enabled BDM Disabled BKPT Background Breakpoint Exception Double Bus Fault Background Halted BGND Instruction Background Illegal Instruction BKPT Instruction Opcode Substitution/ Illegal Instruction Opcode Substitution/ Illegal Instruction 5.6.2.2.1 External BKPT Signal. Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has the same timing relationship to the data strobe trailing edge as does read cycle data. There is no breakpoint acknowledge bus cycle when BDM is entered. 5.6.2.2.2 BGND Instruction. An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32 defines $4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is disabled, an illegal instruction trap is acknowledged. Illegal instruction traps are discussed in 5.5.2.8 Illegal or Unimplemented Instructions. 5.6.2.2.3 Double Bus Fault. The CPU32 normally treats a double bus fault (two bus faults in succession) as a catastrophic system error and halts. When this condition occurs during initial system debug (a fault in the reset logic), further debugging is impossible until the problem is corrected. In BDM, the fault can be temporarily bypassed so that its origin can be isolated and eliminated. 5.6.2.3 ENTERING BDM. When the processor detects a BKPT or a double bus fault or decodes a BGND instruction, it suspends instruction execution and asserts the FREEZE output. FREEZE assertion is the first indication that the processor has entered BDM. Once FREEZE has been asserted, the CPU enables the serial communication hardware and awaits a command. 5-66 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The CPU writes a unique value indicating the source of BDM transition into temporary register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP and determine the source (see Table 5-20) by issuing a read system register command (RSREG). ATEMP is used in most debugger commands for temporary storage--it is imperative that the RSREG command be the first command issued after transition into BDM. Freescale Semiconductor, Inc... Table 5-20. Polling the BDM Entry Source Source ATEMP 31-16 ATEMP 15-0 Double Bus Fault SSW* $FFFF BGND Instruction $0000 $0001 Hardware Breakpoint $0000 $0000 *SSW is described in detail in 5.5.3 Fault Recovery. A double bus fault during initial SP/PC fetch sequence is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other time will the processor write an odd value into this register. 5.6.2.4 COMMAND EXECUTION. Figure 5-21 summarizes BDM command execution. Commands consist of one 16-bit operation word and can include one or more 16-bit extension words. Each incoming word is read as it is assembled by the serial interface. The microcode routine corresponding to a command is executed as soon as the command is complete. Result operands are loaded into the output shift register to be shifted out as the next command is read. This process is repeated for each command until the CPU returns to normal operating mode. 5.6.2.5 BDM REGISTERS. BDM processing uses three special-purpose registers to track program context during development. A description of each register follows. 5.6.2.5.1 Fault Address Register (FAR). The FAR contains the address of the faulting bus cycle immediately following a bus or address error. This address remains available until overwritten by a subsequent bus cycle. Following a double bus fault, the FAR contains the address of the last bus cycle. The address of the first fault (if one occurred) is not visible to the user. 5.6.2.5.2 Return Program Counter (RPC). The RPC points to the location where fetching will commence after transition from BDM to normal mode. This register should be accessed to change the flow of a program under development. Changing the RPC to an odd value will cause an address error when normal mode prefetching begins. 5.6.2.5.3 Current Instruction Program Counter (PCC). The PCC holds a pointer to the first word of the last instruction executed prior to transition into BDM. Due to instruction pipelining, the instruction pointed to may not be the instruction which caused the transition. An example is a breakpoint on a released write. The bus cycle may overlap as many as two subsequent instructions before stalling the instruction sequencer. A BKPT asserted during this cycle will not be acknowledged until the end of the instruction MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-67 Freescale Semiconductor, Inc. executing at completion of the bus cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immediately out of reset. CPU32 ACTIVITY DEVELOPMENT SYSTEM ACTIVITY . ENTER (BDM) * ASSERT FREEZE SIGNAL * WAIT FOR COMMAND SEND INITIAL COMMAND * LOAD COMMAND REGISTER * ENABLE SHIFT CLOCK * SHIFT OUT 17 BITS * DISABLE SHIFT CLOCK Freescale Semiconductor, Inc... EXECUTE COMMAND * LOAD: NOT READY/ RESPONSE * PERFORM COMMAND * STORE RESULTS READ RESULTS/NEW COMMAND * LOAD COMMAND REGISTER * ENABLE SHIFT CLOCK * SHIFT IN/OUT 17 BITS * DISABLE SHIFT CLOCK * READ RESULT REGISTER IF RESULTS = "NOT READY" YES NO CONTINUE Figure 5-21. BDM Command Execution Flowchart 5.6.2.6 RETURNING FROM BDM. BDM is terminated when a resume execution (GO) or call user code (CALL) command is received. Both GO and CALL flush the instruction pipeline and prefetch instructions from the location pointed to by the RPC. The return PC and the memory space referred to by the SR SUPV bit reflect any changes made during BDM. FREEZE is negated prior to initiating the first prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals revert to IPIPE and IFETCH functionality. 5.6.2.7 SERIAL INTERFACE. Communication with the CPU32 during BDM occurs via a dedicated serial interface, which shares pins with other development features. The BKPT signal becomes the DSCLK; DSI is received on IFETCH , and DSO is transmitted on IPIPE. 5-68 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The serial interface uses a full-duplex synchronous protocol similar to the serial peripheral interface (SPI) protocol. The development system serves as the master of the serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the operating frequency of the target processor. Operable frequency range of the serial clock is from DC to one-half the processor system clock frequency. The serial interface operates in full-duplex mode--i.e., data is transmitted and received simultaneously by both master and slave devices. In general, data transitions occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data is transmitted MSB first and is latched on the rising edge of DSCLK. Freescale Semiconductor, Inc... The serial data word is 17 bits wide--16 data bits and a status/control (S/C) bit. 16 15 0 S/C DATA FIELD Bit 16 indicates the status of CPU-generated messages as shown in Table 5-21. Table 5-21. CPU Generated Message Encoding Encoding Data Message Type 0 xxxx Valid Data Transfer 0 FFFF Command Complete; Status OK 1 0000 Not Ready with Response; Come Again 1 0001 BERR Terminated Bus Cycle; Data Invalid 1 FFFF Illegal Command Command and data transfers initiated by the development system should clear bit 16. The current implementation ignores this bit; however, Motorola reserves the right to use this bit for future enhancements. 5.6.2.7.1 CPU Serial Logic. CPU serial logic, shown in the left-hand portion of Figure 522, consists of transmit and receive shift registers and of control logic that includes synchronization, serial clock generation circuitry, and a received bit counter. Both DSCLK and DSI are synchronized to on-chip clocks, thereby minimizing the chance of propagating metastable states into the serial state machine. Data is sampled during the high phase of CLKOUT. At the falling edge of CLKOUT, the sampled value is made available to internal logic. If there is no synchronization between CPU32 and development system hardware, the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-69 Freescale Semiconductor, Inc. CPU DEVELOPMENT SYSTEM INSTRUCTION REGISTER BUS DATA 16 16 0 . RCV DATA LATCH SERIAL IN PARALLEL OUT COMMAND LATCH DSI PARALLEL IN SERIAL OUT Freescale Semiconductor, Inc... DSO SERIAL IN PARALLEL OUT PARALLEL IN SERIAL OUT 16 STATUS RESULT LATCH EXECUTION UNIT 16 STATUS SYNCHRONIZE MICROSEQUENCER CONTROL LOGIC DSCLK DATA CONTROL LOGIC SERIAL CLOCK Figure 5-22. Debug Serial I/O Block Diagram The serial state machine begins a sequence of events based on the rising edge of the synchronized DSCLK (see Figure 5-23). Synchronized serial data is transferred to the input shift register, and the received bit counter is decremented. One-half clock period later, the output shift register is updated, bringing the next output bit to the DSO signal. DSO changes relative to the rising edge of DSCLK and does not necessarily remain stable until the falling edge of DSCLK. One clock period after the synchronized DSCLK has been seen internally, the updated counter value is checked. If the counter has reached zero, the receive data latch is updated from the input shift register. At this same time, the output shift register is reloaded with the "not ready/come again" response. Once the receive data latch has been loaded, the CPU is released to act on the new data. Response data overwrites the "not ready" response when the CPU has completed the current operation. Data written into the output shift register appears immediately on the DSO signal. In general, this action changes the state of the signal from a high ("not ready" response status bit) to a low (valid data status bit) logic level. However, this level change only occurs if the command completes successfully. Error conditions overwrite the "not ready" response with the appropriate response that also has the status bit set. 5-70 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. CLKOUT FREEZE DSCLK DSI Freescale Semiconductor, Inc... SAMPLE WINDOW INTERNAL SYNCHRONIZED DSCLK INTERNAL SYNCHRONIZED DSI DSO . CLKOUT Figure 5-23. Serial Interface Timing Diagram A user can use the state change on DSO to signal hardware that the next serial transfer may begin. A timeout of sufficient length to trap error conditions that do not change the state of DSO should also be incorporated into the design. Hardware interlocks in the CPU prevent result data from corrupting serial transfers in progress. 5.6.2.7.2 Development System Serial Logic. The development system, as the master of the serial data link, must supply the serial clock. However, normal and BDM operations could interact if the clock generator is not properly designed. Breakpoint requests are made by asserting BKPT to the low state in either of two ways. The primary method is to assert BKPT during a single bus cycle for which an exception is desired. Another method is to assert BKPT , then continue to assert it until the CPU32 responds by asserting FREEZE. This method is useful for forcing a transition into BDM when the bus is not being monitored. Each method requires a slightly different serial logic design to avoid spurious serial clocks. Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-71 Freescale Semiconductor, Inc. SHIFT_CLK FORCE_BGND BKPT_TAG BKPT . . .... .. . . . . .. . . . . FREEZE Freescale Semiconductor, Inc... Figure 5-24. BKPT Timing for Single Bus Cycle Figure 5-25 depicts the timing of the BKPT/FREEZE method. In both cases, the serial clock is left high after the final shift of each transfer. This technique eliminates the possibility of accidentally tagging the prefetch initiated at the conclusion of a BDM session. As mentioned previously, all timing within the CPU is derived from the rising edge of the clock; the falling edge is effectively ignored. SHIFT_CLK FORCE_BGND BKPT_TAG BKPT . . .... .. . . . . .. . . . .. . FREEZE Figure 5-25. BKPT Timing for Forcing BDM Figure 5-26 represents a sample circuit providing for both BKPT assertion methods. As the name implies, FORCE_BGND is used to force a transition into BDM by the assertion of BKPT. FORCE_BGND can be a short pulse or can remain asserted until FREEZE is asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT_CLK is applied. BKPT_TAG SHIFT_CLK ... BKPT/DSCLK S1 RESET FORCE_BGND Q S2 R Q Figure 5-26. BKPT/DSCLK Logic Diagram BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the first DSCLK. 5-72 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSCLK, the gated serial clock, is normally high, but it pulses low for each bit to be transferred. At the end of the seventeenth clock period, it remains high until the start of the next transmission. Clock frequency is implementation dependent and may range from DC to the maximum specified frequency. Although performance considerations might dictate a hardware implementation, software solutions can be used provided serial bus timing is maintained. 5.6.2.8 COMMAND SET. The following paragraphs describe the command set available in BDM. 5.6.2.8.1 Command Format. The following standard bit format is utilized by all BDM commands. Freescale Semiconductor, Inc... 15 10 OPERATION 9 8 0 R/W 7 6 OP SIZE 5 4 3 0 0 A/D 2 0 REGISTER EXTENSION WORD(S) Bits 15-0--Operation Field The operation field specifies the commands. This 6-bit field provides for a maximum of 64 unique commands. R/W Field The R/W field specifies the direction of operand transfer. When the bit is set, the transfer is from CPU to development system. When the bit is cleared, data is written to the CPU or to memory from the development system. Operand Size For sized operations, this field specifies the operand data size. All addresses are expressed as 32-bit absolute values. The size field is encoded as listed in Table 5-22. Table 5-22. Size Field Encoding Encoding Operand Size 00 Byte 01 Word 10 Long 11 Reserved Address/Data (A/D) Field The A/D field is used by commands that operate on address and data registers. It determines whether the register field specifies a data or address register. One indicates an address register; zero indicates a data register. For other commands, this field may be interpreted differently. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-73 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Register Field: In most commands, this field specifies the register number for operations performed on an address or data register. Extension Word(s) (as required): At this time, no command requires an extension word to specify fully the operation to be performed, but some commands require extension words for addresses or immediate data. Addresses require two extension words because only absolute long addressing is permitted. Immediate data can be either one or two words in length--byte and word data each require a single extension word, long-word data requires two words. Both operands and addresses are transferred most significant word first. 5.6.2.8.2 Command Sequence Diagram. A command sequence diagram (see Figure 527) illustrates the serial bus traffic for each command. Each bubble in the diagram represents a single 17-bit transfer across the bus. The top half in each diagram corresponds to the data transmitted by the development system to the CPU; the bottom half corresponds to the data returned by the CPU in response to the development system commands. Command and result transactions are overlapped to minimize latency. The cycle in which the command is issued contains the development system command mnemonic (in this example, read memory location). During the same cycle, the CPU responds with either the lowest order results of the previous command or with a command complete status (if no results were required). During the second cycle, the development system supplies the high-order 16 bits of the memory address. The CPU returns a "not ready" response unless the received command was decoded as unimplemented, in which case the response data is the illegal command encoding. If an illegal command response occurs, the development system should retransmit the command. NOTE The "not ready" response can be ignored unless a memory bus cycle is in progress. Otherwise, the CPU can accept a new serial transfer with eight system clock periods. In the third cycle, the development system supplies the low-order 16 bits of a memory address. The CPU always returns the "not ready" response in this cycle. At the completion of the third cycle, the CPU initiates a memory read operation. Any serial transfers that begin while the memory access is in progress return the "not ready" response. Results are returned in the two serial transfer cycles following the completion of memory access. The data transmitted to the CPU during the final transfer is the opcode for the following command. Should a memory access generate either a bus or address error, an error status is returned in place of the result data. 5-74 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. COMMANDS TRANSMITTED TO THE CPU32 COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH-ORDER 16 BITS OF MEMORY ADDRESS LOW-ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL-RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED Freescale Semiconductor, Inc... READ (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION XXX "NOT READY" NEXT COMMAND CODE XXX XXX MS RESULT NEXT CMD LS RESULT XXX BERR/AERR NEXT CMD "NOT READY" DATA UNUSED FROM THIS TRANSFER SEQUENCE TAKEN IF BUS ERROR OR ADDRESS ERROR OCCURS ON MEMORY ACCESS SEQUENCE TAKEN IF ILLEGAL COMMAND IS RECEIVED BY CPU32 RESULTS FROM PREVIOUS COMMAND HIGH- AND LOW-ORDER 16 BITS OF RESULT . . .... .. . . . . .. . . . .. .. .. . RESPONSES FROM THE CPU Figure 5-27. Command-Sequence Diagram 5.6.2.8.3 Command Set Summary. The BDM command set is summarized in Table 5-23. Subsequent paragraphs contain detailed descriptions of each command. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-75 Freescale Semiconductor, Inc. Table 5-23. BDM Command Summary Freescale Semiconductor, Inc... Command Mnemonic Description Read A/D Register Read the selected address or data register and return the results via the serial interface. RAREG/RDREG Write A/D Register WAREG/WDREG The data operand is written to the specified address or data register. Read System Register RSREG The specified system control register is read. All registers that can be read in supervisor mode can be read in BDM. Write System Register WSREG The operand data is written into the specified system control register. Read Memory Location READ Read the sized data at the memory location specified by the longword address. The SFC register determines the address space accessed. Write Memory Location WRITE Write the operand data to the memory location specified by the long-word address. The DFC register determines the address space accessed. Dump Memory Block DUMP Used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command. Fill Memory Block FILL Used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. Subsequent operands are written with the FILL command. Resume Execution GO The pipeline is flushed and refilled before resuming instruction execution at the return PC. Call User Code CALL Current PC is stacked at the location of the current SP. Instruction execution begins at user patch code. Reset Peripherals RST Asserts RESET for 512 clock cycles. The CPU is not reset by this command. Synonymous with the CPU RESET instruction. No Operation NOP NOP performs no operation and may be used as a null command. 5.6.2.8.4 Read A/D Register (RAREG/RDREG). Read the selected address or data register and return the results via the serial interface. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 1 0 0 0 0 1 1 0 0 0 A/D 2 1 0 REGISTER Command Sequence: RDREG/RAREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None 5-76 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Result Data: The contents of the selected register are returned as a long-word value. The data is returned most significant word first. 5.6.2.8.5 Write A/D Register (WAREG/WDREG). The operand (long-word) data is written to the specified address or data register. All 32 bits of the register are altered by the write. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 1 0 0 0 0 0 1 0 0 0 A/D 2 0 REGISTER Freescale Semiconductor, Inc... Command Sequence: WDREG/WAREG ??? MS DATA "NOT READY" LS DATA "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE" Operand Data: Long-word data is written into the specified address or data register. The data is supplied most significant word first. Result Data: Command complete status ($0FFFF) is returned when register write is complete. 5.6.2.8.6 Read System Register (RSREG). The specified system control register is read. All registers that can be read in supervisor mode can be read in BDM. Several internal temporary registers are also accessible. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 0 0 1 0 0 1 0 0 1 0 0 0 3 0 REGISTER Command Sequence: RSREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-77 Freescale Semiconductor, Inc. Result Data: Always returns 32 bits of data, regardless of the size of the register being read. If the register is less than 32 bits, the result is returned zero extended. Register Field: The system control register is specified by the register field (see Table 5-24). Table 5-24. Register Field for RSREG and WSREG Freescale Semiconductor, Inc... System Register Select Code Return Program Counter (RPC) 0000 Current Instruction Program Counter (PCC) 0001 Status Register (SR) 1011 User Stack Pointer (USP) 1100 Supervisor Stack Pointer (SSP) 1101 Source Function Code Register (SFC) 1110 Destination Function Code Register (DFC) 1111 Temporary Register A (ATEMP) 1000 Fault Address Register (FAR) 1001 Vector Base Register (VBR) 1010 5.6.2.8.7 Write System Register (WSREG). Operand data is written into the specified system control register. All registers that can be written in supervisor mode can be written in BDM. Several internal temporary registers are also accessible. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 0 0 1 0 0 1 0 0 1 0 0 0 3 0 REGISTER Command Sequence: WSREG ??? MS DATA "NOT READY" LS DATA "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE" Operand Data: The data to be written into the register is always supplied as a 32-bit long word. If the register is less than 32 bits, the least significant word is used. Result Data: "Command complete" status is returned when register write is complete. 5-78 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Register Field: The system control register is specified by the register field (see Table 5-24). The FAR is a read-only register--any write to it is ignored. 5.6.2.8.8 Read Memory Location (READ). Read the sized data at the memory location specified by the long-word address. Only absolute addressing is supported. The SFC register determines the address space accessed. Valid data sizes include byte, word, or long word. Freescale Semiconductor, Inc... Command Format: 15 14 13 12 11 10 9 8 7 6 0 0 0 1 1 0 0 1 OP SIZE 5 4 3 2 1 0 0 0 0 0 0 0 Command Sequence: READ (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION XXX "NOT READY" NEXT CMD RESULT XXX BERR/AERR READ (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION NEXT CMD "NOT READY" XXX "NOT READY" XXX MS RESULT NEXT CMD LS RESULT XXX BERR/AERR NEXT CMD "NOT READY" Operand Data: The single operand is the long-word address of the requested memory location. Result Data: The requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result, with the upper byte cleared. Word results return 16 bits of significant data; long-word results return 32 bits. A successful read operation returns data bit 16 cleared. If a bus or address error is encountered, the returned data is $10001. 5.6.2.8.9 Write Memory Location (WRITE). Write the operand data to the memory location specified by the long-word address. The DFC register determines the address MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-79 Freescale Semiconductor, Inc. space accessed. Only absolute addressing is supported. Valid data sizes include byte, word, and long word. Command Format: 15 14 13 12 11 10 9 8 7 6 0 0 0 1 1 0 0 0 OP SIZE 5 4 3 2 1 0 0 0 0 0 0 0 Command Sequence: Freescale Semiconductor, Inc... WRITE (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR/AERR NEXT CMD "NOT READY" WRITE (LONG) ??? MS ADDR "NOT READY" XXX "ILLEGAL" LS ADDR "NOT READY" MS DATA "NOT READY" NEXT CMD "NOT READY" LS DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" NEXT XXX CMD "CMD COMPLETE" XXX BERR/AERR NEXT CMD "NOT READY" Operand Data: Two operands are required for this instruction. The first operand is a long-word absolute address that specifies a location to which the operand data is to be written. The second operand is the data. Byte data is transmitted as a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively. Result Data: Successful write operations return a status of $0FFFF. Bus or address errors on the write cycle are indicated by the assertion of bit 16 in the status message and by a data pattern of $0001. 5.6.2.8.10 Dump Memory Block (DUMP). DUMP is used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the 5-80 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent DUMP commands use this address, increment it by the current operand size, and store the updated address back in the temporary register. NOTE Freescale Semiconductor, Inc... The DUMP command does not check for a valid address in the temporary register--DUMP is a valid command only when preceded by another DUMP or by a READ command. Otherwise, the results are undefined. The NOP command can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a DUMP command is given, allowing the operand size to be altered dynamically. Command Format: 15 14 13 12 11 10 9 8 7 0 0 0 1 1 1 0 1 OP SIZE 6 5 4 3 2 1 0 0 0 0 0 0 0 Command Sequence: DUMP (LONG) ??? READ MEMORY LOCATION XXX "NOT READY" NEXT CMD RESULT DUMP (LONG) ??? READ MEMORY LOCATION XXX BERR/AERR NEXT CMD "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD MS RESULT MOTOROLA NEXT CMR LS RESULT XXX BERR/AERR NEXT CMD "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-81 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Operand Data: None Result Data: Requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result. Word results return 16 bits of significant data; long-word results return 32 bits. Status of the read operation is returned as in the READ command: $0xxxx for success, $10001 for bus or address errors. 5.6.2.8.11 Fill Memory Block (FILL). FILL is used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. Subsequent operands are written with the FILL command. The initial address is incremented by the operand size (1, 2, or 4) and is saved in a temporary register. Subsequent FILL commands use this address, increment it by the current operand size, and store the updated address back in the temporary register. NOTE The FILL command does not check for a valid address in the temporary register--FILL is a valid command only when preceded by another FILL or by a WRITE command. Otherwise, the results are undefined. The NOP command can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a FILL command is given, allowing the operand size to be altered dynamically. Command Format: 15 14 13 12 11 10 9 8 7 0 0 0 1 1 1 0 0 OP SIZE 5-82 6 5 4 3 2 1 0 0 0 0 0 0 0 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Command Sequence: FILL (B/W) ??? WRITE MEMORY LOCATION LS DATA "NOT READY" MS DATA "NOT READY" XXX "ILLEGAL" XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" Freescale Semiconductor, Inc... XXX BERR/AERR FILL (LONG) ??? DATA "NOT READY" WRITE MEMORY LOCATION XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" XXX BERR/AERR Operand Data: A single operand is data to be written to the memory location. Byte data is transmitted as a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively. Result Data: Status is returned as in the WRITE command: $0FFFF for a successful operation and $10001 for a bus or address error during write. 5.6.2.8.12 Resume Execution (GO). The pipeline is flushed and refilled before normal instruction execution is resumed. Prefetching begins at the return PC and current privilege level. If either the PC or SR is altered during BDM, the updated value of these registers is used when prefetching commences. NOTE The processor exits BDM when a bus error or address error occurs on the first instruction prefetch from the new PC--the error is trapped as a normal mode exception. The stacked value of the current PC may not be valid in this case, depending on the state of the machine prior to entering BDM. For address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-83 Freescale Semiconductor, Inc. Command Sequence: GO ??? NORMAL MODE XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None Freescale Semiconductor, Inc... Result Data: None 5.6.2.8.13 Call User Code (CALL). This instruction provides a convenient way to patch user code. The return PC is stacked at the location pointed to by the current SP. The stacked PC serves as a return address to be restored by the RTS command that terminates the patch routine. After stacking is complete, the 32-bit operand data is loaded into the PC. The pipeline is flushed and refilled from the location pointed to by the new PC, BDM is exited, and normal mode instruction execution begins. NOTE If a bus error or address error occurs during return address stacking, the CPU returns an error status via the serial interface and remains in BDM. If a bus error or address error occurs on the first instruction prefetch from the new PC, the processor exits BDM and the error is trapped as a normal mode exception. The stacked value of the current PC may not be valid in this case, depending on the state of the machine prior to entering BDM. For address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 5-84 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Command Sequence: CALL ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" STACK RETURN PC FREEZE NEGATED PREFETCH STARTED NORMAL MODE Freescale Semiconductor, Inc... XXX BERR/AERR NEXT CMD "NOT READY" Operand Data: The 32-bit operand data is the starting location of the patch routine, which is the initial PC upon exiting BDM. Result Data: None As an example, consider the following code segment. It outputs a character from the MC68340 serial module channel A. CHKSTAT: MOVE.B BNE.B MOVE.B SRA,D0 CHKSTAT TBA,OUTPUT Move serial status to D0 Loop until condition true Transmit character MISSING: ANDI.B RTS #3,D0 Check for TxEMP flag BDM and the CALL command can be used to patch the code as follows: 1. 2. 3. 4. 5. 6. Breakpoint user program at CHKSTAT Enter BDM Execute CALL command to MISSING Exit BDM Execute MISSING code Return to user program 5.6.2.8.14 Reset Peripherals (RST). RST asserts RESET for 512 clock cycles. The CPU is not reset by this command. This command is synonymous with the CPU RESET instruction. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-85 Freescale Semiconductor, Inc. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Command Sequence: RESET ??? ASSERT RESET XXX "NOT READY" Freescale Semiconductor, Inc... NEXT CMD "CMD COMPLETE" XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None Result Data: The "command complete" response ($0FFFF) is loaded into the serial shifter after negation of RESET. 5.6.2.8.15 No Operation (NOP). NOP performs no operation and may be used as a null command where required. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Command Sequence: NOP ??? NEXT CMD "CMD COMPLETE" XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None Result Data: The "command complete" response ($0FFFF) is returned during the next shift operation. 5-86 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.6.2.8.16 Future Commands. Unassigned command opcodes are reserved by Motorola for future expansion. All unused formats within any revision level will perform a NOP and return the ILLEGAL command response. 5.6.3 Deterministic Opcode Tracking Freescale Semiconductor, Inc... The CPU32 utilizes deterministic opcode tracking to trace program execution. Two signals, IPIPE and IFETCH, provide all information required to analyze instruction pipeline operation. 5.6.3.1 INSTRUCTION FETCH (IFETCH ) . IFETCH indicates which bus cycles are accessing data to fill the instruction pipeline. IFETCH is pulse-width modulated to multiplex two indications on a single pin. Asserted for a single clock cycle, IFETCH indicates that the data from the current bus cycle is to be routed to the instruction pipeline. IFETCH held low for two clock cycles indicates that the instruction pipeline has been flushed. The data from the bus cycle is used to begin filling the empty pipeline. Both user and supervisor mode fetches are signaled by IFETCH. Proper tracking of bus cycles via IFETCH on a fast bus requires a simple state machine. On a two-clock bus, IFETCH may signal a pipeline flush with associated prefetch followed immediately by a second prefetch. That is, IFETCH remains asserted for three clocks, two clocks indicating the flush/fetch and a third clock signaling the second fetch. These two operations are easily discerned if the tracking logic samples IFETCH on the two rising edges of CLKOUT, which follow the AS ( DS during show cycles) falling edge. Three-clock and slower bus cycles allow time for negation of the signal between consecutive indications and do not experience this operation. 5.6.3.2 INSTRUCTION PIPE (IPIPE ) . The internal instruction pipeline can be modeled as a three-stage FIFO (see Figure 5-28). Stage A is an input buffer--data can be used out of stages B and C. IPIPE signals advances of instructions in the pipeline. Instruction register A (IRA) holds incoming words as they are prefetched. No decoding takes place in the buffer. Instruction register B (IRB) provides initial decoding of the opcode and decoding of extension words; it is a source of immediate data. Instruction register C (IRC) supplies residual opcode decoding during instruction execution. DATA BUS I I I R R R A B C EXTENSION WORDS OPCODES RESIDUAL . Figure 5-28. Functional Model of Instruction Pipeline MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-87 Freescale Semiconductor, Inc. Assertion of IPIPE for a single clock cycle indicates the use of data from IRB. Regardless of the presence of valid data in IRA, the contents of IRB are invalidated when IPIPE is asserted. If IRA contains valid data, the data is copied into IRB (IRA IRB), and the IRB stage is revalidated. Freescale Semiconductor, Inc... Assertion of IPIPE for two clock cycles indicates the start of a new instruction and subsequent replacement of data in IRC. This action causes a full advance of the pipeline (IRB IRC and IRA IRB). IRA is refilled during the next instruction fetch bus cycle. Data loaded into IRA propagates automatically through subsequent empty pipeline stages. Signals that show the progress of instructions through IRB and IRC are necessary to accurately monitor pipeline operation. These signals are provided by IRA and IRB validity bits. When a pipeline advance occurs, the validity bit of the stage being loaded is set, and the validity bit of the stage supplying the data is negated. Because instruction execution is not timed to bus activity, IPIPE is synchronized with the system clock, not the bus. Figure 5-29 illustrates the timing in relation to the system clock. IR IR IR IRB IR IRC IR IRB .. . IR IR IR IRC CLKOUT IPIPE EXTENSION WORD USED INSTRUCTION START EXTENSION WORD USED INSTRUCTION START Figure 5-29. Instruction Pipeline Timing Diagram IPIPE should be sampled on the falling edge of the clock. The assertion of IPIPE for a single cycle after one or more cycles of negation indicates use of the data in IRB (advance of IRA into IRB). Assertion for two clock cycles indicates that a new instruction has started (IRB IRC and IRA IRB transfers have occurred). Loading IRC always indicates that an instruction is beginning execution--the opcode is loaded into IRC by the transfer. In some cases, instructions using immediate addressing begin executing and initiate a second pipeline advance simultaneously at the same time. IPIPE will not be negated between the two indications, which implies the need for a state machine to track the state of IPIPE. The state machine can be resynchronized during periods of inactivity on the signal. 5.6.3.3 OPCODE TRACKING DURING LOOP MODE. IPIPE and IFETCH continue to work normally during loop mode. IFETCH indicates all instruction fetches up through the point that data begins recirculating within the instruction pipeline. IPIPE continues to signal the start of instructions and the use of extension words even though data is being recirculated internally. IFETCH returns to normal operation with the first fetch after exiting loop mode. 5-88 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.7 INSTRUCTION EXECUTION TIMING This section describes the instruction execution timing of the CPU32. External clock cycles are used to provide accurate execution and operation timing guidelines, but not exact timing for every possible circumstance. This approach is used because exact execution time for an instruction or operation depends on concurrence of independently scheduled resources, on memory speeds, and on other variables. Freescale Semiconductor, Inc... An assembly language programmer or compiler writer can use the information in this section to predict the performance of the CPU32. Additionally, timing for exception processing is included so that designers of multitasking or real-time systems can predict task-switch overhead, maximum interrupt latency, and similar timing parameters. Instruction timing is given in clock cycles to eliminate clock frequency dependency. 5.7.1 Resource Scheduling The CPU32 contains several independently scheduled resources. The organization of these resources within the CPU32 is shown in Figure 5-30. Some variation in instruction execution timing results from concurrent resource utilization. Because resource scheduling is not directly related to instruction boundaries, it is impossible to make an accurate prediction of the time required to complete an instruction without knowing the entire context within which the instruction is executing. 5.7.1.1 MICROSEQUENCER. The microsequencer either executes microinstructions or awaits completion of accesses necessary to continue microcode execution. The microsequencer supervises the bus controller, instruction execution, and internal processor operations such as calculation of EA and setting of condition codes. It also initiates instruction word prefetches after a change of flow and controls validation of instruction words in the instruction pipeline. 5.7.1.2 INSTRUCTION PIPELINE. The CPU32 contains a two-word instruction pipeline where instruction opcodes are decoded. Each stage of the pipeline is initially filled under microsequencer control and subsequently refilled by the prefetch controller as it empties. Stage A of the instruction pipeline is a buffer. Prefetches completed on the bus before stage B empties are temporarily stored in this buffer. Instruction words (instruction operation words and all extension words) are decoded at stage B. Residual decoding and execution occur in stage C. Each pipeline stage has an associated status bit that shows whether the word in that stage was loaded with data from a bus cycle that terminated abnormally. 5.7.1.3 BUS CONTROLLER RESOURCES. The bus controller consists of the instruction prefetch controller, the write pending buffer, and the microbus controller. These three resources transact all reads, writes, and instruction prefetches required for instruction execution. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-89 Freescale Semiconductor, Inc. The bus controller and microsequencer operate concurrently. The bus controller can perform a read or write or schedule a prefetch while the microsequencer controls EA calculation or sets condition codes. The microsequencer can also request a bus cycle that the bus controller cannot perform immediately. When this happens, the bus cycle is queued, and the bus controller runs the cycle when the current cycle is complete. INSTRUCTION PIPELINE MICROSEQUENCER AND CONTROL Freescale Semiconductor, Inc... STAGE B STAGE C CONTROL STORE CONTROL LOGIC EXECUTION UNIT PROGRAM COUNTER SECTION DATA SECTION WRITE-PENDING BUFFER DATA BUS PREFETCH CONTROLLER ADDRESS BUS MICROBUS CONTROLLER BUS CONTROL SIGNALS Figure 5-30. Block Diagram of Independent Resources 5.7.1.3.1 Prefetch Controller. The instruction prefetch controller receives an initial request from the microsequencer to initiate prefetching at a given address. Subsequent prefetches are initiated by the prefetch controller whenever a pipeline stage is invalidated, either through instruction completion or through use of extension words. Prefetch occurs as soon as the bus is free of operand accesses previously requested by the microsequencer. Additional state information permits the controller to inhibit prefetch requests when a change in instruction flow (e.g., a jump or branch instruction) is anticipated. In a typical program, 10 to 25 percent of the instructions cause a change of flow. Each time a change occurs, the instruction pipeline must be flushed and refilled from the new instruction stream. If instruction prefetches, rather than operand accesses, were given 5-90 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. priority, many instruction words would be flushed unused, and necessary operand cycles would be delayed. To maximize available bus bandwidth, the CPU32 will schedule a prefetch only when the next instruction is not a change-of-flow instruction and when there is room in the pipeline for the prefetch. Freescale Semiconductor, Inc... 5.7.1.3.2 Write Pending Buffer. The CPU32 incorporates a single-operand write pending buffer. The buffer permits the microsequencer to continue execution after a request for a write cycle is queued in the bus controller. The time needed for a write at the end of an instruction can overlap the head cycle time for the following instruction, thus reducing overall execution time. Interlocks prevent the microsequencer from overwriting the buffer. 5.7.1.3.3 Microbus Controller. The microbus controller performs bus cycles issued by the microsequencer. Operand accesses always have priority over instruction prefetches. Word and byte operands are accessed in a single CPU-initiated bus cycle, although the external bus interface may be required to initiate a second cycle when a word operand is sent to a byte-sized external port. Long operands are accessed in two bus cycles, most significant word first. The instruction pipeline is capable of recognizing instructions that cause a change of flow. It informs the bus controller when a change of flow is imminent, and the bus controller refrains from starting prefetches that would be discarded due to the change of flow. 5.7.1.4 INSTRUCTION EXECUTION OVERLAP. Overlap is the time, measured in clock cycles, that an instruction executes concurrently with the previous instruction. As shown in Figure 5-31, portions of instructions A and B execute simultaneously, reducing total execution time. Because portions of instructions B and C also overlap, overall execution time for all three instructions is also reduced. Each instruction contributes to the total overlap time. The portion of execution time at the end of instruction A that can overlap the beginning of instruction B is called the tail of instruction A. The portion of execution time at the beginning of instruction B that can overlap the end of instruction A is called the head of instruction B. The total overlap time between instructions A and B is the smaller tail of A and the head of B. INSTRUCTION A INSTRUCTION B INSTRUCTION C OVERLAP OVERLAP Figure 5-31. Simultaneous Instruction Execution MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-91 Freescale Semiconductor, Inc. The execution time attributed to instructions A, B, and C after considering the overlap is illustrated in Figure 5-32. The overlap time is attributed to the execution time of the completing instruction. The following equation shows the method for calculating the overlap time: Overlap = min (Tail N, HeadN+1 ) INSTRUCTION A INSTRUCTION B Freescale Semiconductor, Inc... INSTRUCTION C OVERLAP PERIOD OVERLAP PERIOD (ABSORBED BY INSTRUCTION A) (ABSORBED BY INSTRUCTION B) Figure 5-32. Attributed Instruction Times 5.7.1.5 EFFECTS OF WAIT STATES. The CPU32 access time for on-chip peripherals is two clocks. While two-clock external accesses are possible when the bus is operated in a synchronous mode, a typical external memory speed is three or more clocks. All instruction times listed in this section are for word access only (unless an explicit exception is given), and are based on the assumption that both instruction fetches and operand cycles are to a two-clock memory. Any time a long access is made, time for the additional bus cycle(s) must be added to the overall execution time. Wait states due to slow external memory must be added to the access time for each bus cycle. A typical application has a mixture of bus speeds--program execution from an off-chip ROM, accesses to on-chip peripherals, storage of variables in slow off-chip RAM, and accesses to external peripherals with speeds ranging from moderate to very slow. To arrive at an accurate instruction time calculation, each bus access must be individually considered. Many instructions have a head cycle count, which can overlap the cycles of an operand fetch to slower memory started by a previous instruction. In these cases, an increase in access time has no effect on the total execution time of the pair of instructions. To trace instruction execution time by monitoring the external bus, note that the order of operand accesses for a particular instruction sequence is always the same provided bus speed is unchanged and the interleaving of instruction prefetches with operands within each sequence is identical. 5.7.1.6 INSTRUCTION EXECUTION TIME CALCULATION. The overall execution time for an instruction depends on the amount of overlap with previous and subsequent instructions. To calculate an instruction time estimate, the entire code sequence must be 5-92 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. analyzed. To derive the actual instruction execution times for an instruction sequence, the instruction times listed in the tables must be adjusted to account for overlap. The formula for this calculation is as follows: C1 - min (T1 , H2 ) + C 2 - min (T2 , H3 ) + C 3 - min (T3 , H4 ) + .. .. . where: CN is the number of cycles listed for instruction N TN is the tail time for instruction N Freescale Semiconductor, Inc... HN is the head time for instruction N min (T N, HM) is the minimum of parameters T N and HM The number of cycles for the instruction (CN) can include one or two EA calculations in addition to the raw number in the cycles column. In these cases, calculate overall instruction time as if it were for multiple instructions, using the following equation: CEA - min (T EA, HOP) + C OP where: CEA is the instruction's EA time COP is the instruction's operation time TEA is the EA's tail time HOP is the instruction operation's head time min (T N, HM) is the minimum of parameters T N and HM The overall head for the instruction is the head for the EA, and the overall tail for the instruction is the tail for the operation. Therefore, the actual equation for execution time becomes: COP1 - min (TOP1 , HEA2 ) + CEA2 - min (TEA2 , HOP2 ) + C OP2 - min (TOP2 , HEA3 ) + . . . Every instruction must prefetch to replace itself in the instruction pipe. Usually, these prefetches occur during or after an instruction. A prefetch is permitted to begin in the first clock of any indexed EA mode operation. Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of an instruction provided the bus is not being used. If the bus is being used, then the prefetch occurs at the next available time when the bus would otherwise be idle. 5.7.1.7 EFFECTS OF NEGATIVE TAILS. When the CPU32 changes instruction flow, the instruction decode pipeline must begin refilling before instruction execution can resume. Refilling forces a two-clock idle period at the end of the change-of-flow instruction. This idle period can be used to prefetch an additional word on the new instruction path. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-93 Freescale Semiconductor, Inc. Because of the stipulation that each instruction must prefetch to replace itself, the concept of negative tails has been introduced to account for these free clocks on the bus. On a two-clock bus, it is not necessary to adjust instruction timing to account for the potential extra prefetch. The cycle times of the microsequencer and bus are matched, and no additional benefit or penalty is obtained. In the instruction execution time equations, a zero should be used instead of a negative number. Freescale Semiconductor, Inc... Negative tails are used to adjust for slower fetches on slower buses. Normally, increasing the length of prefetch bus cycles directly affects the cycle count and tail values found in the tables. In the following equations, negative tail values are used to negate the effects of a slower bus. The equations are generalized, however, so that they may be used on any speed bus with any tail value. NEW_TAIL = OLD_TAIL + (NEW_CLOCK - 2) IF ((NEW_CLOCK - 4) >0) THEN NEW_CYCLE = OLD_CYCLE + (NEW_CLOCK -2) + (NEW_CLOCK - 4) ELSE NEW_CYCLE = OLD_CYCLE + (NEW _CLOCK - 2) where: NEW_TAIL/NEW_CYCLE OLD_TAIL/OLD_CYCLE NEW_CLOCK is the adjusted tail/cycle at the slower speed is the value listed in the instruction timing tables is the number of clocks per cycle at the slower speed Note that many instructions listed as having negative tails are change-of-flow instructions and that the bus speed used in the calculation is that of the new instruction stream. 5.7.2 Instruction Stream Timing Examples The following programming examples provide a detailed examination of timing effects. In all examples, the memory access is from external synchronous memory, the bus is idle, and the instruction pipeline is full at the start. 5.7.2.1 TIMING EXAMPLE 1--EXECUTION OVERLAP. Figure 5-33 illustrates execution overlap caused by the bus controller's completion of bus cycles while the sequencer is calculating the next EA. One clock is saved between instructions since that is the minimum time of the individual head and tail numbers. Instructions MOVE.W ADDQ.W CLR.W 5-94 A1, (A0) + #1, (A0) $30 (A1) MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 0 1 2 4 3 5 6 7 8 CLOCK 1 PREFETCH BUS CONTROLLER WRITE FOR 1 INSTRUCTION CONTROLLER MOVE A1,(AO)+ EXECUTION TIME READ FOR 2 EA FETCH ADDQ 2 PREFETCH WRITE FOR 2 ADDQ TO <EA> MOVE.W A1,(AO)+ 3 PREFETCH EA CALC CLR 3 PREFETCH WRITE FOR 3 CLR <EA> CLR.W $30(A1) ADDQ.W #1,(AO) Freescale Semiconductor, Inc... Figure 5-33. Example 1--Instruction Stream 5.7.2.2 TIMING EXAMPLE 2--BRANCH INSTRUCTIONS. Example 2 shows what happens when a branch instruction is executed for both the taken and not-taken cases. (see Figures 5-34 and 5-35). The instruction stream is for a simple limit check with the variable already in a data register. Instructions MOVEQ CMP.L BLE.B MOVE.L 1 2 3 4 5 6 #7, D1 D1, D0 NEXT D1, (A0) 7 8 9 0 1 2 4 3 CLOCK BUS CONTROLLER 1 PREFETCH 2 PREFETCH INSTRUCTION CONTROLLER MOVEQ CMP EXECUTION TIME MOVEQ #7,D1 CMP D1,D0 OFFSET CALC PREFETCH PREFETCH TAKEN TAKEN PREFETCH TAKEN WRITE FOR 3 NEXT INST. BLE.B NOT TAKEN Figure 5-34. Example 2--Branch Taken MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-95 Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 0 1 2 4 3 CLOCK BUS CONTROLLER 1 PREFETCH 2 PREFETCH INSTRUCTION CONTROLLER MOVEQ CMP EXECUTION TIME MOVEQ #7,D1 CMP D1,D0 OFFSET CALC 3 PREFETCH 4 PREFETCH NOT TAKEN MOVE TO (A0) BLE.B NOT TAKEN WRITE FOR 4 WRITE FOR 4 MOVE.L D1,(AO) Freescale Semiconductor, Inc... Figure 5-35. Example 2--Branch Not Taken 5.7.2.3 TIMING EXAMPLE 3--NEGATIVE TAILS. This example (see Figure 5-36) shows how to use negative tail figures for branches and other change-of-flow instructions. In this example, bus speed is assumed to be four clocks per access. Instruction three is at the branch destination. Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum branch instruction time to be three bus cycles. The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus; on a slower bus, there is no extra time for the third word. Instructions MOVEQ BRA.W MOVE.L 1 2 3 4 5 6 7 #7, D1 FARAWAY D1, D0 8 9 0 1 2 3 4 5 6 7 8 9 CLOCK BUS CONTROLLER INSTRUCTION CONTROLLER EXECUTION TIME BRANCH OFFSET MOVEQ MOVEQ #7,D1 FETCH MOVE.L OFFSET CALC TAKEN FETCH NEXT INSTRUCTION TAKEN BRA.W FARAWAY PREFETCH MOVE TO D0 MOVE.L D1,D0 Figure 5-36. Example 3--Branch Negative Tail 5-96 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Example 3 illustrates three different aspects of instruction time calculation: 1. The branch instruction does not attempt to prefetch beyond the minimum number of words needed for itself. 2. The negative tail allows execution to begin sooner than a three-word pipeline would allow. 3. There is a one-clock delay due to late arrival of the displacement at the CPU. Only changes of flow require negative tail calculation, but the concept can be generalized to any instruction--only two words are required to be in the pipeline, but up to three words may be present. When there is an opportunity for an extra prefetch, it is made. A prefetch to replace an instruction can begin ahead of the instruction, resulting in a faster processor. Freescale Semiconductor, Inc... 5.7.3 Instruction Timing Tables The following assumptions apply to the times shown in the subsequent tables. --A 16-bit data bus is used for all memory accesses. --Memory access times are based on two clock bus cycles with no wait states. --The instruction pipeline is full at the beginning of the instruction and is refilled by the end of the instruction. Three values are listed for each instruction and addressing mode: Head: The number of cycles available at the beginning of an instruction to complete a previous instruction write or to perform a prefetch. Tail: The number of cycles an instruction uses to complete a write. Cycles: Four numbers per entry, three contained in parentheses. The outer number is the minimum number of cycles required for the instruction to complete. Numbers within the parentheses represent the number of bus accesses performed by the instruction. The first number is the number of operand read accesses performed by the instruction. The second number is the number of instruction fetches performed by the instruction, including all prefetches that keep the instruction and the instruction pipeline filled. The third number is the number of write accesses performed by the instruction. As an example, consider an ADD.L (12, A3, D7.W 4), D2 instruction. Paragraph 5.7.3.5 Arithmetic/Logic Instructions shows that the instruction has a head = 0, a tail = 0, and cycles = 2 (0/1/0). However, in indexed, address register indirect addressing mode, additional time is required to fetch the EA. Paragraph 5.7.3.1 Fetch Effective Address gives addressing mode data. For (d 8 , An, Xn.Sz Scale), head = 4, tail = 2, cycles = 8 (2/1/0). Because this example is for a long access and the fetch EA table lists data for word accesses, add two clocks to the tail and to the number of cycles ("X" in table notation) to obtain head = 4, tail = 4, cycles = 10 (2/1/0). Assuming that no trailing write exists from the previous instruction, EA calculation requires six clocks. Replacement fetch for the EA occurs during these six clocks, leaving a head of MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-97 Freescale Semiconductor, Inc. four. If there is no time in the head to perform a prefetch due to a previous trailing write, then additional time to perform the prefetches must be allotted in the middle of the instruction or after the tail. 8 (2 /1 /0) Freescale Semiconductor, Inc... TOTAL NUMBER OF CLOCKS NUMBER OF READ CYCLES NUMBER OF INSTRUCTION ACCESS CYCLES NUMBER OF WRITE CYCLES The total number of clocks for bus activity is as follows: (2 Reads x 2 Clocks/Read) + (1 Instruction Access x 2 Clocks/Access) + (0 Writes x 2 Clocks/Write) = 6 Clocks of Bus Activity The number of internal clocks (not overlapped by bus activity) is as follows: 10 Clocks Total - 6 Clocks Bus Activity = 4 Internal Clocks Memory read requires two bus cycles at two clocks each. This read time, implied in the tail figure for the EA, cannot be overlapped with the instruction because the instruction has a head of zero. An additional two clocks are required for the ADD instruction itself. The total is 6 + 4 + 2 = 12 clocks. If bus cycles take more time (i.e., the memory is off-chip), add an appropriate number of clocks to each memory access. The instruction sequence MOVE.L D0, (A0) followed by LSL.L #7, D2 provides an example of overlapped execution. The MOVE instruction has a head of zero and a tail of four because it is a long write. The LSL instruction has a head of four. The trailing write from the MOVE overlaps the LSL head completely. Thus, the two-instruction sequence has a head of zero and a tail of zero, and a total execution of 8 rather than 12 clocks. General observations regarding calculation of execution time are as follows: * Any time the number of bus cycles is listed as "X", substitute a value of one for byte and word cycles and a value of two for long cycles. For long bus cycles, usually add a value of two to the tail. * The time calculated for an instruction on a three-clock (or longer) bus is usually longer than the actual execution time. All times shown are for two-clock bus cycles. * If the previous instruction has a negative tail, then a prefetch for the current instruction can begin during the execution of that previous instruction. * Certain instructions requiring an immediate extension word (immediate word EA, absolute word EA, address register indirect with displacement EA, conditional branches with word offsets, bit operations, LPSTOP, TBL, MOVEM, MOVEC, MOVES, MOVEP, MUL.L, DIV.L, CHK2, CMP2, and DBcc) are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle. This does not apply to long offsets or displacements. 5-98 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.7.3.1 FETCH EFFECTIVE ADDRESS. The fetch EA table indicates the number of clock periods needed for the processor to calculate and fetch the specified EA. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... Instruction Head Tail Cycles Notes Dn - - 0(0/0/0) - An - - 0(0/0/0) - (An) 1 1 3(X/0/0) 1 (An) + 1 1 3(X/0/0) 1 -(An) 2 2 4(X/0/0) 1 (d 16 ,An) or (d16 ,PC) 1 3 5(X/1/0) 1,3 (xxx).W 1 3 5(X/1/0) 1 (xxx).L 1 5 7(X/2/0) 1 #data.B 1 1 3(0/1/0) 1 #data.W 1 1 3(0/1/0) 1 #data.L 1 3 5(0/2/0) 1 (d 8,An,Xn.Sz x Sc) or (d8,PC,Xn.Sz x Sc) 4 2 8(X/1/0) 1,2,3,4 (0) (All Suppressed) 2 2 6(X/1/0) 1,4 (d 16 ) 1 3 7(X/2/0) 1,4 (d 32 ) 1 5 9(X/3/0) 1,4 (An) 1 1 5(X/1/0) 1,2,4 (Xm.Sz x Sc) 4 2 8(X/1/0) 1,2,4 (An,Xm.Sz x Sc) 4 2 8(X/1/0) 1,2,3,4 (d 16 ,An) or (d16 ,PC) 1 3 7(X/2/0) 1,3,4 (d 32 ,An) or (d32 ,PC) 1 5 9(X/3/0) 1,3,4 (d 16 ,An,Xm) or (d16 ,PC,Xm) 2 2 8(X/2/0) 1,3,4 (d 32 ,An,Xm) or (d32 ,PC,Xm) 1 3 9(X/3/0) 1,3,4 (d 16 ,An,Xm.Sz x Sc) or (d16 ,PC,Xm.Sz x Sc) 2 2 8(X/2/0) 1,2,3,4 (d 32 ,An,Xm.Sz x Sc) or (d32 ,PC,Xm.Sz x Sc) 1 3 9(X/3/0) 1,2,3,4 X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. NOTES: 1. The read of the EA and replacement fetches overlap the head of the operation by the amount specified in the tail. 2. Size and scale of the index register do not affect execution time. 3. The PC may be substituted for the base address register An. 4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-99 Freescale Semiconductor, Inc. 5.7.3.2 CALCULATE EFFECTIVE ADDRESS. The calculate EA table indicates the number of clock periods needed for the processor to calculate a specified EA. The timing is equivalent to fetch EA except there is no read cycle. The tail and cycle time are reduced by the amount of time the read would occupy. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Instruction Freescale Semiconductor, Inc... Head Tail Cycles Notes Dn - - 0(0/0/0) - An - - 0(0/0/0) - (An) 1 0 2(0/0/0) - (An) + 1 0 2(0/0/0) - -(An) 2 0 2(0/0/0) - (d 16 ,An) or (d16 ,PC) 1 1 3(0/1/0) 1,3 (xxx).W 1 1 3(0/1/0) 1 (xxx).L 1 3 5(0/2/0) 1 (d 8,An,Xn.Sz x Sc) or (d 8,PC,Xn.Sz x Sc) 4 0 6(0/1/0) 2,3,4 (0) (All Suppressed) 2 0 4(0/1/0) 4 (d 16 ) 1 1 5(0/2/0) 1,4 (d 32 ) 1 3 7(0/3/0) 1,4 (An) 1 0 4(0/1/0) 4 (Xm.Sz x Sc) 4 0 6(0/1/0) 2,4 (An,Xm.Sz x Sc) 4 0 6(0/1/0) 2,4 (d 16 ,An) or (d16 ,PC) 1 1 5(0/2/0) 1,3,4 (d 32 ,An) or (d32 ,PC) 1 3 7(0/3/0) 1,3,4 (d 16 ,An,Xm) or (d16 ,PC,Xm) 2 0 6(0/2/0) 3,4 (d 32 ,An,Xm) or (d32 ,PC,Xm) 1 1 7(0/3/0) 1,3,4 (d 16 ,An,Xm.Sz x Sc) or (d16 ,PC,Xm.Sz x Sc) 2 0 6(0/2/0) 2,3,4 (d 32 ,An,Xm.Sz x Sc) or (d32 ,PC,Xm.Sz x Sc) 1 1 7(0/3/0) 1,2,3,4 X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. NOTES: 1. Replacement fetches overlap the head of the operation by the amount specified in the tail. 2. Size and scale of the index register do not affect execution time. 3. The PC may be substituted for the base address register An. 4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts. 5-100 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.7.3.3 MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock periods needed for the processor to calculate the destination EA and to perform a MOVE or MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate that portion of the instruction time. Destination EAs are divided by their formats (see 5.3.4.4 Effective Address Encoding Summary). The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... When using this table, begin at the top and move downward. Use the first entry that matches both source and destination addressing modes. Head Tail Cycles MOVE Rn, Rn Instruction 0 0 2(0/1/0) MOVE FEA, Rn 0 0 2(0/1/0) MOVE Rn, (Am) 0 2 4(0/1/x) MOVE Rn, (Am) + 1 1 5(0/1/x) MOVE Rn, -(Am) 2 2 6(0/1/x) MOVE Rn, CEA 1 3 5(0/1/x) MOVE FEA, (An) 2 2 6(0/1/x) MOVE FEA, (An) + 2 2 6(0/1/x) MOVE FEA, -(An) 2 2 6(0/1/x) MOVE #, CEA 2 2 6(0/1/x) MOVE CEA, FEA 2 2 6(0/1/x) X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. = An # fetch EA time must be added for this instruction: FEA +CEA + OPER NOTE: For instructions not explicitly listed, use the MOVE CEA , FEA entry. The source EA is calculated by the calculate EA table, and the destination EA is calculated by the fetch EA table, even though the bus cycle is for the source EA. 5.7.3.4 SPECIAL-PURPOSE MOVE INSTRUCTION. The special-purpose MOVE instruction table indicates the number of clock periods needed for the processor to fetch, calculate, and perform the special-purpose MOVE operation on control registers or a specified EA. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-101 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Instruction Head Tail Cycles EXG Rn, Rm 2 0 4(0/1/0) MOVEC Cr, Rn 10 0 14(0/2/0) MOVEC Rn, Cr 12 0 14-16(0/1/0) MOVE CCR, Dn 2 0 4(0/1/0) MOVE CCR, CEA 0 2 4(0/1/1) MOVE Dn, CCR 2 0 4(0/1/0) MOVE FEA, CCR 0 0 4(0/1/0) MOVE SR, Dn 2 0 4(0/1/0) MOVE SR, CEA 0 2 4(0/1/1) MOVE Dn, SR 4 -2 10(0/3/0) MOVE FEA, SR 0 -2 10(0/3/0) MOVEM.W CEA, RL 1 0 8 + n x 4 (n + 1, 2, 0) MOVEM.W RL, CEA 1 0 8 + n x 4 (0, 2, n) MOVEM.L CEA, RL 1 0 12 + n x 4(2n + 2, 2, 0) MOVEM.L RL, CEA 1 2 10 + n x 4 (0, 2, 2n) MOVEP.W Dn, (d16 , An) 2 0 10(0/2/2) MOVEP.W (d 16 , An), Dn 1 2 11(2/2/0) MOVEP.L Dn, (d16 , An) 2 0 14(0/2/4) MOVEP.L (d 16 , An), Dn 1 2 19(4/2/0) MOVES (Save) CEA, Rn 1 1 3(0/1/0) MOVES (Op) CEA, Rn 7 1 11(X/1/0) MOVES (Save) Rn, CEA 1 1 3(0/1/0) MOVES (Op) Rn, CEA 9 2 12(0/1/X) MOVE USP, An 0 0 2(0/1/0) MOVE An, USP 0 0 2(0/1/0) SWAP Dn 4 0 6(0/1/0) X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. = Each bus cycle may take up to four clocks without increasing total execution time. Cr = Control registers USP, VBR, SFC, and DFC n = Number of registers to transfer RL = Register List < = Maximum time (certain data or mode combinations may execute faster). NOTE: The MOVES instruction has an additional save step which other instructions do not have. To calculate the total instruction time, calculate the save, the EA, and the operation execution times, and combine in the order listed, using the equations given in 5.7.1.6 Instruction Execution Time Calculation. 5.7.3.5 ARITHMETIC/LOGIC INSTRUCTIONS. The arithmetic/logic instruction table indicates the number of clock periods needed to perform the specified arithmetic/logical instruction using the specified addressing mode. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. 5-102 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Instruction Freescale Semiconductor, Inc... Head Tail Cycles ADD(A) Rn, Rm 0 0 2(0/1/0) ADD(A) FEA, Rn 0 0 2(0/1/0) ADD Dn, FEA 0 3 5(0/1/x) AND Dn, Dm 0 0 2(0/1/0) AND FEA, Dn 0 0 2(0/1/0) AND Dn, FEA 0 3 5(0/1/x) EOR Dn, Dm 0 0 2(0/1/0) EOR Dn, FEA 0 3 5(0/1/x) OR Dn, Dm 0 0 2(0/1/0) OR FEA, Dn 0 0 2(0/1/0) OR Dn, FEA 0 3 5(0/1/x) SUB(A) Rn, Rm 0 0 2(0/1/0) SUB(A) FEA, Rn 0 0 2(0/1/0) SUB Dn, FEA 0 3 5(0/1/x) CMP(A) Rn, Rm 0 0 2(0/1/0) CMP(A) FEA, Rn 0 0 2(0/1/0) CMP2 (Save) * FEA, Rn 1 1 3(0/1/0) CMP2 (Op) FEA, Rn 2 0 16-18(X/1/0) MUL(su).W FEA, Dn 0 0 26(0/1/0) MUL(su).L (Save) * FEA, Dn 1 1 3(0/1/0) MUL(su).L (Op) FEA, Dl 2 0 46-52(0/1/0) MUL(su).L (Op) FEA, Dn:Dl 2 0 46(0/1/0) DIVU.W FEA, Dn 0 0 32(0/1/0) DIVS.W FEA, Dn 0 0 42(0/1/0) DIVU.L (Save)* FEA, Dn 1 1 3(0/1/0) DIVU.L (Op) FEA, Dn 2 0 <46(0/1/0) DIVS.L (Save) * FEA, Dn 1 1 3(0/1/0) DIVS.L (Op) FEA, Dn 2 0 <62(0/1/0) TBL(su) Dn:Dm, Dp 26 0 28-30(0/2/0) TBL(su) (Save) * CEA, Dn 1 1 3(0/1/0) TBL(su) (Op) CEA, Dn 6 0 33-35(2X/1/0) TBLSN Dn:Dm, Dp 30 0 30-34(0/2/0) TBLSN (Save)* CEA, Dn 1 1 3(0/1/0) TBLSN (Op) CEA, Dn 6 0 35-39(2X/1/0) MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-103 Freescale Semiconductor, Inc. Instruction Head Tail Cycles TBLUN Dn:Dm, Dp 30 0 34-40(0/2/0) TBLUN (Save)* CEA, Dn 1 1 3(0/1/0) TBLUN (Op) CEA, Dn 6 0 39-45(2X/1/0) X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. < = Maximum time (certain data or mode combinations may execute faster). Freescale Semiconductor, Inc... su = The execution time is identical for signed or unsigned operands. *These instructions have an additional save operation that other instructions do not have. To calculate total instruction time, calculate save, ea, and operation execution times, then combine in the order shown, using equations in 5.7.1.6 Instruction Execution Time Calculations. A save operation is not run for long-word divide and multiply instructions when FEA = Dn, 5-104 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.7.3.6 IMMEDIATE ARITHMETIC/LOGIC INSTRUCTIONS. The immediate arithmetic/logic instruction table indicates the number of clock periods needed for the processor to fetch the source immediate data value and to perform the specified arithmetic/logic instruction using the specified addressing mode. Footnotes indicate when to account for the appropriate fetch effective or fetch immediate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Instruction Freescale Semiconductor, Inc... Head Tail Cycles MOVEQ #, Dn 0 0 2(0/1/0) ADDQ #, Rn 0 0 2(0/1/0) ADDQ #, FEA 0 3 5(0/1/x) SUBQ #, Rn 0 0 2(0/1/0) SUBQ #, FEA 0 3 5(0/1/x) ADDI #, Rn 0 0 2(0/1/0) ADDI #, FEA 0 3 5(0/1/x) ANDI #, Rn 0 0 2(0/1/0) ANDI #, FEA 0 3 5(0/1/x) EORI #, Rn 0 0 2(0/1/0) EORI #, FEA 0 3 5(0/1/x) ORI #, Rn 0 0 2(0/1/0) ORI #, FEA 0 3 5(0/1/x) SUBI #, Rn 0 0 2(0/1/0) SUBI #, FEA 0 3 5(0/1/x) CMPI #, Rn 0 0 2(0/1/0) CMPI #, FEA 0 3 5(0/1/x) X = There is one bus cycle for byte and word operands and two bus cycles for longword operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. = An # fetch EA time must be added for this instruction: FEA +FEA + OPER MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-105 Freescale Semiconductor, Inc. 5.7.3.7 BINARY-CODED DECIMAL AND EXTENDED INSTRUCTIONS. The BCD and extended instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... Instruction 5-106 Head Tail Cycles ABCD Dn, Dm 2 0 4(0/1/0) ABCD -(An), -(Am) 2 2 12(2/1/1) SBCD Dn, Dm 2 0 4(0/1/0) SBCD -(An), -(Am) 2 2 12(2/1/1) ADDX Dn, Dm 0 0 2(0/1/0) ADDX -(An), -(Am) 2 2 10(2/1/1) SUBX Dn, Dm 0 0 2(0/1/0) SUBX -(An), -(Am) 2 2 10(2/1/1) CMPM (An)+, (Am)+ 1 0 8(2/1/0) MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.7.3.8 SINGLE OPERAND INSTRUCTIONS. The single operand instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... Instruction Head Tail Cycles CLR Dn 0 0 2(0/1/0) CLR CEA 0 2 4(0/1/x) NEG Dn 0 0 2(0/1/0) NEG FEA 0 3 5(0/1/x) NEGX Dn 0 0 2(0/1/0) NEGX FEA 0 3 5(0/1/x) NOT Dn 0 0 2(0/1/0) NOT FEA 0 3 5(0/1/x) EXT Dn 0 0 2(0/1/0) NBCD Dn 2 0 4(0/1/0) NBCD FEA 0 2 6(0/1/1) Scc Dn 2 0 4(0/1/0) Scc CEA 2 2 6(0/1/1) TAS Dn 4 0 6(0/1/0) TAS CEA 1 0 10(0/1/1) TST FEA 0 0 2(0/1/0) X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-107 Freescale Semiconductor, Inc. 5.7.3.9 SHIFT/ROTATE INSTRUCTIONS. The shift/rotate instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate EA times. The number of bits shifted does not affect the execution time, unless noted. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... Instruction Head Tail Cycles Note -2 0 (0/1/0) 1 LSd Dn, Dm LSd #, Dm 4 0 6(0/1/0) -- LSd FEA 0 2 6(0/1/1) -- ASd Dn, Dm -2 0 (0/1/0) 1 ASd #, Dm 4 0 6(0/1/0) -- ASd FEA 0 2 6(0/1/1) -- ROd Dn, Dm -2 0 (0/1/0) 1 ROd #, Dm 4 0 6(0/1/0) -- ROd FEA 0 2 6(0/1/1) -- ROXd Dn, Dm -2 0 (0/1/0) 2 ROXd #, Dm -2 0 (0/1/0) 3 ROXd FEA 0 2 6(0/1/1) -- d = Direction (left or right) NOTES: 1. Head and cycle times can be derived from the following table or calculated as follows: Max (3 + (n/4) + mod(n,4) + mod (((n/4) + mod (n,4) + 1,2), 6) 2. Head and cycle times are calculated as follows: (count 63): max (3 + n + mod (n + 1,2), 6). 3. Head and cycle times are calculated as follows: (count 8): max (2 + n + mod (n,2), 6). Clocks 5-108 Shift Counts 6 0 1 2 3 4 5 6 8 8 7 10 11 13 14 16 17 20 10 15 18 19 21 22 24 25 28 12 23 26 27 29 30 32 33 36 14 31 34 35 37 38 40 41 44 16 39 42 43 45 46 48 49 52 18 47 50 51 53 54 56 57 60 20 55 58 59 61 62 22 63 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9 12 MOTOROLA Freescale Semiconductor, Inc. 5.7.3.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... Instruction Head Tail Cycles BCHG #, Dn 2 0 6(0/2/0) BCHG Dn, Dm 4 0 6(0/1/0) BCHG #, FEA 1 2 8(0/2/1) BCHG Dn, FEA 2 2 8(0/1/1) BCLR #, Dn 2 0 6(0/2/0) BCLR Dn, Dm 4 0 6(0/1/0) BCLR #, FEA 1 2 8(0/2/1) BCLR Dn, FEA 2 2 8(0/1/1) BSET #, Dn 2 0 6(0/2/0) BSET Dn, Dm 4 0 6(0/1/0) BSET #, FEA 1 2 8(0/2/1) BSET Dn, FEA 2 2 8(0/1/1) BTST #, Dn 2 0 4(0/2/0) BTST Dn, Dm 2 0 4(0/1/0) BTST #, FEA 1 0 4(0/2/0) BTST Dn, FEA 2 0 8(0/1/0) = An # fetch EA time must be added for this instruction: FEA + FEA + OPER MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-109 Freescale Semiconductor, Inc. 5.7.3.11 CONDITIONAL BRANCH INSTRUCTIONS. The conditional branch instruction table indicates the number of clock periods needed for the processor to perform the specified branch on the given branch size, with complete execution times given. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... Instruction Head Tail Cycles Bcc (taken) 2 -2 8(0/2/0) Bcc.B (not taken) 2 0 4(0/1/0) Bcc.W (not taken) 0 0 4(0/2/0) Bcc.L (not taken) 0 0 6(0/3/1) DBcc (T, not taken) 1 1 4(0/2/0) DBcc (F, -1, not taken) 2 0 6(0/2/0) DBcc (F, not -1, taken) 6 -2 10(0/2/0) DBcc (T, not taken) 4 0 6(0/1/0) DBcc (F, -1, not taken) 6 0 8(0/1/0) DBcc (F, not -1, taken) 6 0 10(0/0/0) = In loop mode 5-110 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.7.3.12 CONTROL INSTRUCTIONS. The control instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Instruction Freescale Semiconductor, Inc... Head Tail Cycles ANDI #, SR 0 -2 12(0/2/0) EORI #, SR 0 -2 12(0/2/0) ORI #, SR 0 -2 12(0/2/0) ANDI #, CCR 2 0 6(0/2/0) EORI #, CCR 2 0 6(0/2/0) ORI #, CCR 2 0 6(0/2/0) BSR.B 3 -2 13(0/2/2) BSR.W 3 -2 13(0/2/2) BSR.L 1 -2 13(0/2/2) CHK FEA, Dn (no ex) 2 0 8(0/1/0) CHK FEA, Dn (ex) 2 -2 42(2/2/6) CHK2 (Save) FEA, Dn (no ex) 1 1 3(0/1/0) CHK2 (Op) FEA, Dn (no ex) 2 0 18(X/0/0) CHK2 (Save) FEA, Dn (ex) 1 1 3(0/1/0) CHK2 (Op) FEA, Dn (ex) 2 -2 52(X + 2/1/6) JMP CEA 0 -2 6(0/2/0) JSR CEA 3 -2 13(0/2/2) LEA CEA, An 0 0 2(0/1/0) LINK.W An, # 2 0 10(0/2/2) LINK.L An, # 0 0 10(0/3/2) 0 0 2(0/1/0) NOP PEA CEA 0 0 8(0/1/2) RTD # 1 -2 12(2/2/0) RTR 1 -2 14(3/2/0) RTS 1 -2 12(2/2/0) 1 0 9(2/1/0) UNLK An X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. NOTE: The CHK2 instruction involves a save step which other instructions do not have. To calculate the total instruction time, calculate the save, the EA, and the operation execution times, and combine in the order listed using the equations given in 5.7.1.6 Instruction Execution Time Calculation. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-111 Freescale Semiconductor, Inc. 5.7.3.13 EXCEPTION-RELATED INSTRUCTIONS AND OPERATIONS. The exceptionrelated instructions and operations table indicates the number of clock periods needed for the processor to perform the specified exception-related actions. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... Instruction Head Tail Cycles BKPT (Acknowledged) 0 0 14(1/0/0) BKPT (Bus Error) 0 -2 35(3/2/4) Breakpoint (Acknowledged) 0 0 10(1/0/0) Breakpoint (Bus Error) 0 -2 42(3/2/6) Interrupt 0 -2 30(3/2/4) RESET 0 0 518(0/1/0) STOP 2 0 12(0/1/0) LPSTOP 3 -2 25(0/3/1) Divide-by-Zero 0 -2 36(2/2/6) Trace 0 -2 36(2/2/6) TRAP # 4 -2 29(2/2/4) ILLEGAL 0 -2 25(2/2/4) A-line 0 -2 25(2/2/4) F-line (First word illegal) 0 -2 25(2/2/4) F-line (Second word illegal) ea = Rn 1 -2 31(2/3/4) F-line (Second word illegal) ea Rn (Save) 1 1 3(0/1/0) F-line (Second word illegal) ea Rn (Op) 4 -2 29(2/2/4) Privileged 0 -2 25(2/2/4) TRAPcc (trap) 2 -2 38(2/2/6) TRAPcc (no trap) 2 0 4(0/1/0) TRAPcc.W (trap) 2 -2 38(2/2/6) TRAPcc.W (no trap) 0 0 4(0/2/0) TRAPcc.L (trap) 0 -2 38(2/2/6) TRAPcc.L (no trap) 0 0 6(0/3/0) TRAPV (trap) 2 -2 38(2/2/6) TRAPV (no trap) 2 0 4(0/1/0) = Minimum interrupt acknowledge cycle time is assumed to be three clocks. NOTE: The F-line (second word illegal) operation involves a save step which other operations do not have. To calculate the total operation time, calculate the save, the calculate EA, and the operation execution times, and combine in the order listed, using the equations given in 5.7.1.6 Instruction Execution Time Calculation. 5-112 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 5.7.3.14 SAVE AND RESTORE OPERATIONS. The save and restore operations table indicates the number of clock periods needed for the processor to perform the specified state save or return from exception. Complete execution times and stack length are given. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Freescale Semiconductor, Inc... Instruction Head Tail Cycles BERR on instruction 0 -2 <58(2/2/12) BERR on exception 0 -2 48(2/2/12) RTE (four-word frame) 1 -2 24(4/2/0) RTE (six-word frame) 1 -2 26(4/2/0) RTE (BERR on instruction) 1 -2 50(12/12/Y) RTE (BERR on four-word frame) 1 -2 66(10/2/4) RTE (BERR on six-word frame) 1 -2 70(12/2/6) < = Maximum time is indicated (certain data or mode combinations execute faster). Y = If a bus error occurred during a write cycle, the cycle is rerun by the RTE. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-113 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 6 DMA CONTROLLER MODULE The direct memory access (DMA) controller module provides for high-speed transfer capability to/from an external peripheral or for memory-to-memory data transfer. The DMA module, shown in Figure 6-1, provides two channels that allow byte, word, or long-word operand transfers. These transfers can be either single or dual address and to either onor off-chip devices. The DMA contains the following features: * Two, Independent, Fully Programmable DMA Channels * Single-Address Transfers with 32-Bit Address and 32-Bit Data Capability * Dual-Address Transfers with 32-Bit Address and 16-Bit Data Capability * Two 32-Bit Transfer Counters * Four 32-Bit Address Pointers That Can Increment or Remain Constant * Operand Packing and Unpacking for Dual-Address Transfers * Supports All Bus-Termination Modes * Provides Two-Clock-Cycle Internal Module Access * Provides Two-Clock-Cycle External Access Using MC68340 Chip Selects * Provides Full DMA Handshake for Burst Transfers and Cycle Steal INTERRUPT ARBITRATION DMA CHANNEL 1 DMA HANDSHAKE SIGNALS DMA CHANNEL 2 DMA HANDSHAKE SIGNALS SLAVE BIU I M B MASTER BIU BUS ARBITRATION . Figure 6-1. DMA Block Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-1 Freescale Semiconductor, Inc. 6.1 DMA MODULE OVERVIEW The main purpose of the DMA controller module is to transfer data at very high rates, usually much faster than the CPU32 under software control can handle. The term DMA is used to refer to the ability of a peripheral device to access memory in a system in the same manner as a microprocessor does. DMA operations can greatly increase overall system performance. Freescale Semiconductor, Inc... The MC68340 DMA module consists of two, independent, programmable channels. The term DMA is used throughout this section to reference either channel 1 or channel 2 since the two are functionally equivalent. Each channel has independent request, acknowledge, and done signals. However, both channels cannot own the bus at the same time. Therefore, it is impossible to implicitly address both DMA channels at the same time. The MC68340 on-chip peripherals do not support the single-address transfer mode. DMA requests may be internally generated by the channel or externally generated by a device. For an internal request, the amount of bus bandwidth allocated for the DMA can be programmed. The DMA channels support two external request modes: burst mode and cycle steal mode. The DMA controller supports single- and dual-address transfers. In single-address mode, a channel supports 32 bits of address and 32 bits of data. Only an external request can be used to start a transfer in the single-address mode. The DMA provides address and control signals during a single-address transfer. The requesting device either sends or receives data to or from the specified address (see Figure 6-2). In dual-address mode, a channel supports 32 bits of address and 16 bits of data. The dual-address transfers can be started by either the internal request mode or by an external device using the request signal. In this mode, two bus transfers occur, one from a source device and the other to a destination device (see Figure 6-3). In dual-address mode, operands are packed or unpacked according to port sizes and addresses. Any operation involving the DMA will follow the same basic steps: channel initialization, data transfer, and channel termination. In the channel initialization step, the DMA channel registers are loaded with control information, address pointers, and a byte transfer count. The channel is then started. During the data transfer step, the DMA accepts requests for operand transfers and provides addressing and bus control for the transfers. The channel termination step occurs after operation is complete. The channel indicates the status of the operation in the channel status register. 6-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DMA DMA PERIPHERAL PERIPHERAL MEMORY . Freescale Semiconductor, Inc... DMA PERIPHERAL MEMORY Figure 6-2. Single-Address Transfers MEMORY DMA MEMORY ... Figure 6-3. Dual-Address Transfer MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-3 Freescale Semiconductor, Inc. 6.2 DMA MODULE SIGNAL DEFINITIONS This section contains a brief description of the DMA module signals used to provide handshake control for either a source or destination external device. NOTE Freescale Semiconductor, Inc... The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 6.2.1 DMA Request ( DREQ) This active-low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory. The assertion of DREQ starts the DMA process. The assertion level in external burst mode is level sensitive; in external cycle steal mode, it is falling-edge sensitive. 6.2.2 DMA Acknowledge ( DACK) This active-low output is asserted by the DMA to signal to a peripheral that an operand is being transferred in response to a previous transfer request. 6.2.3 DMA Done (DONE) This active-low bidirectional signal is asserted by the DMA or a peripheral device during any DMA bus cycle to indicate that the last data transfer is being performed. DONE is an active input in any mode. As an output, DONE is only active in external request mode. An external pullup resistor is required even if operating only in the internal request mode. 6.3 TRANSFER REQUEST GENERATION The DMA channel supports two types of request generation methods: internal and external. Internally generated requests can be programmed to limit the amount of bus utilization. Externally generated requests can be either burst mode or cycle steal mode. The request generation method used for the channel is programmed by the channel control register (CCR) in the REQ field. 6.3.1 Internal Request Generation Internal requests are accessed in two clocks by the intermodule bus (IMB). The channel is started as soon as the STR bit in the CCR is set. The channel immediately requests the bus and begins transferring data. Only internal requests can limit the amount of bus utilization. The percentage of the bandwidth that the DMA channel can use during a transfer can be selected by the CCR BB field. 6-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 6.3.1.1 INTERNAL REQUEST, MAXIMUM RATE. Internal generation using 100% of the internal bus always has a transfer request pending for the channel until the transfer is complete. As soon as the channel is started, the DMA will arbitrate for the internal bus and begin to transfer data when it becomes bus master. If no exceptions occur, all operands in the data block will be transferred in one burst so that the DMA will use 100% of the available bus bandwidth. Freescale Semiconductor, Inc... 6.3.1.2 INTERNAL REQUEST, LIMITED RATE. To guarantee that the DMA will not use all of the available bus bandwidth during a transfer, internal requests can be generated according to the amount of bus bandwidth allocated to the DMA. There are three programmed constants in the CCR used to monitor the bus activity and allow the DMA to use a percentage of the bus bandwidth. Options are 25%, 50%, and 75% of 1024 clock periods. See Table 6-5 for more information. 6.3.2 External Request Generation To control the transfer of operands to or from memory in an orderly manner, a peripheral device uses the DREQ input signal to request service. If the channel is programmed for external request and the CCR STR bit is set, an external request ( DREQ) signal must be asserted before the channel requests the bus and begins a transfer. The DMA supports external burst mode and external cycle steal mode. The generation of the request from the source or destination is specified by the ECO bit of the CCR. The external requests can be for either single- or dual-address transfers. 6.3.2.1 EXTERNAL BURST MODE. For external devices that require very high data transfer rates, the burst request mode allows the DMA channel to use all of the bus bandwidth under control of the external device. In burst mode, the DREQ input to the DMA is level sensitive and is sampled at certain points to determine when a valid request is asserted by the device. The device requests service by asserting DREQ and leaving it asserted. In response, the DMA arbitrates for the bus and performs an operand transfer. During each operand transfer, the DMA asserts DMA acknowledge (DACK) to indicate to the device that a request is being serviced. DACK is asserted on the cycle of either the source or destination device, depending on which one generated the request as programmed by the CCR ECO bit. To allow more than one transfer to be recognized, DREQ must meet the asynchronous setup and hold times while DACK is asserted in the DMA bus cycle. Upon completion of a request, DREQ should be held asserted (bursting) into the following DMA bus cycle to allow another transfer to occur. The recognized request will immediately be serviced. If DREQ is negated before DACK is asserted, a new request is not recognized, and the DMA channel releases ownership of the bus. 6.3.2.2 EXTERNAL CYCLE STEAL MODE. For external devices that generate a pulsed signal for each operand to be transferred, the cycle steal request mode uses the DREQ signal as a falling-edge-sensitive input. The DREQ pulse generated by the device must be asserted during two consecutive falling edges of the clock to be recognized as valid. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-5 Freescale Semiconductor, Inc. Therefore, if a peripheral generates it asynchronously, it must be at least two clock periods long. Freescale Semiconductor, Inc... The DMA channel responds to cycle steal requests the same as all other requests. However, if subsequent DREQ pulses are generated before DACK is asserted in response to each request, they are ignored. If DREQ is asserted after the DMA channel asserts DACK for the previous request but before DACK is negated, then the new request is serviced before bus ownership is released. If a new request is not generated by the time DACK is negated, the bus is released. 6.3.2.3 EXTERNAL REQUEST WITH OTHER MODULES. The DMA controller can be externally connected to the serial module and used in conjunction with the serial module to send or receive data. The DMA takes the place of a separate service routine for accessing or storing data that is sent or received by the serial module. Using the DMA also lowers the CPU32 overhead required to handle the data transferred by the serial module. Figure 6-4 shows the external connections required for using the DMA with the serial module. DMA MODULE SERIAL MODULE .. . DREQ1 TxRDYA DREQ2 RxRDYA Figure 6-4. DMA External Connections to Serial Module For serial receive, the DMA reads data from the serial receive buffer (RB) register (when the serial module has filled the buffer on input) and writes data to memory. For serial transmit, the DMA reads data from memory and writes data to the serial transmit buffer (TB) register. Only dual-address mode can be used with the serial module. The MC68340 on-chip peripherals do not support single-address transfers. The timer modules can be used with the DMA in a similar manner. By connecting TOUTx to DREQ, the timer can request a DMA transfer. 6.4 DATA TRANSFER MODES The DMA channel supports single- and dual-address transfers. The single-address transfer mode consists of one DMA bus cycle, which allows either a read or a write cycle to occur. The dual-address transfer mode consists of a source operand read and a destination operand write. Two DMA bus cycles are executed for the dual-address mode: a DMA read cycle and a DMA write cycle. 6.4.1 Single-Address Mode The single-address DMA bus cycle allows data to be transferred directly between a device and memory without going through the DMA. In this mode, the operand transfer takes 6-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... place in one bus cycle, where only the memory is explicitly addressed. The DMA bus cycle may be either a read or a write cycle. The DMA provides the address and control signals required for the operation. The requesting device either sends or receives data to or from the specified address. Only external requests can be used to start a transfer when the single-address mode is selected. An external device uses DREQ to request a transfer. Each DMA channel can be independently programmed to provide single-address transfers. The CCR ECO bit controls whether a source read or a destination write cycle occurs on the data bus. If the ECO bit is set, the external handshake signals are used with the source operand and a single-address source read occurs. If the ECO bit is cleared, the external handshake signals are used with the destination operand, and a singleaddress destination write occurs. The channel can be programmed to operate in either burst transfer mode or cycle steal mode. See 6.7 Register Description for more information. If external 32-bit devices and a 32-bit bus are used with the MC68340, the DMA can control 32-bit transfers between devices that use the 32-bit bus in single-address mode only. External logic is required to complete a 32-bit (long-word) transfer. If both byte and word devices are used on an external bus, then an external multiplexer must be used to correctly transfer data. The SIZx and A0 signals can be used to control this external multiplexer. 6.4.1.1 SINGLE-ADDRESS READ. During the single-address source (read) cycle, the DMA controls the transfer of data from memory to a device. The memory selected by the address specified in the source address register (SAR), the source function codes in the function code register (FCR), and the source size in the CCR provides the data and control signals on the data bus. This bus cycle operates like a normal read bus cycle. The DMA control signals (DACK and DONE) are asserted in the source (read) cycle. See Figures 6-5 and 6-6 for timing diagrams single-address read for external burst and cycle steal modes. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-7 Freescale Semiconductor, Inc. DMA READ CPU CYCLE S0 S2 S4 S0 S2 DMA READ S4 S0 S2 CPU CYCLE S4 S0 CLKOUT A31-A0 FC3-FC0 Freescale Semiconductor, Inc... SIZ1-SIZ0 AS DS R/W D15-D0 DSACKx DREQx DONEx (INPUT) ..... DACKx DONEx (OUTPUT) NOTE: 1. Timing to generate more than one DMA request. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized. Figure 6-5. Single-Address Read Timing (External Burst) 6-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 S2 S4 CPU CYCLE S0 S2 DMA READ Figure 6-6. Single-Address Read Timing (Cycle Steal) NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. DONEx (OUTPUT) DACKx DONEx (INPUT) DREQx DSACKx D15-D0 R/W DS AS SIZ1-SIZ0 FC3-FC0 A31-A0 CLKOUT S0 CPU CYCLE Freescale Semiconductor, Inc... S4 Freescale Semiconductor, Inc. 6-9 Freescale Semiconductor, Inc. 6.4.1.2 SINGLE-ADDRESS WRITE. During the single-address destination (write) cycle, the DMA controls the transfer of data from a device to memory. The data is written to memory selected by the address specified in the destination address register (DAR), the destination function codes in the FCR, and the size in the CCR. The destination (write) DMA bus cycle has timing identical to a write bus cycle. The DMA control signals (DACK and DONE ) are asserted in the destination (write) cycle. See Figures 6-7 and 6-8 for timing diagrams of single-address write for external burst and cycle steal modes. DMA WRITE CPU CYCLE S0 S2 S4 S0 S2 S4 CPU CYCLE DMA WRITE S0 S2 S4 S0 Freescale Semiconductor, Inc... CLKOUT A31-A0 FC3-FC0 SIZ1-SIZ0 AS DS R/W D15-D0 DSACKx DREQx DONEx (INPUT) . DACKx DONEx (OUTPUT) NOTE: 1. Timing to generate more than one DMA request. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 2. DREQx must be asserted while DACKx is asserted, and meet the setup and hold times for more than one DMA transfer to be recognized. Figure 6-7. Single-Address Write Timing (External Burst) 6-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 CPU CYCLE S0 S2 S4 DMA WRITE S0 S2 S4 CPU CYCLE S0 S2 Figure 6-8. Single-Address Write Timing (Cycle Steal) S4 DMA WRITE NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle. DONEx (OUTPUT) DACKx DONEx (INPUT) DREQx DSACKx D15-D0 R/W DS AS SIZ1-SIZ0 FC3-FC0 A31-A0 CLKOUT S0 CPU CYCLE Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 6-11 Freescale Semiconductor, Inc. 6.4.2 Dual-Address Mode Freescale Semiconductor, Inc... The dual-address DMA bus cycle transfers data between a device or memory and the DMA internal holding register (DHR). In this mode, any operand transfer takes place in two DMA bus cycles, one where a device is addressed and one where memory is addressed. The data transferred during a dual-address operation is either read from the data bus into the DHR or written from the DHR to the data bus. Each DMA channel can each be programmed to operate in the dual-address transfer mode. In this mode, the operand is read from the source address specified in the SAR and placed in the DHR. The operand read may take up to four bus cycles to complete because of differences in operand sizes of the source and destination. The operand is then written to the address specified in the DAR. This transfer may also be up to four bus cycles long. In this manner, various combinations of peripheral, memory, and operand sizes may be used. See 6.7 Register Description for more information. The dual-address transfers can be started by either the internal request mode or by an external device using the DREQ input signal. When the external device uses DREQ, the channel can be programmed to operate in either burst transfer mode or cycle steal mode. 6.4.2.1 DUAL-ADDRESS READ. During the dual-address read cycle, the DMA reads data from a device or memory into the internal DHR. The device or memory is selected by the address specified in the SAR, the source function codes in the FCR, and the source size in the CCR. Data is read from the memory or peripheral and placed in the DHR when the bus cycle is terminated. When the complete operand has been read, the SAR is incremented by 0, 1, 2, or 4, according to the size and increment information specified by the SSIZE and SAPI bits of the CCR. The DMA control signals (DACK and DONE) are asserted in the source (read) cycle when the source device makes a request. See Figures 6-9 and 6-10 for timing diagrams of dual-address read for external burst and cycle steal modes. 6-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 CPU CYCLE Figure 6-9. Dual-Address Read Timing (External Burst-Source Requesting) NOTE: 1. Timing to generate more than one DMA transfer. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized. 4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one. DONEx (OUTPUT) DACKx DONEx (INPUT) DREQx DSACKx D15-D0 R/W DS AS SIZ1-SIZ0 FC3-FC0 A31-A0 CLKOUT S0 CPU CYCLE Freescale Semiconductor, Inc... S4 Freescale Semiconductor, Inc. 6-13 6-14 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 CPU CYCLE S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 Figure 6-10. Dual-Address Read Timing (Cycle Steal-Source Requesting) NOTE 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. 4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one. DONEx (OUTPUT) DACKx DONEx (INPUT) DREQx DSACKx D15-D0 R/W DS AS SIZ1-SIZ0 FC3-FC0 A31-A0 CLKOUT S0 Freescale Semiconductor, Inc... S2 S4 DMA WRITE Freescale Semiconductor, Inc. 6.4.2.2 DUAL-ADDRESS WRITE. During the dual-address write cycle, the DMA writes data to a device or memory from the internal DHR. The data in the DHR is written to the device or memory selected by the address in the DAR, the destination function codes in MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... the FCR, and the size in the CCR. When the complete operand is written, the DAR is incremented by 0, 1, 2, or 4, according to the increment and size information specified by the DAPI and DSIZE bits of the CCR, and the byte transfer count register (BTC) is decremented by the number of bytes transferred. If the BTC is equal to zero and there were no errors, the CSR DONE bit is set, and the DONE signal for the DMA handshake is asserted. The DMA control signals (DACK and DONE) are asserted in the destination (write) cycle when the destination device makes a request. See Figures 6-11 and 6-12 for timing diagrams of dual-address write for external burst and cycle steal modes. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-15 6-16 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 CPU CYCLE Figure 6-11. Dual-Address Write Timing (External Burst-Destination Requesting) NOTE: 1. Timing to generate more than one DMA transfer. 2. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle. 3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized. 4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one. DONEx (OUTPUT) DACKx DONEx (INPUT) DREQx DSACKx D15-D0 R/W DS AS SIZ1-SIZ0 FC3-FC0 A31-A0 CLKOUT S0 CPU CYCLE Freescale Semiconductor, Inc... S4 Freescale Semiconductor, Inc. MOTOROLA MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com S2 S4 S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 S2 S4 DMA WRITE S0 S2 S4 CPU CYCLE S0 S2 S4 DMA READ S0 Figure 6-12. Dual-Address Write Timing (Cycle Steal-Destination Requesting) S2 S4 DMA WRITE NOTE: 1. DREQx must be active for two consecutive clocks for a DMA request to be recognized. 2. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 3. DACKx and DONEx (DMA control signals) are asserted in the destination (write) DMA cycle. 4. DONEx (Input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one. DONEx (OUTPUT) DACKx DONEx (INPUT) DREQx DSACKx D15-D0 R/W DS AS SIZ1-SIZ0 FC3-FC0 A31-A0 CLKOUT S0 CPU CYCLE Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 6-17 Freescale Semiconductor, Inc. 6.5 BUS ARBITRATION The DMA controller module uses the M68000 bus arbitration protocol to request bus mastership for DMA transfers. Each channel arbitrates for the bus independently. The source (read) DMA bus cycle has timing identical to a read bus cycle. The destination (write) DMA bus cycle has timing identical to a write bus cycle. However, the DMA channel transfers are unique in one respect--FC3 can be asserted during the source operand bus cycle and remain asserted until the end of the destination operand bus cycle. Freescale Semiconductor, Inc... For internal request generation as soon as the CCR STR bit is set, the DMA channel arbitrates for the bus and begins to transfer data when it becomes bus master. For external request generation, the STR bit must be set and a DREQ signal must be asserted before the channel arbitrates for the bus and begins a transfer. 6.6 DMA CHANNEL OPERATION The following paragraphs describe the programmable channel functions available for the DMA channel, the data transfer operations, and behavior during cycle termination. This description applies to both channels. Any DMA channel operation adheres to the following basic sequence: 1. Channel Initialization and Startup--The channel registers are initialized. The channel is then started by setting the CCR STR bit. The first operand transfer request (either internally or externally generated) is recognized. 2. Data Transfer--After a channel is started, it transfers one operand in response to each request until an entire data block is transferred. 3. Channel Termination--The channel can terminate by normal completion or from an error. The channel status register (CSR) indicates the status of the operation. 6.6.1 Channel Initialization and Startup Before starting a block transfer operation, the channel registers must be initialized with information describing the channel configuration, request generation method, and data block. This initialization is accomplished by programming the appropriate information into the channel registers. The SAR is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to a peripheral device or memory to memory, the source address is the starting address of the data block. This address may be any byte address. In the single-address mode with the destination (write) device requesting mode of operation, this register is not used. The DAR should contain the destination (write) address. If the transfer is from a peripheral device to memory or memory to memory, the DAR is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, the DAR is loaded with the address of the peripheral data register. This address may be any byte 6-18 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. address. In the single-address mode with the source (read) device requesting mode of operation, this register is not used. Freescale Semiconductor, Inc... The manner in which the SAR and DAR change after each cycle depends upon the values in the CCR SSIZE and DSIZE fields and SAPI and DAPI bits, and the starting address in the SAR and DAR. If programmed to increment, the increment value is 1, 2, or 4 for byte, word, or long-word operands, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the operand transfer. The SAR and DAR are incremented if a bus error terminates the transfer. Therefore, either the SAR or the DAR contain the next address after the one that caused the bus error. The BTC must be loaded with the number of byte transfers that are to occur. This register is decremented by 1, 2, or 4 at the end of each transfer. The FCR must be loaded with the source and destination function codes. Although these function codes may not be used in the address decode for the memory or peripheral, they are provided if needed. The CSR must be cleared for channel startup. Once the channel has been initialized, it is started by writing a one to the STR bit in the CCR. Programming the channel for internal request causes the channel to request the bus and start transferring data immediately. If the channel is programmed for external request, DREQ must be asserted before the channel requests the bus. The DREQ input is ignored until the channel is started, since the channel does not recognize transfer requests until it is active. If any fields in the CCR are modified while the channel is active, that change is effective immediately. To avoid any problems with changing the setup for the DMA channel, a zero should be written to the STR bit in the CCR to halt the DMA channel at the end of the current bus cycle. 6.6.2 Data Transfers Each operand transfer requires from one to five bus cycles to complete. Once a bus request is recognized and the operand transfer begins, both the source (read) cycle and/or the destination (write) cycle occur before a new bus request may be honored, even if the new bus request is of higher priority. 6.6.2.1 INTERNAL REQUEST TRANSFERS. Internally generated request transfers are accessed as two-clock bus cycles. (The IMB can access on-chip peripherals in two clocks.) The percentage of bus bandwidth utilization can be limited for internal request transfers. 6.6.2.2 EXTERNAL REQUEST TRANSFERS. In single-address mode, only one bus cycle is run for each request. Since the operand size must be equal to the device port size in single-address mode, the number of normally terminated bus cycles executed during a transfer operation is always equal to the value programmed into the corresponding size field of the CCR. The sequencing of the address bus follows the programming of the CCR and address register (SAR or DAR) for the channel. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-19 Freescale Semiconductor, Inc. Each operand transfer in dual-address mode requires from two to five bus cycles in response to each operand transfer request. If the source and destination operands are the same size, two cycles will transfer the complete operand. If the source and destination operands are different sizes, the number of cycles will vary. If the source is a long-word and the destination is a byte, there would be one bus cycle for the read and four bus cycles for the write. Once the DMA channel has started a dual-address operand transfer, it must complete that transfer before releasing ownership of the bus or servicing a request for another channel of equal or higher priority, unless one of the bus cycles is terminated with a bus error during the transfer. Freescale Semiconductor, Inc... 6.6.3 Channel Termination The channel can terminate by normal completion or from an error. The status of a DMA operation can be determined by reading the CSR. The DMA channel can also interrupt the processor to inform it of errors, normal transfer completion, or breakpoints. The fast termination option can also be used to provide a two-clock access for external requests. 6.6.3.1 CHANNEL TERMINATION. The channel operation can be terminated for several reasons: the BTC is decremented to zero, a peripheral device asserts DONE during an operand transfer, the STR bit is cleared in the CCR, a bus cycle is terminated with a bus error, or a reset occurs. 6.6.3.2 INTERRUPT OPERATION. Interrupts can be generated by error termination of a bus cycle or by normal channel completion. Specifically, if the CCR interrupt error (INTE) bit is set and a bus error on source (CCR BES) bit, bus error on destination (CCR BED) bit, or configuration error (CCR CONF) bit is set, the CCR IRQ bit is set. In this case, clearing the INTE, BES, BED, or CONF bits causes the IRQ bit to be cleared. If the interrupt normal (CCR INTN) bit is set and the CCR DONE bit is set, the IRQ bit is set. In this case, clearing the INTN or the DONE bit causes the IRQ bit to be cleared. If the interrupt breakpoint (CCR INTB) and the CSR BRKP bits are set, the IRQ bit is set. Clearing INTB or BRKP clears IRQ. 6.6.3.3 FAST TERMINATION OPTION. Using the system integration module (SIM40) chip select logic, the fast termination option (Figure 6-13) can be employed to give a fast bus access of two clock cycles rather than the standard three-cycle access time for external requests. The fast termination option is described in Section 3 Bus Operation and Section 4 System Integration Module. 6-20 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. CPU CYCLE S0 S2 DMA READ S4 S0 S4 CPU CYCLE S0 S2 S4 DMA READ .. .. .. ...... .. .. . S0 S2 CLKOUT A31-A0 FC3-FC0 SIZ1-SIZ0 AS Freescale Semiconductor, Inc... DS R/W D15-D0 DSACKx DREQx DACKx DONEx (OUTPUT) NOTE: 1. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before DACKx is negated. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. Figure 6-13. Fast Termination Option (Cycle Steal) If the fast termination option is used with external burst request mode (Figure 6-14), an extra DMA cycle may result on every burst transfer. Normally, DREQ is negated when DACK is returned. In the burst mode with fast termination selected, a new cycle starts even if DREQ is negated simultaneously with DACK assertion. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-21 Freescale Semiconductor, Inc. CPU CYCLE S0 S2 S4 DMA READ S0 S4 DMA WRITE S0 S4 DMA READ CPU CYCLE S0 S2 ... . S4 S0 S4 DMA WRITE S0 S4 S0 CLKOUT A31-A0 FC3-FC0 SIZ1-SIZ0 AS Freescale Semiconductor, Inc... DS R/W D15-D0 DSACKx DREQx DACKx DONEx (OUTPUT) NOTE 1. To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated. 2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle. Figure 6-14. Fast Termination Option (External Burst-Source Requesting) 6.7 REGISTER DESCRIPTION The following paragraphs contain a detailed description of each register and its specific function. Figure 6-15 is a programmer's model (register map) of all registers in the DMA module. Each channel has an independent set of registers. For more information about a particular register, refer to the individual register description. The ADDRESS column indicates the offset of the register from the base address of the DMA channel. The FC column designation of S indicates that register access is restricted to supervisor only. A designation of S/U indicates that access is governed by the SUPV bit in the module configuration register (MCR). Unimplemented memory locations return logic zero when accessed. All registers support both byte and word transfers. 6-22 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ADDRESS FC CH1 CH2 15 8 7 780 7A0 S MODULE CONFIGURATION REGISTER (MCR) 782 7A2 S RESERVED 784 7A4 S INTERRUPT REGISTER 786 7A6 S/U RESERVED 788 7A8 S/U 78A 7AA S/U 78C 7AC S/U SOURCE ADDRESS REGISTER MSBs 78E 7AE S/U SOURCE ADDRESS REGISTER LSBs 790 7B0 S/U DESTINATION ADDRESS REGISTER MSBs 792 7B2 S/U DESTINATION ADDRESS REGISTER LSBs 794 7B4 S/U BYTE TRANSFER COUNTER MSBs 796 7B6 S/U BYTE TRANSFER COUNTER LSBs 798 7B8 S/U RESERVED 79A 7BA S/U RESERVED 79C 7BC S/U RESERVED 79E 7BE S/U RESERVED 0 CHANNEL CONTROL REGISTER CHANNEL STATUS REGISTER FUNCTION CODE REGISTER Figure 6-15. DMA Module Programming Model In the registers discussed in the following paragraphs, the numbers in the upper righthand corner indicate the offset of the register from the base address specified by the module base address register (MBAR) in the SIM40. The first number is the offset for channel 1; the second number is the offset for channel 2. The numbers above the register represent the bit position in the register. The register contains the mnemonic for the bit. The value of these bits after a hardware reset is shown below the register. The access privilege is shown in the lower right-hand corner. NOTE A CPU32 RESET instruction will not affect the MCR but will reset all other registers in the DMA module as though a hardware reset occurred. The term DMA is used to reference either channel 1 or channel 2, since the two are functionally equivalent. 6.7.1 Module Configuration Register (MCR) The MCR controls the DMA channel configuration. Each DMA channel has an MCR. This register can be either read or written when the channel is enabled and is in the supervisor state. The MCR is not affected by a CPU32 RESET instruction. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-23 Freescale Semiconductor, Inc. MCR1, MCR2 $780, $7A0 15 14 13 12 11 STP FRZ1 FRZ0 SE 0 RESET: 0 0 0 0 0 10 9 8 ISM 0 7 6 SUPV 0 0 1 5 4 3 2 MAID 0 0 1 0 0 0 IARB 0 0 0 Freescale Semiconductor, Inc... Supervisor Only STP--Stop Bit 1 = Setting the STP bit stops all clocks within the DMA module except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR. The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to DMA module registers while in stop mode produce a bus error. The DMA module should be disabled in a known state before setting the STP bit. The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption. 0 = The channel operates in normal mode. NOTE The DMA module uses only one STP bit for both channels. A read or write to either MCR accesses the same STP control bit. FRZ1, FRZ0--Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB when the CPU32 has entered background debug mode. The DMA module negates BR and keeps it negated until FREEZE is negated or reset. Table 6-1 lists the action taken for each bit combination. Table 6-1. FRZx Control Bits FRZ1 FRZ0 Action 0 0 Ignore FREEZE 0 1 Reserved 1 0 Freeze on Boundary* 1 1 Reserved *The boundary is defined as any bus cycle by the DMA module. NOTE The DMA module uses only one set of FRZx bits for both channels. A read or write to either MCR accesses the same FRZx control bits. 6-24 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SE--Single-Address Enable This bit is implemented for future MC683xx family compatibility. 1 = In single-address mode, the external data bus is driven during a DMA transfer. 0 = In single-address mode, the external data bus remains in a high-impedance state during a DMA transfer (used for intermodule DMA). In dual-address mode, the SE bit has no effect. Freescale Semiconductor, Inc... Bit 11--Reserved ISM2-ISM0--Interrupt Service Mask These bits contain the interrupt service mask level for the channel. When the interrupt service level on the IMB is greater than the interrupt service mask level, the DMA vacates the bus and negates BR until the interrupt service level is less than or equal to the interrupt service mask level. NOTE When the CPU32 status register (SR) interrupt priority mask bits I2-I0 are at a higher level than the DMA ISM bits, the DMA channel will not start. The channel will begin operation when the level of the SR I2-I0 bits is less than or equal to the level of the DMA ISM bits. SUPV--Supervisor/User The value of this bit has no effect on registers permanently defined as supervisor-only access. 1 = The DMA channel registers defined as supervisor/user reside in supervisor data space and are only accessible from supervisor programs. 0 = The DMA channel registers defined as supervisor/user reside in user data space and are accessible from either supervisor or user programs. MAID--Master Arbitration ID These bits establish bus arbitration priority level among modules that have the capability of becoming bus master. For the MC68340, the MAID bits are used to arbitrate between DMA channel 1 and channel 2. If both channels are programmed with the same MAID level, channel 1 will have priority. These bits are implemented for future MC683xx Family compatibility. In the MC68340, only the SIM and the DMA can be bus masters. However, future versions of the MC683xx Family may incorporate other modules that may also be bus masters. For these devices, the MAID bits will be required. For the MAID bits, zero is the lowest priority and seven is the highest priority. IARB -- Interrupt Arbitration ID Each module that generates interrupts has an IARB field. These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-25 Freescale Semiconductor, Inc. The reset value of the IARB field is $0, which prevents the DMA module from arbitrating during the interrupt acknowledge cycle. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). NOTE The DMA module uses only one set of IARB bits for both channels. A read or write to either MCR accesses the same IARB control bits. Freescale Semiconductor, Inc... 6.7.2 Interrupt Register (INTR) The INTR contains the priority level for the channel interrupt request and the 8-bit vector number of the interrupt. The register can be read or written to at any time while in supervisor mode and while the DMA module is enabled (i.e., the STP bit in the MCR is cleared). INTR1, INTR2 $784, $7A4 15 14 13 12 11 0 0 0 0 0 RESET: 0 0 0 0 0 10 9 8 7 6 5 4 INTL 0 0 3 2 1 0 1 1 1 1 INTV 0 0 0 0 0 Supervisor Only Bits 15-11--Reserved INTL--Interrupt Level Bits Each module that can generate interrupts has an interrupt level field. The interrupt level field contains the priority level of the interrupt for its associated channel. The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal. The CPU32 uses this value to determine servicing priority. See Section 5 CPU32 for more information. INTV--Interrupt Vector Bits Each module that can generate interrupts has an interrupt vector field. The interrupt vector field contains the vector number of the interrupt for its associated channel. This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The INTV field is reset to $0F, which indicates an uninitialized interrupt condition. See Section 5 CPU32 for more information. 6.7.3 Channel Control Register (CCR) The CCR controls the configuration of the DMA channel. This register is accessible in either supervisor or user space. The CCR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). 6-26 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. CCR1, CCR2 $788, $7A8 15 14 13 12 11 10 INTB INTN INTE ECO SAPI DAPI RESET: U U U U U U 9 8 7 SSIZE U 6 5 DSIZE U U 4 REQ U U 2 BB U U = Unaffected by reset Freescale Semiconductor, Inc... 3 U U 1 0 S/D STR U 0 Supervisor/User INTB--Interrupt Breakpoint Setting the interrupt breakpoint bit sets the BRKP bit in the CSR. The logic AND of INTB and BRKP generates an interrupt request. 1 = Enables an IRQ when a breakpoint is recognized and the channel is the bus master. 0 = Does not enable an IRQ when a breakpoint is recognized and the channel is the bus master. INTN--Interrupt Normal 1 = Enables an IRQ when the channel finishes a transfer without an error condition (CSR DONE bit is set). 0 = Does not enable an IRQ when the channel finishes a transfer without an error condition. INTE--Interrupt Error 1 = Enables an IRQ when the channel encounters an error on source read (CSR BES bit is set), destination write (CSR BED bit is set), or configuration for channel setup (CSR CONF bit is set). 0 = Does not enable an IRQ when the channel encounters an error on source read, destination write, or configuration for channel setup. ECO--External Control Option If request generation is programmed to be internal (REQ bits = 00), this bit has no effect. Single-Address Mode--This bit defines the direction of transfer. 1 = If request generation is programmed to be external (REQ = 1x), the requesting device receives the data (read from memory), and the control signals ( DREQ, DACK, and DONE) are used by the requesting device to write data during the source (read) portion of the transfer. 0 = If request generation is programmed to be external (REQ = 1x), the requesting device provides the data (write to memory), and the control signals ( DREQ, DACK, and DONE) are used by the requesting device to provide data during the destination (write) portion of the transfer. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-27 Freescale Semiconductor, Inc. Dual-Address Mode--This bit defines which device generates requests. Freescale Semiconductor, Inc... 1 = If request generation is programmed to be external (REQ = 1x), the source device generates the request, and the control signals ( DREQ, DACK, and DONE) are part of the source (read) portion of the transfer. 0 = If request generation is programmed to be external (REQ = 1x), the destination device generates the request, and the control signals ( DREQ, DACK, and DONE) are part of the destination (write) portion of the transfer. SAPI--Source Address Pointer Increment 1 = The SAR is incremented by 1, 2, or 4 after each transfer, according to the source size. The address that is written into the SAR points to a memory block and is incremented to complete the data transfer. 0 = The SAR is not incremented during operand transfer. The address that is written into the SAR points to a peripheral device and is used for the complete data transfer. DAPI--Destination Address Pointer Increment 1 = The DAR is incremented by 1, 2, or 4 after each transfer, according to the source size. The address that is written into the DAR points to a memory block and is incremented to complete the data transfer. 0 = The DAR is not incremented during operand transfer. The address that is written into the DAR points to a peripheral device and is used for the complete data transfer. SSIZE--Source Size Control Field This field controls the size of the source (read) bus cycle that the DMA channel is running. Table 6-2 defines these bits. Table 6-2. SSIZEx Encoding Bit 9 Bit 8 Definition 0 0 Long Word* 0 1 Byte 1 0 Word 1 1 Not Used *External logic is required to complete a longword transfer. 6-28 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSIZE--Destination Size Control Field This field controls the size of the destination (write) bus cycle that the DMA channel is running. Table 6-3 defines these bits. Freescale Semiconductor, Inc... Table 6-3. DSIZEx Encoding Bit 7 Bit 6 Definition 0 0 Long Word* 0 1 Byte 1 0 Word 1 1 Not Used *External logic is required to complete a longword transfer. REQ--Request Generation Field This field controls the mode of operation the DMA channel uses to make an operand transfer request. Table 6-4 defines these bits. Table 6-4. REQx Encoding Bit 5 Bit 4 Definition 0 0 Internal Request at Programmable Rate 0 1 Reserved 1 0 External Request Burst Transfer Mode 1 1 External Request Cycle Steal BB--Bus Bandwidth Field This field controls the percentage of 1024 clock periods of the IMB that the DMA channel can use during internal requests only. Table 6-5 defines these bits. Table 6-5. BBx Encoding and Bus Bandwidth REQ Field MOTOROLA BB Field Bus Bandwidth Bit 5 Bit 4 Bit 3 Bit 2 Definition (Clock Periods) 0 0 0 0 25% 256 0 0 0 1 50% 512 0 0 1 0 75% 768 0 0 1 1 100% 1024 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-29 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... S/D--Single-/Dual-Address Transfer 1 = The DMA channel runs single-address transfers from a peripheral to memory or from memory to a peripheral. The destination holding register is not used for these transfers because the data is transferred directly into the destination location. The MC68340 on-chip peripherals do not support single-address transfers. 0 = The DMA channel runs dual-address transfers. STR--Start This bit is cleared by a hardware/software reset, writing a logic zero, or setting one of the following CSR bits: DONE, BES, BED, CONF, or BRKP. The STR bit cannot be set when the CSR IRQ bit is set. The DMA channel cannot be started until the CSR DONE, BES, BED, CONF, and BRKP bits are cleared. Internal Request Mode: 1 = The DMA transfer starts as soon as this bit is set. 0 = The DMA transfer can be stopped by clearing this bit. External Request Mode: 1 = Setting this bit allows the DMA to start the transfer when a DREQ input is received from an external device. 0 = The DMA transfer can be stopped by clearing this bit. NOTE If any fields in the CCR are modified while the channel is active, that change is effective immediately. To avoid any problems with changing the setup for the DMA channel, a zero should be written to the STR bit in the CCR to halt the DMA channel at the end of the current bus cycle. 6.7.4 Channel Status Register (CSR) The CSR contains the channel status information. This register is accessible in either supervisor or user space. The CSR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). CSR1, CSR2 $78A, $7AA 7 6 5 4 3 2 1 0 IRQ DONE BES BED CONF BRKP 0 0 RESET 0 0 0 0 0 0 0 0 Supervisor/User 6-30 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... IRQ--Interrupt Request This bit is the logical OR of the DONE, BES, BED, CONF, and BRKP bits and is cleared when they are all cleared. IRQ is positioned to allow conditional testing as a signed binary integer. The state of this bit is not affected by the interrupt enable bits in the CCR. The STR bit in the CCR cannot be set when this bit is set; all error status bits, except the BRKP bit, must be cleared before the STR bit can be set. 1 = An interrupt condition has occurred. 0 = An interrupt condition has not occurred. DONE--DMA Done 1 = The DMA channel has terminated normally. 0 = The DMA channel has not terminated normally. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. BES--Bus Error on Source 1 = The DMA channel has terminated with a bus error during the read bus cycle. 0 = The DMA channel has not terminated with a bus error during the read bus cycle. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. BED--Bus Error on Destination 1 = The DMA channel has terminated with a bus error during the write bus cycle. 0 = The DMA channel has not terminated with a bus error during the write bus cycle. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. CONF--Configuration Error A configuration error results when either the SAR or the DAR contains an address that does not match the port size specified in the CCR and the BTC register does not match the larger port size or is zero. 1 = The CCR STR bit is set, and a configuration error is present. 0 = The CCR STR bit is set, and no configuration error exists. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. BRKP--Breakpoint 1 = The breakpoint signal was set during a DMA transfer. 0 = The breakpoint signal was not set during a DMA transfer. This bit is cleared by writing a logic one or by a hardware reset. Writing a zero has no effect. Bits 1, 0--Reserved NOTE The CSR is cleared by writing $7C to its location. The DMA channel cannot be started until the CSR DONE, BES, BED, CONF and BRKP bits are cleared. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-31 Freescale Semiconductor, Inc. 6.7.5 Function Code Register (FCR) The FCR contains the source and destination function codes for the channel. This register is accessible in either supervisor or user space. The FCR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). FCR1, FCR2 7 6 $78B, $7AB 5 4 3 2 SFC RESET: U U 0 U U DFC U U U U = Unaffected by reset. Freescale Semiconductor, Inc... 1 U Supervisor/User SFC--Source Function Code Field This field can be used to specify the source access to a certain address space type. The source function code bits are defined in Table 6-6. DFC--Destination Function Code Field This field can be used to specify the destination access to a certain address space type. The destination function code bits are defined in Table 6-6. Table 6-6. Address Space Encoding Function Code Bits 3 2 1 0 Address Spaces 0 0 0 0 Reserved (Motorola) 0 0 0 1 User Data Space 0 0 1 0 User Program Space 0 0 1 1 Reserved (User) 0 1 0 0 Reserved (Motorola) 0 1 0 1 Supervisor Data Space 0 1 1 0 Supervisor Program Space 0 1 1 1 CPU Space 1 x x x DMA Space NOTE Although FC3 can be set for DMA transfers to distinguish the source or destination space from other data or program spaces, it is not required to be set. Since the CPU32 currently has only 3-bit SFC and DFC capability, it cannot emulate FC3 = 1 at this time. However, it is recommended that FC3 be set to one to distinguish DMA or CPU access during debug. 6-32 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 6.7.6 Source Address Register (SAR) The SAR is a 32-bit register that contains the address of the source operand used by the DMA to access memory or peripheral registers. This register is accessible in either supervisor or user space. The SAR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). Freescale Semiconductor, Inc... SAR1, SAR2 $78C, $7AC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 RESET: U U U U U U U U U U U U U U U U 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RESET: U U U U U U U U U U U U U U U U U = Unaffected by reset Supervisor/User During the DMA read cycle, the SAR drives the address on the address bus. This register can be programmed to increment (CCR SAPI bit set) or remain constant (CCR SAPI bit cleared) after each operand transfer. The register is incremented using unsigned arithmetic and will roll over if overflow occurs. For example, if the register contains $FFFFFFFF and is incremented by 1, it will roll over to $00000000. This register is incremented by 1, 2, or 4, depending on the size of the operand and the memory starting address. If the operand size is byte, then the register is always incremented by 1. If the operand size is word and the starting address is evenword aligned, then the register is incremented by 2. If the operand size is long word and the address is even-word aligned, then the register is incremented by 4. The SAR value must be aligned to an even-word boundary if the transfer size is word or long word; otherwise, the CSR CONF bit is set, and the transfer does not occur. When read, this register always contains the next source address. If a bus error terminates the transfer, this register contains the next source address that would have been run had the error not occurred. 6.7.7 Destination Address Register (DAR) The DAR is a 32-bit register that contains the address of the destination operand used by the DMA to write to memory or peripheral registers. This register is accessible in either supervisor or user space. The DAR can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-33 Freescale Semiconductor, Inc. DAR1, DAR2 $790, $7B0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 RESET: U U U U U U U U U U U U U U U U 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RESET: U U U U U U U U U U U U U U U U Freescale Semiconductor, Inc... U = Unaffected by reset Supervisor/User During the DMA write cycle, this register drives the address on the address bus. This register can be programmed to increment (CCR DAPI bit set) or remain constant (CCR DAPI bit cleared) after each operand transfer. The register is incremented using unsigned arithmetic and will roll over if overflow occurs. For example, if a register contains $FFFFFFFF and is incremented by 1, it will roll over to $00000000. This register can be incremented by 1, 2, or 4, depending on the size of the operand and the starting address. If the operand size is byte, the register is always incremented by 1. If the operand size is word and the starting address is even-word aligned, the register is incremented by 2. If the operand size is long word and the address is even-word aligned, the register is incremented by 4. The DAR value must be aligned to an even-word boundary if the transfer size is word or long word; otherwise, the CSR CONF bit is set, and the transfer does not occur. When read, this register always contains the next destination address. If a bus error terminates the transfer, this register contains the next destination address that would have been run had the error not occurred. 6.7.8 Byte Transfer Counter Register (BTC) The BTC is a 32-bit register that contains the number of bytes left to transfer in a given block. This register is accessible in either supervisor or user space. The BTC can always be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is cleared). BTC1, BTC2 $794, $7B4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 RESET: U U U U U U U U U U U U U U U U 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RESET: U U U U U U U U U U U U U U U U U = Unaffected by reset 6-34 Supervisor/User MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... This register is decremented by 1, 2, or 4 for each successful operand transfer from source to destination locations. When the BTC decrements to zero and no error has occurred, the CSR DONE bit is set. In the external request mode, the DONE handshake line is also asserted when the BTC is decremented to zero. If the operand size is byte, then the register is always decremented by 1. If the operand size is word and the starting count is even word, the register is decremented by 2. If the operand size is word and the byte count is not a multiple of 2, the CSR CONF bit is set, and a transfer does not occur. If the operand size is long word and the count is even long word, then the register is decremented by 4. If the operand size is long word and the byte count is not a multiple of 4, the CSR CONF bit is set, and a transfer does not occur. If the STR bit is set with a zero count in the BTC, the CONF bit is set, and the STR bit is cleared. When read, this register always contains the count for the next access. If a bus error terminates the transfer, this register contains the count for the next access that would have been run had the error not occurred. 6.8 DATA PACKING The internal DHR is a 32-bit register that can serve as a buffer register for the data being transferred during dual-address DMA cycles. No address is specified since this register can not be addressed by the programmer. The DHR allows the data to be packed and unpacked by the DMA during the dual-address transfer. For example, if the source operand size is byte and the destination operand size is word, then two-byte read cycles occur, followed by a one-word write cycle (see Figure 6-16). The two bytes of data are buffered in the DHR until the destination (write) word cycle occurs. The DHR allows for packing and unpacking of operands for the following sizes: bytes to words, bytes to long words, words to long words, words to bytes, long words to bytes, and long words to words. SOURCE/DESTINATION DESTINATION/SOURCE .. ..... ..... ..... ... . BYTE0 BYTE0 BYTE1 BYTE0 BYTE1 BYTE2 BYTE3 BYTE0 BYTE1 BYTE2 BYTE3 BYTE1 BYTE0 BYTE1 BYTE2 BYTE3 BYTE0 BYTE1 BYTE2 BYTE3 Figure 6-16. Packing and Unpacking of Operands MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-35 Freescale Semiconductor, Inc. For normal transfers aligned with the size and address, only two bus cycles are required for each transfer: a read from the source and a write to the destination. 6.9 DMA CHANNEL INITIALIZATION SEQUENCE The following paragraphs describe DMA channel initialization and operation. If the DMA capability of the MC68340 is being used, the initialization steps should be performed during the part initialization sequence. The mode operation steps should be performed to start a DMA transfer. The DONE pin requires an external pullup resistor even if operating only in the internal request mode. Freescale Semiconductor, Inc... 6.9.1 DMA Channel Configuration The following steps can be accomplished in any order when initializing the DMA channel. These steps need to be performed for each channel used. Module Configuration Register (MCR) * Clear the stop bit (STP) for normal operation. (Only one STP bit exists for both channels.) * Select whether to respond to or ignore FREEZE (FRZx bits). (Only one set of FRZx bits exits for both channels.) * If desired, enable the external data bus operation in single-address mode (SE bit). * Program the interrupt service mask to set the level below which interrupts are ignored during a DMA transfer (ISM bits). The channel will begin operation when the level of the CPU32 SR I2-I0 bits is less than or equal to the level of the DMA ISM bits. * Select the access privilege for the supervisor/user registers (SUPV bit). * Program the master arbitration ID (MAID) to establish priority on the IMB between both DMA channels. Note that the two DMA channels should have distinct MAIDs if both channels are being used. (If they are programmed the same, channel 1 has priority.) * Select the interrupt arbitration level for the DMA channel (IARB bits). (Only one set of IARB bits exits for both channels.) Interrupt Register (INTR) * Program the interrupt priority level for the channel interrupt (INTL bits). * Program the vector number for the channel interrupt (INTV bits). Channel Control Register (CCR) * If desired, enable the interrupt when breakpoint is recognized and the channel is the bus master (INTB bit). * If desired, enable the interrupt when done without an error condition (INTN bit). * If desired, enable the interrupt when the channel encounters an error (INTE bit). 6-36 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. * Select the direction of transfer if in single-address mode (ECO bit), or select which device generates requests if in dual-address mode. 6.9.1.1 DMA CHANNEL OPERATION IN SINGLE-ADDRESS MODE. The following steps are required to begin a DMA transfer in single-address mode. Channel Control Register (CCR) * Write a zero to the start bit (STR) to prevent the channel from starting the transfer prematurely. Freescale Semiconductor, Inc... * Select the amount by which to increment the source address for a read cycle (SAPI bit) or the destination address for a write cycle (DAPI bit). * Define the transfer size by selecting the source size for a read cycle (SSIZE field) or by selecting the destination size for a write cycle (DSIZE field). * Select external burst request mode or external cycle steal request mode (REQ field). * Set the S/D bit for signal-address transfer. Channel Status Register (CSR) * Clear the CSR by writing $7C into it. The DMA cannot be started until the DONE, BES, BED, CONF, and BRKP bits are cleared. Function Code Register (FCR) * Encode the source function code for a read cycle or the destination function code for a write cycle. Address Register (SAR or DAR) * Write the source address for a read cycle or the destination address for a write cycle. Byte Transfer Counter (BTC) * Encode the number of bytes to be transferred. Channel Control Register (CCR) * Write a one to the start bit (STR) to allow the transfer to begin. 6.9.1.2 DMA CHANNEL OPERATION IN DUAL-ADDRESS MODE. The following steps are required to begin a DMA transfer in dual-address mode. Channel Control Register (CCR) * Write a zero to the start bit (STR) to prevent the channel from starting the transfer prematurely. * Select the amount by which to increment the source and destination addresses (SAPI and DAPI bits). * Select the source and destination sizes (SSIZE and DSIZE fields). * Select internal request, external burst request mode, or external cycle steal request mode (REQ field). MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-37 Freescale Semiconductor, Inc. * If using internal request, select the amount of bus bandwidth to be used by the DMA (BB field). * Clear the S/D bit for dual-address transfer. Channel Status Register (CSR) * Clear the CSR by writing $7C into it. The DMA cannot be started until the DONE, BES, BED, CONF, and BRKP bits are cleared. Function Code Register (FCR) * Encode the source and destination function codes. Freescale Semiconductor, Inc... Address Registers (SAR and DAR) * Write the source and destination addresses. Byte Transfer Counter (BTC) * Encode the number of bytes to be transferred. Channel Control Register (CCR) * Write a one to the start bit (STR) to allow the transfer to begin. 6.9.2 DMA Channel Example Configuration Code The following are examples of configuration sequences for a DMA channel in single- and dual-addressing modes. *************************************************************************** * MC68340 basic DMA channel register initialization example code. * This code is used to initialize the 68340's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for external burst request generation, * single-address mode, long word size transfers. * Control signals are asserted on the DMA read cycle. *************************************************************************** Example 1: External Burst Request Generation, Single-Address Transfers. *************************************************************************** * SIM40 equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value *************************************************************************** * DMA Channel 1 equates DMACH1 EQU $780 Offset from MBAR for channel 1 regs DMAMCR1 EQU $0 MCR for channel 1 * Channel 1 register offsets from channel 1 base address 6-38 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... DMAINT1 DMACCR1 DMACSR1 DMAFCR1 DMASAR1 DMADAR1 DMABTC1 SARADD NUMBYTE EQU EQU EQU EQU EQU EQU EQU EQU EQU $4 $8 $A $B $C $10 $14 $10000 $C interrupt register channel 1 control register channel 1 status register channel 1 function code register channel 1 source address register channel 1 destination address register channel 1 byte transfer count register channel 1 source address number of bytes to transfer *************************************************************************** *************************************************************************** * Initialize DMA Channel 1 *************************************************************************** LEA MODBASE+DMACH1,A0 Pointer to channel 1 * Initialize DMA channel 1 MCR * Normal Operation, ignore FREEZE, single-address mode. ISM field at 2. Make * sure CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel startup. * Supervisor/user reg. unrestricted, MAID field at 7. IARB priority at 1. MOVE.W #$1271,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) * Initialize interrupt reg. * Interrupt priority at 7, interrupt vector at $42. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, user data space for source. MOVE.B #$99,DMAFCR1(A0) * Initialize source operand address * Source address is equal to $10000. MOVE.L SARADD,DMASAR1(A0) * Initialize the byte transfer count reg. * The number of bytes to be transferred is $C or 3 long words MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-39 Freescale Semiconductor, Inc. * No interrupts are enabled, source (read) cycle. Increment source * address, source size is long word, REQ is external burst request. * Single-address mode, start the DMA transfers. MOVE.W #$1823,DMACCR1(A0) Freescale Semiconductor, Inc... *************************************************************************** END *************************************************************************** Example 2: Internal Request Generation, Memory to Memory Transfers. *************************************************************************** * MC68340 basic DMA channel register initialization example code. * This code is used to initialize the 68340's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for internal request generation * memory to memory transfers. *************************************************************************** *************************************************************************** * SIM40 equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value *************************************************************************** * DMA Channel 1 equates DMACH1 EQU $780 Offset from MBAR for channel 1 regs DMAMCR1 EQU $0 MCR for channel 1 * Channel 1 register offsets from channel 1 base address DMAINT1 EQU $4 interrupt register channel 1 DMACCR1 EQU $8 control register channel 1 DMACSR1 EQU $A status register channel 1 DMAFCR1 EQU $B function code register channel 1 DMASAR1 EQU $C source address register channel 1 DMADAR1 EQU $10 destination address register channel 1 DMABTC1 EQU $14 byte transfer count register channel 1 SARADD EQU $6000 source address DARADD EQU $8000 destination address NUMBYTE EQU $E number of bytes to transfer *************************************************************************** *************************************************************************** * Initialize DMA Channel 1 *************************************************************************** LEA MODBASE+DMACH1,A0 Pointer to channel 1 * Initialize DMA channel 1 MCR 6-40 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. * Normal Operation, ignore FREEZE, dual-address mode. ISM field at 3. Make * sure CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel startup. * Supervisor/user reg. unrestricted, MAID field at 3. IARB priority at 4. MOVE.W #$0334,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) Freescale Semiconductor, Inc... * Initialize interrupt reg. * Interrupt priority at 7, interrupt vector at $42. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, supervisor data space for source and destination. MOVE.B #$DD,DMAFCR1(A0) * Initialize source operand address * Source address is equal to $6000. MOVE.L SARADD,DMASAR1(A0) * Initialize destination operand address * Destination address is equal to $8000. MOVE.L DARADD,DMADAR1(A0) * Initialize the byte transfer count reg. * The number of bytes to be transferred is $E or 7 words MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers * No interrupts are enabled, destination (write) cycle. Increment source and * destination addresses,source size is word, destination size is word. * REQ is internal. 100% of bus bandwidth, dual-address transfers, * start the DMA transfers. MOVE.W #$0E8D,DMACCR1(A0) *************************************************************************** END *************************************************************************** Example 3: Internal Request Generation, Memory Block Initialization. *************************************************************************** * MC68340 basic DMA channel register initialization example code. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-41 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... * This code is used to initialize the 68340's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for internal request generation * to perform a memory block initialization for 100 bytes. *************************************************************************** *************************************************************************** * SIM40 equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value *************************************************************************** * DMA Channel 1 equates DMACH1 EQU $780 Offset from MBAR for channel 1 regs DMAMCR1 EQU $0 MCR for channel 1 * Channel 1 register offsets from channel 1 base address DMAINT1 EQU $4 interrupt register channel 1 DMACCR1 EQU $8 control register channel 1 DMACSR1 EQU $A status register channel 1 DMAFCR1 EQU $B function code register channel 1 DMASAR1 EQU $C source address register channel 1 DMADAR1 EQU $10 destination address register channel 1 DMABTC1 EQU $14 byte transfer count register channel 1 SARADD EQU $6000 source address DARADD EQU $8000 destination address NUMBYTE EQU $64 number of bytes to transfer *************************************************************************** *************************************************************************** * Initialize DMA Channel 1 *************************************************************************** LEA MODBASE+DMACH1,A0 Pointer to channel 1 * Initialize DMA channel 1 MCR * Normal Operation, ignore FREEZE, dual-address mode. ISM field at 3. Make * sure CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel * startup.Supervisor/user reg. unrestricted, MAID field at 3. * IARB priority at 4. MOVE.W #$0334,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) * Initialize interrupt reg. * Interrupt priority at 7, interrupt vector at $42. 6-42 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, supervisor data space for source and destination. MOVE.B #$DD,DMAFCR1(A0) Freescale Semiconductor, Inc... * Initialize source operand address * Source address is equal to $6000. MOVE.L SARADD,DMASAR1(A0) * Initialize destination operand address * Destination address is equal to $8000. MOVE.L DARADD,DMADAR1(A0) * Initialize the byte transfer count register * The number of bytes to be transferred is $64 or 50 words MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers * No interrupts are enabled, destination (write) cycle. * Source address is not incremented. Increment the destination address. * Source size is word, destination size is word. REQ is internal. * 100% of bus bandwidth, dual-address transfers, start the DMA transfers. MOVE.W #$068D,DMACCR1(A0) *************************************************************************** END *************************************************************************** Example 4: Cycle Steal Request Generation, Dual-Address Transfers. *************************************************************************** * MC68340 basic DMA channel register initialization example code. * This code is used to initialize the 68340's internal DMA channel * registers, providing basic functions for operation. * The code sets up channel 1 for external cycle steal request generation, * dual-address transfers. DMA 16-bit wide data from an odd address to an * even address. Control signals are asserted on the DMA read cycle. *************************************************************************** *************************************************************************** * SIM40 equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-43 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... *************************************************************************** * DMA Channel 1 equates DMACH1 EQU $780 Offset from MBAR for channel 1 regs DMAMCR1 EQU $0 MCR for channel 1 * Channel 1 register offsets from channel 1 base address DMAINT1 EQU $4 interrupt register channel 1 DMACCR1 EQU $8 control register channel 1 DMACSR1 EQU $A status register channel 1 DMAFCR1 EQU $B function code register channel 1 DMASAR1 EQU $C source address register channel 1 DMADAR1 EQU $10 destination address register channel 1 DMABTC1 EQU $14 byte transfer count register channel 1 SARADD EQU $6001 source address is an ODD address DARADD EQU $10000 destination address is and EVEN address NUMBYTE EQU $14 number of bytes to transfer *************************************************************************** *************************************************************************** * Initialize DMA Channel 1 *************************************************************************** LEA MODBASE+DMACH1,A0 Pointer to channel 1 * Initialize DMA channel 1 MCR * Normal Operation, ignore FREEZE, dual-address mode. ISM field at 0. Make * CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel startup. * Supervisor/user reg. unrestricted, MAID field at 4. IARB priority at 8. MOVE.W #$00C8,(A0) * Clear channel control reg. * Clear STR (start) bit to prevent the channel from starting a transfer early. CLR.W DMACCR1(A0) * Initialize interrupt reg. * Interrupt priority at 7, interrupt vector at $42. MOVE.W #$0742,DMAINT1(A0) * Initialize channel status reg. * Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup. MOVE.B #$7C,DMACSR1(A0) * Initialize function code reg. * DMA space, supervisor data space for source and destination. MOVE.B #$DD,DMAFCR1(A0) * Initialize source operand address 6-44 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. * Source address is equal to $6001, and odd address. MOVE.L SARADD,DMASAR1(A0) * Initialize destination operand address * Destination address is equal to $10000, and even address. MOVE.L DARADD,DMADAR1(A0) Freescale Semiconductor, Inc... * Initialize the byte transfer count register * The number of bytes to be transferred is $14 or 20 bytes MOVE.L NUMBYTE,DMABTC1(A0) * Channel control reg. init. and Start DMA transfers * No interrupts are enabled, source (read) cycle. * Increment the source and destination addresses. * Source size is byte, destination size is word. REQ is external cycle steal. * dual-address transfers, start the DMA transfers. MOVE.W #$1DB1,DMACCR1(A0) *************************************************************************** END *************************************************************************** MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-45 Freescale Semiconductor, Inc. SECTION 7 SERIAL MODULE Freescale Semiconductor, Inc... The MC68340 serial module is a dual universal asynchronous/synchronous receiver/transmitter that interfaces directly to the CPU32 processor via the intermodule bus (IMB). The serial module, shown in Figure 7-1, consists of the following major functional areas: * Two Independent Serial Communication Channels (A and B) * Baud Rate Generator Logic * Internal Channel Control Logic * Interrupt Control Logic SERIAL COMMUNICATIONS CHANNELS A AND B BAUD RATE GENERATOR LOGIC CTSA RTSA RxDA TxDA RxRDYA TxRDYA CTSB RTSB RxDB TxDB ..... ..... . X1 X2 SCLK INTERNAL CHANNEL CONTROL LOGIC INTERRUPT CONTROL LOGIC Figure 7-1. Simplified Block Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-1 Freescale Semiconductor, Inc. 7.1 MODULE OVERVIEW Features of the serial module are as follows: * Two, Independent, Full-Duplex Asynchronous/Synchronous Receiver/Transmitter Channels * Maximum Data Transfer Rate: --1x mode: 3 Mbps @ 8.39 MHz CLKOUT, 9.8 Mbps @25 MHz CLKOUT --16x mode: 188 kbps @ 8.39 MHz CLKOUT, 612 kbps @25 MHz CLKOUT * Quadruple-Buffered Receiver Freescale Semiconductor, Inc... * Double-Buffered Transmitter * Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable from: --19 Fixed Rates: 50 to 76.8k Baud --External 1x Clock or 16x Clock * Programmable Data Format: --Five to Eight Data Bits Plus Parity --Odd, Even, No Parity, or Force Parity --Nine-Sixteenths to Two Stop Bits Programmable in One-Sixteenth Bit Increments * Programmable Channel Modes: --Normal (Full Duplex) --Automatic Echo --Local Loopback --Remote Loopback * Automatic Wakeup Mode for Multidrop Applications * Seven Maskable Interrupt Conditions * Parity, Framing, and Overrun Error Detection * False-Start Bit Detection * Line-Break Detection and Generation * Detection of Breaks Originating in the Middle of a Character * Start/End Break Interrupt/Status * On-Chip Crystal Oscillator 7-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 7.1.1 Serial Communication Channels A and B Each communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter using an operating frequency independently selected from a baud rate generator or an external clock input. Freescale Semiconductor, Inc... The transmitter accepts parallel data from the IMB, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits, then outputs a composite serial data stream on the channel transmitter serial data output (TxDx). Refer to 7.3.2.1 Transmitter for additional information. The receiver accepts serial data on the channel receiver serial data input (RxDx), converts it to parallel format, checks for a start bit, stop bit, parity (if any), or break condition, and transfers the assembled character onto the IMB during read operations. Refer to 7.3.2.2 Receiver for additional information. 7.1.2 Baud Rate Generator Logic The crystal oscillator operates directly from a 3.6864-MHz crystal connected across the X1 input and the X2 output or from an external clock of the same frequency connected to X1. The clock serves as the basic timing reference for the baud rate generator and other internal circuits. The baud rate generator operates from the oscillator or external TTL clock input and is capable of generating 19 commonly used data communication baud rates ranging from 50 to 76.8k by producing internal clock outputs at 16 times the actual baud rate. Refer to 7.2 Serial Module Signal Definitions and 7.3.1 Baud Rate Generator for additional information. The external clock input (SCLK), which bypasses the baud rate generator, provides a synchronous clock mode of operation when used as a divide-by-1 clock and an asynchronous clock mode when used as a divide-by-16 clock. The external clock input allows the user to use SCLK as the only clock source for the serial module if multiple baud rates are not required. 7.1.3 Internal Channel Control Logic The serial module receives operation commands from the host and, in turn, issues appropriate operation signals to the internal serial module control logic. This mechanism allows the registers within the module to be accessed and various commands to be performed. Refer to 7.4 Register Description and Programming for additional information. 7.1.4 Interrupt Control Logic Seven interrupt request (IRQ7-IRQ1) signals are provided to notify the CPU32 that an interrupt has occurred. These interrupts are described in 7.4 Register Description and Programming. The interrupt status register (ISR) is read by the CPU32 to determine all MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-3 Freescale Semiconductor, Inc. currently active interrupt conditions. The interrupt enable register (IER) is programmable to mask any events that can cause an interrupt. 7.1.5 Comparison of Serial Module to MC68681 The serial module is code compatible with the MC68681 with some modifications. The following paragraphs describe the differences. The programming model is slightly altered. The supervisor/user block in the MC68340 closely follows the MC68681. The supervisor-only block has the following changes: Freescale Semiconductor, Inc... * The interrupt vector register is moved from supervisor/user to supervisor only at a new address. * MR2A and MR2B are moved from a hidden address location to a location at the bottom of the programming model. The timer/counter is eliminated as well as all associated command and status registers. Only certain output port pins are available. There are no IP pins on the MC68340. RxRTS and TxRTS are more automated on the MC68340. The XTAL_RDY bit in the ISR should be polled until it is cleared to prevent an unstable frequency from being applied to the baud rate generator. The following code is an example: if (XTAL_RDY==0) begin write CSR end else begin wait jump loop end 7.2 SERIAL MODULE SIGNAL DEFINITIONS The following paragraphs contain a brief description of the serial module signals. Figure 72 shows both the external and internal signal groups. NOTE The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 7-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. ADDRESS BUS IMB INTERFACE SIGNALS X1 CONTROL DATA DATA BUS MUX S E R I A L BAUD RATE GENERATOR LOGIC X2 SCLK CHANNEL A D7-D0 M O D U L E FOUR-CHARACTER RECEIVE BUFFER RxDA TWO-CHARACTER TRANSMIT BUFFER TxDA RTSA I N T E R N A L B U S CTSA TxRDYA EXTERNAL INTERFACE SIGNALS Freescale Semiconductor, Inc... DATA BUS D15-D0 INTERNAL CONTROL LOGIC RxRDYA ..... ..... . .. CHANNEL B FOUR-CHARACTER RECEIVE BUFFER RxDB TWO-CHARACTER TRANSMIT BUFFER TxDB RTSB CTSB Figure 7-2. External and Internal Interface Signals 7.2.1 Crystal Input or External Clock (X1) This input is one of two connections to a crystal or a single connection to an external clock. A crystal or an external clock signal, at 3.6864 MHz, must be supplied when using the baud rate generator. If a crystal is used, a capacitor of approximately 10 pF should be connected from this signal to ground. If this input is not used, it must be connected to VCC or GND. Refer to Section 10 Applications for an example of a clock driver circuit. 7.2.2 Crystal Output (X2) This output is the additional connection to a crystal. If a crystal is used, a capacitor of approximately 5 pF should be connected from this signal to ground. If an external TTLlevel clock is used on X1, the X2 output must be left open. Refer to Section 10 Applications for an example of a clock driver circuit. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-5 Freescale Semiconductor, Inc. 7.2.3 External Input (SCLK) This input can be used as the clock input for channel A and/or channel B and is programmable in the clock-select registers (CSR). When used as the receiver clock, received data is sampled on the rising edge of the clock. When used as the transmitter clock, data is output on the falling edge of the clock. If this input is not used, it must be connected to VCC or GND. 7.2.4 Channel A Transmitter Serial Data Output (TxDA) Freescale Semiconductor, Inc... This signal is the transmitter serial data output for channel A. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal on the falling edge of the clock source, with the least significant bit transmitted first. 7.2.5 Channel A Receiver Serial Data Input (RxDA) This signal is the receiver serial data input for channel A. Data received on this signal is sampled on the rising edge of the clock source, with the least significant bit received first. 7.2.6 Channel B Transmitter Serial Data Output (TxDB) This signal is the transmitter serial data output for channel B. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal at the falling edge of the clock source, with the least significant bit transmitted first. 7.2.7 Channel B Receiver Serial Data Input (RxDB) This signal is the receiver serial data input for channel B. Data on this signal is sampled on the rising edge of the clock source, with the least significant bit received first. 7.2.8 Channel A Request-To-Send ( RTSA) This active-low output signal is programmable as the channel A request-to-send or as a dedicated parallel output. 7.2.8.1 RTSA . When used for this function, this signal can be programmed to be automatically negated and asserted by either the receiver or transmitter. When connected to the clear-to-send ( CTS) input of a transmitter, this signal can be used to control serial data flow. 7.2.8.2 OP0. When used for this function, this output is controlled by bit 0 in the output port data register (OP). 7.2.9 Channel B Request-To-Send ( RTSB) This active-low output signal is programmable as the channel B request-to-send or as a dedicated parallel output. 7-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 7.2.9.1 RTSB . When used for this function, this signal can be programmed to be automatically negated and asserted by either the receiver or transmitter. When connected to the CTS input of a transmitter, this signal can be used to control serial data flow. 7.2.9.2 OP1. When used for this function, this output is controlled by bit 1 in the OP. 7.2.10 Channel A Clear-To-Send (CTSA) This active-low input is the channel A clear-to-send. 7.2.11 Channel B Clear-To-Send (CTSB) Freescale Semiconductor, Inc... This active-low input is the channel B clear-to-send. 7.2.12 Channel A Transmitter Ready (TRDYA) This active-low output signal is programmable as the channel A transmitter ready or as a dedicated parallel output, and cannot be masked by the interrupt enable register (IER). 7.2.12.1 TRDYA. When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register (SRA). This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character. 7.2.12.2 OP6. When used for this function, this output is controlled by bit 6 in the OP. 7.2.13 Channel A Receiver Ready ( RRDYA) This active-low output signal is programmable as the channel A receiver ready, channel A FIFO full indicator, or a dedicated parallel output, and cannot be masked by the IER. 7.2.13.1 RRDYA. When used for this function, this signal reflects the complement of the status of bit 1 of the ISR. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver contains a character. 7.2.13.2 FFULLA. When used for this function, this signal reflects the complement of the status of bit 1 of the ISR. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full. 7.2.13.3 OP4. When used for this function, this output is controlled by bit 4 in the OP. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-7 Freescale Semiconductor, Inc. 7.3 OPERATION The following paragraphs describe the operation of the baud rate generator, transmitter and receiver, and other functional operating modes of the serial module. 7.3.1 Baud Rate Generator Freescale Semiconductor, Inc... The baud rate generator consists of a crystal oscillator, baud rate generator, and clock selectors (see Figure 7-3). The crystal oscillator operates directly from a 3.6864-MHz crystal or from an external clock of the same frequency. The SCLK input bypasses the baud rate generator and provides a synchronous clock mode of operation when used as a divide-by-1 clock and an asynchronous clock mode when used as a divide-by-16 clock. The clock is selected by programming the clock-select register (CSR) for each channel. BAUD RATE GENERATOR LOGIC CRYSTAL OSCILLATOR EXTERNAL INTERFACE ..... ..... . ... . X1 BAUD RATE GENERATOR X2 SCLK CLOCK SELECTORS Figure 7-3. Baud Rate Generator Block Diagram 7.3.2 Transmitter and Receiver Operating Modes The functional block diagram of the transmitter and receiver, including command and operating registers, is shown in Figure 7-4. The paragraphs that follow contain descriptions for both these functions in reference to this diagram. For detailed register information, refer to 7.4 Register Description and Programming. 7-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. CHANNEL A EXTERNAL INTERFACE COMMAND REGISTER (CRA) W MODE REGISTER A (MR1A) R/W MODE REGISTER B (MR2A) R/W STATUS REGISTER (SRA) Freescale Semiconductor, Inc... TRANSMIT BUFFER (TBA) (2 REGISTERS) R TRANSMIT HOLDING REGISTER W TxDA TRANSMIT SHIFT REGISTER RECEIVER HOLDING REGISTER 1 FIFO R RECEIVER HOLDING REGISTER 2 RECEIVE BUFFER (RBA) (4 REGISTERS) RECEIVER HOLDING REGISTER 3 RxDA RECEIVER SHIFT REGISTER CHANNEL B COMMAND REGISTER (CRB) TRANSMIT BUFFER (TBB) (2 REGISTERS) W MODE REGISTER 1 (MR1B) R/W MODE REGISTER 2 (MR2B) R/W STATUS REGISTER (SRB) R TRANSMIT HOLDING REGISTER W TxDB TRANSMIT SHIFT REGISTER RECEIVER HOLDING REGISTER 1 R FIFO RECEIVER HOLDING REGISTER 2 RECEIVE BUFFER (RBB) (4 REGISTERS) RECEIVER HOLDING REGISTER 3 RECEIVER SHIFT REGISTER RxDB NOTE: R/W = READ/WRITE R = READ W = WRITE ..... ..... . ... . . . Figure 7-4. Transmitter and Receiver Functional Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-9 Freescale Semiconductor, Inc. 7.3.2.1 TRANSMITTER. The transmitters are enabled through their respective command registers (CR) located within the serial module. The serial module signals the CPU32 when it is ready to accept a character by setting the transmitter-ready bit (TxRDY) in the channel's status register (SR). Functional timing information for the transmitter is shown in Figure 7-5. Freescale Semiconductor, Inc... The transmitter converts parallel data from the CPU32 to a serial bit stream on TxDx. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Data is shifted from the transmitter output on the falling edge of the clock source. C1 IN TRANSMISSION TxDx C1 C2 C3 C4 W W W W W W W W C1 C2 C3 START BREAK C4 STOP BREAK C5 NOT TRANSMITTED C6 BREAK C6 TRANSMITTER ENABLED TxRDY (SR2) CS CTS1 RTS 2 MANUALLY ASSERTED BY BIT- SET COMMAND MANUALLY ASSERTED NOTES: 1. TIMING SHOWN FOR MR2(4) = 1 2. TIMING SHOWN FOR MR2(5) = 1 3. C N = TRANSMIT CHARACTER 4. W = WRITE Figure 7-5. Transmitter Timing Diagram Following transmission of the stop bits, if a new character is not available in the transmitter holding register, the TxDx output remains high ('mark' condition), and the transmitter empty bit (TxEMP) in the SR is set. Transmission resumes and the TxEMP bit is cleared when the CPU32 loads a new character into the transmitter buffer (TB). If a disable command is sent to the transmitter, it continues operating until the character in the 7-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. transmit shift register, if any, is completely sent out. If the transmitter is reset through a software command, operation ceases immediately (refer to 7.4.1.7 Command Register (CR)). The transmitter is re-enabled through the CR to resume operation after a disable or software reset. Freescale Semiconductor, Inc... If clear-to-send operation is enabled, CTS must be asserted for the character to be transmitted. If CTS is negated in the middle of a transmission, the character in the shift register is transmitted, and TxDx remains in the 'mark' state until CTS is asserted again. If the transmitter is forced to send a continuous low condition by issuing a send break command, the state of CTS is ignored by the transmitter. The transmitter can be programmed to automatically negate request-to-send (RTS) outputs upon completion of a message transmission. If the transmitter is programmed to operate in this mode, RTS must be manually asserted before a message is transmitted. In applications in which the transmitter is disabled after transmission is complete and RTS is appropriately programmed, RTS is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually re-enabled by reasserting RTS before the next message is to be sent. 7.3.2.2 RECEIVER. The receivers are enabled through their respective CRs located within the serial module. Functional timing information for the receiver is shown in Figure 7-6. The receiver looks for a high-to-low (mark-to-space) transition of the start bit on RxDx. When a transition is detected, the state of RxDx is sampled each 16x clock for eight clocks, starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If RxDx is sampled high, the start bit is invalid, and the search for the valid start bit begins again. If RxDx is still low, a valid start bit is assumed, and the receiver continues to sample the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the RxDx input is sampled on the rising edge of the programmed clock source. The least significant bit is received first. The data is then transferred to a receiver holding register, and the RxRDY bit in the appropriate SR is set. If the character length is less than eight bits, the most significant unused bits in the receiver holding register are cleared. After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a nonzero character is received without a stop bit (framing error) and RxDx remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit is detected. The parity error (PE), framing error (FE), overrun error (OE), and received break (RB) conditions (if any) set error and break flags in the appropriate SR at the received character boundary and are valid only when the RxRDY bit in the SR is set. If a break condition is detected (RxDx is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register, and the RB and RxRDY bits in the SR are set. The RxDx signal must return to a high condition for at least one-half bit time before a search for the next start bit begins. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-11 Freescale Semiconductor, Inc. RxD C2 C1 C3 C4 C5 C6 C8 C7 C6, C7, C8 ARE LOST RECEIVER ENABLED RxRDY (SR0) Freescale Semiconductor, Inc... FFULL (SR1) RxRDYA CS R R R R R R R R STATUS DATA STATUS DATA STATUS DATA STATUS DATA C1 C2 C3 C4 C5 LOST OVERRUN (SR4) 1 RTS RESET BY COMMAND OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1 2. Timing shown for OPCR(4) = 1 and MR1(6) = 0 3. R = Read 4. CN = Received Character Figure 7-6. Receiver Timing Diagram The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. When the break begins in the middle of a character, the receiver places the damaged character in the receiver first-in-first-out (FIFO) stack and sets the corresponding error conditions and RxRDY bit in the SR. Then, if the break persists until the next character time, the receiver places an all-zero character into the receiver FIFO and sets the corresponding RB and RxRDY bits in the SR. 7.3.2.3 FIFO STACK. The FIFO stack is used in each channel's receiver buffer logic. The stack consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the RxDx (refer to Figure 7-4). Data is 7-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the CPU32 is quadruple buffered. Freescale Semiconductor, Inc... In addition to the data byte, three status bits, PE, FE, and RB, are appended to each data character in the FIFO; OE is not appended. By programming the ERR bit in the channel's mode register (MR1), status is provided in character or block modes. The RxRDY bit in the SR is set whenever one or more characters are available to be read by the CPU32. A read of the receiver buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are 'popped', and new data can be added at the bottom of the stack by the receiver shift register. The FIFO-full status bit (FFULL) is set if all three stack positions are filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt. In the character mode, status provided in the SR is given on a character-by-character basis and thus applies only to the character at the top of the FIFO. In the block mode, the status provided in the SR is the logical OR of all characters coming to the top of the FIFO stack since the last reset error command. A continuous logical OR function of the corresponding status bits is produced in the SR as each character reaches the top of the FIFO stack. The block mode is useful in applications where the software overhead of checking each character's error cannot be tolerated. In this mode, entire messages are received, and only one data integrity check is performed at the end of the message. This mode allows a data-reception speed advantage, but does have a disadvantage since each character is not individually checked for error conditions by software. If an error occurs within the message, the error is not recognized until the final check is performed, and no indication exists as to which character in the message is at fault. In either mode, reading the SR does not affect the FIFO. The FIFO is 'popped' only when the receive buffer is read. The SR should be read prior to reading the receive buffer. If all three of the FIFO's receiver holding registers are full when a new character is received, the new character is held in the receiver shift register until a FIFO position is available. If an additional character is received during this state, the contents of the FIFO are not affected. However, the character previously in the receiver shift register is lost, and the OE bit in the SR is set when the receiver detects the start bit of the new overrunning character. To support control flow capability, the receiver can be programmed to automatically negate and assert RTS . When in this mode, RTS is automatically negated by the receiver when a valid start bit is detected and the FIFO stack is full. When a FIFO position becomes available, RTS is asserted by the receiver. Using this mode of operation, overrun errors are prevented by connecting the R T S to the CTS input of the transmitting device. If the FIFO stack contains characters and the receiver is disabled, the characters in the FIFO can still be read by the CPU32. If the receiver is reset, the FIFO stack and all receiver status bits, corresponding output ports, and interrupt request are reset. No additional characters are received until the receiver is re-enabled. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-13 Freescale Semiconductor, Inc. 7.3.3 Looping Modes Each serial module channel can be configured to operate in various looping modes as shown in Figure 7-7. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs with further information available in 7.4 Register Description and Programming. Freescale Semiconductor, Inc... The channel's transmitter and receiver should both be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. 7.3.3.1 AUTOMATIC ECHO MODE. In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU32-to-receiver communication continues normally, but the CPU32-to-transmitter link is disabled. While in this mode, received data is clocked on the receiver clock and retransmitted on TxDx. The receiver must be enabled, but the transmitter need not be enabled. Since the transmitter is not active, the SR TxEMP and TxRDY bits are inactive, and data is transmitted as it is received. Received parity is checked, but not recalculated for transmission. Character framing is also checked, but stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected. 7.3.3.2 LOCAL LOOPBACK MODE. In this mode, TxDx is internally connected to RxDx. This mode is useful for testing the operation of a local serial module channel by sending data to the transmitter and checking data assembled by the receiver. In this manner, correct channel operations can be assured. Also, both transmitter and CPU32-to-receiver communications continue normally in this mode. While in this mode, the RxDx input data is ignored, the TxDx is held marking, and the receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be enabled. 7.3.3.3 REMOTE LOOPBACK MODE. In this mode, the channel automatically transmits received data on the TxDx output on a bit-by-bit basis. The local CPU32-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. While in this mode, the receiver clock is used for the transmitter. Since the receiver is not active, received data cannot be read by the CPU32, and the error status conditions are inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected. 7-14 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. RxDx INPUT Rx CPU DISABLED Tx DISABLED TxDx OUTPUT (a) Automatic Echo Rx DISABLED RxDx INPUT DISABLED TxDx OUTPUT Freescale Semiconductor, Inc... CPU Tx (b) Local Loopback DISABLED Rx DISABLED RxDx INPUT DISABLED Tx DISABLED TxDx OUTPUT CPU (c) Remote Loopback Figure 7-7. Looping Modes Functional Diagram 7.3.4 Multidrop Mode A channel can be programmed to operate in a wakeup mode for multidrop or multiprocessor applications. Functional timing information for the multidrop mode is shown in Figure 7-8. The mode is selected by setting bits 3 and 4 in mode register 1 (MR1). This mode of operation allows the master station to be connected to several slave stations (maximum of 256). In this mode, the master transmits an address character followed by a block of data characters targeted for one of the slave stations. The slave stations have their channel receivers disabled. However, they continuously monitor the data stream sent out by the master station. When an address character is sent by the master, the slave receiver channel notifies its respective CPU by setting the RxRDY bit in the SR and generating an interrupt (if programmed to do so). Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. Slave stations not addressed continue to monitor the data stream for the next address character. Data fields in the data stream are separated by an address character. After a slave receives a block of data, the slave station's CPU disables the receiver and initiates the process again. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-15 Freescale Semiconductor, Inc. RxD C2 C1 C3 C4 C5 C6 C8 C7 C6, C7, C8 ARE LOST RECEIVER ENABLED RxRDY (SR0) Freescale Semiconductor, Inc... FFULL (SR1) RxRDYA CS R R R R R R R R STATUS DATA STATUS DATA STATUS DATA STATUS DATA C1 C2 C3 C4 C5 LOST OVERRUN (SR4) 1 RTS RESET BY COMMAND OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1 2. Timing shown for OPCR(4) = 1 and MR1(6) = 0 3. R = Read 4. CN = Received Character Figure 7-8. Multidrop Mode Timing Diagram A transmitted character from the master station consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. The A/D bit identifies the type of character being transmitted to the slave station. The character is interpreted as an address character if the A/D bit is set or as a data character if the A/D bit is cleared. The polarity of the A/D bit is selected by programming bit 2 of the MR1. The MR1 should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer. In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the 7-16 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. RxRDY bit and loads the character into the receiver holding register FIFO stack provided the received A/D bit is a one (address tag). The character is discarded if the received A/D bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU32 via the receiver holding register stack during read operations. Freescale Semiconductor, Inc... In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into the status portion of the stack normally used for a parity error (SR bit 5). Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may still contain error detection and correction information. One way to provide error detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. 7.3.5 Bus Operation This section describes the operation of the IMB during read, write, and interrupt acknowledge cycles to the serial module. All serial module registers must be accessed as bytes. 7.3.5.1 READ CYCLES. The serial module is accessed by the CPU32 with no wait states. The serial module responds to byte reads. Reserved registers return logic zero during reads. 7.3.5.2 WRITE CYCLES. The serial module is accessed by the CPU32 with no wait states. The serial module responds to byte writes. Write cycles to read-only registers and reserved registers complete in a normal manner without exception processing; however, the data is ignored. 7.3.5.3 INTERRUPT ACKNOWLEDGE CYCLES. The serial module is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus, the interrupt vector register (IVR) must be initialized. If the IVR is not initialized, a spurious interrupt exception will be taken if interrupts are generated. 7.4 REGISTER DESCRIPTION AND PROGRAMMING This section contains a detailed description of each register and its specific function as well as flowcharts of basic serial module programming. 7.4.1 Register Description The operation of the serial module is controlled by writing control bytes into the appropriate registers. A list of serial module registers and their associated addresses are shown in Figure 7-9. The mode, status, command, and clock-select registers are duplicated for each channel to provide independent operation and control. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-17 Freescale Semiconductor, Inc. NOTE Freescale Semiconductor, Inc... All serial module registers are only accessible as bytes. The contents of the mode registers (MR1 and MR2), clock-select register (CSR), and the auxiliary control register (ACR) bit 7 should only be changed after the receiver/transmitter is issued a software RESET command--i.e., channel operation must be disabled. Care should also be taken if the register contents are changed during receiver/transmitter operations, as undesirable results may be produced. In the registers discussed in the following pages, the numbers in the upper right-hand corner indicate the offset of the register from the base address specified in the module base address register (MBAR) in the SIM40. The numbers above the register description represent the bit position in the register. The register description contains the mnemonic for the bit. The values shown below the register description are the values of those register bits after a hardware reset. A value of U indicates that the bit value is unaffected by reset. The read/write status and the access privilege are shown in the last line. NOTE A CPU32 RESET instruction will not affect the MCR, but will reset all the other serial module registers as though a hardware reset had occurred. The module is enabled when the STP bit in the MCR is cleared. The module is disabled when the STP bit in the MCR is set. 7-18 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Address Register Read (R/W = 1) Register Write (R/W = 0) 700 FC S1 MCR (HIGH BYTE) MCR (HIGH BYTE) 701 S 702 S MCR (LOW BYTE) DO NOT ACCESS3 MCR (LOW BYTE) DO NOT ACCESS3 703 S DO NOT ACCESS3 DO NOT ACCESS3 704 S INTERRUPT LEVEL (ILR) NTERRUPT LEVEL (ILR) 705 S INTERRUPT VECTOR (IVR) INTERRUPT VECTOR (IVR) 710 S/U2 MODE REGISTER 1A (MR1A) MODE REGISTER 1A (MR1A) 711 S/U S/U STATUS REGISTER A (SRA) DO NOT ACCESS3 CLOCK-SELECT REGISTER A (CSRA) 712 713 S/U RECEIVER BUFFER A (RBA) TRANSMITTER BUFFER A (TBA) 714 S/U INPUT PORT CHANGE REGISTER (IPCR) AUXILIARY CONTROL REGISTER (ACR) 715 S/U 716 S/U INTERRUPT STATUS REGISTER (ISR) DO NOT ACCESS3 INTERRUPT ENABLE REGISTER (IER) DO NOT ACCESS3 717 S/U DO NOT ACCESS3 DO NOT ACCESS3 718 S/U MODE REGISTER 1B (MR1B) MODE REGISTER 1B (MR1B) 719 S/U S/U STATUS REGISTER B (SRB) DO NOT ACCESS3 CLOCK-SELECT REGISTER B (CSRB) 71A 71B S/U 71C S/U RECEIVER BUFFER B (RBB) DO NOT ACCESS3 TRANSMITTER BUFFER B (TBB) DO NOT ACCESS3 71D S/U 71E S/U INPUT PORT REGISTER (IP) DO NOT ACCESS3 OUTPUT PORT CONTROL REGISTER (OPCR) OUTPUT PORT (OP)4 BIT SET 71F S/U DO NOT ACCESS3 OUTPUT PORT (OP)4 BIT RESET 720 S/U MODE REGISTER 2A (MR2A) MODE REGISTER 2A (MR2A) 721 S/U MODE REGISTER 2B (MR2B) MODE REGISTER 2B (MR2B) COMMAND REGISTER A (CRA) COMMAND REGISTER B (CRB) NOTES: 1. S = Register permanently defined as supervisor-only access 2. S/U = Register programmable as either supervisor or user access 3. A read or write to these locations currently has no effect. 4. Address-triggered commands Figure 7-9. Serial Module Programming Model 7.4.1.1 MODULE CONFIGURATION REGISTER (MCR). The MCR controls the serial module configuration. This register can be either read or written when the module is enabled and is in the supervisor state. The MCR is not affected by a CPU32 RESET instruction. Only the MCR can be accessed when the module is disabled (i.e., the STP bit in the MCR is set). MCR $700 15 14 13 12 11 10 9 8 7 6 5 4 STP FRZ1 FRZ0 ICCS 0 0 0 0 SUPV 0 0 0 RESET: 0 0 0 0 0 0 0 0 1 0 0 0 Read/Write MOTOROLA 3 2 1 0 0 0 IARB 0 0 Supervisor Only MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-19 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... STP--Stop Mode Bit 1 = The serial module will be disabled. Setting the STP bit stops all clocks within the serial module (including the crystal or external clock and SCLK), except for the clock from the IMB. The clock from the IMB remains active to allow CPU32 access to the MCR. The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to serial module registers while in stop mode produce a bus error. The serial module should be disabled in a known state prior to setting the STP bit; otherwise, unpredictable results may occur. The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption. 0 = The serial module is enabled and will operate in normal mode. When STP = 0, make sure the external crystal is stable (XTAL_RDY bit (bit 3) of the interrupt status register (ISR) is zero) before continuing. NOTE The serial module should be disabled (i.e., the STP bit in the MCR is set) before executing the LPSTOP instruction to obtain the lowest power consumption. The X1/X2 oscillator will continue to run during LPSTOP if STP = 0. FRZ1-FRZ0--Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB when the CPU32 has entered background debug mode. Table 7-1 lists the action taken for each combination of bits. Table 7-1. FRZx Control Bits FRZ1 FRZ0 0 0 Ignore FREEZE Action 0 1 Reserved (FREEZE Ignored) 1 0 Freeze on Character Boundary 1 1 Freeze on Character Boundary If FREEZE is asserted, channel A and channel B freeze independently of each other. The transmitter and receiver freeze at character boundaries. The transmitter does not freeze in the send break mode. Communications can be lost if the channel is not programmed to support flow control. See Section 5 CPU32 for more information on FREEZE. ICCS--Input Capture Clock Select 1 = Selects SCLK as the clear-to-send input capture clock for both channels. Clearto-send operation is enabled by setting bit 4 in MR2. The data is captured on the CTS pins on the rising edge of the clock. 0 = The crystal clock is the clear-to-send input capture clock for both channels. 7-20 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Bits 11-8, 6-4--Reserved Freescale Semiconductor, Inc... SUPV--Supervisor/User The value of this bit has no affect on registers permanently defined as supervisor only. 1 = The serial module registers, which are defined as supervisor or user, reside in supervisor data space and are only accessible from supervisor programs. 0 = The serial module registers, which are defined as supervisor or user, reside in user data space and are accessible from either supervisor or user programs. IARB3-IARB0--Interrupt Arbitration Bits Each module that generates interrupts has an IARB field. These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. The reset value of the IARB field is $0, which prevents this module from arbitrating during the interrupt acknowledge cycle. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). 7.4.1.2 INTERRUPT LEVEL REGISTER (ILR). The ILR contains the priority level for the serial module interrupt request. When the serial module is enabled (i.e., the STP bit in the MCR is cleared), this register can be read or written to at any time while in supervisor mode. ILR $704 7 6 5 4 3 2 1 0 0 0 0 0 0 IL2 IL1 IL0 RESET: 0 0 0 0 0 0 0 0 Read/Write Supervisor Only Bits 7-3--Reserved IL2-IL0--Interrupt Level Bits Each module that can generate interrupts has an interrupt level field. The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal. The CPU32 uses this value to determine servicing priority. The hardware reset value of $00 will not generate any interrupts. See Section 5 CPU32 for more information. 7.4.1.3 INTERRUPT VECTOR REGISTER (IVR). The IVR contains the 8-bit vector number of the interrupt. When the serial module is enabled (i.e., the STP bit in the MCR is cleared), this register can be read or written to at any time while in supervisor mode. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-21 Freescale Semiconductor, Inc. IVR $705 7 6 5 4 3 2 1 0 IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 RESET: 0 0 0 0 1 1 1 1 Read /Write Supervisor Only Freescale Semiconductor, Inc... IVR7-IVR0--Interrupt Vector Bits Each module that generates interrupts has an interrupt vector field. This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The IVR is reset to $0F, which indicates an uninitialized interrupt condition. See Section 5 CPU32 for more information. 7.4.1.4 MODE REGISTER 1 (MR1). MR1 controls some of the serial module configuration. This register can be read or written at any time when the serial module is enabled (i.e., the STP bit in the MCR is cleared). MR1A, MR1B $710, $718 7 6 5 4 3 2 1 0 RxRTS R/F ERR PM1 PM0 PT B/C1 B/C0 RESET: 0 0 0 0 0 0 0 0 Read/Write Supervisor/User RxRTS--Receiver Request-to-Send Control 1 = Upon receipt of a valid start bit, RTS is negated if the channel's FIFO is full. RTS is reasserted when the FIFO has an empty position available. 0 = RTS is asserted by setting bit 1 or 0 in the OP and negated by clearing bit 1 or 0 in the OP. This feature can be used for flow control to prevent overrun in the receiver by using the RTS output to control the CTS input of the transmitting device. If both the receiver and transmitter are programmed for RTS control, RTS control will be disabled for both since this configuration is incorrect. See 7.4.1.17 Mode Register 2 for information on programming the transmitter RTS control. R/F--Receiver-Ready Select 1 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel FIFO full status. These ISR bits are set when the receiver FIFO is full and are cleared when a position is available in the FIFO. 0 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel receiverready status. These ISR bits are set when a character has been received and are cleared when the CPU32 reads the receive buffer. 7-22 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. ERR--Error Mode This bit controls the meaning of the three FIFO status bits (RB, FE, and PE) in the SR for the channel. 1 = Block mode--The values in the channel SR are the accumulation (i.e., the logical OR) of the status for all characters coming to the top of the FIFO since the last reset error status command for the channel was issued. Refer to 7.4.1.7 Command Register (CR) for more information on serial module commands. 0 = Character mode--The values in the channel SR reflect the status of the character at the top of the FIFO. Freescale Semiconductor, Inc... NOTE ERR = 0 must be used to get the correct A/D flag information when in multidrop mode. PM1-PM0--Parity Mode These bits encode the type of parity used for the channel (see Table 7-2). The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. These bits can alternatively select multidrop mode for the channel. PT--Parity Type This bit selects the parity type if parity is programmed by the parity mode bits, and if multidrop mode is selected, it configures the transmitter for data character transmission or address character transmission. Table 7-2 lists the parity mode and type or the multidrop mode for each combination of the parity mode and the parity type bits. Table 7-2. PMx and PT Control Bits PM1 PM0 Parity Mode PT Parity Type 0 0 With Parity 0 Even Parity 0 0 With Parity 1 Odd Parity 0 1 Force Parity 0 Low Parity 0 1 Force Parity 1 High Parity 1 0 No Parity X No Parity 1 1 Multidrop Mode 0 Data Character 1 1 Multidrop Mode 1 Address Character B/C1-B/C0--Bits per Character These bits select the number of data bits per character to be transmitted. The character length listed in Table 7-3 does not include start, parity, or stop bits. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-23 Freescale Semiconductor, Inc. Table 7-3. B/Cx Control Bits B/C1 B/C0 Bits/Character 0 0 Five Bits 0 1 Six Bits 1 0 Seven Bits 1 1 Eight Bits Freescale Semiconductor, Inc... 7.4.1.5 STATUS REGISTER (SR). The SR indicates the status of the characters in the FIFO and the status of the channel transmitter and receiver. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). SRA, SRB $711, $719 7 6 5 4 3 2 1 0 RB FE PE OE TxEMP TxRDY FFULL RxRDY RESET: 0 0 0 0 0 0 0 0 Read Only Supervisor/User RB--Received Break 1 = An all-zero character of the programmed length has been received without a stop bit. The RB bit is only valid when the RxRDY bit is set. Only a single FIFO position is occupied when a break is received. Further entries to the FIFO are inhibited until the channel RxDx returns to the high state for at least one-half bit time, which is equal to two successive edges of the internal or external 1x clock or 16 successive edges of the external 16x clock. The received break circuit detects breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until the end of the next detected character time. 0 = No break has been received. FE--Framing Error 1 = A stop bit was not detected when the corresponding data character in the FIFO was received. The stop-bit check is made in the middle of the first stop-bit position. The bit is valid only when the RxRDY bit is set. 0 = No framing error has occurred. PE--Parity Error 1 = When the with parity or force parity mode is programmed in the MR1, the corresponding character in the FIFO was received with incorrect parity. When the multidrop mode is programmed, this bit stores the received A/D bit. This bit is valid only when the RxRDY bit is set. 0 = No parity error has occurred. 7-24 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... OE--Overrun Error 1 = One or more characters in the received data stream have been lost. This bit is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. This bit is cleared by the reset error status command in the CR. 0 = No overrun has occurred. TxEMP--Transmitter Empty 1 = The channel transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission. 0 = The transmitter buffer is not empty. The transmitter holding register is loaded by the CPU32, or the transmitter is disabled. The transmitter is enabled/disabled by programming the TCx bits in the CR. TxRDY--Transmitter Ready This bit is duplicated in the ISR; bit 0 for channel A and bit 4 for channel B. 1 = The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted and are lost. 0 = The transmitter holding register was loaded by the CPU32, or the transmitter is disabled. FFULL--FIFO Full 1 = A character was transferred from the receiver shift register to the receiver FIFO and the transfer caused the FIFO to become full (all three FIFO holding register positions are occupied). 0 = The CPU32 has read the receiver buffer and one or more FIFO positions are available. Note that if there is a character in the receiver shift register because the FIFO is full, this character will be moved into the FIFO when a position is available, and the FIFO will remain full. RxRDY--Receiver Ready 1 = A character has been received and is waiting in the FIFO to be read by the CPU32. This bit is set when a character is transferred from the receiver shift register to the FIFO. 0 = The CPU32 has read the receiver buffer, and no characters remain in the FIFO after this read. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-25 Freescale Semiconductor, Inc. 7.4.1.6 CLOCK-SELECT REGISTER (CSR). The CSR selects the baud rate clock for the channel receiver and transmitter. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). NOTE This register should only be written after the external crystal is stable (XTAL_RDY bit of the ISR is zero). Freescale Semiconductor, Inc... CSRA, CSRB $711, $719 7 6 5 4 3 2 1 0 RCS3 RCS2 RCS1 RCS0 TCS3 TCS2 TCS1 TCS0 RESET: 0 0 0 0 0 0 0 0 Write Only Supervisor/User RCS3-RCS0--Receiver Clock Select These bits select the baud rate clock for the channel receiver from a set of baud rates listed in Table 7-4. The baud rate set selected depends upon the auxiliary control register (ACR) bit 7. Set 1 is selected if ACR bit 7 = 0, and set 2 is selected if ACR bit 7 = 1. The receiver clock is always 16 times the baud rate shown in this list, except when SCLK is used. Table 7-4. RCSx Control Bits 7-26 RCS3 RCS2 RCS1 RCS0 Set 1 Set 2 0 0 0 0 50 75 0 0 0 1 110 110 0 0 1 0 134.5 134.5 0 0 1 1 200 150 0 1 0 0 300 300 0 1 0 1 600 600 0 1 1 0 1200 1200 0 1 1 1 1050 2000 1 0 0 0 2400 2400 1 0 0 1 4800 4800 1 0 1 0 7200 1800 1 0 1 1 9600 9600 1 1 0 0 38.4k 19.2k 1 1 0 1 76.8k 38.4k 1 1 1 0 SCLK/16 SCLK/16 1 1 1 1 SCLK/1 SCLK/1 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TCS3-TCS0--Transmitter Clock Select These bits select the baud rate clock for the channel transmitter from a set of baud rates listed in Table 7-5. The baud rate set selected depends upon ACR bit 7. Set 1 is selected if ACR bit 7 = 0, and set 2 is selected if ACR bit 7 = 1. The transmitter clock is always 16 times the baud rate shown in this list, except when SCLK is used. Freescale Semiconductor, Inc... Table 7-5. TCSx Control Bits TCS3 TCS2 TCS1 TCS0 Set 1 Set 2 0 0 0 0 50 75 0 0 0 1 110 110 0 0 1 0 134.5 134.5 0 0 1 1 200 150 0 1 0 0 300 300 0 1 0 1 600 600 0 1 1 0 1200 1200 0 1 1 1 1050 2000 1 0 0 0 2400 2400 1 0 0 1 4800 4800 1 0 1 0 7200 1800 1 0 1 1 9600 9600 1 1 0 0 38.4k 19.2k 1 1 0 1 76.8k 38.4k 1 1 1 0 SCLK/16 SCLK/16 1 1 1 1 SCLK/1 SCLK/1 7.4.1.7 COMMAND REGISTER (CR). The CR is used to supply commands to the channel. Multiple commands can be specified in a single write to the CR if the commands are not conflicting--e.g., reset transmitter and enable transmitter commands cannot be specified in a single command. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). CRA, CRB 6 5 4 3 2 1 0 MISC3 MISC2 MISC1 MISC0 TC1 TC0 RC1 RC0 RESET: 0 0 0 0 0 0 0 0 Write Only MOTOROLA $712, $71A 7 Supervisor/User MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-27 Freescale Semiconductor, Inc. MISC3-MISC0--Miscellaneous Commands These bits select a single command as listed in Table 7-6. Freescale Semiconductor, Inc... Table 7-6. MISCx Control Bits MISC3 MISC2 MISC1 MISC0 Command 0 0 0 0 No Command 0 0 0 1 No Command 0 0 1 0 Reset Receiver 0 0 1 1 Reset Transmitter 0 1 0 0 Reset Error Status 0 1 0 1 Reset Break-Change Interrupt 0 1 1 0 Start Break 0 1 1 1 Stop Break 1 0 0 0 Assert RTS 1 0 0 1 Negate RTS 1 0 1 0 No Command 1 0 1 1 No Command 1 1 0 0 No Command 1 1 0 1 No Command 1 1 1 0 No Command 1 1 1 1 No Command Reset Receiver--The reset receiver command resets the channel receiver. The receiver is immediately disabled, the FFULL and RxRDY bits in the SR are cleared, and the receiver FIFO pointer is reinitialized. All other registers are unaltered. This command should be used in lieu of the receiver disable command whenever the receiver configuration is changed because it places the receiver in a known state. Reset Transmitter--The reset transmitter command resets the channel transmitter. The transmitter is immediately disabled, and the TxEMP and TxRDY bits in the SR are cleared. All other registers are unaltered. This command should be used in lieu of the transmitter disable command whenever the transmitter configuration is changed because it places the transmitter in a known state. Reset Error Status--The reset error status command clears the channel's RB, FE, PE, and OE bits (in the SR). This command is also used in the block mode to clear all error bits after a data block is received. Reset Break-Change Interrupt--The reset break-change interrupt command clears the delta break (DBx) bits in the ISR. 7-28 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Start Break--The start break command forces the channel's TxDx low. If the transmitter is empty, the start of the break conditions can be delayed up to one bit time. If the transmitter is active, the break begins when transmission of the character is complete. If a character is in the transmitter shift register, the start of the break is delayed until the character is transmitted. If the transmitter holding register has a character, that character is transmitted after the break. The transmitter must be enabled for this command to be accepted. The state of the CTS input is ignored for this command. Stop Break--The stop break command causes the channel's TxDx to go high (mark) within two bit times. Characters stored in the transmitter buffer, if any, are transmitted. Assert RTS--The assert RTS command forces the channel's RTS output low. Freescale Semiconductor, Inc... Negate RTS--The negate RTS command forces the channel's RTS output high. TC1-TC0--Transmitter Commands These bits select a single command as listed in Table 7-7. Table 7-7. TCx Control Bits TC1 TC0 Command 0 0 No Action Taken 0 1 Enable Transmitter 1 0 Disable Transmitter 1 1 Do Not Use No Action Taken--The no action taken command causes the transmitter to stay in its current mode. If the transmitter is enabled, it remains enabled; if disabled, it remains disabled. Transmitter Enable--The transmitter enable command enables operation of the channel's transmitter. The TxEMP and TxRDY bits in the SR are also set. If the transmitter is already enabled, this command has no effect. Transmitter Disable--The transmitter disable command terminates transmitter operation and clears the TxEMP and TxRDY bits in the SR. However, if a character is being transmitted when the transmitter is disabled, the transmission of the character is completed before the transmitter becomes inactive. If the transmitter is already disabled, this command has no effect. Do Not Use--Do not use this bit combination because the result is indeterminate. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-29 Freescale Semiconductor, Inc. RC1-RC0--Receiver Commands These bits select a single command as listed in Table 7-8. Freescale Semiconductor, Inc... Table 7-8. RCx Control Bits RC1 RC0 Command 0 0 No Action Taken 0 1 Enable Receiver 1 0 Disable Receiver 1 1 Do Not Use No Action Taken--The no action taken command causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled. Receiver Enable--The receiver enable command enables operation of the channel's receiver. If the serial module is not in multidrop mode, this command also forces the receiver into the search-for-start-bit state. If the receiver is already enabled, this command has no effect. Receiver Disable--The receiver disable command disables the receiver immediately. Any character being received is lost. The command has no effect on the receiver status bits or any other control register. If the serial module is programmed to operate in the local loopback mode or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, this command has no effect. Do Not Use--Do not use this bit combination because the result is indeterminate. 7.4.1.8 RECEIVER BUFFER (RB). The receiver buffer contains three receiver holding registers and a serial shift register. The channel's RxDx pin is connected to the serial shift register. The holding registers act as a FIFO. The CPU32 reads from the top of the stack while the receiver shifts and updates from the bottom of the stack when the shift register has been filled (see Figure 7-4). This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). RBA, RBB $713, $71B 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RESET: 0 0 0 0 0 0 0 0 Read Only Supervisor/User RB7-RB0--These bits contain the character in the receiver buffer. 7.4.1.9 TRANSMITTER BUFFER (TB). The transmitter buffer consists of two registers, the transmitter holding register and the transmitter shift register (see Figure 7-4). The holding register accepts characters from the bus master if the TxRDY bit in the channel's SR is set. A write to the transmitter buffer clears the TxRDY bit, inhibiting any more 7-30 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. characters until the shift register is ready to accept more data. When the shift register is empty, it checks to see if the holding register has a valid character to be sent (TxRDY bit cleared). If there is a valid character, the shift register loads the character and reasserts the TxRDY bit in the channel's SR. Writes to the transmitter buffer when the channel's SR TxRDY bit is clear and when the transmitter is disabled have no effect on the transmitter buffer. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). Freescale Semiconductor, Inc... TBA, TBB $713, $71B 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 RESET: 0 0 0 0 0 0 0 0 Write Only Supervisor/User TB7-TB0--These bits contain the character in the transmitter buffer. 7.4.1.10 INPUT PORT CHANGE REGISTER (IPCR). The IPCR shows the current state and the change-of-state for the CTSA and CTSB pins. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). IPCR $714 7 6 5 4 3 2 1 0 0 0 COSB COSA 0 0 CTSB CTSA RESET: 0 0 0 0 0 0 U U Read Only Supervisor/User Bits 7, 6, 3, 2--Reserved COSB, COSA--Change-of-State 1 = A change-of-state (high-to-low or low-to-high transition), lasting longer than 25- 50 s when using a crystal as the sampling clock or longer than one or two periods when using SCLK, has occurred at the corresponding CTS input (MCR ICCS bit controls selection of the sampling clock for clear-to-send operation). When these bits are set, the ACR can be programmed to generate an interrupt to the CPU32. 0 = The CPU32 has read the IPCR. No change-of-state has occurred. A read of the IPCR also clears the ISR COS bit. CTSB, CTSA--Current State Starting two serial clock periods after reset, the CTS bits reflect the state of the CTS pins. If a CTS pin is detected as asserted at that time, the associated COSx bit will be set, which will initiate an interrupt if the corresponding IECx bit of the ACR register is enabled. 1 = The current state of the respective CTS input is negated. 0 = The current state of the respective CTS input is asserted. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-31 Freescale Semiconductor, Inc. 7.4.1.11 AUXILIARY CONTROL REGISTER (ACR). The ACR selects which baud rate is used and controls the handshake of the transmitter/receiver. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). ACR $714 7 6 5 4 3 2 1 0 BRG 0 0 0 0 0 IECB IECA RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Write Only Supervisor/User BRG--Baud Rate Generator Set Select 1 = Set 2 of the available baud rates is selected. 0 = Set 1 of the available baud rates is selected. Refer to 7.4.1.6 Clock-Select Register (CSR) for more information on the baud rates. IECB, IECA--Input Enable Control 1 = ISR bit 7 will be set and an interrupt will be generated when the corresponding bit in the IPCR (COSB or COSA) is set by an external transition on the channel's CTS input (if bit 7 of the interrupt enable register (IER) is set to enable interrupts). 0 = Setting the corresponding bit in the IPCR has no effect on ISR bit 7. 7.4.1.12 INTERRUPT STATUS REGISTER (ISR). The ISR provides status for all potential interrupt sources. The contents of this register are masked by the IER. If a flag in the ISR is set and the corresponding bit in IER is also set, the IRQ output is asserted. If the corresponding bit in the IER is cleared, the state of the bit in the ISR has no effect on the output. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). NOTE The IER does not mask reading of the ISR. True status is provided regardless of the contents of IER. The contents of ISR are cleared when the serial module is reset. ISR $715 7 6 COS DBB RESET: 0 0 5 4 3 RxRDYB TxRDYB XTAL_ RDY 0 Read Only 0 1 2 DBA 1 0 RxRDYA TxRDYA 0 0 0 Supervisor/User COS--Change-of-State 1 = A change-of-state has occurred at one of the CTS inputs and has been selected to cause an interrupt by programming bit 1 and/or bit 0 of the ACR. 0 = The CPU32 has read the IPCR. 7-32 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... DBB--Delta Break B 1 = The channel B receiver has detected the beginning or end of a received break. 0 = The CPU32 has issued a channel B reset break-change interrupt command. Refer to 7.4.1.7 Command Register (CR) for more information on the reset break-change interrupt command. RxRDYB--Channel B Receiver Ready or FIFO Full The function of this bit is programmed by MR1B bit 6. 1 = If programmed as receiver ready, a character has been received in channel B and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a character has been transferred from the receiver shift register to the FIFO, and the transfer has caused the channel B FIFO to become full (all three positions are occupied). 0 = If programmed as receiver ready, the CPU32 has read the receiver buffer. After this read, if more characters are still in the FIFO, the bit is set again after the FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the receiver buffer. If a character is waiting in the receiver shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO. TxRDYB--Channel B Transmitter Ready This bit is the duplication of the TxRDY bit in SRB. 1 = The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted. 0 = The transmitter holding register was loaded by the CPU32, or the transmitter is disabled. XTAL_RDY--Serial Clock Running This bit is always read as a zero when the X1 clock is running. This bit cannot be enabled to generate an interrupt. 1 = This bit is set at reset. 0 = This bit is cleared after the baud rate generator is stable. The CSR should not be accessed until this bit is zero. DBA--Delta Break A 1 = The channel A receiver has detected the beginning or end of a received break. 0 = The CPU32 has issued a channel A reset break-change interrupt command. Refer to 7.4.1.7 Command Register (CR) for more information on the reset break-change interrupt command. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-33 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... RxRDYA--Channel A Receiver Ready or FIFO Full The function of this bit is programmed by MR1A bit 6. 1 = If programmed as receiver ready, a character has been received in channel A and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a character has been transferred from the receiver shift register to the FIFO, and the transfer has caused the channel A FIFO to become full (all three positions are occupied). 0 = If programmed as receiver ready, the CPU32 has read the receiver buffer. After this read, if more characters are still in the FIFO, the bit is set again after the FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the receiver buffer. If a character is waiting in the receiver shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO. TxRDYA--Channel A Transmitter Ready This bit is the duplication of the TxRDY bit in SRA. 1 = The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted. 0 = The transmitter holding register was loaded by the CPU32, or the transmitter is disabled. 7.4.1.13 INTERRUPT ENABLE REGISTER (IER). The IER selects the corresponding bits in the ISR that cause an interrupt output ( IRQ). If one of the bits in the ISR is set and the corresponding bit in the IER is also set, the IRQ output is asserted. If the corresponding bit in the IER is zero, the state of the bit in the ISR has no effect on the IRQ output. The IER does not mask the reading of the ISR. The ISR XTAL_RDY bit cannot be enabled to generate an interrupt. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). IER $715 7 6 COS DBB RESET: 0 0 5 4 RxRDYB TxRDYB 0 Write Only 0 3 2 0 DBA 0 0 1 0 RxRDYA TxRDYA 0 0 Supervisor/User COS--Change-of-State 1 = Enable interrupt 0 = Disable interrupt DBB--Delta Break B 1 = Enable interrupt 0 = Disable interrupt 7-34 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. RxRDYB--Channel B Receiver Ready or FIFO full 1 = Enable interrupt 0 = Disable interrupt TxRDYB--Channel B Transmitter Ready 1 = Enable interrupt 0 = Disable interrupt Bit 3--Reserved Freescale Semiconductor, Inc... DBA--Delta Break A 1 = Enable interrupt 0 = Disable interrupt RxRDYA--Channel A Receiver Ready or FIFO full 1 = Enable interrupt 0 = Disable interrupt TxRDYA--Channel A Transmitter Ready 1 = Enable interrupt 0 = Disable interrupt 7.4.1.14 INPUT PORT (IP). The IP register shows the current state of the CTS inputs. This register can only be read when the serial module is enabled (i.e., the STP bit in the MCR is cleared). IP $71D 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CTSB CTSA RESET: 0 0 0 0 0 0 U U Read Only Supervisor/User CTSB, CTSA--Current State 1 = The current state of the respective CTS input is negated. 0 = The current state of the respective CTS input is asserted. The information contained in these bits is latched and reflects the state of the input pins at the time that the IP is read. NOTE These bits have the same function and value of the IPCR bits 1 and 0. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-35 Freescale Semiconductor, Inc. 7.4.1.15 OUTPUT PORT CONTROL REGISTER (OPCR). The OPCR individually configures four bits of the 8-bit parallel OP for general-purpose use or as an auxiliary function serving the communication channels. This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). OPCR 7 $71D 6 5 4 OP7 OP6 OP5 OP4 TRDYB TRDYA RRDYB RRDYA RESET: 0 0 0 0 3 2 1 0 OP3 OP2 OP1 RTSB OP0 RTSA 0 0 0 0 Write Only Supervisor/User Freescale Semiconductor, Inc... NOTE OP bits 7, 5, 3, and 2 are not pinned out on the MC68340; thus changing bits 7, 5, 3, and 2 of this register has no effect. OP6--Output Port 6/ TRDYA 1 = The OP6/TRDYA pin functions as the transmitter-ready signal for channel A. The signal reflects the complement of the value of bit 2 of the SRA; thus, TRDYA is a logic zero when the transmitter is ready. 0 = The OP6/TRDYA pin functions as a dedicated output. The signal reflects the complement of the value of bit 6 of the OP. OP4--Output Port 4/ RRDYA 1 = The OP4/RRDYA pin functions as the FIFO-full or receiver-ready signal for channel A (depending on the value of bit 6 of MR1A). The signal reflects the complement of the value of ISR bit 1; thus, RRDYA is a logic zero when the receiver is ready. 0 = The OP4/RRDYA pin functions as a dedicated output. The signal reflects the complement of the value of bit 4 of the OP. OP1--Output Port 1/ RTSB 1 = The OP1/RTSB pin functions as the ready-to-send signal for channel B. The signal is asserted and negated according to the configuration programmed by RxRTS bit 7 in the MR1B for the receiver and TxRTS bit 5 in the MR2B for the transmitter. 0 = The OP1/RTSB pin functions as a dedicated output. The signal reflects the complement of the value of bit 1 of the OP. 7-36 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. OP0--Output Port 0/ RTSA 1 = The OP0/RTSA pin functions as the ready-to-send signal for channel A. The signal is asserted and negated according to the configuration programmed by RxRTS bit 7 in the MR1A for the receiver and TxRTS bit 5 in the MR2A for the transmitter. 0 = The OP0/RTSA pin functions as a dedicated output. The signal reflects the complement of the value of bit 0 of the OP. Freescale Semiconductor, Inc... 7.4.1.16 OUTPUT PORT DATA REGISTER (OP). The bits in the OP register are set by performing a bit set command (writing to offset $71E) and are cleared by performing a bit reset command (writing to offset $71F). This register can only be written when the serial module is enabled (i.e., the STP bit in the MCR is cleared). Bit Set OP $71E 7 6 5 4 3 2 1 0 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RESET: 0 0 0 0 0 0 0 0 Write Only Supervisor/User NOTE OP bits 7, 5, 3, and 2 are not pinned out on the MC68340; thus, changing these bits has no effect. OP6, OP4, OP1, OP0--Output Port Parallel Outputs 1 = These bits can be set by writing a one to the bit position(s) at this address. 0 = These bits are not affected by writing a zero to this address. Bit Reset OP $71F 7 6 5 4 3 2 1 0 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RESET: 0 0 0 0 0 0 0 0 Write Only Supervisor/User NOTE OP bits 7, 5, 3, and 2 are not pinned out on the MC68340; thus, changing these bits has no effect. OP6, OP4, OP1, OP0--Output Port Parallel Outputs 1 = These bits can be cleared by writing a one to the bit position(s) at this address. 0 = These bits are not affected by writing a zero to this address. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-37 Freescale Semiconductor, Inc. 7.4.1.17 MODE REGISTER 2 (MR2). MR2 controls some of the serial module configuration. This register can be read or written at any time the serial module is enabled (i.e., the STP bit in the MCR is cleared). MR2A, MR2B $720, $721 7 6 5 4 3 2 1 0 CM1 CM0 TxRTS TxCTS SB3 SB2 SB1 SB0 RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read/Write Supervisor/User CM1-CM0--Channel Mode These bits select a channel mode as listed in Table 7-9. See 7.3.3 Looping Modes for more information on the individual modes. Table 7-9. CMx Control Bits CM1 CM0 Mode 0 0 Normal 0 1 Automatic Echo 1 0 Local Loopback 1 1 Remote Loopback TxRTS--Transmitter Ready-to-Send This bit controls the negation of the RTSA or RTSB signals. The output is normally asserted by setting OP0 or OP1 and negated by clearing OP0 or OP1 (see 7.4.1.15 Output Port Control Register (OPCR)). 1 = In applications where the transmitter is disabled after transmission is complete, setting this bit causes the particular OP bit to be cleared automatically one bit time after the characters, if any, in the channel transmit shift register and the transmitter holding register are completely transmitted, including the programmed number of stop bits. This feature is used to automatically terminate transmission of a message. If both the receiver and the transmitter in the same channel are programmed for RTS control, RTS control is disabled for both since this is an incorrect configuration. 0 = Clearing this bit has no effect on the transmitter RTS. 7-38 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... TxCTS--Transmitter Clear-to-Send 1 = Enables clear-to-send operation. The transmitter checks the state of the CTS input each time it is ready to send a character. If CTS is asserted, the character is transmitted. If CTS is negated, the channel TxDx remains in the high state, and the transmission is delayed until CTS is asserted. Changes in CTS while a character is being transmitted do not affect transmission of that character. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter. 0 = The CTS has no effect on the transmitter. SB3-SB0--Stop-Bit Length Control These bits select the length of the stop bit appended to the transmitted character as listed in Table 7-10. Stop-bit lengths of nine-sixteenth to two bits, in increments of onesixteenth bit, are programmable for character lengths of six, seven, and eight bits. For a character length of five bits, one and one-sixteenth to two bits are programmable in increments of one-sixteenth bit. In all cases, the receiver only checks for a high condition at the center of the first stop-bit position--i.e., one bit time after the last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, MR2 bit 3 = 0 selects one stop bit, and MR2 bit 3 = 1 selects two stop bits for transmission. Table 7-10. SBx Control Bits MOTOROLA SB3 SB2 SB1 SB0 Length 6-8 Bits Length 5 Bits 0 0 0 0 0.563 1.063 0 0 0 1 0.625 1.125 0 0 1 0 0.688 1.188 0 0 1 1 0.750 1.250 0 1 0 0 0.813 1.313 0 1 0 1 0.875 1.375 0 1 1 0 0.938 1.438 0 1 1 1 1.000 1.500 1 0 0 0 1.563 1.563 1 0 0 1 1.625 1.625 1 0 1 0 1.688 1.688 1 0 1 1 1.750 1.750 1 1 0 0 1.813 1.813 1 1 0 1 1.875 1.875 1 1 1 0 1.938 1.938 1 1 1 1 2.000 2.000 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-39 Freescale Semiconductor, Inc. 7.4.2 Programming The basic interface software flowchart required for operation of the serial module is shown in Figure 7-10. The routines are divided into three categories: * Serial Module Initialization * I/O Driver Freescale Semiconductor, Inc... * Interrupt Handling 7.4.2.1 SERIAL MODULE INITIALIZATION. The serial module initialization routines consist of SINIT and CHCHK. SINIT is called at system initialization time to check channel A and channel B operation. Before SINIT is called, the calling routine allocates two words on the system stack. Upon return to the calling routine, SINIT passes information on the system stack to reflect the status of the channels. If SINIT finds no errors in either channel A or channel B, the respective receivers and transmitters are enabled. The CHCHK routine performs the actual channel checks as called from the SINIT routine. When called, SINIT places the specified channel in the local loopback mode and checks for the following errors: * Transmitter Never Ready * Receiver Never Ready * Parity Error * Incorrect Character Received 7.4.2.2 I/O DRIVER EXAMPLE. The I/O driver routines consist of INCH, OUTCH, and POUTCH. INCH is the terminal input character routine and gets a character from the channel A receiver and places it in the lower byte of register D0. OUTCH is used to send the character in the lower byte of register D0 to the channel A transmitter. POUTCH sends the character in the lower byte of D0 to the channel B transmitter. 7.4.2.3 INTERRUPT HANDLING. The interrupt handling routine consists of SIRQ, which is executed after the serial module generates an interrupt caused by a channel A changein-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 7-40 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL MODULE ENABLA SINIT Freescale Semiconductor, Inc... INITIATE: CHANNEL A CHANNEL B INTERRUPTS ANY ERRORS IN CHANNEL A ? Y N CHK1 POINT TO CHANNEL A ENABLE CHANNEL A'S RECEIVER CALL CHCHK ASSERT CHANNEL A REQUEST TO SEND ENABLB SAVE CHANNEL A STATUS CHK2 POINT TO CHANNEL B ANY ERRORS IN CHANNEL B ? Y N CALL CHCHK ENABLE CHANNEL B'S TRANSMITTER SINITR SAVE CHANNEL B STATUS RETURN Figure 7-10. Serial Module Programming Flowchart (1 of 5) MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-41 Freescale Semiconductor, Inc. CHCHK CHCHK Freescale Semiconductor, Inc... PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE CHANNEL'S TRANSMITTER CLEAR CHANNEL STATUS WORD TxCHK N IS TRANSMITTER READY ? Y WAITED TOO LONG ? Y SET TRANSMITTERNEVER-READY FLAG N SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK N HAS RECEIVER RECEIVED CHARACTER ? N WAITED TOO LONG ? Y SET RECEIVERNEVER-READY FLAG Y A B Figure 7-10. Serial Module Programming Flowchart (2 of 5) 7-42 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. A B FRCHK RSTCHN HAVE FRAMING ERROR ? N Y DISABLE CHANNEL'S TRANSMITTER RESTORE CHANNEL TO ORIGINAL MODE Freescale Semiconductor, Inc... SET FRAMING ERROR FLAG PRCHK RETURN HAVE PARITY ERROR ? N Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER SAME AS CHARACTER TRANSMITTED ? Y N SET INCORRECT CHARACTER FLAG B Figure 7-10. Serial Module Programming Flowchart (3 of 5) MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-43 Freescale Semiconductor, Inc. SIRQ INCH ABRKI Freescale Semiconductor, Inc... WAS IRQx CAUSED BY BEGINNING OF A BREAK ? N DOES CHANNEL A RECEIVER HAVE A CHARACTER ? Y N Y CLEAR CHANGE-INBREAK STATUS BIT PLACE CHARACTER IN D0 ABRKI1 HAS END-OF-BREAK IRQx ARRIVED YET ? RETURN N Y CLEAR CHANGE-INBREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE Figure 7-10. Serial Module Programming Flowchart (4 of 5) 7-44 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. OUTCH POUCH Freescale Semiconductor, Inc... IS CHANNEL A TRANSMITTER READY ? N IS CHANNEL B TRANSMITTER READY ? Y N Y SEND CHARACTER IN D0 TO CHANNEL B TRANSMITTER SEND CHARACTER IN D0 TO CHANNEL A TRANSMITTER WAS CHARACTER A CARRIAGE RETURN ? N Y OUTCHI IS CHANNEL A TRANSMITTER READY ? N WAS CHARACTER A CARRIAGE RETURN ? Y POUCHI IS CHANNEL B TRANSMITTER READY ? N N Y Y SEND A LINE FEED CHARACTER TO CHANNEL A TRANSMITTER SEND A LINE FEED CHARACTER TO CHANNEL B TRANSMITTER OUTCHR POUTCHR RETURN RETURN Figure 7-10. Serial Module Programming Flowchart (5 of 5) MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-45 Freescale Semiconductor, Inc. 7.5 SERIAL MODULE INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the serial module. 7.5.1 Serial Module Configuration If the serial capability of the MC68340 is being used, the following steps are required to properly initialize the serial module. NOTE Freescale Semiconductor, Inc... The serial module registers can only be accessed by byte operations. Command Register (CR) * Reset the receiver and transmitter for each channel. The following steps program both channels: Module Configuration Register (MCR) * Initialize the stop bit (STP) for normal operation. * Select whether to respond to or ignore FREEZE (FRZx bits). * Select the input capture clock (ICCS bit). * Select the access privilege for the supervisor/user registers (SUPV bit). * Select the interrupt arbitration level for the serial module (IARBx bits). Interrupt Vector Register (IVR) * Program the vector number for a serial module interrupt. Interrupt Level Register (ILR) * Program the interrupt priority level for a serial module interrupt. Interrupt Enable Register (IER) * Enable the desired interrupt sources. Auxiliary Control Register (ACR) * Select baud rate set (BRG bit). * Initialize the input enable control (IEC bits). Output Port Control Register (OPCR) * Select the function of the output port pins. Interrupt Status Register (ISR) * The XTAL_RDY bit should be polled until it is cleared to ensure that an unstable crystal input is not applied to the baud rate generator. 7-46 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The following steps are channel specific: Clock Select Register (CSR) * Select the receiver and transmitter clock. Mode Register 1 (MR1) * If desired, program operation of receiver ready-to-send (RxRTS bit). * Select receiver-ready or FIFO-full notification (R/F bit). * Select character or block error mode (ERR bit). * Select parity mode and type (PM and PT bits). Freescale Semiconductor, Inc... * Select number of bits per character (B/Cx bits). Mode Register 2 (MR2) * Select the mode of channel operation (CMx bits). * If desired, program operation of transmitter ready-to-send (TxRTS bit). * If desired, program operation of clear-to-send (TxCTS bit). * Select stop-bit length (SBx bits). Command Register (CR) * Enable the receiver and transmitter. 7.5.2 Serial Module Example Configuration Code The following code is an example of a configuration sequence for the serial module. *************************************************************************** * MC68340 basic serial module register initialization example code. * This code is used to initialize the 68340's internal serial module registers, * providing basic functions for operation. * It sets up serial channel A for communication with a 9600 baud terminal. * Note: All serial module registers must be accessed as bytes. *************************************************************************** *************************************************************************** * equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value *************************************************************** * Serial module equates SERIAL EQU $700 Offset from MBAR for serial module regs MCRH EQU $0 serial MCR high byte MCRL EQU $1 serial MCR low byte MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-47 Freescale Semiconductor, Inc. * Serial register offsets from serial base address MR1A EQU $10 Mode register 1 A MR2A EQU $20 Mode register 2 A SRA EQU $11 Status register A CSRA EQU $11 Clock select reg A CRA EQU $12 Command reg A Freescale Semiconductor, Inc... ACR OPCR OP_BS OP_BR EQU EQU EQU EQU $14 $1D $1E $1F Auxiliary control reg Output port control reg Output port bit set (write 1 to set) Output port bit reset (write 1 to clear) *************************************************************************** *************************************************************************** * Initialize Serial channel A *************************************************************************** LEA MODBASE+SERIAL,A0 Pointer to serial channel A * Module configuration register: * Enable serial module for normal operation, ignore FREEZE, select the * crystal clock. Supervisor/user serial registers unrestricted. * Interrupt arbitration at priority $02. MOVE.B #$00,MCRH(A0) MOVE.B #$02,MCRL(A0) * WAIT FOR TRANSMITTER EMPTY (OR TIMEOUT) MOVE.W #$2000,D0 init loop counter XBMTWAIT EQU * BTST #3,SRA(A0) TX empty in status reg? NOP DBNE D0,XBMTWAIT loop until set or timeout * NEGATE RTSA SIGNAL OUTPUT MOVE.B #0,OPCR(A0) MOVE.B #$01,OP_BR(A0) make OP0-7 general purpose clear RTSA/OP0 output * RESET RECEIVER/TRANSMITTER MOVE.B #$20,CRA(A0) MOVE.B #$30,CRA(A0) Issue reset receiver command Issue reset transmitter command * SET BAUD RATE SET 2 MOVE.B #$80,ACR(A0) * MODE REGISTER 1 MOVE.B #$93,MR1A(A0) 7-48 8 bits, no parity, auto RTS control MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. * MODE REGISTER 2 MOVE.B #$07,MR2A(A0) Normal, 1 stop bit Freescale Semiconductor, Inc... * SET UP BAUD RATE FOR PORT IN CLOCK SELECT REGISTER MOVE.B #$BB,CSRA(A0) Set 9600 baud for RX and TX * SET RTSA ACTIVE MOVE.B #$01,OP_BS(A0) set RTSA/OP0 output * ENABLE PORT MOVE.B Reset error status, enable RX & TX #$45,CRA(A0) *************************************************************************** END *************************************************************************** MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-49 Freescale Semiconductor, Inc. SECTION 8 TIMER MODULES Each MC68340 timer module contains a counter/timer (timer 1 and timer 2) as shown in Figure 8-1. Each timer interfaces directly to the CPU32 via the intermodule bus (IMB). Each timer consists of the following major areas: Freescale Semiconductor, Inc... * A General-Purpose Counter/Timer * Internal Control Logic * Interrupt Control Logic TIMER 1 TIMER 2 TIN2 TIN1 TOUT1 TIMER 1 TIMER 2 TOUT2 TGATE2 TGATE1 INTERRUPT CONTROL LOGIC INTERRUPT CONTROL LOGIC IMB INTERFACE IMB INTERFACE Figure 8-1. Simplified Block Diagram 8.1 MODULE OVERVIEW Each timer module consists of the following functional features: * Versatile General-Purpose Timer * 8-Bit Prescaler/16-Bit Counter * Timers Can Be Externally Cascaded for a Maximum Count Width of 48 Bits * Programmable Timer Modes: -- Input Capture/Output Compare -- Square-Wave Generation -- Variable Duty-Cycle Square-Wave Generation -- Variable-Width Single-Shot Pulse Generation MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-1 Freescale Semiconductor, Inc. -- Pulse-Width Measurement -- Period Measurement -- Event Counting * Seven Maskable Interrupt Conditions Based on Programmable Events 8.1.1 Timer and Counter Functions Freescale Semiconductor, Inc... The term 'timer' is used to reference either timer 1 or timer 2, since the two are functionally equivalent. The timer can perform virtually any application traditionally assigned to timers and counters. The timer can be used to generate timed events that are independent of the timing errors to which real-time programmed microprocessors are susceptible--for example, those of dynamic memory refreshing, DMA cycle steals, and interrupt servicing. The timer has several functional areas: an 8-bit countdown prescaler, a 16-bit downcounter, timeout logic, compare logic, and clock selection logic. Figure 8-2 shows a functional diagram of the timer module. 8.1.1.1 PRESCALER AND COUNTER. The counter can be driven directly by the selected clock or the prescaler output. Both the counter and prescaler are updated on the falling edge of the clock. During reset, the prescaler is set to $FF, and the counter is set to $0000. The counter is loaded with a programmed value on the first falling edge of the counter clock after the timer is enabled and again when a timeout occurs (counter reaches $0000). The prescaler and counter can be used as one 24-bit counter by enabling the prescaler and selecting the divide-by-256 prescaler output. Refer to 8.4 Register Description for additional information on how to program the timer. 8.1.1.2 TIMEOUT DETECTION. Timeout is achieved when all 16 stages of the counter transition to zero, a counter value of $0000. Timeout is a defined counter event which triggers specific actions depending upon the programmed mode of operation. Refer to 8.3 Operating Modes for descriptions of the individual modes. 8.1.1.3 COMPARATOR. The comparator block compares the value in the 16-bit compare register (COM) with the output of the 16-bit counter. When an exact match is detected, bits in the status register (SR) are set to indicate this condition. When in the input capture/output compare mode, a match is a defined counter event that can affect the output of the timer (TOUTx). Refer to 8.3.1 Input Capture/Output Compare for additional information on this mode. 8-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TIMER EXTERNAL INTERFACE MODULE CONFIGURATION REGISTER INTERRUPT REGISTER CONTROL REGISTER STATUS REGISTER Freescale Semiconductor, Inc... PRELOAD 1 REGISTER I M B (SYSTEM CLOCK) CLOCK CLOCK LOGIC PRELOAD 2 REGISTER 16-BIT COUNTER MUX COUNTER CLOCK TIN TGATE SELECTED CLOCK MUX COUNTER REGISTER COMPARE REGISTER 8-BIT PRESCALER TIMEOUT TOUT 16-BIT COMPARATOR Figure 8-2. Timer Functional Diagram 8.1.1.4 CLOCK SELECTION LOGIC. The clock selection logic consists of two multiplexers that select the clocks applied to the prescaler and counter. The first multiplexer (labeled clock logic in Figure 8-2) selects between the clock input to the timer (TINx) or one-half the frequency of the system clock (CLKOUT). This output of the first multiplexer (called selected clock) is applied to both the 8-bit prescaler and the second multiplexer. The second multiplexer selects the clock for the 16-bit counter, which is either the selected clock or the 8-bit prescaler output. 8.1.2 Internal Control Logic The timer receives operation commands on the IMB and, in turn, issues appropriate operation signals to the internal timer control logic. This mechanism allows the timer registers to be accessed and programmed. Refer to 8.4 Register Description for additional information. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-3 Freescale Semiconductor, Inc. 8.1.3 Interrupt Control Logic Each timer provides seven interrupt request outputs (IRQ7- IRQ1) to notify the CPU32 that an interrupt has occurred. The interrupts are described in 8.4 Register Description. Bits in the SR indicate all currently active interrupt conditions. The interrupt enable (IE) bits in the control register (CR) are programmable to mask any events that may cause an interrupt. 8.2 TIMER MODULES SIGNAL DEFINITIONS This section contains a brief description of the timer module signals (see Figure 8-3). NOTE Freescale Semiconductor, Inc... The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 8-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TIMER 1 TIN1 CLOCK LOGIC TGATE1 PRESCALER EXTERNAL INTERFACE SIGNALS COUNTER Freescale Semiconductor, Inc... OUTPUT CONTROL TOUT1 INTERRUPT CONTROL I M B TIMER 2 TIN2 CLOCK LOGIC TGATE2 PRESCALER EXTERNAL INTERFACE SIGNALS COUNTER OUTPUT CONTROL TOUT2 INTERRUPT CONTROL Figure 8-3. External and Internal Interface Signals 8.2.1 Timer Input (TIN1, TIN2) This input can be programmed to be the clock that causes events to occur in the counter and prescaler. TINx is internally synchronized to the system clock to guarantee that a valid TINx level is recognized. Additionally, the high and low levels of TINx must each be stable MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-5 Freescale Semiconductor, Inc. for at least one system clock period plus the sum of the setup and hold times for TINx. Refer to Section 11 Electrical Characteristics, for additional information. 8.2.2 Timer Gate ( TGATE1, TGATE2) Freescale Semiconductor, Inc... This active-low input can be programmed to enable and disable the counter and prescaler. TGATE may also be programmed to be a simple input. For more information on the modes of operation, refer to 8.3 OPERATING MODES. To guarantee that the timer recognizes a valid level on TGATE, the signal is synchronized with the system clock. Additionally, the high and low levels of this input must each be stable for at least one system clock period plus the sum of the setup and hold times for TGATE . Refer to Section 11 Electrical Characteristics, for additional information. 8.2.3 Timer Output (TOUT1, TOUT2) This output drives the various output waveforms generated by the timer. The initial level and transitions can be programmed by the output control (OC) bits in the CR. 8.3 OPERATING MODES The following paragraphs contain a detailed description of each timer operation mode and of the IMB operation during accesses to the timer. Changing the contents of the CR should only be attempted when the timer is disabled (the software reset (SWR) bit in the CR is cleared). Changing the CR while the timer is running may produce unpredictable results. 8.3.1 Input Capture/Output Compare This mode has the capability of capturing a counter value by holding the value in the counter register (CNTR). Additionally, this mode can provide compare information via TOUTx to indicate when the counter has reached the compare value. This mode can be used for square-wave generation, pulse-width modulation, or periodic interrupt generation. This mode can be selected by programming the operation mode bits (MODEx) in the CR to 000. The timer is enabled when the counter prescaler enable (CPE) and SWRx bits in the CR are set. Once enabled, the counter enable (ON) bit in the SR is set, and the next falling edge of the counter clock causes the counter to be loaded with the value in the preload 1 register (PREL1). The TGATE signal functions differently in this mode than it does in the other modes. TGATE does not enable or disable the counter/prescaler input clock; instead, it is used to disable shadowing. Normally, the counter is decremented on the falling edge of the counter clock, and the CNTR is updated on the next rising edge of the system clock; thus, the CNTR shadows the actual value of the counter. The timer gate interrupt (TG) bit in the SR must be cleared for shadowing to occur. TGATE is used to set the TG bit and disable shadowing. If the timing gate is enabled (TGE bit of the CR is set), the TG bit is set by the rising edge of TGATE. Shadowing is disabled until the TG bit is cleared by writing a one 8-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. to its location in the SR. See Figure 8-4 for a depiction of this mode. If the timing gate is disabled (CR TGE bit is cleared), TGATE has no effect on the operation of the timer; thus the input capture function is inoperative. At all times, the TGATE level bit (TGL) in the SR reflects the level of the TGATE signal. COUNTER CLOCK COUNTER COUNTER REGISTER 0 0 0 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 8 8 7 7 0 0 0 0 8 8 7 7 6 6 6 6 6 6 6 3 2 2 1 1 0 0 8 8 8 Freescale Semiconductor, Inc... TGATE TG SET TG CLEARED TG SET TOUT ENABLE TC SET TIMEOUT TC SET Modex Bits in Control Register = 000 Preload 1 Register = 8 Compare Register = 7 TGE Bit of Status Register = 1 TG Bit in Status Register Initially = 0 OCx Bits in Control Register = 10 Figure 8-4. Input Capture/Output Compare Mode Since the counter is not affected by TGATE , it continues to decrement on the falling edge of the counter clock and load from the PREL1 at timeout, regardless of the value of TGATE. When the counter counts down to the value contained in the COM, this condition is reflected by setting the timer compare (TC) and compare (COM) bits in the SR. TOUTx responds as selected by the OCx bits in the CR. The output level (OUT) bit in the SR reflects the value on TOUTx. Shadowing does not affect this operation. If the counter counts down to $0000, a timeout is detected, causing the SR timeout interrupt (TO) bit to be set and the SR COM bit to be cleared. On the next falling edge of the counter clock after the timeout is detected, the value in PREL1 is again loaded into the counter. TOUTx responds as selected by the CR OCx bits. A square-wave generator can be implemented by programming the CR OCx bits to toggle mode. The value in the COM should be one-half the value in PREL1 to cause an event to happen twice in the countdown. This mode can be used as a pulse-width modulator by programming the CR OCx bits to zero mode or one mode. The value in the PREL1 specifies the frequency, and the COM determines the pulse width. The pulse widths can be changed by writing a new value to the COM. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-7 Freescale Semiconductor, Inc. Periodic interrupt generation can be accomplished by enabling the TO, TG, and/or TC bits in the SR to generate interrupts by programming the IE bits of the CR. When enabled, the programmed IRQ signal is asserted whenever the specified bits are set. TOUTx signal transitions can be controlled by writing new values into the COM. Caution must be exercised when accessing the COM. If it were to be accessed simultaneously by the compare logic and by a write, the old compare value may actually get compared to the counter value. Freescale Semiconductor, Inc... 8.3.2 Square-Wave Generator This mode can be used for generating both square-wave output and periodic interrupts. The square wave is generated by counting down from the value in the PREL1 to timeout (counter value of $0000). TOUTx changes state on each timeout as programmed. This mode can be selected by programming the CR MODEx bits to 001. The timer is enabled by setting the SWR and CPE bits in the CR and, if TGATE is programmed to control the enabling and disabling of the counter (TGE bit set in the CR), then asserting TGATE. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL1 (N). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first timeout can range from N to N + 1 periods. When TGATE is used to enable the timer, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first timeout can be known. For additional details on timing, see Section 11 Electrical Characteristics. TOUTx behaves as a square wave when the OCx bits of the CR are programmed for toggle mode. A timeout occurs every N + 1 periods (allowing for the zero cycle), resulting in a change of state on TOUTx (see Figure 8-5). The SR OUT bit reflects the level of TOUTx. If this mode is used to generate periodic interrupts, TOUTx may be enabled if a square wave is also desired. COUNTER CLOCK COUNTER TOUT 0 0 3 2 1 0 3 2 1 0 3 N+1 TIMEOUT 1 0 3 N+1 N: N + 1 ENABLE 2 TIMEOUT TIMEOUT MODEx Bits in Control Register = 001 Preload 1 Register = N = 3 OCx Bits in Control Register = 01 Figure 8-5. Square-Wave Generator Mode If TGATE is negated when it is enabled to control the timer (TGE = 1), the prescaler and counter are disabled. Additionally, the SR TG bit is set, indicating that TGATE was negated. The SR ON bit is cleared, indicating that the timer is disabled. If TGATE is 8-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. reasserted, the timer is re-enabled and begins counting from the value attained when TGATE was negated. The SR ON bit is set again. If TGATE is disabled (TGE = 0), TGATE has no effect on the operation of the timer. In this case, the counter begins counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The TG bit of the SR cannot be set. At all times, TGL in the SR reflects the level of TGATE. Freescale Semiconductor, Inc... If the counter counts down to the value stored in the COM register, then the COM and TC bits in the SR are set. The counter continues counting down to timeout. At this time, the SR TO bit is set, and the SR COM bit is cleared. The next falling edge of the counter clock after timeout causes the value in PREL1 to be loaded back into the counter, and the counter begins counting down from this value. The period of the square-wave generator can be changed dynamically by writing a new value into the PREL1. Caution must be used because, if PREL1 is accessed simultaneously by the counting logic and a CPU32 write, the old PREL1 value may actually get loaded into the counter at timeout. Periodic interrupt generation can be accomplished by enabling the TO, TG, and/or TC bits in the SR to generate interrupts by programming the CR IE bits. When enabled, the programmed IRQ signal is asserted whenever the specified bits are set. 8.3.3 Variable Duty-Cycle Square-Wave Generator In this mode, both the PREL1 and PREL2 registers are used to generate a square wave with virtually any duty cycle. The square wave is generated by counting down from the value in the PREL1 to timeout (count value $0000), then loading that value from PREL2 and again counting down to timeout. When this second timeout occurs, the value from PREL1 is loaded into the counter, and the cycle repeats. TOUTx can be programmed to change state with every timeout, thus generating a variable duty-cycle square wave. This mode can be selected by programming the MODE bits in the CR to 010. The timer is enabled by setting both the SWR and CPE bits in the CR and, if TGATE is enabled (CR TGE bit is set), then asserting TGATE. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL1 register (N1). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first timeout can range from N1 to N1+1 periods. When TGATE is used to enable the timer, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first timeout can be known. For additional details on timing, see the Section 11 Electrical Characteristics. If the counter counts down to the value stored in the COM register, the COM and timer compare interrupt (TC) bits in the SR are set. The counter continues counting down to timeout. At this time, the TO bit in the SR is set, and the COM bit is cleared. The next falling edge of the counter clock after timeout causes the value in PREL2 (N2) to be loaded into the counter, and the counter begins counting down from this value. Each MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-9 Freescale Semiconductor, Inc. successive timeout causes the counter to be loaded alternately with the values from PREL1 and PREL2. TOUTx behaves as a variable duty-cycle square wave when the CR OC bits are programmed for toggle mode. The second timeout occurs after N2 + 1 periods (allowing for the zero cycle), resulting in a change of state on TOUTx. The third timeout occurs after N1 + 1 periods, resulting in a change of state on TOUTx, and so on (see Figure 8-6). The OUT bit in the SR reflects the level of TOUTx. COUNTER CLOCK Freescale Semiconductor, Inc... COUNTER TOUT 0 0 4 3 2 1 0 1 0 4 N2 + 1 N1: N1 + 1 ENABLE 2 TIMEOUT 3 2 1 0 1 0 N2 + 1 N1 + 1 TIMEOUT 2 TIMEOUT TIMEOUT MODEx Bits in Control Register = 010 Preload 1 Register = N1 = 4 Preload 2 Register = N2 = 2 OCx Bits in Control Register = 01 Figure 8-6. Variable Duty-Cycle Square-Wave Generator Mode If TGATE is negated when it is enabled (TGE = 1), the prescaler and counter are disabled. Additionally, the TG bit of the SR is set, indicating that TGATE was negated. The ON bit of the SR is cleared, indicating that the timer is disabled. If TGATE is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE was negated. The ON bit is set again. If TGATE is not enabled (TGE = 0), TGATE has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The SR TG bit cannot be set. At all times, the TGL bit in the SR reflects the level of TGATE. The duty cycle of the waveform generated on TOUTx can be dynamically changed by writing new values into PREL1 and/or PREL2. If PREL1 or PREL2 is being accessed simultaneously by the counter logic and a CPU32 write, the old preload value may actually get loaded into the counter at timeout. If at timeout, the counting logic was accessing PREL2 and the CPU32 was writing to PREL1 (or visa versa), there would be no unexpected results. 8.3.4 Variable-Width Single-Shot Pulse Generator This mode is used to produce a one-time pulse that has a delay controlled by the value stored in PREL1 and a duration controlled by the value stored in PREL2. With TOUTx programmed to change state, this sequence creates a single pulse of variable width. This mode can be selected by programming the CR MODE bits to 011. 8-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... The timer is enabled by setting both the SWR and CPE bits in the CR and, if TGATE is enabled (TGE bit in the CR is set), then asserting TGATE. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL1 register (N1). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first timeout can range from N1 to N1 + 1 periods. When TGATE is used to enable the counter, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first timeout can be known. For additional details on timing, see Section 11 Electrical Characteristics. If the counter counts down to the value stored in the COM, the COM and TC bits in the SR are set. The counter continues counting down to timeout. At this time, the SR TO bit is set and the SR COM bit is cleared. The next falling edge of the counter clock after timeout causes the value in PREL2 (N2) to be loaded into the counter, and the counter begins counting down from this value. After the second timeout, the selected clock is held high, disabling the prescaler and counter. Additionally, the SR ON and COM bits are cleared. TOUTx behaves as a variable-width pulse when the OCx bits of the CR are programmed for toggle mode. TOUTx is a logic zero between the time that the timer is enabled and the first timeout. When this event occurs, TOUTx transitions to a logic one. The second timeout occurs after N2 + 1 periods (allowing for the zero cycle), resulting in TOUTx returning to a logic zero (see Figure 8-7). The OUT bit in the SR reflects the level of TOUTx. COUNTER CLOCK COUNTER 0 0 TOUT 2 1 0 5 3 2 1 0 N2 + 1 N1: N1 + 1 ENABLE 4 TIMEOUT TIMEOUT MODEx Bits in Control Register = 011 Preload 1 Register = N1 = 2 Preload 2 Register = N2 = 5 OCx bits in Control Register = 01 Figure 8-7. Variable-Width Single-Shot Pulse Generator Mode If TGATE is negated when it is enabled (TGE = 1), the prescaler and counter are disabled. Additionally, the SR TG bit is set, indicating that TGATE was negated. The SR ON bit is cleared, indicating that the timer is disabled. If TGATE is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE was negated. The ON bit is set again. If TGATE is not enabled (TGE = 0), TGATE has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-11 Freescale Semiconductor, Inc. immediately after the SWR and CPE bits in the CR are set. The SR TG bit cannot be set. At all times, the TGL bit in the SR reflects the level of TGATE. The width of the pulse generated on TOUTx (the value in PREL2) can be changed while the counter is counting down from the value in PREL1. Caution must be used because, if PREL2 is accessed simultaneously by the counting logic and a CPU32 write, the old PREL2 value may actually get loaded into the counter at timeout. Freescale Semiconductor, Inc... 8.3.5 Pulse-Width Measurement This mode is used to count the clock cycles during a particular event (see Figure 8-8). The event is defined by the assertion and negation of TGATE. When TGATE is asserted, the counter begins counting down from $FFFF. When TGATE is negated, the counter stops counting and holds the value at which it stopped. Further assertions and negations of TGATE have no effect on the counter. This mode can be selected by programming the CR MODEx bits to 100. The timer is enabled by setting the SWR, CPE, and TGE bits in the CR. Asserting TGATE starts the counter. When the timer is enabled, the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded with the value $FFFF. With each successive falling edge of the counter clock, the counter decrements. The PREL1 and PREL2 registers are not used in this mode. When TGATE is negated, the SR TG bit is set, the ON bit is negated, and the prescaler and counter are disabled. Subsequent transitions on TGATE do not re-enable the counter. The TGL bit in the SR reflects the level of TGATE at all times. COUNTER CLOCK COUNTER 0 f f f f TGATE f f f e f f f d f f f c f f f b f f f b MEASURED PULSE ENABLE START COUNTING STOP COUNTING NO EFFECT MODEx Bits in Control Register = 100 TGE Bit of Control Register = 1 Figure 8-8. Pulse-Width Measurement Mode If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a timeout is detected. This sets the SR TO, and the clears the COM bit. At timeout, the next falling edge of the counter clock 8-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. causes the counter to reload with $FFFF. TOUTx transitions at timeout or is disabled as programmed by the CR OCx bits. The SR OUT bit reflects the level on TOUTx. To determine the number of cycles counted, the value in the CNTR must be read, inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater duration, the value in the POx bits in the SR is readable and can be thought of as an extension of the least significant bits in the CNTR. NOTE Freescale Semiconductor, Inc... Once the timer has been enabled, do not clear the SR TG bit until the pulse has been measured and TGATE has been negated. 8.3.6 Period Measurement This mode is used to count the period of a particular event. The event is defined by the assertion, negation, and subsequent reassertion of TGATE. When TGATE is asserted, the counter begins counting down from $FFFF. The negation of TGATE has no effect on the counter. When TGATE is reasserted, the counter stops counting and holds the value at which it stopped. Further assertions and negations of TGATE have no effect on the counter. This mode can be selected by programming the CR MODEx bits to 101. The timer is enabled by setting the SWR, CPE, and the TGE bits in the CR. The assertion of TGATE starts the counter. When the timer is enabled, the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded with the value of $FFFF. With each successive falling edge of the counter clock, the counter decrements. The PREL1 and PREL2 registers are not used in this mode. The first negation of TGATE is ignored, but on the second assertion of TGATE, the SR TG bit is set, the SR ON bit is negated, and the prescaler and counter are disabled. Subsequent transitions on TGATE do not re-enable the counter. See Figure 8-9 for a depiction of this mode. The SR TGL bit reflects the level of TGATE at all times. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-13 Freescale Semiconductor, Inc. COUNTER CLOCK COUNTER 0 f f f f f f f e f f f d f f f c f f f b f f f a f f f 9 f f f 9 TGATE ENABLE PERIOD MEASURED START COUNTING STOP COUNTING NO EFFECT Freescale Semiconductor, Inc... MODEx Bits in Control Register = 101 TGE Bit of Control Register = 1 Figure 8-9. Period Measurement Mode If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a timeout is detected. This sets the SR TO bit, and clears the SR COM bit. At timeout, the next falling edge of the counter clock reloads the counter with $FFFF. TOUTx transitions at timeout or is disabled as programmed by the OCx bits of the CR, and the OUT bit in the SR reflects the level on TOUTx. To determine the number of cycles counted, the value in the CNTR must be read, inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater duration, the value in the POx bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR. NOTE Once the timer has been enabled, do not clear the SR TG bit until the pulse has been measured and TGATE has been negated. 8.3.7 Event Count This mode is used to count events by interpreting the falling edges of the counter clock as events (see Figure 8-10). These events may be external or internal to the chip--for example, counting the number of system clock cycles required to execute a sequence of instructions. As another example, by connecting AS to TINx, the number of bus cycles to complete a sequence of instructions could be counted. This mode can be selected by programming the CR MODEx bits to 110. 8-14 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. COUNTER CLOCK COUNTER 0 f f f f f f f e f f f d f f f c f f f b 0 0 0 2 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 f f f f f f f e TGATE ENABLE TG BIT SET TIMEOUT TO BIT SET Freescale Semiconductor, Inc... MODEx Bits in Control Register = 110 TGE Bit of the Control Register = 1 Figure 8-10. Event Count Mode The timer is enabled by setting the SWR and CPE bits in the CR and, if TGATE is enabled (TGE bit of the CR is set), then asserting TGATE. When the timer is enabled, the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded with the value of $FFFF. With each successive falling edge of the counter clock, the counter decrements. The PREL1 and PREL2 registers are not used in this mode. If TGATE is not enabled (CR TGE bit is cleared), then TGATE does not start or stop the timer or affect the TG bit of the SR. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. If TGATE is enabled (CR TGE bit is set), then the assertion of TGATE starts the counter. The negation of TGATE disables the counter, sets the SR TG bit, and clears the ON bit in the SR. If TGATE is reasserted, the timer resumes counting from where it was stopped, and the ON bit is set again. Further assertions and negations of TGATE have the same effect. The TGL bit in the SR reflects the level of TGATE at all times. If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a timeout is detected. This event sets the TO in the SR and clears the COM bit. At timeout, the next falling edge of the counter clock reloads the counter with $FFFF. TOUTx transitions at timeout or is disabled as programmed by the CR OC bits. The SR OUT bit reflects the level on TOUTx. To determine the number of cycles counted, the value in the CNTR must be read, inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater duration, the value in the POx bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-15 Freescale Semiconductor, Inc. 8.3.8 Timer Bypass In this mode, the counter and prescaler cannot be enabled. However TGATE and TOUTx can be used for I/O. This mode can be selected by programming the CR MODE bits to 111. TGATE can be used as a simple input port when the CR is configured as follows: CR 15 14 13 12 11 10 9 8 7 6 5 SWR IE2 IE1 IE0 TGE PCLK CPE CLK POT2 POT1 POT0 X X 1 X X X X 4 3 2 MODE2 MODE1 MODE0 1 0 OC1 OC0 X X TGATE AS A SIMPLE INPUT Freescale Semiconductor, Inc... X X 0 X 1 1 1 X-Don't care When TGATE is asserted, the SR ON bit is set. When TGATE is negated, the ON bit is cleared. The value of the TGL bit in the SR reflects the level of TGATE. TGATE can also be used as an input port that generates interrupts on a low-to-high transition of TGATE when the CR is configured as follows: CR 15 14 13 12 11 SWR IE2 IE1 IE0 TGE 10 9 8 7 6 5 PCLK CPE CLK POT2 POT1 POT0 X 1 X X X X 4 3 2 MODE2 MODE1 MODE0 1 0 OC1 OC0 X X TGATE AS AN INPUT/INTERRUPT X X 1 X 1 1 1 1 When TGATE is negated, the SR TG bit is set, and the programmed IRQx signal is asserted to the CPU32. The TG bit can only be cleared by writing a one to this bit position. The value of the SR TGL bit reflects the level of TGATE. Additionally, TOUTx can be used as a simple output port when the CR is configured as follows: CR 15 14 13 12 11 10 9 8 7 6 5 SWR IE2 IE1 IE0 TGE PCLK CPE CLK POT2 POT1 POT0 X X 1 X X X X 4 3 2 MODE2 MODE1 MODE0 1 0 OC1 OC0 OC1 OC0 TGATE AS A SIMPLE OUTPUT 0 X X X 1 1 1 SWR must be a zero to change the value of TOUTx. Changing the value of the CR OCx bits determines the level of TOUTx as shown in Table 8-1. 8-16 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table 8-1. OCx Encoding OC1 OC0 TOUTx 0 0 Hi-Z 0 1 0 1 0 0 1 1 1 A read of the SR while in this mode always shows the TO, TC, and COM bits cleared, and the PO bits as $FF. The SR OUT bit always indicates the level on the TOUTx pin. Freescale Semiconductor, Inc... 8.3.9 Bus Operation The following paragraphs describe the operation of the IMB during read, write, and interrupt acknowledge cycles to the timer. 8.3.9.1 READ CYCLES. The timer is accessed with no wait states. The timer responds to byte, word, and long-word reads, and 16 bits of valid data are returned. Read cycles from reserved registers return logic zero. 8.3.9.2 WRITE CYCLES. The timer is accessed with no wait states. The timer responds to byte, word, and long-word writes. Write cycles to read-only registers and bits as well as reserved registers complete in a normal manner without exception processing; however, the data is ignored. 8.3.9.3 INTERRUPT ACKNOWLEDGE CYCLES. The timer is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus, the interrupt register (IR) must be initialized. If the IR is not initialized, a spurious interrupt exception will be taken if interrupt servicing is necessary. 8.4 REGISTER DESCRIPTION The following paragraphs contain a detailed description of each register and its specific function. The operation of the timer is controlled by writing control words into the appropriate registers. Timer registers and their associated addresses are listed in Figure 8-11. For more information about a particular register, refer to the individual register description. The ADDR column indicates the offset of the register from the base address of the timer. An FC column designation of S indicates that register access is restricted to supervisor only. A designation of S/U indicates that access is governed by the SUPV bit in the module configuration register (MCR). MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-17 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. TIMER 1 TIMER 2 FC 15 0 $600 $640 S MODULE CONFIGURATION REGISTER (MCR) $602 $642 S RESERVED $604 $644 S INTERRUPT REGISTER (IR) $606 $646 S/U CONTROL REGISTER (CR) $608 $648 S/U STATUS/PRESCALER REGISTER (SR) $60A $64A S/U COUNTER REGISTER (CNTR) $60C $64C S/U PRELOAD 1 REGISTER (PREL1) $60E $64E S/U PRELOAD 2 REGISTER (PREL2) $610 $650 S/U COMPARE REGISTER (COM) $612-$63F $652-$67F S/U RESERVED Figure 8-11. Timer Module Programming Model In the registers discussed in the following paragraphs, the numbers in the upper righthand corner indicate the offset of the register from the base address specified by the module base address register (MBAR) in the SIM40. The first number is the offset for timer 1; the second number is the offset for timer 2. The numbers on the top line of the register represent the bit position in the register. The register contains the mnemonic for the bit. The value of these bits after a hardware reset is shown below the register. The access privilege is shown in the lower right-hand corner. NOTE A CPU32 RESET instruction will not affect the MCR, but will reset all other registers in the timer modules as though a hardware reset occurred. The term 'timer' is used to reference either timer 1 or timer 2, since the two are functionally equivalent. 8.4.1 Module Configuration Register (MCR) The MCR controls the timer module configuration. This register can be either read or written when the module is enabled and is in the supervisor state. The MCR is not affected by a CPU32 RESET instruction. MCR $600, $640 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STP FRZ1 FRZ0 0 0 0 0 0 SUPV 0 0 0 IARB3 IARB2 IARB1 IARB0 RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Supervisor Only 8-18 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... STP--Stop bit 1 = Setting the STP bit stops all clocks within the timer module except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR. The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to timer module registers while in stop mode produce a bus error. The timer module should be disabled in a known state prior to setting the STP bit; otherwise, unpredictable results may occur. The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption. 0 = The timer operates in normal mode. FRZ1, FRZ0--Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB, when the CPU32 has entered background debug mode. Table 8-2 lists the action taken for each bit combination. Table 8-2. FRZx Control Bits FRZ1 FRZ0 ACTION 0 0 Ignore FREEZE 0 1 Reserved (FREEZE ignored) 1 0 Execution Freeze 1 1 Execution Freeze Bits 12-8, 6-4--Reserved SUPV--Supervisor/User The value of this bit has no effect on registers permanently defined as supervisor-only access. 1 = The timer registers defined as supervisor/user reside in supervisor data space and are only accessible from supervisor programs. 0 = The timer registers defined as supervisor/user reside in user data space and are accessible from either supervisor or user programs. IARB3-IARB0--Interrupt Arbitration Bits Each module that generates interrupts has an IARB field. These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. (Timer 1 and timer 2 should be programmed with different values if both are used.) The reset value of the IARB field is $0, which prevents this module from arbitrating during the interrupt acknowledge cycle. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-19 Freescale Semiconductor, Inc. 8.4.2 Interrupt Register (IR) The IR contains the priority level for the timer interrupt request and the 8-bit vector number of the interrupt. The register can be read or written to at any time while in supervisor mode and while the timer module is enabled (i.e., the STP bit in the MCR is cleared). IR $604, $644 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 IL2 IL1 IL0 IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Supervisor Only Freescale Semiconductor, Inc... Bits 15-11--Reserved IL2-IL0--Interrupt Level Bits Each module that can generate interrupts has an interrupt level field. The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal. The CPU32 uses this value to determine servicing priority. See Section 5 CPU32 for more information. IV7-IV0--Interrupt Vector Bits Each module that can generate interrupts has an interrupt vector (IV) field. This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The IV field is reset to $0F, which indicates an uninitialized interrupt condition. See Section 5 CPU32 for more information. 8.4.3 Control Register (CR) The CR controls the operation of the timer. The register can always be read or written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). Changing the contents of the CR should only be attempted when the timer is disabled (the SWR bit in the CR is cleared). Changing the CR while the timer is running may produce unpredictable results. CR $606, $646 15 14 13 12 11 10 9 8 7 6 5 SWR IE2 IE1 IE0 TGE PCLK CPE CLK POT2 POT1 POT0 RESET: 0 0 0 0 0 0 0 0 0 0 0 4 3 2 MODE2 MODE1 MODE0 0 0 0 1 0 OC1 OC0 0 0 Supervisor/User SWR--Software Reset 1 = Removes the software reset. 0 = A software reset is performed by first clearing this bit and then clearing the TO, TG, and TC bits in the SR. The prescaler is loaded with $FF, the counter is set to $0000, and the SR COM bit is cleared. When this bit is zero, the timer is disabled. 8-20 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. IE2-IE0--Interrupt Enable These bits determine which sources of interrupts, TO, TG, and TC, are enabled to generate an interrupt request to the CPU32. Table 8-3 lists which interrupts are enabled for all bit combinations. Freescale Semiconductor, Inc... Table 8-3. IEx Encoding IE2 IE1 IE0 Enabled Interrupts 0 0 0 Polling Mode (No Interrupts Enabled) 0 0 1 TC Enabled 0 1 0 TG Enabled 0 1 1 TG and TC Enabled 1 0 0 TO Enabled 1 0 1 TO and TC Enabled 1 1 0 TO and TG Enabled 1 1 1 TO, TG, and TC Enabled TGE--Timing Gate Enable 1 = The TGATE signal is enabled to control the enabling and disabling of the prescaler and counter, except in the input capture/output compare mode (see 8.3.1 Input Capture/Output Compare). 0 = The TGATE signal has no effect on the timer operation. PCLK--Prescaler Clock Select This bit selects which clock is used for the counter clock. 1 = The counter is decremented by the prescaler output tap as selected by the POT field in the CR. 0 = The counter is decremented by the selected clock. The prescaler continues to decrement regardless of how PCLK is set. CPE--Counter Prescaler Enable 1 = The selected clock is enabled. If the TGE bit is set, then TGATE must also be asserted (except in the input capture/output compare mode). 0 = The selected clock is held high, halting the prescaler and counter. CLK--Clock 1 = The selected clock is taken from the TINx input. 0 = The selected clock is one-half the system clock's frequency. The TOUTx of one timer can be fed externally into the TINx input of the other timer, resulting in a 32-bit counter if the prescalers are not used and a 48-bit counter if they are used. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-21 Freescale Semiconductor, Inc. POT2-POT0--Prescaler Output Tap If PCLK is set, these bits encode which of the prescaler's output taps act as the counter clock. A division of the selected clock is applied to the counter as listed in Table 8-4. Freescale Semiconductor, Inc... Table 8-4. POT Encoding Division of Selected Clock POT2 POT1 POT0 0 0 1 Divide by 2 0 1 0 Divide by 4 0 1 1 Divide by 8 1 0 0 Divide by 16 1 0 1 Divide by 32 1 1 0 Divide by 64 1 1 1 Divide by 128 0 0 0 Divide by 256 MODE2-MODE0--Operation Mode These bits select one of the eight modes of operation for the timer as listed in Table 8-5. Refer to 8.3 Operating Modes for more information on the individual modes. Table 8-5. MODEx Encoding MODE2 MODE1 MODE0 OPERATION MODE 0 0 0 Input Capture/Output Compare 0 0 1 Square-Wave Generator 0 1 0 Variable Duty-Cycle Square-Wave Generator 0 1 1 Variable-Width Single-Shot Pulse Generator 1 0 0 Pulse-Width Measurement 1 0 1 Period Measurement 1 1 0 Event Count 1 1 1 Timer Bypass (Simple Test Mode) OC1-OC0--Output Control These bits select the conditions under which TOUTx changes (see Table 8-6). These bits may have a different effect when in the input capture/output compare mode. Caution should be used when modifying the OC bits near timer events. Table 8-6. OCx Encoding 8-22 OC1 OC0 TOUTx MODE 0 0 Disabled 0 1 Toggle Mode 1 0 Zero Mode 1 1 One Mode MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Disabled--TOUTx is disabled and three-stated. Freescale Semiconductor, Inc... Toggle Mode--If the timer is disabled (SWR = 0) when this encoding is programmed, TOUTx is immediately set to zero. If the timer is enabled (SWR = 1), timeout events (counter reaches $0000) toggle TOUTx. In the input capture/output compare mode, TOUTx is immediately set to zero if the timer is disabled (SWR = 0). If the timer is enabled (SWR = 1), timer compare events toggle TOUTx. (Timer compare events occur when the counter reaches the value stored in the COM.) Zero Mode--If the timer is disabled (SWR = 0) when this encoding is programmed, TOUTx is immediately set to zero. If the timer is enabled (SWR = 1), TOUTx will be set to zero at the next timeout. In the input capture/output compare mode, TOUTx is immediately set to zero if the timer is disabled (SWR = 0). If the timer is enabled (SWR = 1), TOUTx will be set to zero at timeouts and set to one at timer compare events. If the COM is $0000, TOUTx will be set to zero at the timeout/timer compare event. One Mode--If the timer is disabled (SWR = 0) when this encoding is programmed, TOUTx is immediately set to one. If the timer is enabled (SWR = 1), TOUTx will be set to one at the next timeout. In the input capture/output compare mode, TOUTx is immediately set to one if the timer is disabled (SWR = 0). If the timer is enabled (SWR = 1), TOUTx will be set to one at timeouts and set to zero at timer compare events. If the COM is $0000, TOUTx will be set to one at the timeout/timer compare event. 8.4.4 Status Register (SR) The SR contains timer status information as well as the state of the prescaler. This register is updated on the rising edge of the system clock when a read of its location is not in progress, allowing the most current information to be contained in this register. The register can be read, and the TO, TG, and TC bits can be written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). SR $608, $648 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ TO TG TC TGL ON OUT COM PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 RESET ( TGATE NEGATED): 0 0 0 0 RESET ( TGATE ASSERTED): 0 0 0 0 Supervisor/User IRQ--Interrupt Request bit The positioning of this bit in the most significant location in this register allows it it be conditionally tested as if it were a signed binary integer. 1 = An interrupt condition has occurred. This bit is the logical OR of the enabled TO, TG, and TC interrupt bits. 0 = The bit(s) that caused the interrupt condition has been cleared. If an IRQ signal has been asserted, it is negated when this bit is cleared. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-23 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... TO--Timeout Interrupt 1 = The counter has transitioned from $0001 to $0000, and the counter has rolled over. This bit does not affect the programmed IRQ signal if the IE2 bit in the CR is cleared. 0 = This bit is cleared by the timer whenever the RESET signal is asserted on the IMB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR = 0). TG--Timer Gate Interrupt 1 = This bit is set whenever the CR TGE bit is set and the TGATE signal transitions in the manner to which the particular mode of operation responds. Refer to 8.3 Operating Modes for more details. This bit does not affect the programmed IRQ signal if the IE1 bit in the CR is cleared. 0 = This bit is cleared by the timer whenever the RESET signal is asserted on the IMB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR = 0). TC--Timer Compare Interrupt 1 = This bit is set when the counter transitions (off a clock/event falling edge) to the value in the COM. This bit does not affect the programmed IRQ signal if the IE0 bit in the CR is cleared. 0 = This bit is cleared by the timer whenever the RESET signal is asserted on the IMB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR = 0). TGL--TGATE Level 1 = The TGATE signal is negated. 0 = The TGATE signal is asserted. ON--Counter Enabled 1 = This bit is set whenever the SWR and CPE bits are set in the CR. If the CR TGE bit is set, TGATE must also be asserted (except in the input capture/output compare mode) since this signal then controls the enabling and disabling of the counter. If all these conditions are met, the counter is enabled and begins counting down. 0 = The counter is not enabled and does not begin counting down. OUT--Output Level 1 = TOUTx is a logic one. 0 = TOUTx is a logic zero, or the pin is three-stated. COM--Compare Bit This bit is used to indicate when the counter output value is at or between the value in the COM and $0000 (timeout). 8-24 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 1 = This bit is set when the counter output equals the value in the COM. 0 = This bit is cleared when a timeout occurs, the COM register is accessed (read or write), the timer is reset with the SWR bit, or the RESET signal is asserted on the IMB. This bit is cleared regardless of the state of the TC bit. This bit can be used to indicate when a write to the PREL1 or PREL2 registers will not cause a problem during a counter reload at timeout. To ensure that the write to the PREL register is recognized at timeout, the latency between the read of the COM bit and the write to the PREL register must be considered. Freescale Semiconductor, Inc... PO7-PO0--Prescaler Output These bits show the levels on each of the eight output taps of the prescaler. These values are updated every time that the system clock goes high and a read cycle of this byte in the SR is not in progress. 8.4.5 Counter Register (CNTR) The CNTR reflects the value of the counter. This value can be reliably read at any time since it is updated on every rising edge of the system clock (except in the input capture/output compare mode) when a read of the register is not in progress. This readonly register can be read when the timer module is enabled (i.e. the STP bit in the MCR is cleared). CNTR $60A, $64A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET: 0 Supervisor/User All 24 bits of the prescaler and the counter may be obtained by one long-word read at the address of the SR, since the CNTR is contiguous to it. Any changes in the prescaler value due to the two cycles necessary to perform a long-word read should be considered. If this latency presents a problem, the TGATE signal may be used to disable the decrement function while the reads are occurring. 8.4.6 Preload 1 Register (PREL1) The PREL1 stores a value that is loaded into the counter in some modes of operation. This value is loaded into the counter on the first falling edge of the counter clock after the counter is enabled. This register can be be read and written when the timer module is enabled (i.e. the STP bit in the MCR is cleared). However, a write to this register must be completed before timeout for the new value to be reliably loaded into the counter. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-25 Freescale Semiconductor, Inc. PREL1 15 $60C, $64C 14 13 12 11 10 PR1-15 PR1-14 PR1-13 PR1-12 PR1-11 PR1-10 9 8 7 6 5 4 3 2 1 0 PR1-9 PR1-8 PR1-7 PR1-6 PR1-5 PR1-4 PR1-3 PR1-2 PR1-1 PR1-0 1 1 1 1 1 1 1 1 1 1 RESET: 1 1 1 1 1 1 Supervisor/User For some modes of operation, this register is also used to reload the counter one falling clock edge after a timeout occurs. Refer to 8.3 Operating Modes for more information on the individual modes. Freescale Semiconductor, Inc... 8.4.7 Preload 2 Register (PREL2) PREL2 is used in addition to PREL1 in the variable duty-cycle square-wave generator and variable-width single-shot pulse generator modes. When in either of these modes, the value in PREL1 is loaded into the counter on the first falling edge of the counter clock after the counter is enabled. After timeout, the value in PREL2 is loaded into the counter. This register can be be read and written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). However, a write to this register must be completed before timeout for the new value to be reliably loaded into the counter. PREL2 15 $60E, $64E 14 13 12 11 10 PR2-15 PR2-14 PR2-13 PR2-12 PR2-11 PR2-10 9 8 7 6 5 4 3 2 1 0 PR2-9 PR2-8 PR2-7 PR2-6 PR2-5 PR2-4 PR2-3 PR2-2 PR2-1 PR2-0 1 1 1 1 1 1 1 1 1 1 RESET: 1 1 1 1 1 1 Supervisor/User 8.4.8 Compare Register (COM) The COM can be used in any mode. When the 16-bit counter reaches the value in the COM, the TC and COM bits in the SR are set. In the input capture/output compare mode, a compare event can be programmed to set, clear, or toggle TOUTx. The register can be be read and written when the timer module is enabled (i.e., the STP bit in the MCR is cleared). COM 15 $610, $650 14 13 12 11 10 COM15 COM14 COM13 COM12 COM11 COM10 9 8 7 6 5 4 3 2 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 0 0 0 0 0 0 0 0 1 COM1 0 COM0 RESET: 0 0 0 0 0 0 0 0 Supervisor/User The COM can be used to produce an interrupt when the SR TC bit has been enabled to produce an interrupt and the counter counts down to a preselected value. The COM can also be used to indicate that the timer is approaching timeout. 8-26 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Caution must be exercised when accessing the COM. If it were to be accessed simultaneously by the compare logic and by a write, the old compare value may get compared to the counter value. 8.5 TIMER MODULE INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the timer module. Since both timers are functionally equivalent, only one timer module will be referenced. Freescale Semiconductor, Inc... 8.5.1 Timer Module Configuration If the timer capability of the MC68340 is being used, the following steps should be followed to initialize a timer module properly. Note that this sequence must be done for each timer module used. Control Register (CR) * Clear the SWR bit to disable the timer. Status Register (SR) * Clear the TO, TG, and TG bits to reset the interrupts. Module Configuration Register (MCR) * Initialize the STP for normal operation. * Select whether to respond to or ignore FREEZE (FRZx bits). * Select the access privilege for the supervisor/user registers (SUPV bit). * Select the interrupt arbitration level for the timer module (IARBx bits). Interrupt Register (IR) * Program the interrupt priority level for the timer interrupts (ILx bits). * Program the interrupt vector number for the timer interrupts (IVx bits). Preload Registers (PREL1 and PREL2) * If required, initialize the preload registers for mode of operation. Compare Register (COM) * If desired, initialize the compare register. The following steps begin operation: Control Register (CR) * Set the SWR bit to enable the timer. * Enable the desired interrupts (IEx bits). * Enable TGATE if required for mode of operation (TGE bit). * Select the prescaler clock (PCLK bit). MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-27 Freescale Semiconductor, Inc. * Enable the counter prescaler (CPE bit). * Select the selected clock (CLK bit). * If the PCLK bit is set, select the POTx bits. * Select the mode of operation (MODEx bits). * Select the operation of TOUT (OCx bits). 8.5.2 Timer Module Example Configuration Code Freescale Semiconductor, Inc... The following code is an example of a configuration sequence for the timer module. *************************************************************************** * MC68340 basic timer module register initialization example code. * This code is used to initialize the 68340's internal timer module * registers, providing basic functions for operation. * It sets up timer1 for square wave generation. *************************************************************************** *************************************************************************** * equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value *************************************************************************** * Timer1 module equates TIMER1 EQU $600 Offset from MBAR for timer1 module regs MCR1 EQU $0 MCR for timer1 * Timer1 register offsets from timer1 base address IR1 EQU $604 interrupt register timer1 CR1 EQU $606 control register timer1 SR1 EQU $608 status register timer1 CNTR1 EQU $60A counter register timer1 PRLD11 EQU $60C preload register 1 timer1 COM1 EQU $610 compare register timer1 *************************************************************************** *************************************************************************** * Initialize Timer1 *************************************************************************** LEA MODBASE+TIMER1,A0 Pointer to timer1 module * Disable timer1 CLR.W CR1(A0) * Clear the TO, TG, and TC bits CLR.W SR1(A0) 8-28 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. * Module configuration register: * Timer1 module is set for normal operation, ignore FREEZE. * Supervisor/user timer1 registers unrestricted. * Interrupt arbitration at priority $03. MOVE.W #$0003,MCR1(A0) * Initialize timer1 interrupt level to 2 and vector to $0F MOVE.W #$020F,IR1(A0) Freescale Semiconductor, Inc... * Initialize preload 1 to 3 MOVE.W #$0003,PRLD11(A0) * Initialize the compare register to 0 CLR.W COM1(A0) * Control register 1: * Enable timer1, no interrupts are enabled, TGATE signal has no effect. * Use the selected clock for the counter clock, and enable it. * Selected clock is 1/2 system's freq. Square-wave generation, toggle TOUT. MOVE.W #$8205,CR1(A0) *************************************************************************** END *************************************************************************** *************************************************************************** * MC68340 basic timer module register initialization example code. * This code is used to initialize the 68340's internal timer module * registers, providing basic functions for operation. * It sets up timer1 for pulse-width measurement. In this mode, the number * of clock cycles during a particular event are counted. The event is * defined by the assertion and negation of TGATE. *************************************************************************** *************************************************************************** * equates *************************************************************************** MBAR EQU $0003FF00 Address of SIM40 Module Base Address Reg. MODBASE EQU $FFFFF000 SIM40 MBAR address value *************************************************************************** * Timer1 module equates TIMER1 EQU $600 Offset from MBAR for timer1 module regs MCR1 EQU $0 MCR for timer1 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-29 Freescale Semiconductor, Inc. * Timer1 register offsets from timer1 base address IR1 EQU $604 interrupt register timer1 CR1 EQU $606 control register timer1 SR1 EQU $608 status register timer1 CNTR1 EQU $60A counter register timer1 COM1 EQU $610 compare register timer1 Freescale Semiconductor, Inc... *************************************************************************** *************************************************************************** * Initialize Timer1 *************************************************************************** LEA MODBASE+TIMER1,A0 Pointer to timer1 module * Disable timer1 CLR.W CR1(A0) * Allow TGATE to negate and assert so that an accurate count will result. * If SR1 TGL bit=1, continue looping. TGATE is negated. LOOP1 BTST.B #$3,SR1(A0) BNE.B LOOP1 * If TGL bit=0, continue looping. TGATE is asserted. LOOP2 BTST.B #$3,SR1(A0) BEQ.B LOOP2 * Ready to initialize timer1, TGATE is negated. * Module configuration register: * Timer1 module is set for normal operation, ignore FREEZE. * Supervisor/user timer1 registers unrestricted. * Interrupt arbitration at priority $03. MOVE.W #$0003,MCR1(A0) * Initialize timer1 interrupt level to 2 and vector to $0F MOVE.W #$020F,IR1(A0) * Initialize the compare register to 0 CLR.W COM1(A0) * Clear the SR1 TG bit (by writing a 1) to use as a flag MOVE.B #$20,SR1(A0) * Control register 1: * Enable timer1, no interrupts are enabled, TGATE signal used to control * the counter. Use the selected clock for the counter clock, and enable it. * Selected clock is 1/2 system's freq. Pulse-width measurement, * disable TOUT. 8-30 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MOVE.W #$8A10,CR1(A0) Freescale Semiconductor, Inc... * If SR TG bit=0, continue looping TGATE is asserted, * else TG=1 indicating TGATE was negated. When TG=1, counting is stopped. LOOP3 BTST.B #$5,SR1(A0) BEQ.B LOOP3 * Counting is complete. To determine the number of cycles counted, the value * in CNTR1 must be read, inverted, and incremented by 1. MOVE.W CNTR1(A0),D0 NOT.W D0 ADDQ.W #$1,DO * D0 contains the number of cycles counted. *************************************************************************** END *************************************************************************** MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-31 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 9 IEEE 1149.1 TEST ACCESS PORT The MC68340 includes dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The MC68340 implementation supports circuit-board test strategies based on this standard. The test logic includes a test access port (TAP) consisting of four dedicated signal pins, a 16-state controller, an instruction register, and two test data registers. A boundary scan register links all device signal pins into a single shift register. The test logic, implemented using static logic design, is independent of the device system logic. The MC68340 implementation provides the following capabilities: a. Perform boundary scan operations to test circuit-board electrical continuity b. Sample the MC68340 system pins during operation and transparently shift out the result in the boundary scan register c. Bypass the MC68340 for a given circuit-board test by effectively reducing the boundary scan register to a single bit d. Disable the output drive to pins during circuit-board testing NOTE Certain precautions must be observed to ensure that the IEEE 1149.1 test logic does not interfere with nontest operation. See 9.6 Non-IEEE 1149.1 Operation for details. 9.1 OVERVIEW NOTE This description is not intended to be used without the supporting IEEE 1149.1 document. The discussion includes those items required by the standard and provides additional information specific to the MC68340 implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-1 Freescale Semiconductor, Inc. An overview of the MC68340 implementation of IEEE 1149.1 is shown in Figure 9-1. The MC68340 implementation includes a 16-state controller, a 3-bit instruction register, and two test registers (a 1-bit bypass register and a 132-bit boundary scan register). This implementation includes a dedicated TAP consisting of the following signals: a test clock input to synchronize the test logic a test mode select input (with an internal pullup resistor) that is sampled on the rising edge of TCK to sequence the TAP controller's state machine TDI -- a test data input (with an internal pullup resistor) that is sampled on the rising edge of TCK. TDO -- a three-state test data output that is actively driven in the shift-IR and shiftDR controller states. TDO changes on the falling edge of TCK. Freescale Semiconductor, Inc... TCK -- TMS -- TEST DATA REGISTERS 132 0 BOUNDARY SCAN REGISTER (133 BITS) M U X TDI BYPASS DECODER 2 0 M U X TDO 3-BIT INSTRUCTION REGISTER TMS TCK TAP CTLR Figure 9-1. Test Access Port Block Diagram 9.2 TAP CONTROLLER The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic. The state machine is shown in Figure 9-2; the value shown adjacent to each arc represents the value of the TMS signal sampled on the rising edge of the TCK signal. For a description of the TAP controller states, please refer to the IEEE 1149.1 document. 9-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 1 TEST LOGIC RESET 0 1 0 SELECT-DR_SCAN RUN-TEST/IDLE 1 1 SELECT-IR_SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 Freescale Semiconductor, Inc... SHIFT-DR SHIFT-IR 0 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR EXIT2-DR 0 1 1 0 0 0 EXIT2-IR 1 1 UPDATE -IR UPDATE-DR 1 1 0 0 Figure 9-2. TAP Controller State Machine 9.3 BOUNDARY SCAN REGISTER The MC68340 IEEE 1149.1 implementation has a 132-bit boundary scan register. This register contains bits for all device signal and clock pins and associated control signals. The XTAL, X2, and XFC pins are associated with analog signals and are not included in the boundary scan register. All MC68340 bidirectional pins, except the open-drain I/O pins (DONE1, DONE2, HALT, and RESET), have a single register bit for pin data and an associated control bit in the boundary scan register. All open drain I/O pins have two register bits, input and output, for pin data and no associated control bit. To ensure proper operation, the open-drain pins require external pullups. Twenty-three control bits in the boundary scan register define the output enable signal for associated groups of bidirectional and three-state pins. The control bits and their bit positions are listed in Table 9-1. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 9-1. Boundary Scan Control Bits Name Bit Number Name Bit Number Name Bit Number tout2.ctl 29 cs0.ctl 66 ab28.ctl 95 irq7.ctl 52 ab.ctl 83 ab29.ctl 97 irq6.ctl 54 berr.ctl 84 ab30.ctl 99 irq5.ctl 56 db.ctl 85 ab31.ctl 101 cs3.ctl 58 ab24.ctl 87 modck.ctl 122 irq3.ctl 60 ab25.ctl 89 ifetch.ctl 125 cs2.ctl 62 ab26.ctl 91 tout1.ctl 130 cs1.ctl 64 ab27.ctl 93 Boundary scan bit definitions are shown in Table 9-2. The first column in Table 9-2 defines the bit's ordinal position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted out is 131. The second column references one of the five MC68340 cell types depicted in Figures 9-3-9-7, which describe the cell structure for each type. The third column lists the pin name for all pin-related bits or defines the name of bidirectional control register bits. The active level of the control bits (i.e., output driver on) is defined by the last digit of the cell type listed for each control bit. For example, the active-high level for irq7.ctl (bit 52) is logic zero since the cell type is IO.Ctl0. The active level for ab.ctl (bit 83) is logic one, since the cell type is IO.Ctl1. IO.Ctl0 (see Figure 9-6) differs from IO.Ctl1 (see Figure 9-5) by an inverter in the output enable path. The fourth column lists the pin type: TS-Output indicates a three-state output pin, I/O indicates a bidirectional pin, and OD-I/O denotes an open-drain bidirectional pin. An opendrain output pin has two states: off (high impedance) and logic zero. The last column indicates the associated boundary scan register control bit for bidirectional, three-state, and open-drain output pins. Bidirectional pins include a single scan bit for data (IO.Cell) as depicted in Figure 9-7. These bits are controlled by one of the two bits shown in Figures 9-5 and 9-6. The value of the control bit determines whether the bidirectional pin is an input or an output. One or more bidirectional data bits can be serially connected to a control bit as shown in Figure 98. Note that, when sampling the bidirectional data bits, the bit data can be interpreted only after examining the IO control bit to determine pin direction. 9-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 9-2. Boundary Scan Bit Definitions Bit Num Cell Type Pin/Cell Name Pin Type Output CTL Cell Bit Num Cell Type Pin/Cell Name Pin Type Output CTL Cell 0 IO.Cell FC3 I/O* ab.ctl 35 O.Latch RRDYA Output -- 1 IO.Cell FC2 I/O* ab.ctl 36 O.Latch TRDYA Output -- 2 IO.Cell FC1 I/O* ab.ctl 37 I.Pin RxDB Input -- 3 IO.Cell FC0 I/O* ab.ctl 38 O.Latch TxDB Output -- 4 IO.Cell A23 I/O* ab.ctl 39 O.Latch RTSB Output -- 5 IO.Cell A22 I/O* ab.ctl 40 I.Pin CTSB Input -- 6 IO.Cell A21 I/O* ab.ctl 41 I.Pin SCLK Input -- 7 IO.Cell A20 I/O* ab.ctl 42 I.Pin X1 Input -- 8 IO.Cell A19 I/O* ab.ctl 43 I.Pin DREQ1 Input -- 9 IO.Cell A18 I/O* ab.ctl 44 O.Latch DACK1 Output -- 10 IO.Cell A17 I/O* ab.ctl 45 O.Latch DONE1 OD-I/O -- 11 IO.Cell A16 I/O* ab.ctl 46 I.Pin DONE1 OD-I/O -- 12 IO.Cell A15 I/O* ab.ctl 47 I.Pin DREQ2 Input -- 13 IO.Cell A14 I/O* ab.ctl 48 O.Latch DACK2 Output -- 14 IO.Cell A13 I/O* ab.ctl 49 O.Latch DONE2 OD-I/O -- 15 IO.Cell A12 I/O* ab.ctl 50 I.Pin DONE2 OD-I/O -- 16 IO.Cell A11 I/O* ab.ctl 51 IO.Cell IRQ7 I/O irq7.ctl 17 IO.Cell A10 I/O* ab.ctl 52 IO.Ctl0 irq7.ctl -- -- 18 IO.Cell A9 I/O* ab.ctl 53 IO.Cell IRQ6 I/O irq6.ctl 19 IO.Cell A8 I/O* ab.ctl 54 IO.Ctl0 irq6.ctl -- -- 20 IO.Cell A7 I/O* ab.ctl 55 IO.Cell IRQ5 I/O irq5.ctl 21 IO.Cell A6 I/O* ab.ctl 56 IO.Ctl0 irq5.ctl -- -- 22 IO.Cell A5 I/O* ab.ctl 57 IO.Cell CS3 I/O cs3.ctl 23 IO.Cell A4 I/O* ab.ctl 58 IO.Ctl0 cs3.ctl -- -- 24 IO.Cell A3 I/O* ab.ctl 59 IO.Cell IRQ3 I/O irq3.ctl 25 IO.Cell A2 I/O* ab.ctl 60 IO.Ctl0 irq3.ctl -- -- 26 IO.Cell A1 I/O* ab.ctl 61 IO.Cell CS2 I/O cs2.ctl 27 I.Pin TGATE2 Input -- 62 IO.Ctl0 cs2.ctl -- -- 28 O.Latch TOUT2 TS-Output tout2.ctl 63 IO.Cell CS1 I/O cs1.ctl 29 IO.Ctl0 tout2.ctl -- -- 64 IO.Ctl0 cs1.ctl -- -- 30 I.Pin TIN2 Input -- 65 IO.Cell CS0 I/O cs0.ctl 31 I.Pin RxDA Input -- 66 IO.Ctl0 cs0.ctl -- -- 32 O.Latch TxDA Output -- 67 IO.Cell D0 I/O db.ctl 33 O.Latch RTSA Output -- 68 IO.Cell D1 I/O db.ctl 34 I.Pin CTSA Input -- 69 IO.Cell D2 I/O db.ctl MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-5 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 9-2. Boundary Scan Bit Definitions (Continued) Bit Num Cell Type Pin/Cell Name Pin Type Output CTL Cell Bit Num Cell Type Pin/Cell Name Pin Type Output CTL Cell 70 IO.Cell D3 I/O db.ctl 101 IO.Ctl0 ab31.ctl -- -- 71 IO.Cell D4 I/O db.ctl 102 IO.Cell A0 I/O* ab.ctl 72 IO.Cell D5 I/O db.ctl 103 IO.Cell DSACK0 I/O** berr.ctl 73 IO.Cell D6 I/O db.ctl 104 IO.Cell DSACK1 I/O** berr.ctl 74 IO.Cell D7 I/O db.ctl 105 IO.Cell RMC I/O* ab.ctl 75 IO.Cell D8 I/O db.ctl 106 IO.Cell R/ W I/O* ab.ctl 76 IO.Cell D9 I/O db.ctl 107 IO.Cell SIZ1 I/O* ab.ctl 77 IO.Cell D10 I/O db.ctl 108 IO.Cell SIZ0 I/O* ab.ctl 78 IO.Cell D11 I/O db.ctl 109 IO.Cell DS I/O* ab.ctl 79 IO.Cell D12 I/O db.ctl 110 IO.Cell AS I/O* ab.ctl 80 IO.Cell D13 I/O db.ctl 111 I.Pin BGACK Input -- 81 IO.Cell D14 I/O db.ctl 112 O.Latch BG Output -- 82 IO.Cell D15 I/O db.ctl 113 I.Pin BR Input -- 83 IO.Ctl1 ab.ctl -- -- 114 IO.Cell BERR I/O** berr.ctl 84 IO.Ctl0 berr.ctl -- -- 115 O.Latch HALT OD-I/O -- 85 IO.Ctl1 db.ctl -- -- 116 I.Pin HALT OD-I/O -- 86 IO.Cell A24 I/O ab24.ctl 117 O.Latch RESET OD-I/O -- 87 IO.Ctl0 ab24.ctl -- -- 118 I.Pin RESET OD-I/O -- 88 IO.Cell A25 I/O ab25.ctl 119 O.Latch CLKOUT Output -- 89 IO.Ctl0 ab25.ctl -- -- 120 I.Pin EXTAL Input -- 90 IO.Cell A26 I/O ab26.ctl 121 IO.Cell MODCK I/O modck.ctl 91 IO.Ctl0 ab26.ctl -- -- 122 IO.Ctl0 modck.ctl -- -- 92 IO.Cell A27 I/O ab27.ctl 123 O.Latch IPIPE Output -- 93 IO.Ctl0 ab27.ctl -- -- 124 IO.Cell IFETCH I/O* ifetch.ctl 94 IO.Cell A28 I/O ab28.ctl 125 IO.Ctl0 ifetch.ctl -- -- 95 IO.Ctl0 ab28.ctl -- -- 126 I.Pin BKPT Input -- 96 IO.Cell A29 I/O ab29.ctl 127 O.Latch FREEZE Output -- 97 IO.Ctl0 ab29.ctl -- -- 128 I.Pin TIN1 Input -- 98 IO.Cell A30 I/O ab30.ctl 129 O.Latch TOUT1 TS-Output tout1.ctl 99 IO.Ctl0 ab30.ctl -- -- 130 IO.Ctl0 tout1.ctl -- -- 100 IO.Cell A31 I/O ab31.ctl 131 I.Pin TGATE1 Input -- NOTES: The noted pins are implemented differently than defined in the signal definition description: * Input during Motorola factory test ** Output during Motorola factory test 9-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 1 - EXTEST 0 - OTHERWISE TO NEXT CELL SHIFT DR G1 DATA FROM SYSTEM LOGIC 1 TO OUTPUT BUFFER MUX 1 G1 1 1D Freescale Semiconductor, Inc... MUX 1 1D C1 C1 FROM LAST CELL CLOCK DR UPDATE DR Figure 9-3. Output Latch Cell (O.Latch) 1 - EXTEST 0 - OTHERWISE TO NEXT CELL G1 INPUT PIN 1 MUX 1 G1 1 1D 1D C1 C1 UPDATE DR MUX 1 CLOCK DR FROM LAST CELL SHIFT DR Figure 9-4. Input Pin Cell (I.Pin) MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-7 Freescale Semiconductor, Inc. 1 - EXTEST 0 - OTHERWISE TO NEXT CELL G1 OUTPUT CONTROL FROM SYSTEM LOGIC 1 TO OUTPUT ENABLE (1 = DRIVE) MUX 1 G1 1 1D MUX 1 1D C1 Freescale Semiconductor, Inc... C1 R SHIFT DR CLOCK DR FROM LAST CELL RESET UPDATE DR Figure 9-5. Active-High Output Control Cell (IO.Ctl1) 1 - EXTEST 0 - OTHERWISE OUTPUT CONTROL FROM SYSTEM LOGIC TO NEXT CELL FIG. 9-4 G1 1 TO OUTPUT ENABLE (1 = DRIVE) MUX 1 G1 1 1D MUX 1 1D C1 C1 R SHIFT DR FROM LAST CELL CLOCK DR RESET UPDATE DR Figure 9-6. Active-Low Output Control Cell (IO.Ctl0) 9-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 1 - EXTEST 0 - OTHERWISE TO NEXT CELL SHIFT DR G1 OUTPUT FROM SYSTEM LOGIC TO OUTPUT DRIVER 1 MUX 1 G1 G1 1 1 MUX 1D MUX 1 1 1D C1 Freescale Semiconductor, Inc... C1 FROM OUTPUT ENABLE FROM PIN FROM LAST CELL CLOCK DR UPDATE DR Figure 9-7. Bidirectional Data Cell (IO.Cell) TO NEXT CELL IO.CTL0 OR IO.CTL1 OUTPUT ENABLE * EN I/O PIN OUTPUT DATA IO.CELL INPUT DATA FROM LAST CELL TO NEXT BIDIRECTIONAL PIN NOTE: More than one lO.Cell could be serially connected and controlled by a single IO.Ctlx cell. Figure 9-8. General Arrangement for Bidirectional Pins 9.4 INSTRUCTION REGISTER The MC68340 IEEE 1149.1 implementation includes the three mandatory public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), but does not support any of the optional public instructions defined by IEEE 1149.1. One additional public instruction (HI-Z) provides the capability for disabling all device output drivers. The MC68340 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-9 Freescale Semiconductor, Inc. includes a 3-bit instruction register without parity, consisting of a shift register with three parallel outputs. Data is transferred from the shift register to the parallel outputs during the update-IR controller state. The three bits are used to decode the four unique instructions listed in Table 9-3. The parallel output of the instruction register is reset to all ones in the test-logic-reset controller state. Note that this preset state is equivalent to the BYPASS instruction. Table 9-3. Instructions Freescale Semiconductor, Inc... Code Instruction B2 B1 B0 0 0 0 EXTEST 0 0 1 SAMPLE/PRELOAD X 1 X BYPASS 1 0 0 HI-Z 1 0 1 BYPASS During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with the standard 2-bit binary value (01) into the two least significant bits and the loss-of-crystal (LOC) status signal into bit 2. The parallel outputs, however, remain unchanged by this action since an update-IR signal is required to modify them. The LOC status bit of the instruction register indicates whether an internal clock is detected when operating with a crystal clock source. The LOC bit is clear when a clock is detected and set when it is not. The LOC bit is always clear when an external clock is used. The LOC bit can be used to detect faulty connectivity when a crystal is used to clock the device. 9.4.1 EXTEST (000) The external test (EXTEST) instruction selects the 132-bit boundary scan register. EXTEST asserts internal reset for the MC68340 system logic to force a predictable benign internal state while performing external boundary scan operations. By using the TAP, the register is capable of a) scanning user-defined values into the output buffers, b) capturing values presented to input pins, c) controlling the direction of bidirectional pins, and d) controlling the output drive of three-state output pins. For more details on the function and uses of EXTEST, please refer to the IEEE 1149.1 document. 9.4.2 SAMPLE/PRELOAD (001) The SAMPLE/PRELOAD instruction selects the 132-bit boundary scan register and provides two separate functions. First, it provides a means to obtain a snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the captureDR controller state. The data can be observed by shifting it transparently through the boundary scan register. 9-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. NOTE Since there is no internal synchronization between the IEEE 1149.1 clock (TCK) and the system clock (CLKOUT), the user must provide some form of external synchronization to achieve meaningful results. The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output bits prior to selection of EXTEST. This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction. Freescale Semiconductor, Inc... 9.4.3 BYPASS (X1X, 101) The BYPASS instruction selects the single-bit bypass register as shown in Figure 9-9. This creates a shift-register path from TDI to the bypass register and, finally, to TDO, circumventing the 132-bit boundary scan register. This instruction is used to enhance test efficiency when a component other than the MC68340 becomes the device under test. SHIFT DR G1 0 1 FROM TDI 1 1D MUX C1 TO TDO CLOCK DR Figure 9-9. Bypass Register When the bypass register is selected by the current instruction, the shift-register stage is set to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the first bit to be shifted out after selecting the bypass register will always be a logic zero. 9.4.4 HI-Z (100) The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a manufacturer's optional public instruction to prevent having to backdrive the output pins during circuit-board testing. When HI-Z is invoked, all output drivers, including the twostate drivers, are turned off (i.e., high impedance). The instruction selects the bypass register. 9.5 MC68340 RESTRICTIONS The control afforded by the output enable signals using the boundary scan register and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. The user must avoid situations in which the MC68340 output drivers are enabled into actively driven networks. Overdriving the TDO driver when it is active is not recommended. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-11 Freescale Semiconductor, Inc. The MC68340 includes on-chip circuitry to detect the initial application of power to the device. Power-on reset (POR), the output of this circuitry, is used to reset both the system and IEEE 1149.1 logic. The purpose for applying POR to the IEEE 1149.1 circuitry is to avoid the possibility of bus contention during power-on. The time required to complete device power-on is power-supply dependent. However, the IEEE 1149.1 TAP controller remains in the test-logic-reset state while POR is asserted. The TAP controller does not respond to user commands until POR is negated. Freescale Semiconductor, Inc... The MC68340 features a low-power stop mode that uses a CPU instruction called LPSTOP. The interaction of the IEEE 1149.1 interface with LPSTOP mode is as follows: 1. Leaving the TAP controller test-logic-reset state negates the ability to achieve minimal power consumption, but does not otherwise affect device functionality. 2. The TCK input is not blocked in LPSTOP mode. To consume minimal power, the TCK input should be externally connected to V CC or ground. 3. The TMS and TDI pins include on-chip pullup resistors. In LPSTOP mode, these two pins should remain either unconnected or connected to VCC to achieve minimal power consumption. 9.6 NON-IEEE 1149.1 OPERATION In non-IEEE 1149.1 operation, there are two constraints. First, the TCK input does not include an internal pullup resistor and should be pulled up externally to preclude mid-level inputs. The second constraint is to ensure that the IEEE 1149.1 test logic is kept transparent to the system logic by forcing the TAP controller into the test-logic-reset state, using either of two methods. During power-on, POR forces the TAP controller into this state. Alternatively, sampling TMS as a logic one for five consecutive TCK rising edges also forces the TAP controller into this state. If TMS either remains unconnected or is connected to VCC , then the TAP controller cannot leave the test-logic-reset state, regardless of the state of TCK. 9-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 10 APPLICATIONS Freescale Semiconductor, Inc... This section provides guidelines for using the MC68340. Minimum system-configuration requirements and memory interface information are discussed. 10.1 MINIMUM SYSTEM CONFIGURATION One of the powerful features of the MC68340 is the small number of external components needed to create an entire system. The information contained in the following paragraphs details a simple high-performance MC68340 system (see Figure 10-1). This system configuration features the following hardware: * Processor Clock Circuitry * Reset Circuitry * SRAM Interface * ROM Interface * Serial Interface CLOCK CIRCUITRY SRAM MC68340 SERIAL INTERFACE ROM Figure 10-1. Minimum System Configuration Block Diagram 10.1.1 Processor Clock Circuitry The MC68340 has an on-chip clock synthesizer that can operate from an on-chip phaselocked loop (PLL) and a voltage-controlled oscillator (VCO). The clock synthesizer uses an external crystal connected between the EXTAL and XTAL pins as a reference frequency source. Figure 10-2 shows a typical circuit using an inexpensive 32.768-kHz watch crystal. The 20-M resistor connected between the EXTAL and XTAL pins provides biasing for a faster oscillator startup time. The crystal manufacturer's documentation should be consulted for specific recommendations on external component values. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-1 Freescale Semiconductor, Inc. 330 k 4.7 pF XTAL MC68340 20 M 32.768 kHz EXTAL 10 pF Freescale Semiconductor, Inc... Figure 10-2. Sample Crystal Circuit The circuit shown in Figure 10-3 is the typical circuit recommended by Statek Corporation, for 32768 kHz crystal, part number CX-IV. It is recommended to start with these values, but parameter values may need to be adjusted to compensate for variables in layout. 470 k 10 pF XTAL MC68340 22 M 32.768 kHz EXTAL 20 pF Figure 10-3. Statek Corporation Crystal Circuit A separate power pin (V CCSYN ) is used to allow the clock circuits to operate with the rest of the device powered down and to provide increased noise immunity for the clock circuits. The source for V CCSYN should be a quiet power supply, and external bypass capacitors (see Figure 10-4) should be placed as close as possible to the V CCSYN pin to ensure a stable operating frequency. Additionally, the PLL requires that an external low-leakage filter capacitor, typically in the range of 0.01 to 0.1 F, be connected between the XFC and VCCSYN pins. The XFC capacitor should provide 50-M insulation but should not be electrolytic. For external clock mode without PLL, the XFC pin can be left open. Smaller values of the external filter capacitor provide a faster response time for the PLL, and larger values provide greater frequency stability. Figure 10-4 depicts examples of both an external filter capacitor and bypass capacitors for V CCSYN . 10-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. VCCSYN VCCSYN 0.1 F 1 MC68340 0.1 F 0.01 F XFC NOTE 1: Must be a low-leakage capacitor. Freescale Semiconductor, Inc... Figure 10-4. XFC and V CCSYN Capacitor Connections 10.1.2 Reset Circuitry Because it is optional, reset circuitry is not shown in Figure 10-1. The MC68340 holds itself in reset after power-up and asserts RESET to the rest of the system. If an external reset pushbutton switch is desired, an external reset circuit is easily constructed by using open-collector cross-coupled NAND gates to debounce the output from the switch. 10.1.3 SRAM Interface The SRAM interface is very simple when the programmable chip selects are used. External circuitry to decode address information and circuitry to return data and size acknowledge (DSACK) is not required. However, external ICs are required to provide write enables for the high and low bytes of data. A15-A1 SIZ0 A0 AS UWE . ... MCM6206-35 MC68340 LWE ... . ... MCM6206-35 R/W R/W CE CE E .. R/W D15-D0 . D7-D0 CS .. E ... .. . .. D15-D8 Figure 10-5. SRAM Interface The SRAM interface shown in Figure 10-5 is a two-clock interface at 16.78-MHz operating frequency. The MCM6206C-35 memories provide an access time of 15 ns when the chip enable (E) input is low. If buffers are required to reduce signal loading or if slower and less expensive memories are desired, a three-clock cycle can be used. In the circuit shown in Figure 10-5, additional memories can be used provided the MC68340 specification for MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-3 Freescale Semiconductor, Inc. load capacitance on the chip-select (CS) signal is not exceeded. (Address buffers may be needed, however.) 10.1.4 ROM Interface Using the programmable chip selects creates a very straightforward ROM interface. As shown in Figure 10-6, no external circuitry is needed. Care must be used, however, not to overload the address bus. Address buffers may be required to ensure that the total system input capacitance on the address signals does not exceed the CL specification. MC68340 Freescale Semiconductor, Inc... A16-A1 16-BIT ROM D15-D0 CS0 CE CE Figure 10-6. ROM Interface 10.1.5 Serial Interface The necessary circuitry to create an RS-232 interface with the MC68340 includes an external crystal and an RS-232 receiver/driver (see Figure 10-7). The resistor and capacitor values shown are typical; the crystal manufacturer's documentation should be consulted for specific recommendations on external component values. The circuit shown does not include modem support (ready-to-send (RTS) and clear-to-send (CTS) are not shown); however, these signals can be connected to the receiver/driver and to the connector in a similar manner as the connections for TxDx and RxDx. 10-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 15 pF X1 3.6864 MHz X2 RxDx R TxDx RS 232 CONNECTOR 5 pF MC68340 Rx1 Tx1 T MC145407 VCC Freescale Semiconductor, Inc... 10 F 10 F C1+ C2+ C1- C1- VSS C2+ GND C2- 10 F 10 F Figure 10-7. Serial Interface 10.2 MEMORY INTERFACE INFORMATION The following paragraphs contain information on using an 8-bit boot ROM, performing access time calculations, calculating frequency-adjusted outputs, and interfacing an 8-bit device to 16-bit memory using the DMA channel single-address mode. 10.2.1 Using an 8-Bit Boot ROM Upon power-up, the MC68340 uses CS0 to begin operation. CS0 is a three-wait-state, 16bit chip select, until otherwise programmed. If an 8-bit ROM is desired, external circuitry can be added to return an 8-bit DSACK in two wait states (see Figure 10-8). '393 CLKOUT CS0 CP MR Q0 Q1 Q2 Q3 DSACK0 Figure 10-8. External Circuitry for 8-Bit Boot ROM The 393 is a falling edge-triggered counter; thus, CS0 is stable during the time in which it is being clocked. CS0 acts as the asynchronous reset--i.e., when it is asserted, the 393 is allowed to count. The falling edge of S2 provides the first counting edge. Q1 does not transition on this falling edge, but transitions to a logic one on the subsequent edge. DSACK0 is Q1 inverted; thus, on the next falling edge, DSACK0 is seen as asserted, indicating an 8-bit port. When CS0 is negated, Q1 is again held in reset and DSACK0 is negated. The timing diagram in Figure 10-9 illustrates this operation. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-5 Freescale Semiconductor, Inc. S0 S1 S2 SW SW SW SW S3 S4 S5 S0 S1 S2 CLKOUT CS0 Q1 DSACK0 Freescale Semiconductor, Inc... Figure 10-9. 8-bit Boot ROM Timing 10.2.2 Access Time Calculations The two time paths that are critical in an MC68340 application using the CS signals are shown in Figure 10-10. The first path is the time from address valid to when data must be available to the processor; the second path is the time from CS asserted to when data must be available to the processor. S0 S1 S4 S5 S0 CLKOUT t6 A31-A0 t9 CS t CSDV t 27 D15-D0 t ADV Figure 10-10. Access Time Computation Diagram As shown in the diagram, an equation for the address access time, t ADV , can be developed as follows: tADV = t cyc(N c - 0.5) - t s9 - t s27 where: tcyc = system CLKOUT period Nc = number of clocks per bus cycle ts6 = CLKOUT high to address valid = 30 ns maximum at 16.78 MHz ts27 = data-in valid to CLKOUT low setup = 5 ns minimum at 16.78 MHz 10-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. An equation for the chip select access time, tCSDV, can be developed as follows: tCSDV = t cyc(N c - 1) - t s9 - ts27 where: tcyc = system clock period Nc = number of clocks per access ts9 = CLKOUT low to CS asserted = 30 ns maximum at 16.78 MHz ts27 = data-in valid to CLKOUT low setup = 5 ns minimum at 16.78 MHz Freescale Semiconductor, Inc... Using these equations, the memory access times at 16.78 MHz are shown in Table 10-1. See Section 11 Electrical Characteristics for more timing information. Table 10-1. Memory Access Times at 16.78 MHz Access Time N=2 N=3 N=4 N=5 N=6 t ADV 54 ns 114 ns 173 ns 233 ns 292 ns t CSDV 24 ns 84 ns 143 ns 203 ns 263 ns The values can be used to determine how many clock cycles an access will take, given the access time of the memory devices and any delays through buffers or external logic that may be needed. 10.2.3 Calculating Frequency-Adjusted Output The general relationship between the CLKOUT and most input and output signals is shown in Figure 10-11. Most outputs transition off of a falling edge of CLKOUT, but the same principle applies to those outputs that transition off of a rising edge. CLKOUT td OUTPUTS t su th ASYNCHRONOUS INPUTS Figure 10-11. Signal Relationships to CLKOUT For outputs that are referenced to a clock edge, the propagation delay (td ) does not change as the frequency changes. For instance, specification 6 in the electrical characteristics, shown in Section 11 Electrical Characteristics, shows that address, function code, and size information is valid 3 to 30 ns after the rising edge of S0. This specification does not change even if the device frequency is less than 16.78 MHz. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-7 Freescale Semiconductor, Inc. Additionally, the relationship between the asynchronous inputs and the clock edge, as shown in Figure 10-11, does not change as frequency changes. A second type of specification indicates the minimum amount of time a signal will be asserted. This type of specification is illustrated in Figure 10-12. T/2 N CLKOUT td OUTPUT Freescale Semiconductor, Inc... tw Figure 10-12. Signal Width Specifications The method for calculating a frequency-adjusted tw is as follows: tw' = tw + N (T f'/2 - T f/2) + (T f'/2 - t d) where: tw' = the frequency-adjusted signal width tw = the signal width at 16.78 MHz N = the number of full one-half clock periods in tw Tf'/2 = one-half the new clock period Tf/2 = one-half the clock period at full speed td = the propagation time from the clock edge The following calculation uses a 16.78-MHz part, specification 14, AS width asserted, at 12.5 MHz as an example: tw = 100 ns N=3 Tf'/2 = 80/2 = 40 ns Tf/2 = 60/2 = 30 ns td = 30 ns maximum therefore: tw' = 100 + 3(40 - 30) + (40 - 30) = 140 ns The third type of specification used is a skew between two outputs (see Figure 10-13). 10-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. T/2 CLKOUT td1 OUTPUT1 t d2 OUTPUT2 ts Figure 10-13. Skew between Two Outputs Freescale Semiconductor, Inc... The method for calculating a frequency-adjusted ts is as follows: ts' = ts + N (T f'/2 - T f/2) + (T f'/2 - td1) where: ts' = the frequency-adjusted skew ts = the skew at full speed N = the number of full one-half clock periods in ts, if any Tf'/2 = one-half the new clock period Tf/2 = one-half the clock period at full speed td1 = the propagation time for the first output from the clock edge The following calculation uses a 16.78-MHz port, specification 21, R/ W high to A S asserted, at 8 MHz as an example: ts = 15 ns minimum N=0 Tf'/2 = 125/2 = 62.5 ns Tf/2 = 60/2 = 30 ns td1 = 30 ns maximum therefore: ts' = 15 + 0(62.5 - 30) + (62.5 - 30) = 47.5 ns minimum In this manner, new specifications for lower frequencies can be derived for an MC68340. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-9 Freescale Semiconductor, Inc. 10.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using SingleAddress DMA Mode One of the requirements of single-address mode is that the source and destination must be the same port size. However, the MC68340 can perform direct memory accesses in single-address mode between an 8-bit device and 16-bit memory. The port size must be specified as 8 bits, and some external logic is required as shown in Figure 10-14. Freescale Semiconductor, Inc... DEVICE MC68340 D15-D8 R/W A0 SIZ1 SIZ0 T/R B MEMORY 74F245 OE A D7-D0 Figure 10-14. Circuitry for Interfacing 8-Bit Device to 16-Bit Memory in Single-Address DMA Mode During even-byte accesses, the data is transferred directly on D15-D8. However, during odd-byte accesses, the data must be routed on D15-D8 for the 8-bit device and on D7- D0 for the 16-bit memory. 10.3 POWER CONSUMPTION CONSIDERATIONS The MC68340 can be designed into low-power applications that involve high-performance processing capability (32-bits), high functional density, small size, portable capability, and battery operation. The MC68340 fits into the following types of applications: * "Palmtop" Computers * Telephony -- Stylus Input -- Cordless Phones -- Voice Input -- Cellular Phones -- Image Input * CD-I, CD-ROM * Transaction Tracking * Defense Industry -- Car Rental -- Guidance Systems -- Cargo -- Tracking Systems -- Courier * Data Entry -- Handheld * Instruments * Bar Code Scanners * Handheld Games 10-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 10.3.1 MC68340 Power Reduction at 5V The following figures show how different variables affect typical power consumption at 5 V. Figure 10-15 shows how system activity affects current drain. Figure 10-16 shows how voltage affects current drain at some typical operating temperatures. Figure 10-17 shows how system clock frequency affects current drain. 120 Typical values 32KHz xtal 16.78 MHz 24 C 93 81 I cc (mA) Freescale Semiconductor, Inc... 90 73 66 60 62 42 30 .06 0 INITIALIZATION MAX CURRENT SERIAL OFF +TIMER 1 OFF +TIMER 2 OFF +DMA OFF +LPSTOP Figure 10-15. MC68340 Current vs. Activity at 5 V MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-11 Freescale Semiconductor, Inc. 120 0 C 24 C 100 100 C Icc (mA) Typical values 32KHz xtal 16.78 MHz peak current Freescale Semiconductor, Inc... 80 60 4 5.5 5 VCC (V) Figure 10-16. MC68340 Current vs. Voltage/Temperature 120 Icc (mA) 90 Typical values 32KHz xtal peak current 24 C 60 30 0 0 2 4 6 8 10 12 14 16 Clock Frequency (MHz) Figure 10-17. MC68340 Current vs. Clock Frequency at 5 V 10-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 10.3.2 MC68340V (3.3 V) The MC68340V can operate with a 3.3-V power supply for significant power savings. The formula for power dissipation is Pd V2 x f + dc Table 10-2 shows typical electrical characteristics for both the MC68340 and MC68340V. Table 10-2. Typical Electrical Characteristics Parameter MC68340 (5.0 V) MC68340V (3.3 V) 0-16.78 MHz 0-25 MHz 0-8.39 MHz 0-16.78 MHz Typical Current (16 MHz) 95 mA TBD Typical Current (8 MHz) 55 mA 30 mA Standby Current 60 A 25 A Freescale Semiconductor, Inc... Clock Frequency Running at 3.3 V saves 66% of the power consumption. The 3.3 V operation provides the following user advantages: Advantage Benefit Lower Supply Voltage Fewer Batteries Fewer Batteries Less Weight Smaller Size Lower Current Drain Extended Battery Life Less Heat Generated No Fan No Fan Noise Less EMF Radiation Easier FCC Certification Less Crosstalk Closer PCB Traces High Functional Integration All-In-One 3.3 V Part: Processor Peripherals Glue Logic These advantages result in a much more portable system. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-13 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 11 ELECTRICAL CHARACTERISTICS This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MC68340. Refer to Section 12 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage, frequency, and temperature ratings. 11.1 MAXIMUM RATINGS Rating Supply Voltage 1, 2 Input Voltage1, 2 Operating Temperature Range Symbol Value Unit VCC Vin -0.3 to +6.5 V -0.3 to +6.5 V TA 0 to 70 or -40 to +85 C Storage Temperature Range Tstg -55 to +150 C NOTES: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. This device contains protective circuitry against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V CC ). The following ratings define a range of conditions in which the device will operate without being damaged. However, sections of the device may not operate normally while being exposed to the electrical extremes. 11.2 THERMAL CHARACTERISTICS Characteristic Symbol Thermal Resistance--Junction to Case JC Ceramic 144-Pin QFP Thermal Resistance--Junction to Ambient Plastic 145-Pin PGA * Estimated MOTOROLA Unit C/W 6 TBD Plastic 145-Pin PGA Ceramic 144-Pin QFP Value JA C/W 33 27* MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-1 Freescale Semiconductor, Inc. 11.3 POWER CONSIDERATIONS The average chip-junction temperature, TJ, in C can be obtained from: Freescale Semiconductor, Inc... TJ = T A + (PD * JA) (1) where: TA = Ambient Temperature, C JA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PINT + PI/O PINT = ICC x VCC, Watts--Chip Internal Power PI/O = Power Dissipation on Input and Output Pins--User Determined For most applications, P I/O < PINT and can be neglected. An approximate relationship between P D and T J (if P I/O is neglected) is: PD = K / (TJ + 273C) Solving Equations (1) and (2) for K gives: K = P D * (TA + 273C) + JA * P D2 where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P D (at thermal equilibrium) for a known TA. Using this value of K, the values of PD and T J can be obtained by solving Equations (1) and (2) iteratively for any value of T A. 11.4 AC ELECTRICAL SPECIFICATION DEFINITIONS The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. The measurement of the AC specifications is defined by the waveforms shown in Figure 11-1. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown. Inputs are specified with minimum setup and hold times and are measured as shown. Finally, the measurement for signal-to-signal specifications are shown. Note that the testing levels used to verify conformance to the AC specifications do not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics. 11-2 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The MC68340V low voltage parts can operate up to 8.39 MHz or 16.78 MHz with a 3.3 V 0.3 V supply. Separate part numbers are used to distinguish the operation of the parts according to the supply voltage. Refer to Section 12 Ordering Information and Mechanical Data for the part numbering schemes. MC68340 is used throughout this section to refer to the 16.78- or 25.16-MHz parts at 5.0 V 5%. MC68340V is used throughout this section to refer to the 8.39- or 16.78-MHz parts at 3.3 V 0.3 V. NOTE Freescale Semiconductor, Inc... The electrical specifications in this section for the MC68340 25.16 MHz at 5.0 V 5% and the 3.3 V 0.3 V specifications for both the 8.39- and 16.78-MHz parts are preliminary. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-3 Freescale Semiconductor, Inc. 2.0 V 2.0 V CLKOUT 0.8 V 0.8 V A B OUTPUTS(1) VALID OUTPUT n 2.0 V 2.0 V 0.8 V 0.8 V VALID OUTPUT A n+1 B VALID OUTPUT n Freescale Semiconductor, Inc... OUTPUTS(2) C 2.0 V INPUTS(3) 0.8 V 2.0 V 2.0 V 0.8 V 0.8 V VALID OUTPUT n+1 D 2.0 V VALID INPUT 0.8 V C 2.0 V INPUTS(4) 0.8 V D VALID INPUT 2.0 V 0.8 V DRIVE TO 2.4 V DRIVE TO 0.5 V 2.0 V ALL SIGNALS(5) 0.8 V E F 2.0 V 0.8 V NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This output timing is applicable to all parameters specified relative to the falling edge of the clock. 3. This input timing is applicable to all parameters specified relative to the rising edge of the clock. 4. This input timing is applicable to all parameters specified relative to the falling edge of the clock. 5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal. LEGEND: A. Maximum output delay specification. B. Minimum output hold time. C. Minimum input setup time specification. D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum). Figure 11-1. Drive Levels and Test Points for AC Specifications 11-4 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 11.5 DC ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70C; see numbered notes) Characteristic Symbol Min Max Unit VIH VIL 2.0 VCC 0.8 V GND V Input High Voltage (except clock) Input Low Voltage Clock Input High Voltage Undershoot VIHC -- 0.7 * (V CC ) -- VCC +0.3 -0.8 I in I OZ -2.5 2.5 A -20 20 A IL -0.015 0.2 mA IH -0.015 0.2 mA VOH 2.4 -- V VOL -- Freescale Semiconductor, Inc... Input Leakage Current (All Input Only Pins) Vin = VCC or GND Hi-Z (Off-State) Leakage Current (All Noncrystal Outputs and I/O Pins) Vin = 0.5/2.4 V1 Signal Low Input Current VIL = 0.8 V Signal High Input Current VIH = 2.0 V V TMS, TDI TMS, TDI Output High Voltage1, 2 I OH = -0.8 mA, V CC = 4.75 V All Noncrystal Outputs except HALT, RESET, DONE2, DONE1 Output Low Voltage1 I OL = 2.0 mA I OL = 3.2 mA I OL = 5.3 mA I OL = 15.3 mA V CLKOUT, FREEZE, IPIPE, IFETCH A23-A0, D15-D0, FC3-FC0, SIZ1, SIZ0 All Other Output Only and Group 2 I/O Pins HALT, RESET Total Supply Current at 5 V +5% @ 16.78 MHz RUN3 LPSTOP (VCO Off) Power Dissipation at 5 V +5% @ 16.78 MHz4 Total Supply Current at 3.3 V + 0.3 V @ 8.39 MHz RUN5 LPSTOP (VCO Off) Power Dissipation at 3.3 V +0.3 V @ 8.39 MHz 6 V 0.5 0.5 0.5 0.5 -- I CC SICC PD -- 180 500 mA A 945 mW TBD TBD mA A TBD mW -- I CC SICC PD -- Cin -- Input Capacitance 7 All Input-Only Pins All I/O Pins pF 10 20 Load Capacitance 7 CL -- 100 pF NOTES: (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary. (d) For extended temperature parts TA = -40 to +85C. These specifications are preliminary. 1. Input-Only Pins: BERR, BG, BKPT, BR, CTSB, CTSA, DREQ2, DREQ1, DSACK1, DSACK0, EXTAL, RxDB, RxDA, SCLK, TCK, TDI, TGATE2, TGATE1, TIN2, TIN1, TMS Output-Only Pins: A23-A0, AS, BG, CLKOUT, DACK2, DACK1, DS, FC3-FC0, FREEZE, IFETCH, IPIPE, RMC, RTSB, RTSA, R/ W, RRDYA, SIZ1, SIZ0, TDO, TOUT2, TOUT1, TxDB, TxDA, TRDYA Input/Output Pins: Group 1: D15-D0 Group 2: A31-A24, CS3-CS0, DONE2, DONE1, IRQ7, IRQ5, IRQ3, MODCK Group 3: HALT, RESET 2. VOH specification for HALT, RESET, DONE2, and DONE1 is not applicable because they are open-drain pins. 3. Supply current measured with system clock frequency of 16.78 MHz @ 5.25 V. 4. Power dissipation measured with a system clock frequency of 16.78 MHz, all modules active. 5. Supply current measured with system clock frequency of 8.39 MHz @ 3.6 V. 6. Power dissipation measured with a system clock frequency of 8.39 MHz, all modules active. 7. Capacitance is periodically sampled rather than 100% tested. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-5 Freescale Semiconductor, Inc. 11.6 AC ELECTRICAL SPECIFICATIONS CONTROL TIMING (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70C; see numbered notes) 3.3 V 3.3 V or 5.0 V 8.39 MHz Num. Characteristic System Frequency1 Min Max Min Max Min Max Unit f sys dc 8.39 dc 16.78 dc 25.16 MHz f XTAL 25 50 25 50 25 50 kHz On-Chip VCO System Frequency f sys 0.13 8.39 0.13 16.78 0.13 25.16 MHz On-Chip VCO Frequency Range f VCO 0.1 16.78 0.1 33.5 0.1 50.3 MHz f sys 0 8 0 16 0 25 MHz t rc -- 20 -- 20 -- 20 ms -- -- -- -- -- -- -1 f sys /2 f sys +1 -1 f sys /2 f sys +1 % External Clock Operation Freescale Semiconductor, Inc... 25.16 MHz Symbol Crystal Frequency PLL Start-up Time2 Limp Mode Clock Frequency 3 f limp SYNCR X-bit = 0 SYNCR X-bit = 1 CLKOUT stability 4 15 16.78 MHz 5.0 V CLKOUT Period in Crystal Mode kHz CLK -1 f sys /2 f sys +1 t cyc 119.2 -- 59.6 -- 40 -- ns 1B6 External Clock Input Period t EXTcyc 125 -- 62.5 -- 40 -- ns 1C 7 External Clock Input Period with PLL t EXTcyc 125 -- 62.5 -- 40 -- ns 2,3 8 CLKOUT Pulse Width in Crystal Mode t CW 56 -- 28 -- 19 -- ns 2B, 3B9 CLKOUT Pulse Width in External Mode t EXTCW 56 -- 28 -- 18 -- ns CLKOUT Pulse Width in External w/PLL Mode t EXTCW 62.5 -- 31 -- 20 -- ns t Crf -- 10 -- 5 -- 4 ns 2C, 3C 10 4,5 CLKOUT Rise and Fall Times NOTES: (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary. (d) For extended temperature parts T A = -40 to +85C. These specifications are preliminary. 1. All internal registers retain data at 0 Hz. 2. Assumes that a stable VCCSYN is applied, that an external filter capacitor with a value of 0.1 F is attached to the XFC pin, and that the crystal oscillator is stable. Lock time is measured from power-up to RESET release. This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP. 3. Determined by the initial control voltage applied to the on-chip VCO. The X-bit in the SYNCR controls a divideby-two scaler on the system clock output. 4. CLKOUT stability is the average deviation from programmed frequency measured at maximum f sys . Measurement is made with a stable external clock input applied using the PLL. 5. All crystal mode clock specifications are based on using a 32.768-kHz crystal for the input. 6. When using the external clock input mode (MODCK reset value = 0 V), the minimum allowable t EXTcyc period will be reduced when the duty cycle of the signal applied to EXTAL exceeds 5% tolerance. The relationship between external clock input duty cycle and minimum t EXTcyc is expressed: Minimum tEXTcyc period = minimum tEXTCW / (50% - external clock input duty cycle tolerance). Minimum external clock low and high times are based on a 45% duty cycle. 7. When using the external clock input mode with the PLL (MODCK reset value = 0 V), the external clock input duty cycle can be at minimum 20% to produce a CLKOUT with a 50% duty cycle. 8. For crystal mode operation, the minimum CLKOUT pulse width is based on a 47% duty cycle. 9. For external clock mode operation, the minimum CLKOUT pulse width is based on a 45% duty cycle, with a 50% duty cycle input clock. 11-6 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 10. For external clock w/PLL mode operation, the minimum CLKOUT pulse width is based on a 50% duty cycle. 11. For external clock mode, there is a 10-40 ns skew between the input clock signal and the output CLKOUT signal from the MC68340. Clock skew is measured from the rising edges of the clock signals. 12. For external clock mode w/PLL, there is a 5 ns skew between the input clock signal and the output CLKOUT signal from the MC68340. Clock skew is measured from the rising edges of the clock signals. MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-7 Freescale Semiconductor, Inc. 11.7 AC TIMING SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70C; see numbered notes; see Figures 11-2-11-11) Freescale Semiconductor, Inc... Num. 3.3 V 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Min Min Characteristic Symbol Min 6 CLKOUT High to Address, FC, SIZ, RMC Valid 60 0 30 0 20 ns CLKOUT High to Address, Data, FC, SIZ, RMC High Impedance t CHAV t CHAZx 0 7 0 120 0 60 0 40 ns 8 CLKOUT High to Address, FC, SIZ, RMC Invalid t CHAZn 0 -- 0 -- 0 -- ns 99 CLKOUT Low to AS, DS, CS, IFETCH, IPIPE, IACK Asserted t CLSA 3 60 3 30 3 20 ns AS to DS or CS Asserted (Read) t STSA -30 30 -15 15 -6 6 ns 11 Address, FC, SIZ, RMC Valid to AS, CS (and DS Read) Asserted t AVSA 30 -- 15 -- 10 -- ns 12 CLKOUT Low to AS, DS, CS, IFETCH, IPIPE, IACK Negated t CLSN 3 60 3 30 3 20 ns 13 AS, DS, CS, IACK Negated to Address, FC, SIZ Invalid (Address Hold) t SNAI 30 -- 15 -- 10 -- ns 14 AS, CS (and DS Read) Width Asserted t SWA t SWAW 200 -- 100 -- 70 -- ns 90 -- 45 -- 30 -- ns t SWDW 80 -- 40 -- 30 -- ns t SN 80 -- 40 -- 30 -- ns 9A2 14A DS Width Asserted (Write) 14B AS, CS, IACK (and DS Read) Width Asserted (Fast Termination Cycle) 153 AS, DS, CS Width Negated Max Max Max Unit 16 CLKOUT High to AS, DS, R/ W High Impedance t CHSZ -- 120 -- 60 -- 40 ns 17 AS, DS, CS Negated to R/W High t SNRN 30 -- 15 -- 10 -- ns 18 CLKOUT High to R/W High 60 0 30 0 20 ns CLKOUT High to R/W Low t CHRH t CHRL 0 20 219 0 60 0 30 0 20 ns R/ W High to AS, CS Asserted t RAAA 30 -- 15 -- 10 -- ns R/ W Low to DS Asserted (Write) t RASA 140 -- 70 -- 47 -- ns 23 CLKOUT High to Data-Out Valid 60 -- 30 -- 20 ns Data-Out Valid to Negating Edge of AS, CS, (Fast Termination Write) t CHDO t DVASN -- 24 30 -- 15 -- 10 -- ns 25 DS, CS, Negated to Data-Out Invalid (Data-Out Hold) t SNDOI 30 -- 15 -- 10 -- ns 26 Data-Out Valid to DS Asserted (Write) t DVSA 30 -- 15 -- 10 -- ns 27 Data-In Valid to CLKOUT Low (Data Setup) t DICL t BELCL 10 -- 5 -- 5 -- ns 40 -- 20 -- 10 -- ns 22 27A Late BERR, HALT, BKPT Asserted to CLKOUT Low (Setup Time) 28 AS, DS Negated to DSACK, BERR, HALT Negated t SNDN 0 160 0 80 0 50 ns 294 DS, CS Negated to Data-In Invalid (Data-In Hold) t SNDI 0 -- 0 -- 0 -- ns 29A4 DS, CS Negated to Data-In High Impedance t SHDI -- 120 -- 60 -- 40 ns 11-8 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 11.7 AC TIMING SPECIFICATIONS (Continued) 3.3 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Symbol Min Max Min Max Min Max Unit CLKOUT Low to Data-In Invalid (Fast Termination Hold) t CLDI 30 -- 15 -- 10 -- ns CLKOUT Low to Data-In High Impendance t CLDH -- 180 -- 90 -- 60 ns DSACK Asserted to Data-In Valid t DADI -- 100 -- 50 -- 32 ns DSACK Asserted to DSACK Valid (Skew) t DADV -- 60 -- 30 -- 20 ns 32 HALT and RESET Input Transition Time 400 -- 200 -- 140 ns CLKOUT Low to BG Asserted t HRrf t CLBA -- 33 -- 60 -- 30 -- 20 ns 34 356 CLKOUT Low to BG Negated t CLBN -- 60 -- 30 -- 20 ns BR Asserted to BG Asserted (RMC Not Asserted) t BRAGA 1 -- 1 -- 1 -- CLKOUT 37 BGACK Asserted to BG Negated t GAGN 1 2.5 1 2.5 1 2.5 CLKOUT 39 BG Width Negated t GH 2 -- 2 -- 2 -- CLKOUT 39A BG Width Asserted t GA t RWA 1 -- 1 -- 1 -- CLKOUT 300 -- 150 -- 100 -- ns t RWAS 180 -- 90 -- 60 -- ns Num. 304 30A4 315 31A Freescale Semiconductor, Inc... 3.3 V or 5.0 V 46 46A Characteristic R/ W Width Asserted (Write or Read) R/ W Width Asserted (Fast Termination Write or Read) 47A8 Asynchronous Input Setup Time t AIST 15 -- 8, 5 -- 5 -- ns 47B 485,7 Asynchronous Input Hold Time t AIHT 30 -- 15 -- 10 -- ns DSACK Asserted to BERR, HALT Asserted t DABA -- 60 -- 30 -- 20 ns 53 Data-Out Hold from CLKOUT High t DOCH 0 -- 0 -- 0 -- ns 54 CLKOUT High to Data-Out High Impedance t CHDH -- 60 -- 30 -- 20 ns 55 R/ W Asserted to Data Bus Impedance Change t RADC 80 -- 40 -- 25 -- ns 56 RESET Pulse Width (Reset Instruction) t HRPW 512 -- 512 -- 512 -- CLKOUT 56A RESET Pulse Width (Input from External Device) t RPWI 590 -- 590 -- 590 -- CLKOUT 57 BERR Negated to HALT Negated (Rerun) t BNHN 0 -- 0 -- 0 -- ns 70 CLKOUT Low to Data Bus Driven (Show Cycle) 60 0 30 0 20 ns Data Setup Time to CLKOUT Low (Show Cycle) t SCLDD t SCLDS 0 71 30 -- 15 -- 10 -- ns 72 Data Hold from CLKOUT Low (Show Cycle) t SCLDH 20 -- 10 -- 6 -- ns 80 DSI Input Setup Time t DSISU 30 -- 15 -- 10 -- ns 81 DSI Input Hold Time t DSIH 20 -- 10 -- 6 -- ns 82 DSCLK Setup Time t DSCSU 30 -- 15 -- 10 -- ns 83 DSCLK Hold Time t DSCH 20 -- 10 -- 6 -- ns 84 DSO Delay Time t DSOD -- t cyc + 50 -- t cyc + 25 -- t cyc + 16 ns MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-9 Freescale Semiconductor, Inc. 11.7 AC TIMING SPECIFICATIONS (Continued) 3.3 V Freescale Semiconductor, Inc... Num. Characteristic 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Symbol Min Max Min Max Min Max Unit t DSCCYC 2 -- 2 -- 2 -- CLKOUT 0 100 0 50 0 35 ns 85 DSCLK Cycle 86 CLKOUT High to FREEZE Asserted t FRZA 87 CLKOUT High to FREEZE Negated t FRZN 0 100 0 50 0 35 ns 88 CLKOUT High to IFETCH High Impedance t IFZ 0 100 0 50 0 35 ns 89 CLKOUT High to IFETCH Valid t IF 0 100 0 50 0 35 ns NOTES: (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary. (d) For extended temperature parts T A = -40 to +85C. These specifications are preliminary. 1. All AC timing is shown with respect to 0.8 V and 2.0 V levels unless otherwise noted. 2. This number can be reduced to 5 ns if strobes have equal loads. 3. If multiple chip selects are used, the CS width negated (#15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. 4. These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast termination reads. The user is free to use either hold time for fast termination reads. 5. If the asynchronous setup time (#47) requirements are satisfied, the DSACK low to data setup time (#31) and DSACK low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKOUT low setup time (#27) for the following clock cycle: BERR must only satisfy the late BERR low to CLKOUT low setup time (#27A) for the following clock cycle. 6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the current operand transfer are complete and RMC is negated. 7. In the absence of DSACK, BERR is an asynchronous input using the asynchronous setup time (#47). 8. Specification #47A for 16.78 MHz @ 3.3 V 0.3V will be 8 ns. 9. During interrupt acknowledge cycles up to two wait states may be inserted by the processor between states S0 and S1. 11-10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 CLKOUT 6 8 SIZ1-SIZ0 FC3-FC0 A31-A0 RMC Freescale Semiconductor, Inc... 11 14 AS 12 9 13 DS 9A CS 18 21 20 R/W 46 28 47A DSACK0 DSACK1 29 31 D15-D0 29A 27 BERR 48 27A HALT 9 12 12 IFETCH 47A 47B ASYNCHRONOUS INPUTS 27A BKPT NOTE: All timing is shown with respect to 0.8V and 2.0V levels. Figure 11-2. Read Cycle Timing Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-11 Freescale Semiconductor, Inc. S1 S0 S3 S2 S4 S5 CLKOUT 6 8 A31-A0 FC3-FC0 SIZ1-SIZ0 11 15 14 Freescale Semiconductor, Inc... AS 9 12 9 13 DS CS 20 14A 22 17 R/W 46 DSACK0 28 47A DSACK1 25 55 53 D15-D0 23 54 26 BERR 48 27A HALT BKPT NOTE: All timing is shown with respect to 0.8-V and 2.0-V levels. Figure 11-3. Write Cycle Timing Diagram 11-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S1 S4 S5 S0 CLKOUT 8 6 Freescale Semiconductor, Inc... A31-A0 FC3-FC0 SIZ1-SIZ0 9 14B AS 12 DS CS 18 R/W 46A 27 30 D15-D0 27A 30A BKPT Figure 11-4. Fast Termination Read Cycle Timing Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-13 Freescale Semiconductor, Inc. S0 S4 S1 S5 S0 CLKOUT 8 6 Freescale Semiconductor, Inc... A31-A0 FC3-FC0 SIZ1-SIZ0 12 AS 9 14B DS CS 20 46A R/W 23 24 18 D15-D0 27A 25 BKPT Figure 11-5. Fast Termination Write Cycle Timing Diagram 11-14 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 CLKOUT A31-A0 7 Freescale Semiconductor, Inc... D15-D0 AS 16 DS R/W DSACK0 DSACK1 47A BR 35 39A BG 33 34 BGACK 37 Figure 11-6. Bus Arbitation Timing--Active Bus Case MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-15 Freescale Semiconductor, Inc. CLKOUT A31-A0 D15-D0 AS 47A 47A BR 37 Freescale Semiconductor, Inc... 35 BG 33 47A 34 BGACK Figure 11-7. Bus Arbitration Timing--Idle Bus Case S41 S0 S42 S43 S1 S0 S2 CLKOUT 8 6 A31-A0 18 R/W 20 AS 12 15 9 DS 70 72 71 D15-D0 27A BKPT SHOW CYCLE START OF EXTERNAL CYCLE Figure 11-8. Show Cycle Timing Diagram 11-16 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 0-2 CLOCKS * S0 S1 S2 S3 S4 S5 CLKOUT 6 8 SIZ1-SIZ0 Freescale Semiconductor, Inc... FC3-FC0 A31-A0, 11 14 AS 13 9 12 DS 9A IACKx 18 20 21 R/W 46 31A 28 DSACK0 47A DSACK1 31 29 D15-D0 29A 27 * Up to two wait states may be inserted by the processor between states S0 and S1. Figure 11-9. IACK Cycle Timing Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-17 Freescale Semiconductor, Inc. CLKOUT FREEZE 83 82 Freescale Semiconductor, Inc... BKPT/DSCLK 85 81 80 IFETCH/DSI 84 IPIPE/DSO Figure 11-10. Background Debug Mode Serial Port Timing CLKOUT 86 FREEZE 87 IFETCH/DSI 88 89 Figure 11-11. Background Debug Mode FREEZE Timing 11-18 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 11.8 DMA MODULE AC ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70C; see Figure 11-12) 3.3 V 3.3 V or 5.0 V 8.39 MHz Freescale Semiconductor, Inc... Num. Characteristic 5.0 V 16.78 MHz 25.16 MHz Min Max Min Max Min Max Unit 1 CLKOUT Low to AS, DACK, DONE Asserted -- 60 -- 30 -- 20 ns 2 CLKOUT Low to AS, DACK Negated -- 60 -- 30 -- 20 ns 3 DREQ Asserted to AS Asserted (for DMA Bus Cycle) 41 Asynchronous Input Setup Time to CLKOUT Low 15 -- 8, 5 -- 5 -- ns 5 Asynchronous Input Hold Time from CLKOUT Low 30 -- 15 -- 10 -- ns 6 AS to DACK Assertion Skew -30 30 -15 15 -10 10 ns 7 DACK to DONE Assertion Skew -30 30 -15 15 -8 8 ns 8 AS, DACK, DONE Width Asserted 200 -- 100 -- 70 -- ns 80 -- 40 -- 28 -- ns 8A AS, DACK, DONE Width Asserted (Fast Termination Cycle) 3t cyc + tAIST + tCLSA ns NOTES: (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary. (d) For extended temperature parts T A = -40 to +85C. These specifications are preliminary. 1. Specification #4 for 16.78 MHz @ 3.3 V 0.3 V will be 8 ns. CPU_CYCLE (DMA REQUEST) S0 S1 S2 DMA_CYCLE S4 S3 S5 S0 S1 S2 S3 S4 S5 CLKOUT 4 5 1 DONE (INPUT) DREQ 6 3 8 AS 1 2 DACK 7 DONE (OUTPUT) 1 Figure 11-12. DMA Signal Timing Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-19 Freescale Semiconductor, Inc. 11.9 TIMER MODULE ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70C; see Figures 11-13 and 11-14) 3.3 V 3.3 V or 5.0 V 8.39 MHz Freescale Semiconductor, Inc... Num. Characteristic 16.78 MHz 5.0 V 25MHz Symbol Min Max Min Max Min Max Unit t cyc 119.2 -- 59.6 -- 40 -- ns 1 CLKOUT Period in Crystal Mode 2 Clock Rise and Fall Time t rf -- 20 -- 10 -- 5 ns 3 TIN/ TGATE High or Low Time, Minimum Pulse Width -- t cyc +40 -- t cyc +20 -- t cyc +12 -- ns 41 Asynchronous Input Setup Time to CLKOUT Low -- 15 -- 8, 5 -- 5 -- ns 5 Asynchronous Input Hold Time from CLKOUT Low -- 30 -- 15 -- 8 -- ns 6 Asynchronous Input Setup Time to CLKOUT High -- 10 -- 5 -- 3 -- ns 7 Asynchronous Input Hold Time from CLKOUT High -- 30 -- 15 -- 8 -- ns 8 CLKOUT High to TOUT Valid t TO 3 60 3 30 3 20 ns NOTES: (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary. (d) For extended temperature parts T A = -40 to +85C. These specifications are preliminary. 1. Specification #4 for 16.78 MHz @ 3.3 V 0.3 V will be 8 ns. 1 CLKOUT 2 2 TIN TGATE 3 3 Figure 11-13. Timer Module Clock Signal Timing Diagram 11-20 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. CLKOUT 5 4 TIN 6 7 TGATE 8 TOUT Figure 11-14. Timer Module Signal Timing Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-21 Freescale Semiconductor, Inc. 11.10 SERIAL MODULE ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70C; see numbered notes; see Figures 11-15-11-18) Num. Freescale Semiconductor, Inc... 1 Characteristic 3.3 V 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Symbol Min Max Min Max Min Max Unit CLKOUT Cycle Time t cyc 119.2 -- 59.6 -- 40 -- ns t rf t CS -- 20 -- 10 -- 5 ns 15 -- 8, 5 -- 5 -- ns 30 -- 15 -- 8 -- ns 2 Clock Rise or Fall Time 32 Clock Input (X1 or SCLK ) Synchronizer Setup Time 4 Clock Input (X1 or SCLK ) Synchronizer Hold Time t CH 5 TxD Data Valid from CLKOUT High t VLD 0.5 t cyc Max 6 X1 Cycle Time 7 X1 High or Low Time t X1 t X1HL Min 8 SCLK High or Low Time, Asynchronous (16x) Mode t AHL 2.25 t cyc 0.55 t cyc + 0.75(tCS + t CH ) t cyc + t CS + t CH 91 SCLK High Time, Synchronous (1x) Mode t SH t cyc (Gx) + tCS (Gx) + tCH (Gx) Min 10 SCLK Low Time, Synchronous (1x) Mode t SL Min 11 TxD Data Valid from SCLK Low, Synchronous (1x) Mode tT x D greater of ({1.5tcyc (Tx) + t CS (Tx) + t VLD (Tx)} + 0.5tcyc (Rx) + t CS (Rx) + t CH (Rx)}) or t SH 1.5tcyc (Tx) + t CS (Tx) + t VLD (Tx) 12 RxD Setup Time to SCLK High, Synchronous (1x) Mode tR x S 0.5tcyc (Rx) + t CS (Rx) + t CH (Rx) Min 13 RxD Hold Time from SCLK High, Synchronous (1x) Mode tR x H 0.5tcyc (Rx) + t CS (Rx) + t CH (Rx) Min Min Min Max NOTES: (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary. (d) For extended temperature parts T A = -40 to +85C. These specifications are preliminary. 1. Asynchronous operation numbers take into account a receiver and transmitter operating at different clock frequencies. (Rx) refers to receiver value. (Tx) refers to transmitter value. (Gx) refers to the value that is greater, either receiver or transmitter. 2. Specification #3 for 16.78 MHz @ 3.3 V 0.3 V will be 8 ns. 1 CLKOUT 5 TxD Figure 11-15. Serial Module General Timing Diagram 11-22 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 6 X1 2 2 7 7 Freescale Semiconductor, Inc... Figure 11-16. Serial Module Asynchronous Mode Timing (X1) 2 2 SCLK (16x) 8 8 Figure 11-17. Serial Module Asynchronous Mode Timing (SCLK-16X) 10 9 2 2 SCLK (1x) 11 TxD 13 12 RxD Figure 11-18. Serial Module Synchronous Mode Timing Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-23 Freescale Semiconductor, Inc. 11.11 IEEE 1149.1 ELECTRICAL SPECIFICATIONS ( See notes (a), (b), (c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70C; see Figures 11-19-11-21) Num. Characteristic 3.3 V or 5.0 V 5.0 V 8.39 MHz 16.78 MHz 25.16 MHz Min Max TCK Frequency of Operation Freescale Semiconductor, Inc... 3.3 V Min Max Min Max Unit 0 8.39 0 16.78 0 25 MHz 119.2 -- 59.6 -- 40 -- ns TCK Clock Pulse Width Measured at 1.5 V 56 -- 28 -- 18 -- ns 3 TCK Rise and Fall Times 0 10 0 5 0 3 ns 6 Boundary Scan Input Data Setup Time 32 -- 16 -- 10 -- ns 7 Boundary Scan Input Data Hold Time 52 -- 26 -- 18 -- ns 8 TCK Low to Output Data Valid 0 80 0 40 0 26 ns 9 TCK Low to Output High Impedance 0 120 0 60 0 40 ns 10 TMS, TDI Data Setup Time 30 -- 15 -- 10 -- ns 11 TMS, TDI Data Hold Time 30 -- 15 -- 10 -- ns 12 TCK Low to TDO Data Valid 0 50 0 25 0 16 ns 13 TCK Low to TDO High Impedance 0 50 0 25 0 16 ns 1 TCK Cycle Time in Crystal Mode 2 NOTES: (a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary, and apply only to the appropriate MC68340V low voltage part. (b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation. (c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary. (d) For extended temperature parts T A = -40 to +85C. These specifications are preliminary. 1 2 2 VIH TCK VIL 3 3 Figure 11-19. Test Clock Input Timing Diagram 11-24 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TCK VIH VIL 7 6 DATA INPUTS INPUT DATA VALID 8 Freescale Semiconductor, Inc... DATA OUTPUTS OUTPUT DATA VALID 9 DATA OUTPUTS 8 DATA OUTPUTS OUTPUT DATA VALID Figure 11-20. Boundary Scan Timing Diagram VIH TCLK VIL 10 TDI TMS 11 INPUT DATA VALID 12 TDO OUTPUT DATA VALID 13 TDO 12 TDO OUTPUT DATA VALID Figure 11-21. Test Access Port Timing Diagram MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-25 Freescale Semiconductor, Inc. SECTION 12 ORDERING INFORMATION AND MECHANICAL DATA Freescale Semiconductor, Inc... This section contains ordering information, pin assignments and package dimensions of the MC68340. 12.1 STANDARD MC68340 ORDERING INFORMATION Supply Voltage Package Type Frequency (MHz) Temperature Order Number 5.0 V Ceramic Quad Flat Pack FE Suffix 0 - 16.78 0 - 16.78 0 - 25 0C to +70C -40C to +85C 0C to +70C MC68340FE16 MC68340CFE16 MC68340FE25 5.0 V Plastic Pin Grid Array RP Suffix 0 - 16.78 0 - 16.78 0 - 25 0C to +70C -40C to +85C 0C to +70C MC68340RP16 MC68340CRP16 MC68340RP25 3.3 V Ceramic Quad Flat Pack FE Suffix 0 - 8.39 0 - 8.39 0 - 16.78 0C to +70C -40C to +85C 0C to +70C MC68340FE8V MC68340CFE8V MC68340FE16V 3.3 V Plastic Pin Grid Array RP Suffix 0 - 8.39 0 - 8.39 0 - 16.78 0C to +70C -40C to +85C 0C to +70C MC68340RP8V MC68340CRP8V MC68340RP16V MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-1 Freescale Semiconductor, Inc. 12.2 PIN ASSIGNMEN -- CERAMIC SURFACE MOUNT RMC R/W D1 109 108 127 126 144 1 D0 D3 D2 D4 GND VCC D5 D7 D6 D9 D8 D11 D10 D12 GND VCC D13 GND D15 D14 A25 A24 A26 VCC A27 A28 GND A30 A29 DSACK0 A0 A31 VCC DSACK1 GND 12.2.1 144-Lead Ceramic Quad Flat Pack (FE Suffix) CS0 CS1 SIZ1 CS2 IRQ3 DS CS3 AS GND BGACK BG VCC IRQ5 BR IRQ6 BERR IRQ7 HALT DONE2 RESET DACK2 GND DREQ2 CLKOUT VCC DACK1 DONE1 XFC DREQ1 VCC X1 EXTAL 18 VCCSYN 19 TOP VIEW MC68340 91 GND 90 VCC XTAL X2 SCLK GND MODCK CTSB VCC RTSB IPIPE TxDB IFETCH RxDB BKPT RxRDYA FREEZE TxRDYA TIN1 CTSA TOUT1 RTSA GND TGATE1 TCK TMS VCC TxDA TDI RxDA TDO TIN2 . VCC TOUT2 12-2 73 72 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com A2 A3 GND A4 VCC A6 A5 A7 A8 A9 A10 GND A11 VCC A12 A13 A14 GND A15 A16 GND A17 VCC A19 A18 A20 A22 A21 A23 FC0 VCC GND FC1 54 55 TGATE2 A1 36 37 FC2 GND FC3 Freescale Semiconductor, Inc... SIZ0 MOTOROLA Freescale Semiconductor, Inc. The VCC and GND pins are separated into groups to help electrically isolate the output drivers for different functions of the MC68340. These groups are shown in the following table for the FE suffix package. Pin Group -- FE Suffix VCC GND 41, 50, 59, 68, 134 42, 51, 60, 69, 135 113, 123 114, 124 15, 17, 35, 143 13, 21, 36, 144 78, 90, 102 79, 91, 103 Oscillator 19 -- Internal Only 23 55, 126 Address Bus, Function Codes Data Bus AS, BG, CLKOUT, DS, FREEZE, HALT, IFETCH, IPIPE, MODCK, RESET, RMC, R/ W, SIZ, TDO, TOUT1, Internal Logic Freescale Semiconductor, Inc... CS, DACK, DONE, IRQ, RTS, RRDYA, TOUT2, TxDx, TRDYA, Internal Logic MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-3 Freescale Semiconductor, Inc. 12.2.2 145-Lead Plastic Pin Grid Array (RP Suffix) Q FC1 FC3 TDI TCK TIN1 FREEZE IPIPE MODCK EXTAL XFC RESET BERR BR AS SIZ1 A23 FC2 TDO TMS TOUT1 BKPT DS R/W RMC A22 FC0 GND VCC A20 GND VCC VCC A0 A3O A18 A19 A21 A31 A29 A28 A16 A17 VCC GND VCC A27 A14 A15 GND A25 A24 A26 GND D14 D15 P V CC XTAL VCC CLKOUT HALT BGACK N TGATE1 IFETCH GND VCCSYN V CC . GND BG SIZ0 GND DSACK1 DSACK0 M Freescale Semiconductor, Inc... L K J BOTTOM VIEW H A12 A13 GND A11 GND VCC GND D12 D13 A10 A9 A8 VCC D11 D10 A7 A6 A5 D7 D8 D9 A4 VCC GND NC GND D5 D6 A3 A2 TGATE2 V CC A1 TOUT2 TxDA TIN2 RxDA 1 2 G F E D C GND TxDB V CC GND X2 X1 DACK1 IRQ7 GND CS2 D1 VCC D4 DONE1 DONE2 VCC CS3 CS1 D0 D3 SCLK DREQ1 DREQ2 DACK2 IRQ6 IRQ5 IRQ3 CS0 D2 11 12 13 14 15 B RTSA TxRDYA RTSB A 12-4 CTSA RxRDYA RxDB 3 4 5 CTSB 6 7 8 9 10 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. The V CC and GND pins are separated into groups to help electrically isolate the different output drivers of the MC68340. These groups are shown in the following table for the RP suffix package. Pin Group -- RP Suffix VCC GND D2, G3, K3, K14, M3 D3, G2, J3, K13, M2 C14, F13 D13, G13 AS, BG, CLKOUT, DS, FREEZE, HALT, IFETCH, IPIPE, MODCK, RESET, RMC, R/ W, SIZx, TDO, TOUT1, Internal Logic M13, N4, N9, P9 N3, N7, N10, N13 CS, DACK, DONE, IRQ, RTS, RRDYA, TOUT2, TxDx, TRDYA, Internal Logic B11, C4, C7 C5, C8, C11 Oscillator N8 -- Internal Only P7 H3, H13 Address Bus, Function Codes Freescale Semiconductor, Inc... Data Bus MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-5 Freescale Semiconductor, Inc. 12.3 PACKAGE DIMENSIONS 12.3.1 FE Suffix X FE SUFFIX PACKAG CERAMIC QFP CASE 863A-01 PIN ONE INDEN A/B Freescale Semiconductor, Inc... TOP VIEW TRIMMED, FORMED DISCRET SHOWING DATUM FEATUR Z R K Q S Z Y S S 0.50M T X Y C M J M W 0.10144X T SEATING PLANE H D 144X G ZS 0.20M T X-Y 0.20M T Z S X-Y S S/V SIDE VIEW GULL WING LEAD CONFIGURA MILLIMETE DIM MIN MAX A 25.84 27.70 B 25.84 27.70 4.31 3.55 C 0.22 0.41 D 0.65 BS G 0.25 0.88 H 0.13 0.25 J 0.65 0.95 K 0 8 M 0.325 BS Q 12-6 INCHE MIN MAX 1.017 1.09 1.017 1.09 0.140 0.170 0.009 0.016 0.0256 BS 0.010 0.035 0.005 0.010 0.026 0.037 0 8 0.0128 BS 0.20 T X-Y Z S 0.20S T Z S X-Y S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIM A AND B DEFINE MAXIMUM CERAMIC BODY DIMEN INCLUDING GLASS PROTRUSION AND MISMATCH OF CE BODY TOP AND BOTTOM. 4. DATUM PLANE -W- IS LOCATED AT THE UNDERSIDE O WHERE LEADS EXIT PACKAGE BODY. 5. DATUMS X-Y AND Z TO BE DETERMINED WHERE CENT EXIT PACKAGE BODY AT DATUM -W-. 6. DIM S AND V TO BE DETERMINED AT SEATING PLANE 7. DIM A AND B TO BE DETERMINED AT DATUM PLANE - MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 12.3.2 RP Suffix V 145 PIN PGA CASE NO. 768E-01 C Q P N M L K J H G F E D C B A T D Freescale Semiconductor, Inc... G S A B PIN A-1 G BOTTOM VIEW 1 L V 2 3 4 5 6 7 8 9 10 11 12 13 14 15 M 145 PL K MILLIMETERS INCHES DIM MIN MAX MIN MAX A 39.37 39.88 1.570 B C D 39.37 22.75 22.75 39.88 22.97 1.550 1.550 0.895 0.905 0.905 22.97 0.895 1.570 G K 2.54 BASIC 2.92 3.43 0.100 BASIC 0.115 0.135 L M S V 1.02 1.52 0.43 0.55 4.32 4.95 35.56 BASIC 0.040 0.060 0.017 0.022 0.170 0.195 1.400 BASIC MOTOROLA .. . . . MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-7 Freescale Semiconductor, Inc. INDEX Freescale Semiconductor, Inc... -- A -- BB Bits, 6-4, 6-29, 6-38 BDM Sources, 5-66 BED Bit, 6-27, 6-27, 6-30-6-31, 6-37 A-Line Instructions, 5-47 BERR Signal, 5-45-5-47 A/D BES Bit, 6-20, 6-31, 6-37 Bit, 7-15-7-16, 7-23 BFC Bits, 4-30 Field, 5-73 BGND Instruction, 5-66 Register, 5-76-5-77 Binary-Coded Decimal A0 Signal, 3-6-3-13 Extended Instructions Timing Table, 5-106 Access Time Calculations, 10-6 Instructions, 5-26 Address Bit Manipulation Instructions, 5-25 Access Time, 10-6 Timing Table, 5-109 Bus Signals, 2-4, 3-4, 3-16 Bit Set/Reset Command, 7-37 Error Exception, 3-7, 3-39, 5-42-5-43, 5-45-5-46 Bits per Character, 7-23 Mask Register Example, 4-33 BKPT Signal, 5-65-5-66, 5-68, 5-71-5-72 Mask Registers, 4-31, 4-37 BKPT_TAG, 5-72 Registers, 5-10, 5-13 Block Mode, 7-13, 7-23 Space Bits, 4-20 BME Bit, 4-6, 4-25, 4-37 Space Block Size, 4-2, 4-3, 4-14 BMT Bits, 4-25-4-26, 4-37 Spaces, 2-5, 3-3-3-4, 4-2, 4-20, 4-30-4-31, 6-32 Strobe Signal, 2-6, 3-2, 3-4, 3-14-3-21, 3-44, 3-46, Boot ROM, 4-14-4-15, 4-36 Boundary Scan 4-22 Bit Definitions, 9-4 with Postincrement, 5-14 Register, 9-1-9-3 with Predecrement, 5-14 Break Condition, 7-11 Advantages, 10-13 Breakpoint Acknowledge Cycle Alternate Function Code Registers, 5-10 Operation, 3-22 Applications Profile, 10-10 Flowchart, 3-24 Arithmetic/Logical Instruction Timing Table, 5-102- Timing, Opcode Returned, 3-25 5-104 Timing, Exception Signaled, 3-26 Assert RTS Command, 7-28-7-29 Breakpoint Exception, 5-42, 5-46-5-47, 5-53 Asynchronous Breakpoint Instruction, 3-22, 5-28, 5-40, 5-42, Inputs, 3-1-3-2, 3-14-3-15, 3-44 5-46, 5-63, 5-94, 5-97 Operation, 3-14 Breakpoint Signal, 2-10, 3-22, 3-24, 6-31 Setup and Hold Times, 3-2, 3-15, 3-18-3-21,10-7 BRG Bit, 7-32, 7-46 ATEMP Register, 5-67 BRKP Bit, 6-20, 6-27, 6-31, 6-37-6-38 Automatic Echo Modes, 7-14, 7-38 Burst Mode Transfers, 6-5 Autovector Bus Operation Timing, 3-31 Arbitration Register, 4-5, 4-6, 4-23 Operation, 3-40, 3-41-3-45 Signal, 2-6, 3-5, 3-29, 3-32, 4-6 Flowchart, 3-41 Auxiliary Control Register, 7-18, 7-26-7-27, 7-32, 7-46 Interaction with Show Cycles, 3-44 Control, 3-44 State Diagram 3-45 -- B -- Bandwidth, 6-4-6-5, 6-29 Controller Operation, 5-89-5-90 B Bits, 5-56, 5-57-5-58 Cycle Termination Response Time, 4-6, 4-30, 4-32 B/C Bits, 7-23-7-24, 7-47 Cycle Termination, 3-34-3-36, 3-47 Background Debug Mode, 5-64-5-65, 5-94 Cycle, 3-2 Command Execution, 5-67 Error Exception, 5-45 Command Summary, 5-75-5-76 Error Signal, 2-8, 3-5, 3-14-3-15, 3-22, 3-24, 3-30, Serial Interface, 5-68-5-69 3-32-3-37, 3-44, 4-4, 4-6, 4-22, 4-30 Background Processing State, 5-7, 5-37, 5-64-5-73, Error Stack Frame, 5-60-5-63 5-95-5-101 Errors Base Address Bits, 4-20 Types, 3-34 Base Address Registers, 4-14, 4-30, 4-33, 4-37 Timing, without DSACK, 3-35 Battery Operation, 10-10 Timing, Late Bus Error, 3-36 Baud Rate Resulting in Double Bus Faults, 3-39 Clock, 7-2, 7-26-7-27 Generator, 7-3, 7-8 MOTOROLA MC68330 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Index-1 Freescale Semiconductor, Inc. During DMA Transfers, 6-18, 6-20, 6-31, 6-33-6-35 Grant Acknowledge Signal, 3-40-3-44 Request Signal, 2-7, 3-37, 3-40-3-44, 6-25 State Diagram, 3-45 Bypass Register, 9-11 Byte Transfer Counter, 6-15, 6-19-6-20, 6-34-6-35, 6-37-6-38 Freescale Semiconductor, Inc... -- C -- Calculate Effective Address Instruction Timing Table, 5-100 Calculating Frequency Adjusted Output, 10-7,-10-9 CALL Command, 5-68, 5-84-5-85 CD-I, 1-9, 10-11 CD-ROM, 10-11 Cell Types, 9-4 Output Latch Diagram, 9-7 Input Pin Diagram, 9-7 Active-High Output Control Diagram, 9-8 Active-Low Output Control Diagram, 9-8 Bidirectional Data Diagram, 9-9 Change of Flow, 5-91, 5-94 Changing Privilege Levels, 5-38 Timer Modes, 8-6 Channel Control Register, 6-4-6-5, 6-18-6-20, 6-26, 6-30, 6-36-6-37 Mode, 7-38 Status Register, 6-18, 6-20, 6-30, 6-37-6-38 Character Mode, 7-13, 7-23 Chip-Select 0 Signal, 3-30, 4-14-4-16, 4-33, 4-36, 10-5 Chip Select, 4-1, 4-13-4-15, 4-29 Access Time, 10-6-10-7 Overlapped, 4-15, 4-33 Programming Example, 4-33 Registers, 4-29 Signals, 2-5, 4-15-4-17, 10-4, 10-6-10-7 Clear to Send Signal, 2-11 CLK Bit, 8-21, 8-27 CLKOUT Signal, 2-8, 4-1, 4-9, 4-11, 4-13, 4-17, 5-69, 8-3, 9-11 Clock Operating Modes, 4-9-4-12 Select Register, 7-8, 7-18, 7-26-7-27, 7-33, 7-47 Synthesizer Control Register, 4-10-4-11, 4-13, 4-28, 4-36, Synthesizer, 4-1, 4-9 CM Bits, 7-38 Code Compatibility, 5-8, 5-11 COM Bit, 8-7-8-9, 8-12, 8-24-8-25, 8-27 Command Format, 5-73-5-74 Register, 7-10-7-11, 7-23, 7-27, 7-46-7-47 Sequence Diagram, 5-74-5-75 Index-2 Compare Register, 8-2, 8-12, 8-26-8-27 Compressed Tables, 5-31-5-32 Condition Code Register, 5-10, 5-14, 5-20-5-21 Condition Codes, 5-10, 5-26-5-27 Condition Test Instructions, 5-20-5-21, 5-29 Conditional Branch Instruction Timing Table, 5-110 CONF Bit, 6-20, 6-30-6-31, 6-37-6-38 Configuration Code (Modules) SIM40, 4-38-4-40 DMA, 6-38-6-45 Serial, 7-47-4-49 Timer, 8-28-8-31 Control Instruction Timing Table, 5-111 Control Register, 8-4, 8-20-8-23 COS Bit, 7-31-7-32, 7-34 Counter Clock, 8-3 Events, 8-2 Register, 8-6-8-7, 8-13-8-14, 8-25 CPE Bit, 8-6, 8-8, 8-21, 8-24, 8-28 CPU Space, 3-3, 3-21-3-23, 3-28 Address Encoding, 3-21 CPU32 Block Diagram, 5-3 Privilege Levels, 5-7, 5-37-5-38 Processing States, 5-7, 5-36-5-37 Programming Model, 5-8-5-9 Serial Logic, 5-71-5-73 Stack Frames, 5-60-5-63 Crystal Oscillator, 4-9-4-10, 4-29 CTS Bits, 7-31, 7-35 Operation, 7-11 CTSx Signal, 7-6-7-7, 7-11, 7-13, 7-20, 7-22, 7-29, 7-31-7-32, 7-35, 7-39 Current Drain, 10-11 Typical Operation Data, 10-12-10-13 Current Instruction Program Counter, 5-67-5-68 Cycle Steal Transfers, 6-5-6-6 Cycle Termination, 3-1 -- D -- DAPI Bits, 6-19, 6-28, 6-37 Data Bus Signals, 2-4, 3-2, 3-16 Holding Register, 6-12, 6-15 Misalignment, 5-45-5-46 Movement Instructions, 5-21 Port Organization, 3-5-3-7 Registers, 5-10 Strobe Signal, 2-7, 3-4, 3-17-3-21, 3-44-3-46, 4-22 Transfer and Size Acknowledge Signals, 2-6, 3-5, 3-8-3-15, 3-17-3-23, 3-28-3-30, 3-32-3-36, 4-2, 4-4, 4-6, 4-14-4-15, 4-32, Transfer Capabilities, 3-5, 3-8-3-15 DBA Bit, 7-33, 7-35 DBB Bit, 7-33, 7-34 DBcc Instruction, 5-3 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. DBF Bit, 4-6, 4-23 DBFE Bit, 4-6, 4-25, 4-37 DD Bits, 4-14, 4-17, 4-32 Destination Address Register, 6-15, 6-18-6-19, 6-28, 6-33-6-34, 6-37-6-38 Deterministic Opcode Tracking, 5-64, 5-87-5-88 DFC Bits, 6-32 Differences between MC68020 Instruction Set and MC68340 Instruction Set, 5-5 DIV Instructions, DMA Acknowledge Signals, 2-10, 6-4-6-7, 6-10, 6-12, 6-15 Capabilities, 6-1 Channel Initialization, 6-18-6-19, 6-36 Operation Sequence, 6-18-6-21 Termination, 6-18, 6-20-6-21 Done Signals, 2-10, 6-4, 6-7, 6-10, 6-12, 6-15 Programming Model, 6-23 Programming Sequence, 6-18 Request Signals, 2-10, 6-4-6-7, 6-18-6-19, 6-21 Timing Single-Address Read (External Burst), 6-8 Single-Address Read (Cycle Steal), 6-9 Single-Address Write (External Burst), 6-10 Single-Address Write (Cycle Steal), 6-11 Dual-Address Read (External Burst--Source Requesting), 6-13 Dual-Address Read (Cycle Steal--Source Requesting), 6-14 Dual-Address Write (External Burst--Destination Requesting), 6-16 Dual-Address Write (Cycle Steal--Destination Requesting), 6-17 Fast Termination (Cycle Steal), 6-21 Fast Termination (External Burst Source Requesting), 6-22 Transfer Type, 3-5 Transfers, Control of Bus, 6-6, 6-18 Transfers, 32 Bits, 6-2, 6-7, 6-35 Documentation, 1-10 DONE Bit, 6-15, 6-20, 6-27, 6-31, 6-37-6-38, 6-30 Double Bus Fault, 3-39, 3-41, 5-43, 5-66 Monitor, 3-40, 4-1, 4-4, 4-6, 4-23, 4-37 DSACK Encoding, 3-5 Signals, 4-2, 4-4, 4-6, 4-14, 4-32, 10-5 DSCLK Signal, 5-69-5-71 DSI Signal, 5-69, 5-71 DSIZE Bits, 6-15, 6-29, 6-37 DSO Signal, 5-69, 5-71 Dual-Address Destination Write, 6-15 Mode, 6-12, 6-28, 6-37 Source Read, 6-12 Transfer, 6-3 Dump Memory Block Command, 5-80-5-81 Dynamic Bus Sizing, 3-5, 3-14 MOTOROLA -- E -- Early Bus Error, 3-34 EBI, 4-2, 4-22, 4-33 ECO Bit, 6-7, 6-27-6-28, 6-37 Effects of Wait States on Instruction Timing, 5-92 Electrical Characteristics, 11-1 AC Electrical Specifications Definitions, 11-2, 11-4 Control Timing, 11-6-11-7 Timing Specifications, 11-8-11-10 Timing Diagram, 11-11-11-18 DMA Module Specifications, 11-19 DMA Timing Diagram, 11-19 Timer Module Specifications, 11-20 Timer Module Timing Diagrams, 11-20-11-21 Serial Module Specifications, 11-22 Serial Module Timing Diagrams, 11-22-11-23 IEEE 1149.1 Specifications, 11-24 IEEE 1149.1 Timing Diagrams, 11-24-11-25 Typical Characteristics, 10-11 DC Electrical Specifications, 11-5 ERR Bit, 7-13, 7-23, 7-47 Error Status, Serial, 7-13 Event Counting, 8-14-8-15 Exception Handler, 5-42, 5-51, 5-57, 5-59, 5-56 Priorities, 5-41-5-42 Processing, 3-32, 5-4, 5-38, 5-61 Faults, 5-54-5-59 Sequence, 5-40-5-41 State, 5-7, 5-38, 5-40-5-41 Stack Frame, 5-4, Vectors, 5-39-5-40 Exception-Related Instructions and Operands Timing Table, 5-112 EXTAL Pin, 2-9, 4-7, 4-9-4-11, 10-21 External Bus Interface, 4-2 Bus Master, 3-4, 3-16, 3-40-3-44, 4-6 DMA Request, 6-2, 6-5-6-6, 6-19-6-20, 6-29-6-30 Exceptions, 5-40 Reset, 10-3 -- F -- F-Line Instructions, 5-47 Fast Termination Timing, 3-15 Operation, 3-4, 3-15, 4-14, 4-30, 4-33 DMA Transfers, 6-20 Fault Address Register, 5-67 Correction, 5-57-5-59 Recovery, 5-52 Types, 5-54-5-55, 5-57-5-59, 5-83-5-86 FC Bits, 4-2 FCM Bits, 4-32 FE Bit, 7-13, 7-24, 7-28 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Index-3 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fetch Effective Address Instruction Timing Table, 5-99 FFULL Bit, 7-25 FFULLA Signal, 7-7 Fill Memory Block Command, 5-82 FIRQ Bit, 4-5, 4-16, 4-22, 4-35-4-36 FORCE_BGND, 5-72 Format Error Exception, 5-47, 5-52 Four-Word Stack Frame, 5-51, 5-60 Framing Error, 7-11, 7-24 Freeze Operation, 4-17, 6-24, 7-20, 8-19 FREEZE Signal, 2-10, 4-3, 4-17, 4-22-4-23, 4-36, 5-66-5-68, 5-71-5-72 Frequency Adjusted Signal Skew, 10-9 Width, 10-8 Frequency Divider, 4-12 FRZ Bits, 4-17-4-18, 4-21-4-22, 4-36, 6-24, 7-20, 7-46, 8-19, 8-27, FTE Bit, 4-14, 4-30 Full Format Instruction Word, Function Code, 3, 6-18, 6-32 Encoding, 2-5, 3-3 Register, 6-7, 6-10, 6-12, 6-15, 6-32, 6-38, 6-37 Signals, 2-5, 3-2, 3-17 -- G -- Global Chip Select, 4-14-4-15, 4-36 GO Command, 5-68, 5-83-5-84 -- H -- Halt Operation, 3-38, 3-39, 3-41 Signal, 2-8, 3-4, 3-13-3-15, 3-30, 3-32-3-38, 4-4, 4-6, 4-17 Halted Processing State, Halted Processor Causes, 3-40 Hardware Breakpoints, 5-60, 5-64-5-65 -- I -- IACK Signals, 4-15, 4-34 IARB Bits, 4-5, 4-22, 4-36, 6-25-6-26, 6-36, 7-21, 7-46, 8-19, 8-27 ICCS Bit, 7-20, 7-46 IE Bits, 8-4, 8-8-8-9, 8-21, 8-27 IEC Bits, 7-32, 7-46 IEEE 1149.1, 4-2, 9-1 Capabilities, 9-1, 9-4 Implementation, 9-2 Block Diagram, 9-2 Instruction Encoding, 9-10 Control Bits, 9-4 Restrictions, 9-11 IFETCH Signal, 5-64, 5-68-5-69, 5-87-5-88 Index-4 IL Bits, 7-21, 7-46, 8-20, 8-27 IMB, 6-19, 7-1, 8-1 Immediate Arithmetic/Logical Instruction Timing Table, 5-105 IN Bit, 5-53, 5-56, 5-61 Input Port, 7-35 Change Register, 7-31 Instruction Cycles, 5-97 Execution Overlap, 5-91-5-92, 5-94-5-95 Execution Time Calculation, 5-92-5-93 Fetch Signal, 2-19 Heads, 5-91-5-94, 5-97 Pipe Signal, 2-10 Pipeline Operation, 5-89-5-90, 5-93 Register, 9-9-9-10 Stream Timing Examples, 5-94-5-97 Tails, 5-91-5-94, 5-97 Timing Table Overview, 5-97-5-98 INTB Bit, 6-20, 6-27, 6-36 INTE Bit, 6-20, 6-27, 6-36 Integer Arithmetic Operations, 5-46-5-47 Internal Autovector, 3-4, 3-29, 4-23, 4-36 Bus Arbitration, 6-18 Bus Masters, 4-6, 6-25 Bus Monitor, 3-4, 3-32, 4-4, 4-6, 4-17 Data Multiplexer, 3-7 DMA Request, 6-2, 6-4, 6-5 DSACK signals, 3-5, 3-13-3-14, 3-28, 4-2, 4-4, 4-14-4-15, 4-32 Exceptions, 5-66 Interrupt Acknowledge Arbitration, 4-6, 6-25-6-26, 7-17 Acknowledge Cycle Types, 3-27 Autovector, 3-29 Autovector, Timing, 3-31 Flowchart, 3-28 Terminated Normally, 3-27, 4-7 Timing, 3-29 Acknowledge Cycle, 3-27 Acknowledge Signals, 3-29 Arbitration, 4-5-4-6, 7-21 Enable Register, 7-4, 7-34, 7-46 Exception, 5-68-5-69 Level Register, 7-21, 7-46 Register, 6-26, 8-20, 8-27 Request Signals, 2-5-2-6, 3-27-3-28, 6-26, 7-3, 7-21, 7-34, 8-4, 8-8, 8-9, 8-20 Status Register, 7-4, 7-22, 7-32, 7-34, 7-46 Vector Register, 7-4, 7-17, 7-21, 7-46 INTL Bits, 6-26, 6-36 INTN Bit, 6-27, 6-36 INTV Bits, 6-26, 6-36 IPIPE Signal, 5-87-5-88, 5-64, 5-68-5-69 IRQ Bit, 6-20, 6-31, 8-23 ISM Bits, 6-25, 6-36 IVR Bits, 7-22, 8-20, 8-27 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. -- J -- -- N -- JTAG, 4-2 NCS Bit, 4-31 Negate RTS Command, 7-29 Negative Tails, 5-93-5-94 No Operation Command, 5-86 Freescale Semiconductor, Inc... -- L -- Late Bus Error, 3-34 LG Bit, 5-56-5-57 Limp Mode, 4-19, 4-29 Local Loopback Mode, 7-14, 7-38 Location of Modules, 4-2-4-3, 4-20 Logical Instructions, 4-48 Long-Word Read 8-Bit Port, Timing, 3-11 16-Bit Port, Timing, 3-13 Write 8-Bit Port, Timing, 3-12 16-Bit Port, Timing, 3-13 Looping Modes, 7-14-7-15 Loss of Input Signal, 4-9, 4-11, 4-29 Low Power Stop Mode, 3-23, 4-13, 4-17, 4-29, 10-12 Low-Voltage, 10-10, 10-11 LPSTOP Cycle, 3-23 -- O -- OC Bits, 8-6-8-8, 8-10, 8-22, 8-28 OE Bit, 7-13, 7-25, 7-28 ON Bit, 8-6, 8-8, 8-11, 8-24 One Mode, 8-23 OP0, 7-6, 7-36-7-38 OP1, 7-7, 7-36-7-38 OP4, 7-7, 7-36-7-37 OP6, 7-7, 7-36-7-37 Opcode Tracking in Loop Mode, 5-88 Operand Faults, 5-56, 5-58, 5-61 Misalignment, 3-7 Size Field, 5-73 Operation Field, 5-73 Ordering Information, 12-1 OUT Bit, 8-7-8-8, 8-10, 8-24 Output Port Control Register, 7-36, 7-46 Data Register, 7-6-7-7, 7-22, 7-37 Overrun Error, 7-11, 7-25 -- M -- MAID Bits, 6-25, 6-36 Master Station, 7-15 Maximum Rating, 11-1 MC68681, 7-4 Memory Access Times, 10-7 Interfacing, 10-5, 10-10 Memory-to-Memory Transfer, 6-1, 6-3, 6-5 Microbus Controller, 5-89, 5-91 Microsequencer Operation, 5-89-5-90 Misaligned Operands, 3-7 MISC Bits, 7-28 MODCK Signal, 2-9, 4-7, 4-35 MODE Bits, 8-6, 8-8-8-10, 8-12-8-14, 8-16, 8-22, 8-28 Mode Register 1, 7-13, 7-16-7-17, 7-22, 7-34, 7-47 Mode Register 2, 7-4, 7-17, 7-38, 7-47 Module Base Address Register, 4-2, 4-20, 4-36 Access, 3-27 Module Configuration Register, 4-21, 4-36, 6-23, 7-19, 7-46, 8-18, 8-27 Locations, 4-3, 4-5 MOVE Instruction Timing Table, 5-101-5-102 MOVEM Faults, 5-56, 5-58-5-59, 5-61 MOVEP Faults, 5-55-5-56 Multidrop Mode, 7-15-7-16, 7-23 Timing, 7-16 Multiprocessor Systems, 5-61 MOTOROLA -- P -- Package Dimensions, 12-6-12-7 Package Types, 1-9, 12-1-12-2, 12-4 Parity Error, 7-11, 7-24 Mode, 7-23 Type, 7-23 PCLK Bit, 8-21, 8-22, 8-27 PE Bit, 7-11, 7-13, 7-24, 7-28 Period Measurement, 8-13 Periodic Interrupt Control Register, 4-7, 4-26, 4-37 Generation, 8-6, 8-8, 8-9 Timer Register, 4-7, 4-27, 4-37 Timer, 4-1, 4-4, 4-7, 4-9, 4-17 Periodic Timer Period Calculation, 4-8 Phase Comparator, 4-11-4-12 Phase-Locked Loop, 4-9-4-12, 10-1-10-2 Pin Group, 12-3, 12-5 PIRQL Bits, 4-7, 4-26, 4-37 PITR Bits, 4-27, 4-37 PIV Bits, 4-26 PM Bits, 7-23, 7-47 PO Bits, 8-25 Port A Data Direction Register, 4-34 Data Register, 4-34 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Index-5 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pin Assignment Register 1, 4-15, 4-33, 4-37 Pin Assignment Register 2, 4-15, 4-34, 4-37 Pins Functions, 4-15 Assignment Encoding, 4-15, 4-34 Port B Configuration, 4-5, 4-16 Data Direction Register, 4-35 Data Register, 4-35 Functions, 4-16 Pin Assignment Register, 4-16, 4-35, 4-37 Pins Functions, 2-6, 2-9, 4-16 Pin Assignment Encoding, 4-16, 4-35 Port Size, 4-14, 6-31 Port Width, 3-1, 3-7 POT Bits, 8-22, 8-28 Power Considerations, 11-2 Power Consumption, 1-8-1-9, 10-11 Power Dissipation, 10-11 Prefetch Controller, 5-90-5-91 Prefetch Faults, 5-55-5-58, 5-62 Preload Register 1, 8-6-8-13, 8-25-8-27 Preload Register 2, 8-10-8-11, 8-13, 8-26-8-27 Privilege Violations, 5-48 Processor Clock Circuitry, 10-1-10-2 Program Control Instructions, 5-26-5-27 Program Counter, 5-6, 5-67-5-68 Programming Model CPU32, 5-8-5-9 DMA, 6-23 Serial, 7-19 SIM40, 4-19 Timer, 8-18 Propagation Delays, 10-7 PS Bits, 4-14, 4-32 PT Bit, 7-23, 7-47 PTP Bit, 4-7, 4-27, 4-37 Pulse-Width Measurement, 8-12-8-13 Pulse-Width Modulation, 8-6-8-7 -- R -- R/F Bit, 7-22, 7-47 R/W Field, 5-73 RB Bit, 7-13, 7-24, 7-30 RC Bits, 7-30 RCS Bits, 7-26 Read A/D Register Command, 5-76-5-77 Cycle Word Read, Flowchart, 3-16 Memory Location Command, 5-79-5-80 Modify Write Cycle, 5-53 Modify Write Faults, 5-55-5-56, 5-58 System Register Command, 5-67, 5-77-5-78 Read-Modify-Write Cycle Timing, 3-19 Retry Operation, 3-36 Interruption, 3-36, 3-43 Operation, 3-4 Index-6 Read-Modify-Write Signal, 2-8, 3-19-3-21, 3-40, 3-42-3-43, 3-45 Read/Write Signal, 2-7, 3-2 Real-Time Clock, 4-9 Receive Data Signal, 2-11 Received Break, 7-11, 7-24, 7-33 Receiver, 7-9, 7-11 Baud Rates, 7-26 Buffer, 7-11-7-12, 7-25, 7-30 Disable Command, 7-30 Enable Command, 7-30 FIFO, 7-12-7-13, 7-17, 7-22-7-23, 7-25, 7-33-7-34 Holding Registers, 7-9, 7-11 Ready Signal, 2-12 Shift Register, 7-9, 7-12 Timing, 7-12 Register Field, 5-74 Indirect Addressing Mode, 5-5 Released Write, 5-57 Remote Loopback Mode, 7-14, 7-38 REQ Bits, 6-27, 6-29, 6-37 Request to Send Signal, 2-11 Reset Break-Change Interrupt, 7-28 Effect on DMA Transfers, 6-20 Error Status Command, 7-28 Exception, 5-43-5-44 Instruction, 5-85 Peripherals Command, 5-85-5-86 Operation, 3-45, 3-46 Receiver Command, 7-28 Signal, 2-8, 3-45-3-48, 5-66 Status Register, 4-3, 4-23 Types, 3-45 Timing, 3-47 Transmitter Command, 7-28 Values for Counter and Prescaler, 8-2 Vector, 5-4 RESET Signal, 3-45-3-48, 5-43 Retry Bus Cycle Operation, 3-32, 3-34-3-35 Timing, 3-37 Timing, Late Retry, 3-38 Return From Exception, 5-51-5-52 Return Program Counter, 5-67-5-68 Returning From Background Mode, 5-68 RM Bit, 5-53 ROM Interface, 10-3 RR Bit, 5-53 RS-232 Interface, 10-4-10-5 RSTEN Bit, 4-29 RTE Instruction, 5-57-5-59, 5-61 RTS Operation, 7-11, 7-22 RTSA Signal, 7-6, 7-37 RTSB Signal, 7-6, 7-36 RTS Signal, 7-11, 7-13, 7-22, 7-29, 7-38 RW Bit, 5-54 RxDx Signal, 7-6, 7-11, 7-14, 7-24 RxRDA Bit, 7-11, 7-13, 7-15, 7-24, 7-25 RxRDYA Bit, 7-34-7-35 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. RRDYA Signal, 7-7, 7-36 RxRDYB Bit, 7-33, 7-35 RxRTS Bit, 7-22, 7-47 Freescale Semiconductor, Inc... -- S -- S/D Bit, 6-30, 6-37 SAPI Bits, 6-12, 6-19, 6-28, 6-37 Save and Restore Operations Timing Table, 5-113 SB Bits, 7-39, 7-47 SCLK Signal, 7-3, 7-6, 7-8, 7-20 SE Bit, 6-25, 6-36 Selected Clock, 8-3, 8-21 Serial Clock Signal, 2-11 Command Control, 7-27 Communication Overview, 7-3 Compatibility with MC68681, 7-4 Crystal Oscillator, 7-3, 7-5 Diagnostic Functions, 7-14 Initialization, 7-46-7-49 Interface Timing, 5-68-5-71 Interface, 10-4-10-5 Maximum Data Transfer Rate, 7-2 Module Capabilities, 7-2 Module Programming Model, 7-19 Module Programming, 7-40 State Machine, 5-69-5-71 SFC Bits, 6-32 Shadowing, 8-6-8-7 SHEN Bits, 4-5, 4-22 Shift and Rotate Instructions, 5-24-5-25 Instruction Timing Table, 5-108 Show Cycles, 4-3, 4-22 Operation, 3-42-3-43, 3-45 Signal Relationships to CLKOUT, 10-7 Signal Widths, 10-8 SIM40 Configuration, 4-3 Programming Model, 4-19 Simultaneous Interrupts, 4-9 Single Address Mode, 6-2, 6-6-6-7, 6-10, 6-19, 6-27, 6-37 Source Read, 6-7-6-8 Source Write, 6-10-6-11 Single Operand Instruction Timing Table, 5-107 Single Step Operation, 3-36 Six-Word Stack Frame, 5-52, 5-60 SIZ Bits, 5-56-5-57, 5-73 Size Signal Encoding, 2-7, 3-3 Signals, 2-7, 3-3, 3-5-3-7 Skew Between Outputs, 10-9 Slave Station, 7-15 SLIMP Bit, 4-11, 4-29 SLOCK, 4-11, 4-29 Software Breakpoints, 5-53-5-54 MOTOROLA Interrupt Vector Register, 4-7, 4-24, 4-36 Operation, 4-4, 4-6, 4-17, 4-27 Service Register, 4-7, 4-28 Service Routine, 4-7, 4-25 Timeout, 4-25 Watchdog, 4-1, 4-4, 4-6 Watchdog Clock Rate, 4-7 Source Address Register, 6-7, 6-12, 6-18-6-19, 6-28, 6-33, 6-37, 6-38 Special Status Word, 5-45, 5-52 Special-Purpose MOVE Instruction Timing Table, 5-101-5-102 Spurious Interrupt, 3-29 Monitor, 4-1, 4-4, 4-6, 4-17, Square-Wave Generation, 8-6, 8-8-8-9 SRAM Interface, 10-3 SSIZE Bits, 6-12, 6-19, 6-29, 6-37 Stack Frames, 5-60-5-63 Pointer, 5-60-5-63 Start Break Command, 7-29 Status Register, 5-57, 5-59-5-60, 5-62-5-63, 7-10, 7-11, 7-24, 8-2, 8-4, 8-23-8-25 STEXT Bit, 4-13, 4-17, 4-29, 4-36 Stop Bit, 7-11 Length, 7-39 Stop Break Command, 7-29 STOP Instruction, 4-17 Stop Module Operation, 6-24, 7-20, 8-19 Stopped Processing State, 5-37 STP Bit, 4-17, 6-24, 6-36, 7-20, 7-46, 8-19, STR Bit, 6-3, 6-4, 6-5, 6-19, 6-30, 6-35, 6-37-6-38 STSIM Bit, 4-13, 4-17, 4-29, 4-36 Supervisor Privilege Level, 3-3 SUPV Bit, 4-22, 6-22, 6-25, 6-36, 7-21, 7-46, 8-19, 8-27 Surface Interpolation with Tables, 5-29-5-36 SW Bit, 4-23 SWE Bit, 4-6, 4=24, 4-37 SWP Bit, 4-7, 4-25, 4-27, 4-37 SWR Bit, 8-6, 8-8, 8-13, 8-20, 8-27 SWRI Bit, 4-7, 4-24, 4-37 SWT Bits, 4-7, 4-25, 4-37 Synchronous Accesses, 3-4 Operation, 3-14 System Clock, 8-3 Configuration and Protection, 4-1, 4-3, 4-6 Control Instructions, 5-27-5-28 Protection and Control Register, 4-6, 4-24, 4-37 -- T -- Table Lookup and Interpolate Instructions, 5-7, 5-12, 5-29-5-36 TAP Controller, 9-2-9-3 TC Bits, 8-7, 8-24 TCK Signal, 2-13, 9-2, 9-11, 9-12 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Index-7 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. TCS Bits, 7-27 TDI Signal, 2-13, 9-2 TDO Signal, 2-13, 9-2, 9-4 Test Access Port, 9-1 TG Bit, 8-6, 8-8, 8-23-8-24, 8-27 TGE Bit, 8-8-8-11, 8-15, 8-24, 8-27 TGL Bit, 8-7, 8-24 Thermal Characteristics, 11-1 Three Point Three Volts, 10-11 Timeout, 8-2, 8-7-8-9, 8-12, 8-15 Timer Bypass, 8-16 Clock Selection Logic, 8-3 Compare Function, 8-2, 8-6-8-9, 8-11-8-12, 8-14, 8-15, 8-25 Counter, 8-2 Counting Function, 8-13, 8-15 Gate Signal, 2-12, 8-6, 8-7-8-16, 8-21, 8-24-8-25 Input Signal, 2-12, 8-2, 8-5-8-17 Interrupt Operation, 8-4, 8-17, 8-19, 8-21, 8-23-8-24, 8-27 Output Signal, 2-12, 8-2, 8-5-8-17 Prescaler, 8-2-8-3, 8-21 Programming Model, 8-28 Uses, 8-2 Using to Compare Values, 8-6-8-8 TMS Signal, 2-13, 9-2 TO Bit, 8-8-8-9, 8-23-8-24, 8-27 Toggle Mode, 8-23 TP Bit, 5-61 TR Bit, 5-56, 5-58, 5-61 Trace Exception, 5-57 Modes, 5-10 on Instruction Execution, 5-63 Tracing, 5-56-5-58 Control Bits Encoding, 5-53 Transfer Cases, 3-5 Mechanism, 3-5, 3-16-3-18 Transition to Background Mode, 5-65-5-68 Transmit Data Signal, 2-11 Shift Register, 7-9, 7-11 Transmitter, 7-10-7-11 Baud Rates, 7-27 Buffer, 7-9-7-10, 7-25, 7-30-7-31 Disable Command, 7-29 Enable Command, 7-29 Holding Register, 7-9-7-10, 7-25, 7-33 Ready Signal, 2-11 Timing, 7-10 TRAP Instruction, 5-46 Two-Clock Bus Cycles, 10-3 TxCTS Bit, 7-39, 7-47 TxDx Signal, 7-3, 7-6, 7-10, 7-14, 7-29 TxEMP Bit, 7-10, 7-25, 7-28 TxRDY Bit, 7-10, 7-25, 7-28, 7-31 TxRDYA Bit, 7-34-7-35 TxRDYA Signal, 7-7, 7-36 TxRDYB Bit, 7-33, 7-35 Index-8 TxRTS Bit, 7-38, 7-47 Types of DMA Interrupts, 6-20 -- U -- Unimplemented Instructions, 5-12 Emulation, 5-74 Exception, 5-48, 5-50 UNLK Instruction, 5-36 Use of Chip Selects, 4-15, 10-3-10-4 User Privilege Level, 5-7, 5-37-5-38, 5-48 Using 8-Bit Boot ROM, 10-5 TGATE as an Input Port, 8-16 Table Lookup and Interpolate Instructions, 5-7, 5-12, 5-20-5-35 TOUT as an Output Port, 8-16-8-17 -- V -- V Bit, 4-14-4-15, 4-20, 4-31, 4-36 Variable Duty-Cycle Square-Wave Generator, 8-9-8-10 Variable-Width Single-Shot Pulse Generator, 8-10-8-12 VCCSYN, 2-13, 4-9-4-11, 10-2-10-3 Vector Base Register, 5-4, 5-10, 5-39-5-41, 5-43 Vector Numbers, 5-34-5-40 Virtual Memory, 5-2 Voltage-Controlled Oscillator, 4-9-4-12, 4-28-4-29, 10-1-10-2 -- W -- W Bit, 4-10, 4-12-4-13, 4-28, 4-36 Wait States, 3-14, 3-16-3-20, 4-1, 4-14-4-15, 4-17, 4-32 Wakeup Mode, 7-15 Word Operands, 5-12 WP Bit, 4-14 Write A/D Register Command, 5-77-5-79 Cycle Word, Flowchart, 3-18 Memory Location Command, 5-79-5-80 System Register Command, 5-78-5-79 Write-Pending Buffer, 5-91 -- X -- X Bit, 4-9, 4-11-4-13, 4-28, 4-36 X1 Signal, 2-11, 7-5 X2 Signal, 2-11, 7-5 XFC Pin, 2-9, 4-12, 10-2-10-3 XTAL Pin, 2-9, 4-9-4-11, 10-1-10-2 XTAL_RDY Bit, 7-4, 7-26, 7-33-7-34, 7-46 MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. -- Y -- Y Bits, 4-12-4-13, 4-28, 4-36 -- Z -- Freescale Semiconductor, Inc... Zero Mode, 8-23 MOTOROLA MC68340 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Index-9