©MOTOROLA INC., 1992
MC68340
Integrated Processor with DMA
User’s Manual
µ MOTOROLA
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PREFACE
The complete documentation package for the MC68340 consists of the MC68340UM/AD,
MC68340 Integrated Processor with DMA User’s Manual
, M68000PM/AD,
MC68000
Family Programmer’s Reference Manual,
and the MC68340P/D,
MC68340 Integrated
Processor with DMA Product Brief
.
The
MC68340 Integrated with DMA Processor User’s Manual
describes the programming,
capabilities, registers, and operation of the MC68340; the
MC68000 Family Programmer’s
Reference Manual
provides instruction details for the MC68340; and
the
MC68340
Integrated Processor with DMA Product Brief
provides a brief description of the MC68340
capabilities.
This user’s manual is organized as follows:
Section 1 Device Overview Section 8 Timer Modules
Section 2 Signal Descriptions Section 9 IEEE 1149.1 Test Access
Section 3 Bus Operation Port
Section 4 System Integration Module Section 10 Applications
Section 5 CPU32 Section 11 Electrical Characteristics
Section 6 DMA Controller Module Section 12 Ordering Information and
Section 7 Serial Module Mechanical Data
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL iii
TABLE OF CONTENTS
Paragraph Page
Number Title Number
Section 1
Device Overview
1.1 M68300 Family.................................................................................................. 1-2
1.1.1 Organization.................................................................................................. 1-3
1.1.2 Advantages.................................................................................................... 1-3
1.2 Central Processor Unit..................................................................................... 1-3
1.2.1 CPU32............................................................................................................ 1-4
1.2.2 Background Debug Mode ........................................................................... 1-4
1.3 On-Chip Peripherals........................................................................................ 1-5
1.3.1 System Integration Module ......................................................................... 1-5
1.3.1.1 External Bus Interface.............................................................................. 1-5
1.3.1.2 System Configuration and Protection ................................................... 1-6
1.3.1.3 Clock Synthesizer..................................................................................... 1-6
1.3.1.4 Chip Select and Wait State Generation............................................... 1-6
1.3.1.5 Interrupt Handling ..................................................................................... 1-6
1.3.1.6 Discrete I/O Pins........................................................................................ 1-6
1.3.1.7 IEEE 1149.1 Test Access Port................................................................ 1-7
1.3.2 Direct Memory Access Module................................................................... 1-7
1.3.3 Serial Module................................................................................................ 1-7
1.3.4 Timer Modules............................................................................................... 1-8
1.4 Power Consumption Management................................................................ 1-8
1.5 Physical.............................................................................................................. 1-9
1.6 Compact Disc-Interactive................................................................................ 1-9
1.7 More Information............................................................................................... 1-10
Section 2
Signal Descriptions
2.1 Signal Index....................................................................................................... 2-2
2.2 Address Bus....................................................................................................... 2-4
2.2.1 Address Bus (A23–A0)................................................................................ 2-4
2.2.2 Address Bus (A31–A24).............................................................................. 2-4
2.3 Data Bus (D15–D0) .......................................................................................... 2-4
2.4 Function Codes (FC3–FC0)............................................................................ 2-5
2. 5 Chip Selects (CS3CS0)................................................................................ 2-5
2.6 Interrupt Request Level (IRQ7, IRQ6, IRQ5, IRQ3)................................... 2-6
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11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
iv MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
2.7 Bus Control Signals......................................................................................... 2-6
2.7.1 Data and Size Acknowledge (DSACK1, DSACK0)................................ 2-6
2.7.2 Address Strobe (AS).................................................................................... 2-6
2.7.3 Data Strobe (DS)........................................................................................... 2-7
2.7.4 Transfer Size (SIZ1, SIZ0).......................................................................... 2-7
2.7.5 Read/Write (R/W)........................................................................................... 2-7
2.8 Bus Arbitration Signals .................................................................................... 2-7
2.8.1 B u s Requ est (BR).......................................................................................... 2-7
2.8.2 Bus Grant (BG)............................................................................................... 2-7
2.8.3 Bus Grant Acknowledge (BGACK)............................................................. 2-7
2.8.4 Read-Modify-Write Cycle (RMC)................................................................. 2-8
2.9 Exception Control Signals.............................................................................. 2-8
2.9.1 Reset (RESET)............................................................................................... 2-8
2.9.2 Halt (HALT).................................................................................................... 2-8
2.9.3 Bus Error (BERR)........................................................................................... 2-8
2.10 Clock Signals .................................................................................................... 2-8
2.10.1 System Clock (CLKOUT)............................................................................ 2-8
2.10.2 Crystal Oscillator (EXTAL, XTAL)............................................................... 2-9
2.10.3 External Filter Capacitor (XFC).................................................................. 2-9
2.10.4 Clock Mode Select (MODCK)..................................................................... 2-9
2.11 Instrumentation and Emulation Signals....................................................... 2-9
2.11.1 Instruction Fetch (IFETCH).......................................................................... 2-9
2.11.2 Instruction Pipe (IPIPE)............................................................................... 2-9
2.11.3 Breakpoint (BKPT)........................................................................................ 2-10
2.11.4 Freeze (FREEZE).......................................................................................... 2-10
2.12 DMA Module Signals....................................................................................... 2-10
2.12.1 DMA Request (DREQ2, DREQ1)................................................................. 2-10
2.12.2 DMA Acknowledge (DACK2, DACK1)...................................................... 2-10
2.12.3 DMA Done (DONE2, DONE1)...................................................................... 2-10
2.13 Serial Module Signals..................................................................................... 2-11
2.13.1 Serial Crystal Oscillator (X2, X1)............................................................... 2-11
2.13.2 Serial External Clock Input (SCLK)........................................................... 2-11
2.13.3 Receive Data (RxDA, RxDB)....................................................................... 2-11
2.13.4 Transmit Data (TxDA, TxDB)....................................................................... 2-11
2.13.5 Clear to Send (CTSA, CTSB)..................................................................... 2-11
2.13.6 Request to Send (RTSA, RTSB)................................................................ 2-11
2.13.7 Transmitter Ready (TRDYA)..................................................................... 2-11
2.13.8 Receiver Ready (RRDYA)......................................................................... 2-12
2.14 Timer Signals.................................................................................................... 2-12
2.14.1 Timer Gate (TGATE2, TGATE1)................................................................ 2-12
2.14.2 Timer Input (TIN2, TIN1).............................................................................. 2-12
2.14.3 Timer Output (TOUT2, TOUT1)................................................................... 2-12
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL v
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
2.15 Test Signals....................................................................................................... 2-13
2.15.1 Test Clock (TCK)........................................................................................... 2-13
2.15.2 Test Mode Select (TMS).............................................................................. 2-13
2.15.3 Test Data In (TDI).......................................................................................... 2-13
2.15.4 Test Data Out (TDO)..................................................................................... 2-13
2.16 Synthesizer Power (VCCSYN).......................................................................... 2-13
2.17 System Power and Ground (VCC and GND)................................................ 2-13
2.18 Signal Summary............................................................................................... 2-13
Section 3
Bus Operation
3.1 Bus Transfer Signals........................................................................................ 3-1
3.1.1 Bus Control Signals..................................................................................... 3-2
3.1.2 Function Code Signals................................................................................ 3-3
3.1.3 Address Bus (A31–A0)................................................................................ 3-4
3.1.4 Address Strobe (AS).................................................................................... 3-4
3.1.5 Data Bus (D15–D0)...................................................................................... 3-4
3.1.6 Data Strobe (DS)........................................................................................... 3-4
3.1.7 Bus Cycle Termination Signals.................................................................. 3-4
3.1.7.1 Data Transfer and Size Acknowledge Signals
(DSACK1 and DSACK0)..................................................................... 3-4
3.1.7.2 Bus Error (BERR)....................................................................................... 3-5
3.1.7.3 Autovector (AVEC).................................................................................... 3-5
3.2 Data Transfer Mechanism............................................................................... 3-5
3.2.1 Dynamic Bus Sizing ..................................................................................... 3-5
3.2.2 Misaligned Operands................................................................................... 3-7
3.2.3 Operand Transfer Cases............................................................................. 3-7
3.2.3.1 Byte Operand to 8-Bit Port, Odd or Even (A0 = X).............................. 3-7
3.2.3.2 Byte Operand to 16-Bit Port, Even (A0 = 0).......................................... 3-8
3.2.3.3 Byte Operand to 16-Bit Port, Odd (A0 = 1)........................................... 3-9
3.2.3.4 Word Operand to 8-Bit Port, Aligned..................................................... 3-9
3.2.3.5 Word Operand to 16-Bit Port, Aligned................................................... 3-10
3.2.3.6 Long-word Operand to 8-Bit Port, Aligned........................................... 3-10
3.2.3.7 Long-Word Operand to 16-Bit Port, Aligned........................................ 3-12
3.2.4 Bus Operation................................................................................................ 3-14
3.2.5 Synchronous Operation with DSACK..................................................... 3-14
3.2.6 Fast Termination Cycles.............................................................................. 3-15
3.3 Data Transfer Cycles........................................................................................ 3-16
3.3.1 Read Cycle..................................................................................................... 3-16
3.3.2 Write Cycle..................................................................................................... 3-18
3.3.3 Read-Modify-Write Cycle............................................................................. 3-19
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11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
vi MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
3.4 CPU Space Cycles........................................................................................... 3-21
3.4.1 Breakpoint Acknowledge Cycle ................................................................. 3-22
3.4.2 LPSTOP Broadcast Cycle........................................................................... 3-23
3.4.3 Module Base Address Register Access.................................................... 3-27
3.4.4 Interrupt Acknowledge Bus Cycles............................................................ 3-27
3.4.4.1 Interrupt Acknowledge Cycle—Terminated Normally........................ 3-27
3.4.4.2 Autovector Interrupt Acknowledge Cycle............................................. 3-29
3.4.4.3 Spurious Interrupt Cycle.......................................................................... 3-30
3.5 Bus Exception Control Cycles........................................................................ 3-32
3.5.1 Bus Errors....................................................................................................... 3-34
3.5.2 Retry Operation............................................................................................. 3-36
3.5.3 Halt Operation............................................................................................... 3-38
3.5.4 Double Bus Fault.......................................................................................... 3-39
3.6 Bus Arbitration ................................................................................................... 3-40
3.6.1 Bus Request................................................................................................... 3-43
3.6.2 Bus Grant........................................................................................................ 3-43
3.6.3 Bus Grant Acknowledge.............................................................................. 3-43
3.6.4 Bus Arbitration Control................................................................................. 3-44
3.6.5 Show Cycles.................................................................................................. 3-44
3. 7 Reset Operation................................................................................................ 3-46
Section 4
System Integration Module
4.1 Module Overview .............................................................................................. 4-1
4.2 Module Operation............................................................................................. 4-2
4.2.1 Module Base Address Register Operation............................................... 4-2
4.2.2 System Configuration and Protection Operation .................................... 4-3
4.2.2.1 System Configuration.............................................................................. 4-5
4.2.2.2 Internal Bus Monitor................................................................................. 4-6
4.2.2.3 Double Bus Fault Monitor........................................................................ 4-6
4.2.2.4 Spurious Interrupt Monitor...................................................................... 4-6
4.2.2.5 Software Watchdog .................................................................................. 4-6
4.2.2.6 Periodic Interrupt Timer........................................................................... 4-7
4.2.2.6.1 Periodic Timer Period Calculation..................................................... 4-8
4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock............................. 4-9
4.2.2.7 Simultaneous Interrupts by Sources in the SIM40............................. 4-9
4.2.3 Clock Synthesizer Operation...................................................................... 4-9
4.2.3.1 Phase Comparator and Filter................................................................. 4-11
4.2.3.2 Frequency Divider.................................................................................... 4-12
4.2.3.3 Clock Control............................................................................................. 4-13
4.2.4 Chip Select Operation................................................................................. 4-13
4.2.4.1 Programmable Features.......................................................................... 4-14
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL vii
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
4.2.4.2 Global Chip Select Operation................................................................ 4-14
4.2.5 External Bus Interface Operation............................................................... 4-15
4.2.5.1 Port A........................................................................................................... 4-15
4.2.5.2 Port B........................................................................................................... 4-16
4.2.6 Low-Power Stop........................................................................................... 4-17
4.2.7 Freeze............................................................................................................. 4-17
4.3 Programming Model......................................................................................... 4-18
4.3.1 Module Base Address Register (MBAR)................................................... 4-20
4.3.2 System Configuration and Protection Registers ..................................... 4-21
4.3.2.1 Module Configuration Register (MCR).................................................. 4-21
4.3.2.2 Autovector Register (AVR)....................................................................... 4-23
4.3.2.3 Reset Status Register (RSR)................................................................... 4-23
4.3.2.4 Software Interrupt Vector Register (SWIV)........................................... 4-24
4.3.2.5 System Protection Control Register (SYPCR)..................................... 4-24
4.3.2.6 Periodic Interrupt Control Register (PICR)........................................... 4-26
4.3.2.7 Periodic Interrupt Timer Register (PITR)............................................... 4-27
4.3.2.8 Software Service Register (SWSR)...................................................... 4-28
4.3.3 Clock Synthesizer Control Register (SYNCR)........................................ 4-28
4.3.4 Chip Select Registers.................................................................................. 4-29
4.3.4.1 Base Address Registers.......................................................................... 4-30
4.3.4.2 Address Mask Registers.......................................................................... 4-31
4.3.4.3 Chip Select Registers Programming Example.................................... 4-33
4.3.5 External Bus Interface Control.................................................................... 4-33
4.3.5.1 Port A Pin Assignment Register 1 (PPARA1)....................................... 4-33
4.3.5.2 Port A Pin Assignment Register 2 (PPARA2)....................................... 4-34
4.3.5.3 Port A Data Direction Register (DDRA)................................................. 4-34
4.3.5.4 Port A Data Register (PORTA)................................................................ 4-34
4.3.5.5 Port B Pin Assignment Register (PPARB)............................................ 4-35
4.3.5.6 Port B Data Direction Register (DDRB)................................................. 4-35
4.3.5.7 Port B Data Register (PORTB, PORTB1).............................................. 4-35
4.4 MC68340 Initialization Sequence................................................................. 4-36
4.4.1 Startup............................................................................................................ 4-36
4.4.2 SIM40 Module Configuration..................................................................... 4-36
4.4.3 SIM40 Example Configuration Code........................................................ 4-38
Section 5
CPU32
5.1 Overview............................................................................................................. 5-1
5.1.1 Features.......................................................................................................... 5-2
5.1.2 Virtual Memory.............................................................................................. 5-2
5.1.3 Loop Mode Instruction Execution.............................................................. 5-3
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11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
viii MC68340 USER'S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
5.1.4 Vector Base Register.................................................................................... 5-4
5.1.5 Exception Handling...................................................................................... 5-4
5.1.6 Addressing Modes........................................................................................ 5-5
5.1.7 Instruction Set................................................................................................ 5-5
5.1.7.1 Table Lookup and Interpolate Instructions........................................... 5-7
5.1.7.2 Low-Power STOP Instruction................................................................. 5-7
5.1.8 Processing States......................................................................................... 5-7
5.1.9 Privilege States............................................................................................. 5-7
5.2 Architecture Summary..................................................................................... 5-8
5.2.1 Programming Model..................................................................................... 5-8
5.2.2 Registers......................................................................................................... 5-10
5.3 Instruction Set.................................................................................................... 5-11
5.3.1 M68000 Family Compatibility ..................................................................... 5-11
5.3.1.1 New Instructions........................................................................................ 5-11
5.3.1.1.1 Low-Power Stop (LPSTOP)................................................................ 5-11
5.3.1.1.2 Table Lookup and Interpolation (TBL) .............................................. 5-12
5.3.1.2 Unimplemented Instructions ................................................................... 5-12
5.3.2 Instruction Format and Notation................................................................. 5-12
5.3.3 Instruction Summary.................................................................................... 5-15
5.3.3.1 Condition Code Register ......................................................................... 5-20
5.3.3.2 Data Movement Instructions................................................................... 5-21
5.3.3.3 Integer Arithmetic Operations................................................................. 5-22
5.3.3.4 Logic Instructions ...................................................................................... 5-24
5.3.3.5 Shift and Rotate Instructions................................................................... 5-24
5.3.3.6 Bit Manipulation Instructions................................................................... 5-25
5.3.3.7 Binary-Coded Decimal (BCD) Instructions.......................................... 5-26
5.3.3.8 Program Control Instructions.................................................................. 5-26
5.3.3.9 System Control Instructions.................................................................... 5-27
5.3.3.10 Condition Tests......................................................................................... 5-29
5.3.4 Using the TBL Instructions.......................................................................... 5-29
5.3.4.1 Table Example 1: Standard Usage ....................................................... 5-30
5.3.4.2 Table Example 2: Compressed Table.................................................. 5-31
5.3.4.3 Table Example 3: 8-Bit Independent Variable.................................... 5-32
5.3.4.4 Table Example 4: Maintaining Precision.............................................. 5-34
5.3.4.5 Table Example 5: Surface Interpolations ............................................. 5-36
5.3.5 Nested Subroutine Calls............................................................................. 5-36
5.3.6 Pipeline Synchronization with the NOP Instruction................................ 5-36
5.4 Processing States............................................................................................. 5-36
5.4.1 State Transitions ........................................................................................... 5-37
5.4.2 Privilege Levels............................................................................................. 5-37
5.4.2.1 Supervisor Privilege Level...................................................................... 5-37
5.4.2.2 User Privilege Level ................................................................................. 5-39
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MOTOROLA MC68340 USER'S MANUAL ix
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
5.4.2.3 Changing Privilege Level........................................................................ 5-39
5.5 Exception Processing...................................................................................... 5-39
5.5.1 Exception Vectors......................................................................................... 5-40
5.5.1.1 Types of Exceptions................................................................................. 5-41
5.5.1.2 Exception Processing Sequence.......................................................... 5-41
5.5.1.3 Exception Stack Frame............................................................................ 5-42
5.5.1.4 Multiple Exceptions.................................................................................. 5-42
5.5.2 Processing of Specific Exceptions............................................................ 5-44
5.5.2.1 Reset........................................................................................................... 5-44
5.5.2.2 B u s E rr o r .. . . . .. . . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . ............................... 5-46
5.5.2.3 Address Error............................................................................................. 5-46
5.5.2.4 Instruction Traps........................................................................................ 5-47
5.5.2.5 Software Breakpoints............................................................................... 5-47
5.5.2.6 Hardware Breakpoints............................................................................. 5-48
5.5.2.7 Format Error............................................................................................... 5-48
5.5.2.8 Illegal or Unimplemented Instructions.................................................. 5-48
5.5.2.9 Privilege Violations................................................................................... 5-49
5.5.2.10 Tracing........................................................................................................ 5-50
5.5.2.11 Interrupts..................................................................................................... 5-51
5.5.2.12 Return from Exception.............................................................................. 5-52
5.5.3 Fault Recovery............................................................................................... 5-53
5.5.3.1 Types of Faults.......................................................................................... 5-55
5.5.3.1.1 Type I—Released Write Faults........................................................... 5-55
5.5.3.1.2 Type II—Prefetch, Operand, RMW, and MOVEP Faults................. 5-56
5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer....................... 5-57
5.5.3.1.4 Type IV—Faults During Exception Processing............................... 5-57
5.5.3.2 Correcting a Fault..................................................................................... 5-57
5.5.3.2.1 Type I—Completing Released Writes via Software....................... 5-57
5.5.3.2.2 Type I—Completing Released Writes via RTE................................ 5-57
5.5.3.2.3 Type II—Correcting Faults via RTE.................................................... 5-58
5.5.3.2.4 Type III—Correcting Faults via Software.......................................... 5-58
5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart................. 5-58
5.5.3.2.6 Type III—Correcting Faults via RTE................................................... 5-59
5.5.3.2.7 Type IV—Correcting Faults via Software......................................... 5-59
5.5.4 CPU32 Stack Frames.................................................................................. 5-60
5.5.4.1 Four-Word Stack Frame.......................................................................... 5-60
5.5.4.2 Six-Word Stack Frame............................................................................. 5-60
5.5.4.3 Bus Error Stack Frame............................................................................. 5-60
5.6 Development Support...................................................................................... 5-63
5.6.1 CPU32 Integrated Development Support ................................................ 5-63
5.6.1.1 Background Debug Mode (BDM) Overview........................................ 5-64
5.6.1.2 Deterministic Opcode Tracking Overview ............................................ 5-64
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Number Title Number
5.6.1.3 On-Chip Hardware Breakpoint Overview............................................. 5-64
5.6.2 Background Debug Mode ........................................................................... 5-65
5.6.2.1 Enabling BDM........................................................................................... 5-65
5.6.2.2 BDM Sources............................................................................................ 5-66
5.6.2.2.1 External
BKPT Signal.......................................................................... 5-66
5.6.2.2.2 BGND Instruction.................................................................................. 5-66
5.6.2.2.3 Double Bus Fault.................................................................................. 5-66
5.6.2.3 Entering BDM............................................................................................ 5-66
5.6.2.4 Command Execution................................................................................ 5-67
5.6.2.5 BDM Registers........................................................................................... 5-67
5.6.2.5.1 Fault Address Register (FAR)............................................................. 5-67
5.6.2.5.2 Return Program Counter (RPC)......................................................... 5-67
5.6.2.5.3 Cu r r ent I n s truc t ion Program Counter (PCC).................................... 5-67
5.6.2.6 Returning from BDM................................................................................. 5-68
5.6.2.7 Serial Interface.......................................................................................... 5-68
5.6.2.7.1 CPU Serial Logic.................................................................................. 5-69
5.6.2.7.2 Development System Serial Logic.................................................... 5-71
5.6.2.8 Command Set........................................................................................... 5-73
5.6.2.8.1 Command Format................................................................................. 5-73
5.6.2.8.2 Command Sequence Diagram.......................................................... 5-74
5.6.2.8.3 Command Set Summary..................................................................... 5-75
5.6.2.8.4 Read A/D Register (RAREG/RDREG)................................................ 5-76
5.6.2.8.5 Write A/D Register (WAREG/WDREG).............................................. 5-77
5.6.2.8.6 Read System Register (RSREG)........................................................ 5-77
5.6.2.8.7 Write System Register (WSREG)....................................................... 5-78
5.6.2.8.8 Read Memory Location (READ)......................................................... 5-79
5.6.2.8.9 Write Memory Location (WRITE)........................................................ 5-79
5.6.2.8.10 Dump Memory Block (DUMP)............................................................ 5-80
5.6.2.8.11 Fill Memory Block (FILL)...................................................................... 5-82
5.6.2.8.12 Resume Execution (GO)...................................................................... 5-83
5.6.2.8.13 Call User Code (CALL)........................................................................ 5-83
5.6.2.8.14 Reset Peripherals (RST)...................................................................... 5-85
5.6.2.8.15 No Operation (NOP)............................................................................. 5-85
5.6.2.8.16 Future Commands ................................................................................ 5-86
5.6.3 Deterministic Opcode Tracking.................................................................. 5-86
5.6.3.1 Instruction Fetch (IFETCH)...................................................................... 5-86
5.6.3.2 Instruction Pipe (IPIPE)........................................................................... 5-87
5.6.3.3 Opcode Tracking during Loop Mode.................................................... 5-88
5.7 Instruction Execution Timing........................................................................... 5-88
5.7.1 Resource Scheduling .................................................................................. 5-88
5.7.1.1 Microsequencer........................................................................................ 5-89
5.7.1.2 Instruction Pipeline ................................................................................... 5-89
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
5.7.1.3 Bus Controller Resources....................................................................... 5-89
5.7.1.3.1 Prefetch Controller................................................................................ 5-90
5.7.1.3.2 Write Pending Buffer............................................................................ 5-90
5.7.1.3.3 Microbus Controller.............................................................................. 5-91
5.7.1.4 Instruction Execution Overlap................................................................. 5-91
5.7.1.5 Effects of Wait States................................................................................ 5-92
5.7.1.6 Instruction Execution Time Calculation................................................ 5-92
5.7.1.7 Effects of Negative Tails.......................................................................... 5-93
5.7.2 Instruction Stream Timing Examples........................................................ 5-94
5.7.2.1 Timing Example 1—Execution Overlap................................................ 5-94
5.7.2.2 Timing Example 2—Branch Instructions.............................................. 5-95
5.7.2.3 Timing Example 3—Negative Tails ....................................................... 5-96
5.7.3 Instruction Timing Tables............................................................................ 5-97
5.7.3.1 Fetch Effective Address........................................................................... 5-99
5.7.3.2 Calculate Effective Address.................................................................... 5-100
5.7.3.3 MOVE Instruction...................................................................................... 5-101
5.7.3.4 Special-Purpose MOVE Instruction....................................................... 5-101
5.7.3.5 Arithmetic/Logic Instructions................................................................... 5-102
5.7.3.6 Immediate Arithmetic/Logic Instructions............................................... 5-105
5.7.3.7 Binary-Coded Decimal and Extended Instructions............................ 5-106
5.7.3.8 Single Operand Instructions ................................................................... 5-107
5.7.3.9 Shift/Rotate Instructions........................................................................... 5-108
5.7.3.10 Bit Manipulation Instructions................................................................... 5-109
5.7.3.11 Conditional Branch Instructions ............................................................. 5-110
5.7.3.12 Control Instructions................................................................................... 5-111
5.7.3.13 Exception-Related Instructions and Operations.................................. 5-111
5.7.3.14 Save and Restore Operations................................................................ 5-111
Section 6
DMA Controller Module
6.1 DMA Module Overview .................................................................................... 6-2
6.2 DMA Module Signal Definitions..................................................................... 6-4
6.2.1 DMA Request (DREQ)................................................................................ 6-4
6.2.2 DMA Acknowledge (DACK)...................................................................... 6-4
6.2.3 DMA Done (DONE)..................................................................................... 6-4
6. 3 Transfer Request Generation......................................................................... 6-4
6.3.1 Internal Request Generation....................................................................... 6-4
6.3.1.1 Internal Request, Maximum Rate........................................................... 6-5
6.3.1.2 Internal Request, Limited Rate............................................................... 6-5
6.3.2 External Request Generation..................................................................... 6-5
6.3.2.1 External Burst Mode................................................................................. 6-5
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
6.3.2.2 External Cycle Steal Mode..................................................................... 6-5
6.4 Data Transfer Modes........................................................................................ 6-6
6.4.1 Single-Address Mode.................................................................................. 6-6
6.4.1.1 Single-Address Read............................................................................... 6-7
6.4.1.2 Single-Address Write............................................................................... 6-9
6.4.2 Dual-Address Mode..................................................................................... 6-12
6.4.2.1 Dual-Address Read .................................................................................. 6-12
6.4.2.2 Dual-Address Write.................................................................................. 6-14
6.5 Bus Arbitration ................................................................................................... 6-18
6.6 DMA Channel Operation ................................................................................. 6-18
6.6.1 Channel Initialization and Startup............................................................. 6-18
6.6.2 Data Transfers............................................................................................... 6-19
6.6.2.1 Internal Request Transfers...................................................................... 6-19
6.6.2.2 External Request Transfers..................................................................... 6-19
6.6.3 Channel Termination................................................................................... 6-20
6.6.3.1 Channel Termination............................................................................... 6-20
6.6.3.2 Interrupt Operation.................................................................................... 6-20
6.6.3.3 Fast Termination Option.......................................................................... 6-20
6.7 Register Description......................................................................................... 6-22
6.7.1 Module Configuration Register (MCR)...................................................... 6-23
6.7.2 Interrupt Register (INTR).............................................................................. 6-26
6.7.3 Channel Control Register (CCR)............................................................... 6-26
6.7.4 Channel Status Register (CSR)................................................................. 6-30
6.7.5 Function Code Register (FCR)................................................................... 6-32
6.7.6 Source Address Register (SAR)................................................................ 6-33
6.7.7 Destination Address Register (DAR)......................................................... 6-33
6.7.8 Byte Transfer Counter Register (BTC)...................................................... 6-34
6.8 Data Packing..................................................................................................... 6-35
6.9 DMA Channel Initialization Sequence......................................................... 6-36
6.9.1 DMA Channel Configuration...................................................................... 6-36
6.9.1.1 DMA Channel Operation in Single-Address Mode............................ 6-37
6.9.1.2 DMA Channel Operation in Dual-Address Mode............................... 6-37
6.9.2 DMA Channel Example Configuration Code.......................................... 6-38
Section 7
Serial Module
7.1 Module Overview .............................................................................................. 7-2
7.1.1 Serial Communication Channels A and B ............................................... 7-3
7.1.2 Baud Rate Generator Logic........................................................................ 7-3
7.1.3 Internal Channel Control Logic .................................................................. 7-3
7.1.4 Interrupt Control Logic................................................................................. 7-3
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MOTOROLA MC68340 USER'S MANUAL xiii
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
7.1.5 Comparison of Serial Module to MC68681 ............................................. 7-4
7.2 Serial Module Signal Definitions................................................................... 7-4
7.2.1 Crystal Input or External Clock (X1).......................................................... 7-5
7.2.2 Crystal Output (X2)....................................................................................... 7-5
7.2.3 External Input (SCLK).................................................................................. 7-6
7.2.4 Channel A Transmitter Serial Data Output (TxDA)................................. 7-6
7.2.5 Channel A Rec eiver S erial D ata Inp u t (R xDA)........................................ 7-6
7.2.6 Channel B Transmitter Serial Data Output (TxDB)................................. 7-6
7.2.7 Channel B Rec eiver S erial D ata Inp u t (R xDB)........................................ 7-6
7.2.8 Channel A Request-To-Send (RTSA) ...................................................... 7-6
7.2.8.1 RTSA........................................................................................................... 7-6
7.2.8.2 OP0.............................................................................................................. 7-6
7.2.9 Channel B Request-To-Send (RTSB)....................................................... 7-6
7.2.9.1 RTSB........................................................................................................... 7-7
7.2.9.2 OP1.............................................................................................................. 7-7
7.2.10 Channel A Clear-To-Send (CTSA) ........................................................... 7-7
7.2.11 Channel B Clear-To-Send (CTSB)............................................................ 7-7
7.2.12 Channel A Transmitter Ready (TRDYA)................................................. 7-7
7.2.12.1 TRDYA...................................................................................................... 7-7
7.2.12.2 OP6.............................................................................................................. 7-7
7.2.13 Channel A Receiver Ready (RRDYA)..................................................... 7-7
7.2.13.1 RRDYA...................................................................................................... 7-7
7.2.13.2 FFULLA....................................................................................................... 7-7
7.2.13.3 OP4.............................................................................................................. 7-7
7.3 Operation............................................................................................................ 7-8
7.3.1 Baud Rate Generator................................................................................... 7-8
7.3.2 Transmitter and Receiver Operating Modes............................................ 7-8
7.3.2.1 Transmitter................................................................................................. 7-10
7.3.2.2 Receiver...................................................................................................... 7-11
7.3.2.3 FIFO Stack.................................................................................................. 7-12
7.3.3 Looping Modes............................................................................................. 7-14
7.3.3.1 Automatic Echo Mode.............................................................................. 7-14
7.3.3.2 Local Loopback Mode............................................................................. 7-14
7.3.3.3 Remote Loopback Mode......................................................................... 7-14
7.3.4 Multidrop Mode............................................................................................. 7-15
7.3.5 Bus Operation................................................................................................ 7-17
7.3.5.1 Read Cycles............................................................................................... 7-17
7.3.5.2 Write Cycles............................................................................................... 7-17
7.3.5.3 Interrupt Acknowledge Cycles................................................................ 7-17
7.4 Register Description and Programming....................................................... 7-17
7.4.1 Register Description ..................................................................................... 7-17
7.4.1.1 Module Configuration Register (MCR).................................................. 7-19
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TABLE OF CONTENTS (Continued)
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Number Title Number
7.4.1.2 Interrupt Level Register (ILR).................................................................. 7-21
7.4.1.3 Interrupt Vector Register (IVR)................................................................ 7-21
7.4.1.4 Mode Register 1 (MR1)............................................................................ 7-22
7.4.1.5 Status Register (SR)................................................................................. 7-24
7.4.1.6 Clock-Select Register (CSR) .................................................................. 7-26
7.4.1.7 Command Register (CR)......................................................................... 7-27
7.4.1.8 Receiver Buffer (RB)................................................................................. 7-30
7.4.1.9 Transmitter Buffer (TB)............................................................................. 7-30
7.4.1.10 Input Port Change Register (IPCR)........................................................ 7-31
7.4.1.11 A u xili a r y C o ntrol R e gist e r (ACR)............................................................ 7-32
7.4.1.12 Interrupt Status Register (ISR)................................................................ 7-32
7.4.1.13 Interrupt Enable Register (IER)............................................................... 7-34
7.4.1.14 Input Port (IP)............................................................................................. 7-35
7.4.1.15 Output Port Control Register (OPCR).................................................... 7-35
7.4.1.16 Output Port Data Register (OP).............................................................. 7-37
7.4.1.17 Mode Register 2 (MR2)............................................................................ 7-37
7.4.2 Programming................................................................................................. 7-40
7.4.2.1 Serial Module Initialization..................................................................... 7-40
7.4.2.2 I/O Driver Example.................................................................................... 7-40
7.4.2.3 Interrupt Handling ..................................................................................... 7-40
7.5 Serial Module Initialization Sequence......................................................... 7-46
7.5.1 Serial Module Configuration...................................................................... 7-46
7.5.2 Serial Module Example Configuration Code.......................................... 7-47
Section 8
Timer Modules
8.1 Module Overview .............................................................................................. 8-1
8.1.1 Timer and Counter Functions..................................................................... 8-2
8.1.1.1 Prescaler and Counter............................................................................. 8-2
8.1.1.2 Timeout Detection..................................................................................... 8-2
8.1.1.3 Comparator................................................................................................ 8-2
8.1.1.4 Clock Selection Logic.............................................................................. 8-3
8.1.2 Internal Control Logic................................................................................... 8-3
8.1.3 Interrupt Control Logic................................................................................. 8-4
8.2 Timer Modules Signal Definitions................................................................. 8-4
8.2.1 Timer Input (TIN1, TIN2).............................................................................. 8-5
8.2.2 Timer Gate (TGATE1, TGATE2)................................................................ 8-6
8.2.3 Timer Output (TOUT1, TOUT2)................................................................... 8-6
8.3 Operating Modes.............................................................................................. 8-6
8.3.1 Input Capture/Output Compare.................................................................. 8-6
8.3.2 Square-Wave Generator............................................................................. 8-8
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TABLE OF CONTENTS (Continued)
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8.3.3 Variable Duty-Cycle Square-Wave Generator........................................ 8-9
8.3.4 Variable-Width Single-Shot Pulse Generator......................................... 8-10
8.3.5 Pulse-Width Measurement.......................................................................... 8-12
8.3.6 Period Measurement.................................................................................... 8-13
8.3.7 Event Count................................................................................................... 8-14
8.3.8 Timer Bypass................................................................................................. 8-16
8.3.9 Bus Operation................................................................................................ 8-17
8.3.9.1 Read Cycles............................................................................................... 8-17
8.3.9.2 Write Cycles............................................................................................... 8-17
8.3.9.3 Interrupt Acknowledge Cycles................................................................ 8-17
8.4 Register Description......................................................................................... 8-17
8.4.1 Module Configuration Register (MCR)...................................................... 8-18
8.4.2 Interrupt Register (IR)................................................................................... 8-20
8.4.3 Control Register (CR)................................................................................... 8-20
8.4.4 Status Register (SR)..................................................................................... 8-23
8.4.5 Counter Register (CNTR)............................................................................ 8-25
8.4.6 Preload 1 Register (PREL1)........................................................................ 8-25
8.4.7 Preload 2 Register (PREL2)........................................................................ 8-26
8.4.8 Compare Register (COM)............................................................................ 8-26
8.5 Timer Module Initialization Sequence .......................................................... 8-27
8.5.1 Timer Module Configuration ....................................................................... 8-27
8.5.2 Timer Module Example Configuration Code........................................... 8-28
Section 9
IEEE 1149.1 Test Access Port
9.1 Overview............................................................................................................. 9-1
9.2 TAP Controller ................................................................................................... 9-2
9.3 Boundary Scan Register................................................................................. 9-3
9. 4 Instruction Register........................................................................................... 9-9
9.4.1 EXTEST (000)............................................................................................... 9-10
9.4.2 SAMPLE/PRELOAD (001).......................................................................... 9-10
9.4.3 BYPASS (X1X, 101)..................................................................................... 9-11
9.4.4 HI-Z (100)....................................................................................................... 9-11
9.5 MC68340 Restrictions...................................................................................... 9-11
9.6 Non-IEEE 1149.1 Operation ........................................................................... 9-12
Section 10
Applications
10.1 Minimum System Configuration................................................................... 10-1
10.1.1 Processor Clock Circuitry.......................................................................... 10-1
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TABLE OF CONTENTS (Concluded)
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10.1.2 Reset Circuitry............................................................................................. 10-3
10.1.3 SRAM Interface........................................................................................... 10-3
10.1.4 ROM Interface.............................................................................................. 10-4
10.1.5 Serial Interface ............................................................................................ 10-4
10.2 Memory Interface Information....................................................................... 10-5
10.2.1 Using an 8-Bit Boot ROM........................................................................... 10-5
10.2.2 Access Time Calculations......................................................................... 10-6
10.2.3 Calculating Frequency-Adjusted Output................................................ 10-7
10.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using
Single-Address DMA Mode.................................................................. 10-10
10.3 Power Consumption Considerations.......................................................... 10-10
10.3.1 MC68340 Power Reduction at 5V .......................................................... 10-11
10.3.2 MC68340V (3.3 V) ..................................................................................... 10-13
Section 11
Electrical Characteristics
11.1 Maximum Rating............................................................................................. 11-1
11.2 Thermal Characteristics................................................................................. 11-1
11.3 Power Considerations................................................................................... 11-2
11.4 AC Electrical Specification Definitions....................................................... 11-2
11.5 DC Electrical Specifications......................................................................... 11-5
11.6 AC Electrical Specifications Control Timing .............................................. 11-6
11.7 AC Timing Specifications .............................................................................. 11-8
11.8 DMA Module AC Electrical Specifications ................................................. 11-19
11.9 Timer Module Electrical Specifications...................................................... 11-20
11.10 Serial Module Electrical Specifications...................................................... 11-22
11.11 IEEE 1149.1 Electrical Specifications......................................................... 11-25
Section 12
Ordering Information and Mechanical Data
12.1 Standard MC68340 Ordering Information................................................. 12-1
12.2 Pin Assignment............................................................................................... 12-2
12.2.1 144-Lead Ceramic Quad Flat Pack (FE Suffix)..................................... 12-2
12.2.2 145-Lead Plastic Pin Grid Array (RP Suffix).......................................... 12-4
12.3 Package Dimensions..................................................................................... 12-6
12.3.1 FE Suffix....................................................................................................... 12-6
12.3.2 RP Suffix....................................................................................................... 12-7
Index
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL xvii
LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1 Block Diagram ......................................................................................................... 1-1
2-1 Functional Signal Groups..................................................................................... 2-1
3-1 Input Sample Window............................................................................................ 3-2
3 -2 MC68340 Interface to Various Port Sizes.......................................................... 3-7
3-3 Long-Word Operand Read Timing from 8-Bit Port............................................ 3-11
3-4 Long-Word Operand Write Timing to 8-Bit Port................................................. 3-12
3 - 5 Long-Word and Word Read and Write Timing—16-Bit Port........................... 3-13
3 -6 Fast Termination Timing........................................................................................ 3-15
3 - 7 Word Read Cycle Flowchart................................................................................. 3-16
3-8 Word Write Cycle Flowchart.................................................................................. 3-18
3 -9 Read-Modify-Write Cycle Timing......................................................................... 3-19
3-10 CPU Space Address Encoding............................................................................ 3-21
3-11 Breakpoint Operation Flowchart.......................................................................... 3-24
3-12 Breakpoint Acknowledge Cycle Timing (Opcode Returned) .......................... 3-25
3-13 Breakpoint Acknowledge Cycle Timing (Exception Signaled)...................... 3-26
3-14 Interrupt Acknowledge Cycle Flowchart............................................................. 3-28
3-15 Interrupt Acknowledge Cycle Timing.................................................................. 3-29
3-16 Autovector Operation Timing................................................................................ 3-31
3-17 Bus Error without DSACK................................................................................... 3-35
3-18 Late Bus Error with DSACK................................................................................ 3-36
3-19 Retry Sequence...................................................................................................... 3-37
3-20 Late Retry Sequence............................................................................................. 3-38
3-21 HALT Timing............................................................................................................ 3-39
3-22 Bus Arbitration Flowchart for Single Request.................................................... 3-41
3-23 Bus Arbitration Timing Diagram—Idle Bus Case.............................................. 3-42
3-24 Bus Arbitration Timing Diagram—Active Bus Case......................................... 3-42
3-25 Bus Arbitration State Diagram.............................................................................. 3-45
3-26 Show Cycle Timing Diagram................................................................................ 3-46
3-27 Timing for External Devices Driving RESET...................................................... 3-47
3-28 Power-Up Reset Timing Diagram........................................................................ 3-48
4-1 SIM40 Module Register Block.............................................................................. 4-3
4-2 System Configuration and Protection Function................................................ 4-5
4-3 Software Watchdog Block Diagram.................................................................... 4-7
4 -4 Clock Block Diagram for Crystal Operation....................................................... 4-10
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
4-5 MC68340 Crystal Oscillator .................................................................................. 4-10
4 -6 Clock Block Diagram for External Oscillator Operation................................... 4-11
4 -7 Full Interrupt Request Multiplexer........................................................................ 4-16
4-8 SIM40 Programming Model.................................................................................. 4-19
5-1 CPU32 Block Diagram........................................................................................... 5-3
5-2 Loop Mode Instruction Sequence....................................................................... 5-3
5-3 User Programming Model ..................................................................................... 5-9
5-4 Supervisor Programming Model Supplement.................................................. 5-9
5 -5 Status Register........................................................................................................ 5-10
5 - 6 Instruction Word General Format......................................................................... 5-12
5-7 Table Example 1..................................................................................................... 5-30
5-8 Table Example 2..................................................................................................... 5-31
5-9 Table Example 3..................................................................................................... 5-33
5-10 Exception Stack Frame.......................................................................................... 5-42
5-11 Reset Operation Flowchart.................................................................................... 5-45
5-12 Format $0—Four-Word Stack Frame.................................................................. 5-60
5-13 Format $2—Six-Word Stack Frame.................................................................... 5-60
5-14 Internal Transfer Count Register.......................................................................... 5-61
5-15 Format $C—BERR Stack for Prefetches and Operands.................................. 5-62
5-16 Format $C—BERR Stack on MOVEM Operand................................................ 5-62
5-17 Format $C—Four- and Six-Word BERR Stack.................................................. 5-63
5-18 In-Circuit Emulator Configuration........................................................................ 5-64
5-19 Bus State Analyzer Configuration....................................................................... 5-64
5-20 BDM Block Diagram............................................................................................... 5-65
5-21 BDM Command Execution Flowchart ................................................................. 5-68
5-22 Debug Serial I/O Block Diagram.......................................................................... 5-70
5-23 Serial Interface Timing Diagram .......................................................................... 5-71
5-24 BKPT Timing for Single Bus Cycle...................................................................... 5-72
5-25 BKPT Timing for Forcing BDM............................................................................. 5-72
5-26 BKPT/DSCLK Logic Diagram.............................................................................. 5-72
5-27 Command-Sequence Diagram............................................................................ 5-75
5-28 Functional Model of Instruction Pipeline............................................................ 5-87
5-29 Instruction Pipeline Timing Diagram ................................................................... 5-88
5-30 Block Diagram of Independent Resources........................................................ 5-90
5-31 Simultaneous Instruction Execution.................................................................... 5-91
5-32 Attributed Instruction Times................................................................................... 5-92
5-33 Example 1—Instruction Stream........................................................................... 5-95
5-34 Example 2—Branch Taken................................................................................... 5-95
5-35 Example 2—Branch Not Taken............................................................................ 5-96
5-36 Example 3—Branch Negative Tail...................................................................... 5-96
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL xix
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
6-1 DMA Block Diagram............................................................................................... 6-1
6-2 Single-Address Transfers..................................................................................... 6-3
6-3 Dual-Address Transfer........................................................................................... 6-3
6-4 DMA External Connections to Serial Module.................................................... 6-6
6-5 Single-Address Read Timing (External Burst).................................................. 6-8
6-6 Single-Address Read Timing (Cycle Steal)....................................................... 6-9
6-7 Single-Address Write Timing (External Burst)................................................... 6-10
6-8 Single-Address Write Timing (Cycle Steal) ....................................................... 6-11
6 -9 Dual-Address Read Timing (External Burst—Source Requesting)............... 6-13
6-10 Dual-Address Read Timing (Cycle Steal—Source Requesting) ................... 6-14
6-11 Dual-Address Write Timing (External Burst—Destination Requesting)........ 6-16
6-12 Dual-Address Write Timing (Cycle Steal—Destination Requesting) ............ 6-17
6-13 Fast Termination Option (Cycle Steal)................................................................ 6-21
6-14 Fast Termination Option (External Burst—Source Requesting).................... 6-22
6-15 DMA Module Programming Model ...................................................................... 6-23
6-16 Packing and Unpacking of Operands................................................................. 6-35
7-1 Simplified Block Diagram...................................................................................... 7-1
7-2 External and Internal Interface Signals.............................................................. 7-5
7-3 Baud Rate Generator Block Diagram.................................................................. 7-8
7-4 Transmitter and Receiver Functional Diagram.................................................. 7-9
7-5 Transmitter Timing Diagram................................................................................. 7-10
7-6 Receiver Timing Diagram...................................................................................... 7-12
7-7 Looping Modes Functional Diagram................................................................... 7-15
7-8 Multidrop Mode Timing Diagram......................................................................... 7-16
7-9 Serial Module Programming Model.................................................................... 7-19
7-10 Serial Module Programming Flowchart.............................................................. 7-41
8-1 Simplified Block Diagram...................................................................................... 8-1
8-2 Timer Functional Diagram..................................................................................... 8-3
8-3 External and Internal Interface Signals.............................................................. 8-5
8-4 Input Capture/Output Compare Mode................................................................. 8-7
8-5 Square-Wave Generator Mode............................................................................ 8-8
8-6 Variable Duty-Cycle Square-Wave Generator Mode...................................... 8-10
8-7 Variable-Width Single-Shot Pulse Generator Mode........................................ 8-11
8-8 Pulse-Width Measurement Mode........................................................................ 8-12
8-9 Period Measurement Mode.................................................................................. 8-14
8-10 Event Count Mode.................................................................................................. 8-15
8-11 Timer Module Programming Model..................................................................... 8-18
9 -1 Test Access Port Block Diagram.......................................................................... 9-2
9-2 TAP Controller State Machine.............................................................................. 9-3
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
9-3 Output Latch Cell (O.Latch)................................................................................... 9-7
9-4 Input Pin Cell (I.Pin)................................................................................................ 9-7
9 -5 Active-High Output Control Cell (IO.Ctl1)........................................................... 9-8
9-6 A c t i v e -L ow O ut pu t Co nt r ol Ce l l ( I O. Ct l 0)............................................................ 9-8
9-7 Bidirectional Data Cell (IO.Cell)........................................................................... 9-9
9-8 General Arrangement for Bidirectional Pins...................................................... 9-9
9 - 9 Bypass Register...................................................................................................... 9-11
10-1 Minimum System Configuration Block Diagram ............................................. 10-1
10-2 Sample Crystal Circuit ......................................................................................... 10-2
10-3 Statek Corporation Crystal Circuit..................................................................... 10-2
10-4 XFC and VCCSYN Capacitor Connections........................................................ 10-3
10-5 SRAM Interface..................................................................................................... 10-3
10-6 ROM Interface........................................................................................................ 10-4
10-7 Serial Interface ...................................................................................................... 10-5
10-8 External Circuitry for 8-Bit Boot ROM................................................................ 10-5
10-9 8-Bit Boot ROM Timing......................................................................................... 10-6
10-10 Access Time Computation Diagram.................................................................. 10-6
10-11 Signal Relationships to CLKOUT...................................................................... 10-7
10-12 Signal Width Specifications................................................................................ 10-8
10-13 Skew between Two Outputs............................................................................... 10-9
10-14 Circuitry for Interfacing 8-Bit Device to 16-Bit Memory in
Single-Address DMA Mode.............................................................................. 10-10
10-15 MC68340 Current vs. Activity at 5 V.................................................................. 10-11
10-16 MC68340 Current vs. Voltage/Temperature.................................................... 10-12
10-17 MC68340 Current vs. Clock Frequency at 5 V................................................ 10-12
11-1 Drive Levels and Test Points for AC Specifications....................................... 11-4
11-2 Read Cycle Timing Diagram............................................................................... 11-11
11-3 Write Cycle Timing Diagram............................................................................... 11-12
11-4 Fast Termination Read Cycle Timing Diagram............................................... 11-13
11-5 Fast Termination Write Cycle Timing Diagram................................................ 11-14
11-6 Bus Arbitation Timing—Active Bus Case......................................................... 11-15
11-7 Bus Arbitration Timing—Idle Bus Case............................................................ 11-16
11-8 Show Cycle Timing Diagram.............................................................................. 11-16
11-9 IACK Cycle Timing Diagram............................................................................... 11-17
11-10 Background Debug Mode Serial Port Timing................................................. 11-18
11-11 Background Debug Mode FREEZE Timing..................................................... 11-18
11-12 DMA Signal Timing Diagram.............................................................................. 11-19
11-13 Timer Module Clock Signal Timing Diagram.................................................. 11-20
11-14 Timer Module Signal Timing Diagram.............................................................. 11-21
11-15 Serial Module General Timing Diagram.......................................................... 11-22
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL xxi
LIST OF ILLUSTRATIONS (Concluded)
Figure Page
Number Title Number
11-16 Serial Module Asynchronous Mode Timing (X1)............................................ 11-23
11-17 Serial Module Asynchronous Mode Timing (SCLK–16X)............................ 11-23
11-18 Serial Module Synchronous Mode Timing Diagram..................................... 11-23
11-19 Test Clock Input Timing Diagram....................................................................... 11-25
11-20 Boundary Scan Timing Diagram....................................................................... 11-26
11-21 Test Access Port Timing Diagram...................................................................... 11-26
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11/2/95 SECTION 1: OVERVIEW UM Rev.1.0
xxii MC68340 USER'S MANUAL MOTOROLA
LIST OF TABLES
Table Page
Number Title Number
2-1 Signal Index............................................................................................................. 2-2
2-2 Address Space Encoding..................................................................................... 2-5
2-3 DSACK Encoding................................................................................................. 2-6
2-4 SIZx Signal Encoding............................................................................................ 2-7
2-5 Signal Summary..................................................................................................... 2-14
3-1 SIZx Signal Encoding............................................................................................ 3-3
3-2 Address Space Encoding..................................................................................... 3-3
3-3 DSACK Encoding................................................................................................. 3-5
3-4 DSACK, BERR, and HALT Assertion Results.................................................. 3-33
4-1 Clock Operating Modes......................................................................................... 4-9
4-2 System Frequencies from 32.768-kHz Reference............................................ 4-13
4-3 Clock Control Signals............................................................................................ 4-13
4 -4 Port A Pin Assignment Register........................................................................... 4-15
4 -5 Port B Pin Assignment Register........................................................................... 4-16
4-6 SHENx Control Bits................................................................................................ 4-22
4-7 Deriving Software Watchdog Timeout ................................................................ 4-25
4-8 BMTx Encoding....................................................................................................... 4-26
4-9 PIRQL Encoding...................................................................................................... 4-26
4-10 DDx Encoding......................................................................................................... 4-32
4-11 PSx Encoding.......................................................................................................... 4-32
5-1 Instruction Set.......................................................................................................... 5-6
5-2 Instruction Set Summary....................................................................................... 5-16
5-3 Condition Code Computations............................................................................. 5-20
5 - 4 D a ta M ov e me n t O p er a ti o ns.................................................................................. 5-21
5 -5 Integer Arithmetic Operations............................................................................... 5-23
5-6 Logic Operations..................................................................................................... 5-24
5-7 Shift and Rotate Operations.................................................................................. 5-25
5-8 Bit Manipulation Operations................................................................................. 5-25
5-9 Binary-Coded Decimal Operations..................................................................... 5-26
5-10 Program Control Operations................................................................................. 5-26
5-11 System Control Operations................................................................................... 5-28
5-12 Condition Tests....................................................................................................... 5-29
5-13 Standard Usage Entries ........................................................................................ 5-30
5-14 Compressed Table Entries................................................................................... 5-32
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11/2/95 SECTION 1: OVERVIEW UM Rev 1
MOTOROLA MC68340 USER'S MANUAL xxiii
LIST OF TABLES (Continued)
Table Page
Number Title Number
5-15 8-Bit Independent Variable Entries..................................................................... 5-33
5-16 Exception Vector Assignments............................................................................. 5-40
5-17 Exception Priority Groups...................................................................................... 5-43
5-18 Tracing Control........................................................................................................ 5-50
5-19 BDM Source Summary.......................................................................................... 5-67
5-20 Polling the BDM Entry Source.............................................................................. 5-68
5-21 CPU Generated Message Encoding................................................................... 5-70
5-22 Size Field Encoding............................................................................................... 5-74
5-23 BDM Command Summary .................................................................................... 5-77
5-24 Register Field for RSREG and WSREG.............................................................. 5-79
6-1 FRZx Control Bits.................................................................................................... 6-24
6-2 SSIZEx Encoding................................................................................................... 6-28
6-3 DSIZEx Encoding................................................................................................... 6-29
6 - 4 REQx Encoding....................................................................................................... 6-29
6-5 BBx Encoding and Bus Bandwidth...................................................................... 6-29
6-6 Address Space Encoding..................................................................................... 6-32
7-1 FRZx Control Bits.................................................................................................... 7-20
7-2 PMx and PT Control Bits........................................................................................ 7-23
7 - 3 B/Cx Control Bits..................................................................................................... 7-24
7 -4 RCSx Control Bits................................................................................................... 7-26
7 -5 TCSx Control Bits................................................................................................... 7-27
7 -6 MISCx Control Bits................................................................................................. 7-28
7 - 7 TCx Control Bits...................................................................................................... 7-29
7 -8 RCx Control Bits...................................................................................................... 7-30
7 - 9 CMx Control Bits..................................................................................................... 7-38
7-10 SBx Control Bits...................................................................................................... 7-39
8-1 OCx Encoding......................................................................................................... 8-17
8-2 FRZx Control Bits.................................................................................................... 8-19
8-3 IEx Encoding............................................................................................................ 8-21
8 -4 POTx Encoding....................................................................................................... 8-22
8-5 MODEx Encoding................................................................................................... 8-22
8-6 OCx Encoding......................................................................................................... 8-22
9-1 Boundary Scan Control Bits................................................................................. 9-4
9-2 Boundary Scan Bit Definitions............................................................................. 9-5
9-3 Instructions............................................................................................................... 9-10
10-1 Memory Access Times at 16.78 MHz................................................................ 10-7
10-2 Typical Electrical Characteristics....................................................................... 10-13
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MOTOROLA MC68340 USER’S MANUAL 1-1
SECTION 1
DEVICE OVERVIEW
The MC68340 is a high-performance 32-bit integrated processor with direct memory
access (DMA), combining an enhanced M68000-compatible processor, 32-bit DMA, and
other peripheral subsystems on a single integrated circuit. The MC68340 CPU32 delivers
32-bit CISC processor performance from a lower cost 16-bit memory system. The
combination of peripherals offered in the MC68340 can be found in a diverse range of
microprocessor-based systems, including embedded control and general computing.
Systems requiring very high-speed block transfers of data can especially benefit from the
MC68340.
The MC68340's high level of functional integration results in significant reductions in
component count, power consumption, board space, and cost while yielding much higher
system reliability and shorter design time. The 3.3-V MC68340V is particularly attractive to
applications requiring a very tight power budget. Complete code compatibility with the
MC68000 and MC68010 affords the designer access to a broad base of established real-
time kernels, operating systems, languages, applications, and development tools—many
oriented towards embedded control.
CPU32
68020– BASED
PROCESSOR
TWO-
CHANNEL
SERIAL
I/O
TWO-CHANNEL DMA
CONTROLLER
EXTERNAL
BUS
INTERFACE
CLOCK
SYNTHESIZER
SYSTEM
INTEGRATION
MODULE
(SIM40)
BUS
ARBITRATION
INTERMODULE BUS
TIMER TIMER
SYSTEM
PROTECTION
IEEE TEST
CHIP SELECTS
AND
WAIT STATES
Figure 1-1. Block Diagram
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1-2 MC68340 USER’S MANUAL MOTOROLA
The primary features of the MC68340, illustrated in Figure 1-1, are as follows:
High Functional Integration on a Single Piece of Silicon
CPU32—MC68020-Derived 32-Bit Central Processor Unit
— Upward Object-Code Compatible with MC68000 and MC68010
— Additional MC68020 Instructions and Addressing Modes
— Unique Embedded Control Instructions
— Fast Two-Clock Register Instructions—10,045 Dhrystones
Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers
— Single- or Dual-Address Transfers
— 32-Bit Addresses and Counters
— 8-, 16-, and 32-Bit Data Transfers
— 50 Mbyte/Sec Sustained Transfers (12.5 Mbyte/Sec Memory-to-Memory)
Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
— Baud Rate Generators
— Modem Control
— MC68681/MC2681 Compatible
— 9.8 Mbits/Sec Maximum Transfer Rate
Two Independent Counter/Timers
— 16-Bit Counter
— Up to 8-Bit Prescaler
— Multimode Operation
— 80-ns Resolution
System Integration Module Incorporates Many Functions Typically Relegated to
External PALs, TTL, and ASIC, such as:
— System Configuration — External Bus Interface
— System Protection — Periodic Interrupt Timer
— Chip Select and Wait State Generation — Interrupt Response
— Clock Generation — Bus Arbitration
— Dynamic Bus Sizing — IEEE 1149.1 Boundary Scan (JTAG)
— Up to 16 Discrete I/O Lines — Power-On Reset
32 Address Lines, 16 Data Lines
Power Consumption Control
— Static HCMOS Technology Reduces Power in Normal Operation
— Low Voltage Operation at 3.3 V ±0.3 V (MC68340V only)
— Programmable Clock Generator Throttles Frequency
— Unused Peripherals Can Be Turned Off
— LPSTOP Provides an Idle State for Lowest Standby Current
0–16.78 MHz or 0–25.16 MHz Operation
144-Pin Ceramic Quad Flat Pack (CQFP) or 145-Pin Plastic Pin Grid Array (PGA)
As a low voltage part, the MC68340V can operate with a 3.3-V power supply. MC68340 is
used throughout this manual to refer to both the low voltage and standard 5-V parts since
both are functionally equivalent.
1.1 M68300 FAMILY
The MC68340 is one of a series of components in the M68300 family. Other members of
the family include the MC68302, MC68330, MC68331, MC68332, and MC68333.
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MOTOROLA MC68340 USER’S MANUAL 1-3
1.1.1 Organization
The M68300 family of integrated processors and controllers is built on an M68000 core
processor, an on-chip bus, and a selection of intelligent peripherals appropriate for a set of
applications. The CPU32 is a powerful central processor with nearly the performance of
the MC68020. A system integration module incorporates the external bus interface and
many of the smaller circuits that typically surround a microprocessor for address decoding,
wait-state insertion, interrupt prioritization, clock generation, arbitration, watchdog timing,
and power-on reset timing.
Each member of the M68300 family is distinguished by its selection of peripherals.
Peripherals are chosen to address specific applications but are often useful in a wide
variety of applications. The peripherals may be highly sophisticated timing or protocol
engines that have their own processors, or they may be more traditional peripheral
functions, such as UARTs and timers. Since each major function is designed in a
standalone module, each module might be found in many different M68300 family parts.
Driver software written for a module on one M68300 part can be used to run the same
module that appears on another part.
1.1.2 Advantages
By incorporating so many major features into a single M68300 family chip, a system
designer can realize significant savings in design time, power consumption, cost, board
space, pin count, and programming. The equivalent functionality can easily require 20
separate components. Each component might have 16–64 pins, totaling over 350
connections. Most of these connections require interconnects or are duplications. Each
connection is a candidate for a bad solder joint or misrouted trace. Each component is
another part to qualify, purchase, inventory, and maintain. Each component requires a
share of the printed circuit board. Each component draws power—often to drive large
buffers to get the signal to another chip. The cumulative power consumption of all the
components must be available from the power supply. The signals between the CPU and
a peripheral might not be compatible nor run from the same clock, requiring time delays or
other special design considerations.
In a M68300 family component, the major functions and glue logic are all properly
connected internally, timed with the same clock, fully tested, and uniformly documented.
Power consumption stays well under a watt, and a special standby mode drops current
well under a milliamp during idle periods. Only essential signals are brought out to pins.
The primary package is the surface-mount quad flat pack for the smallest possible
footprint; pin grid arrays are also available.
1.2 CENTRAL PROCESSOR UNIT
The CPU32 is a powerful central processor that supervises system functions, makes
decisions, manipulates data, and directs I/O. A special debugging mode simplifies
processor emulation during system debug.
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1-4 MC68340 USER’S MANUAL MOTOROLA
1.2.1 CPU32
The CPU32 is an M68000 family processor specially designed for use as a 32-bit core
processor and for operation over the intermodule bus (IMB). Designers used the
MC68020 as a model and included advances of the later M68000 family processors,
resulting in an instruction execution performance of 4 MIPS (VAX-equivalent) at 25.16
MHz.
The powerful and flexible M68000 architecture is the basis of the CPU32. MC68000
(including the MC68HC000 and the MC68EC000) and MC68010 user programs will run
unmodified on the CPU32. The programmer can use any of the eight 32-bit data registers
for fast manipulation of data and any of the eight 32-bit address registers for indexing data
in memory. The CPU32 can operate on data types of single bits, binary-coded decimal
(BCD) digits, and 8, 16, and 32 bits. Peripherals and data in memory can reside anywhere
in the 4-Gbyte linear address space. A supervisor operating mode protects system-level
resources from the more restricted user mode, allowing a true virtual environment to be
developed.
Flexible instructions for data movement, arithmetic functions, logical operations, shifts and
rotates, bit set and clear, conditional and unconditional program branches, and overall
system control are supported, including a fast 32 × 32 multiply and 32-bit conditional
branches. New instructions, such as table lookup and interpolate and low power stop,
support the specific requirements of embedded control applications. Many addressing
modes complement these instructions, including predecrement and postincrement, which
allow simple stack and queue maintenance and scaled indexed for efficient table
accesses. Data types and addressing modes are supported orthogonally by all data
operations and with all appropriate addressing modes. Position-independent code is easily
written.
The CPU32 is specially optimized to run with the MC68340's 16-bit data bus. Most
instructions execute in one-half the number of clocks compared to the original MC68000,
yielding an overall 1.6 times the performance of the same-speed MC68000 and measuring
10,045 Dhrystones/sec @ 25.16 MHz (6,742 Dhrystones/sec @ 16.78 MHz).
Like all M68000 family processors, the CPU32 recognizes interrupts of seven different
priority levels and allows the peripheral to vector the processor to the desired service
routine. Internal trap exceptions ensure proper instruction execution with good addresses
and data, allow operating system intervention in special situations, and permit instruction
tracing. Hardware signals can either terminate or rerun bad memory accesses before
instructions process data incorrectly.
The CPU32 offers the programmer full 32-bit data processing performance with complete
M68000 compatibility, yet with more compact code than is available with RISC
processors. The CPU32 is identical in all CPU32-based M68300 family products.
1.2.2 Background Debug Mode
A special operating mode is available in the CPU32 in which normal instruction execution
is suspended while special on-chip microcode performs the functions of a debugger.
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MOTOROLA MC68340 USER’S MANUAL 1-5
Commands are received over a dedicated, high-speed, full-duplex serial interface.
Commands allow the manual reading or writing of CPU32 registers, reading or writing of
external memory locations, and diversion to user-specified patch code. This background
debug mode permits a much simpler emulation environment while leaving the processor
chip in the target system, running its own debugging operations.
1.3 ON-CHIP PERIPHERALS
To improve total system throughput and reduce part count, board size, and cost of system
implementation, the M68300 family integrates on-chip, intelligent peripheral modules and
typical glue logic. These functions on the MC68340 include the SIM40, a DMA controller,
a serial module, and two timers.
The processor communicates with these modules over the on-chip intermodule bus (IMB).
This backbone of the chip is similar to traditional external buses with address, data, clock,
interrupt, arbitration, and handshake signals. Because bus masters (like the CPU32 and
DMA), peripherals, and the SIM40 are all on the chip, the IMB ensures that
communication between these modules is fully synchronized and that arbitration and
interrupts can be handled in parallel with data transfers, greatly improving system
performance. Internal accesses across the IMB may be monitored from outside of the
chip, if desired.
Each module operates independently. No direct connections between peripheral modules
are made inside the chip; however, external connections could, for instance, link a serial
output to a DMA control line. Modules and their registers are accessed in the memory
map of the CPU32 (and DMA) for easy access by general M68000 instructions and are
relocatable. Each module may be assigned its own interrupt level, response vector, and
arbitration priority. Since each module is a self-contained design and adheres to the IMB
interface specifications, the modules may appear on other M68300 family products,
retaining the investment in the software drivers for the module.
1.3.1 System Integration Module
The MC68340 SIM40 provides the external bus interface for both the CPU32 and the
DMA. It also eliminates much of the glue logic that typically supports the microprocessor
and its interface with the peripheral and memory system. The SIM40 provides
programmable circuits to perform address decoding and chip selects, wait-state insertion,
interrupt handling, clock generation, bus arbitration, watchdog timing, discrete I/O, and
power-on reset timing. A boundary scan test capability is also provided.
1.3.1.1 EXTERNAL BUS INTERFACE. The external bus interface (EBI) handles the
transfer of information between the internal CPU32 or DMA controller and memory,
peripherals, or other processing elements in the external address space. Based on the
MC68030 bus, the external bus provides up to 32 address lines and 16 data lines.
Address extensions identify each bus cycle as CPU32 or DMA initiated, supervisor or user
privilege level, and instruction or data access. The data bus allows dynamic sizing for 8- or
16-bit bus accesses (plus 32 bits for DMA). Synchronous transfers from the CPU32 or the
DMA can be made in as little as two clock cycles. Asynchronous transfers allow the
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1-6 MC68340 USER’S MANUAL MOTOROLA
memory system to signal the CPU32 or DMA when the transfer is complete and to note
the number of bits in the transfer. An external master can arbitrate for the bus using a
three-line handshaking interface.
1.3.1.2 SYSTEM CONFIGURATION AND PROTECTION. The M68000 family of
processors is designed with the concept of providing maximum system safeguards.
System configuration and various monitors and timers are provided in the MC68340.
Power-on reset circuitry is a part of the SIM40. A bus monitor ensures that the system
does not lock up when there is no response to a memory access. The bus fault monitor
can reset the processor when a catastrophic bus failure occurs. Spurious interrupts are
detected and handled appropriately. A software watchdog can pull the processor out of an
infinite loop. An interrupt can be sent to the CPU32 with programmable regularity for
DRAM refresh, time-of-day clock, task switching, etc.
1.3.1.3 CLOCK SYNTHESIZER. The clock synthesizer generates the clock signals used
by all internal operations as well as a clock output used by external devices. The clock
synthesizer can operate with an inexpensive 32768-Hz watch crystal or an external
oscillator for reference, using an internal phase-locked loop and voltage-controlled
oscillator. At any time, software can select clock frequencies from 131 kHz to 16.78 MHz
or 25.16 MHz, favoring either low power consumption or high performance. Alternately, an
external clock can drive the clock signal directly at the operating frequency. With its fully
static HCMOS design, it is possible to completely stop the system clock without losing the
contents of the internal registers.
1.3.1.4 CHIP SELECT AND WAIT STATE GENERATION. Four programmable chip
selects provide signals to enable external memory and peripheral circuits, providing all
handshaking and timing signals with up to 175-ns access times with a 25-MHz system
clock (265 ns @ 16.78 MHz). Each chip select signal has an associated base address and
an address mask that determine the addressing characteristics of that chip select.
Address space and write protection can be selected for each. The block size can be
selected from 256 bytes up to 4 Gbytes in increments of 2n. Accesses can be preselected
for either 8- or 16-bit transfers. Fast synchronous termination or up to three wait states
can be programmed, whether or not the chip select signals are used. External
handshakes can also signal the end of a bus transfer. A system can boot from reset out of
8-bit-wide memory, if desired.
1.3.1.5 INTERRUPT HANDLING. Seven input signals are provided to trigger an external
interrupt, one for each of the seven priority levels supported. Seven separate outputs can
indicate the priority level of the interrupt being serviced. An input can direct the processor
to a default service routine, if desired. Interrupts at each priority level can be
preprogrammed to go to the default service routine. For maximum flexibility, interrupts can
be vectored to the correct service routine by the interrupting device.
1.3.1.6 DISCRETE I/O PINS. When not used for other functions, 16 pins can be
programmed as discrete input or output lines. Additionally, in other peripheral modules,
pins for otherwise unused functions can often be used for general input/output.
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MOTOROLA MC68340 USER’S MANUAL 1-7
1.3.1.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68340
includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1
standard for boundary scan testability, often referred to as JTAG (Joint Test Action
Group).
1.3.2 Direct Memory Access Module
The most distinguishing MC68340 characteristic is the high-speed 32-bit DMA controller,
used to quickly move large blocks of data between internal peripherals, external
peripherals, or memory without processor intervention. The DMA module consists of two,
independent, programmable channels. Each channel has separate request, acknowledge,
and done signals. Each channel can operate in a single-address or a dual-address (flyby)
mode.
In single-address mode, only one (the source or the destination) address is provided, and
a peripheral device such as a serial communications controller receives or supplies the
data. An external request must start a single-address transfer. In this mode, each channel
supports 32 bits of address and 8, 16, or 32 bits of data.
In dual-address mode, two bus transfers occur, one from a source device and the other to
a destination device. Dual-address transfers can be started by either an internal or
external request. In this mode, each channel supports 32 bits of address and 8 or 16 bits
of data (32 bits require external logic). The source and destination port size can be
selected independently; when they are different, the data will be packed or unpacked. An
8-bit disk interface can be read twice before the concatenated 16-bit result is passed into
memory.
Byte, word, and long-word counts up to 32 bits can be transferred. All addresses and
transfer counters are 32 bits. Addresses increment or remain constant, as programmed.
The DMA channels support two external request modes, burst transfer and cycle steal.
Internal requests can be programmed to occupy 25, 50, 75, or 100 percent of the data bus
bandwidth. Interrupts can be programmed to postpone DMA completion.
The DMA module can sustain a transfer rate of 12.5 Mbytes/sec in dual-address mode
and nearly 50 Mbytes/sec in single-address mode @ 25.16 MHz (8.4 and 33.3 Mbytes/sec
@ 16.78 MHz, respectively). The DMA controller arbitrates with the CPU32 for the bus in
parallel with existing bus cycles and is fully synchronized with the CPU32, eliminating all
delays normally associated with bus arbitration by allowing DMA bus cycles to butt
seamlessly with CPU bus cycles.
1.3.3 Serial Module
Most digital systems use serial I/O to communicate with host computers, operator
terminals, or remote devices. The MC68340 contains a two-channel, full-duplex USART.
An on-chip baud rate generator provides standard baud rates up to 76.8k baud
independently to each channel's receiver and transmitter. The module is functionally
equivalent to the MC68681/MC2681 DUART.
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1-8 MC68340 USER’S MANUAL MOTOROLA
Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8
bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive
buffers and two-byte transmit buffers minimize CPU service calls. A wide variety of error
detection and maskable interrupt capability is provided on each channel. Full-duplex,
autoecho loopback, local loopback, and remote loopback modes can be selected.
Multidrop applications are supported.
A 3.6864-MHz crystal drives the baud rate generators. Each transmit and receive channel
can be programmed for a different baud rate, or an external 1× and 16× clock input can be
selected. Full modem support is provided with separate request-to-send (RTS) and clear-
to-send (CTS) signals for each channel. One channel also provides service request
signals. The two serial ports can sustain rates of 9.8 Mbps with a 25-MHz system clock in
1× mode, 612 kbps in 16× mode (6.5 Mbps and 410 kbps @ 16.78 MHz).
1.3.4 Timer Modules
Timers and counters are used in a system to monitor elapsed time, generate waveforms,
measure signals, keep time-of-day clocks, initiate DRAM refresh cycles, count events, and
provide “time slices” to ensure that no task dominates the activity of the processor. A
counter that counts clock pulses makes a timer, which is most useful when it causes
certain actions to occur in response to reaching desired counts.
The MC68340 has two, identical, versatile, on-chip counter/timers as well as a simple
timer in the SIM40. These general-purpose counter/timers can be used for precisely timed
events without the errors to which software-based counters and timers are susceptible
e.g., errors caused by dynamic memory refreshing, DMA cycle steals, and interrupt
servicing. The programmable timer operating modes are input capture, output compare,
square-wave generation, variable duty-cycle square-wave generation, variable-width
single-shot pulse generation, event counting, period measurement, and pulse-width
measurement.
Each timer consists of a 16-bit countdown counter with an 8-bit countdown prescaler for a
composite 24-bit resolution. The two timers can be externally cascaded for a maximum
count width of 48 bits. The counter/timer can be clocked by the internal system clock
generated by the SIM40 (÷2) or by an external clock input. Either the processor or external
stimuli can trigger the starting and stopping of the counter. When a counter reaches a
predetermined value, either an external output signal can be driven, or an interrupt can be
made to the CPU32. The finest resolution of the timer is 80 ns with a 25-MHz system
clock (125 ns @ 16.78 MHz).
1.4 POWER CONSUMPTION MANAGEMENT
The MC68340 is very power efficient due to its advanced 0.8-µ HCMOS process
technology and its static logic design. The resulting power consumption is typically
900 mW in full operation @ 25 MHz (650 mW @ 16.78 MHz)—far less than the
comparable discrete component implementation the MC68340 can replace. For
applications employing reduced voltage operation, selection of the MC68340V, which
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MOTOROLA MC68340 USER’S MANUAL 1-9
requires only a 3.3-V power supply, reduces current consumption by 40–60% in all modes
of operation (as well as reducing noise emissions).
The MC68340 has many additional methods of dynamically controlling power
consumption during operation. The frequency of operation can be lowered under software
control to reduce current consumption when performance is less critical. Idle internal
peripheral modules can be turned off to save power (5–10% each). Running a special low
power stop (LPSTOP) instruction shuts down the active circuits in the CPU and peripheral
modules, halting instruction execution. Power consumption in this standby mode is
reduced to about 350 µW. Processing and power consumption can be resumed by
resetting the part or by generating an interrupt with the SIM40's periodic interrupt timer.
1.5 PHYSICAL
The MC68340 is available as 0–16.78 MHz and 0–25.16 MHz, 0°C to +70°C and -40°C to
+85°C, and 5.0 V ±5% and 3.3 V ±0.3 supply voltages (reduced frequencies at 3.3 V).
Thirty-two power and ground leads minimize ground bounce and ensure proper isolation
of different sections of the chip, including the clock oscillator. A 144 pins are used for
signals and power. The MC68340 is available in a gull-wing ceramic quad flat pack
(CQFP) with 25.6-mil (0.001-in) lead spacing or a 15 × 15 plastic pin grid array (PPGA)
with 0.1-in pin spacing.
1.6 COMPACT DISC-INTERACTIVE
The MC68340 was designed to meet the needs of many markets, including compact disc-
interactive (CD-I). CD-I is an emerging standard for a publishing medium that will bring
multimedia to a broad general audience—the consumer. CD-I players combine television
and stereo systems as output devices, with interactive control using a TV remote-control-
like device to provide a multimedia experience selected from software “titles” contained in
compressed form on standard compact discs.
The highly integrated MC68340 is ideal as the central processor for CD-I players. It
provides the M68000 microprocessor code compatibility and DMA functions required by
the
CD-I Green Book
specification as well as many other useful on-chip functions for a
very cost-effective solution. The extra demands of full-motion video CD-I systems make
the best use of the MC68340 high performance. The MC68340 is CD-I compliant and has
been CD-I qualified. With its low voltage operation, the MC68340V is the only practical
choice for portable CD-I.
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1-10 MC68340 USER’S MANUAL MOTOROLA
1.7 MORE INFORMATION
The following table lists available documentation related to the MC68340:
Document Number Document Name
BR1114/D
M68300 Integrated Processor Family
MC68340/D
MC68340 Technical Summary
MC68340UM/AD
MC68340 User's Manual
M68000PM/AD
M68000 Family Programmer's Reference Manual
AN1063/D
DRAM Controller for the MC68340
AN453
Software Implementation of SPI on the MC68340
BR573/D
M68340 Evaluation System Product Brief
BR729/D
The 68K Source
BR1407/D
3.3 Volt Logic and Interface Circuits
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MOTOROLA MC68340 USER’S MANUAL 2-1
SECTION 2
SIGNAL DESCRIPTIONS
This section contains brief descriptions of the MC68340 input and output signals in their
functional groups as shown in Figure 2-1.
CPU32
CORE
TWO-CHANNEL
SERIAL
I/O
TWO-CHANNEL
DMA
CONTROLLER
TIMER
MODULE
IMB
RxDB
RxDA
TxDB
TxDA
CTSB
CTSA
SCLK
X2
X1
BKPT/DSCLK
FREEZE
IPIPE/DSO
IFETCH/DSI
DREQ2
DREQ1
DACK2
DACK1
DONE2
DONE1
TGATE1
TGATE2
TIN1
TIN2
TOUT1
TOUT2
PORT A
A31/PORT A7/IACK7
A30/PORT A6/IACK6
A29/PORT A5/IACK5
A28/PORT A4/IACK4
A27/PORT A3/IACK3
A26/PORT A2/IACK2
A25/PORT A1/IACK1
A24/PORT A0
PORT B
IRQ7/PORT B7
IRQ6/PORT B6
IRQ5/PORT B5
IRQ3/PORT B3
CS3/IRQ4/PORT B4
CS2/IRQ2/PORT B2
CS1/IRQ1/PORT B1
CS0/AVEC
MODCK/PORT B0
EXTAL
XTAL
CLKOUT
EXTERNAL
BUS
INTERFACE
BUS
ARBITRATION
CLOCK
SYSTEM
INTEGRATION
MODULE
TEST
TCK
TMS
TDI
TDO
A23–A0
FC3–FC0
D15–D0
RESET
BERR
HALT
AS
DS
R/W
SIZ1
SIZ0
DSACK1
DSACK0
BR
BG
BGACK
RMC
OUTPUT
PORT
TxRDYA/OP6
RxRDYA/FFULLA/OP4
RTSB/OP1
RTSA/OP0
TIMER
MODULE
XFC
Figure 2-1. Functional Signal Groups
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2-2 MC68340 USER’S MANUAL MOTOROLA
2.1 SIGNAL INDEX
The input and output signals for the MC68340 are listed in Table 2-1. The name,
mnemonic, and brief functional description are presented. For more detail on each signal,
refer to the signal paragraph. Guaranteed timing specifications for the signals listed in
Table 2-1 can be found in Section 11 Electrical Characteristics.
Table 2-1. Signal Index
Signal Name Mnemonic Function Input/
Output
Address Bus A23–A0 Lower 24 bits of the address bus Out
Address Bus/Port A7–A0/
Interrupt Acknowledge A31–A24 Upper eight bits of the address bus, parallel I/O port, or
interrupt acknowledge lines Out/I/O/Out
Data Bus D15–D0 The 16-bit data bus used to transfer byte or word data I/O
Function Codes FC3–FC0 Identify the processor state and the address space of the
current bus cycle Out
Chip Select 3–1/
Interrupt Request Level/
Port B4, B2, B1
CS3–CS1 Enables peripherals at programmed addresses, interrupt
priority level to the CPU32, or parallel I/O port Out/In/
I/O
Chip Select 0/Autovector CS0 Enables peripherals at programmed addresses or
requests an automatic vector Out/In
Bus Request BR Indicates that an external device requires bus mastership In
Bus Grant BG Indicates that current bus cycle is complete and the
MC68340 has relinquished the bus Out
Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus
mastership In
Data and Size
Acknowledge DSACK1,
DSACK0 Provides asynchronous data transfers and dynamic bus
sizing In
Read-Modify-Write Cycle RMC Identifies the bus cycle as part of an indivisible read-
modify-write operation Out
Address Strobe AS Indicates that a valid address is on the address bus Out
Data Strobe DS During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write
cycle, DS indicates that valid data is on the data bus.
Out
Size SIZ1, SIZ0 Indicates the number of bytes remaining to be transferred
for this cycle Out
Read/Write R/WIndicates the direction of data transfer on the bus Out
Interrupt Request Level/
Port B7, B6, B5, B3 IRQ7, IRQ6,
IRQ5, IRQ3 Provides an interrupt priority level to the CPU32 or
becomes a parallel I/O port In/I/O
Reset RESET System reset I/O
Halt HALT Suspends external bus activity I/O
Bus Error BERR Indicates an invalid bus operation is being attempted In
System Clock CLKOUT System clock out Out
Crystal Oscillator EXTAL, XTAL Connections for an external crystal or oscillator to the
internal oscillator circuit In, Out
External Filter Capacitor XFC Connection pin for an external capacitor to filter the circuit
of the phase-locked loop In
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