| FAIRCHILD eer pepe SEMICONDUCTOR CD4099BC 8-Bit Addressable Latch General Description The CD4089BC is an 8-bit addressable latch with three address inputs (AQ-A2), an active low enable input (E), active high clear input (CL), a data input (D), and eight out- puts (Q0-Q7). Data is entered into a particular bit in the latch when that bit is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH. When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong October 1987 Revised January 1999 address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). Features lf Wide supply voltage range: 3.0V to 15V M High noise immunity: 0.45 Vpp (typ.) HM Low power TTL: fan out of 2 driving 74L compatibility: or 1 driving 74LS Mf Serial to parallel capability lf Storage register capability lM Random (addressable) data entry Bf Active high demultiplexing capability Hi Common active high clear Ordering Code: Order Number | Package Number Package Description CD4099BCN N16E 16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Pin Assignments for DIP YL a7t 16 =Vpp C42 15F-06 D-43 14-95 E44 13;04 A075 12F-Q3 AIm76 1102 A247 10F-Q1 Veg] 8 9f-00 Top View Truth Table Mode Selection E|CL Addressed Unaddressed Mode Latch Latch L| L | Follows Data Holds Previous Data | Addressable Latch H]| L | Holds Previous Data} Holds Previous Data | Memory L| H | Follows Data Reset to 0 Demultiplexer H]| H | Reset to Oo Reset to Q Clear 1999 Fairchild Semiconductor Corporation DS005984. prf www.fairchildsemi.com yo}e] a/Gessoippy 1d-8 DA6607d09CD4099BC Logic Diagram www.fairchildsemi.com NoAbsolute Maximum Ratingsinote 1) (Note 2) DC Supply Voltage (Vpp) Input Voltage (Vin) Storage Temperature Range (Ts) Power Dissipation (Pp) Dual-In-Line Small Outline Lead Temperature (T_) (Soldering, 10 seconds) -0.5 to +18 Voc 0.5 to Vop +0.5 Voc 65C to +150C 700 mW 500 mW 260C DC Electrical Characteristics (note 2) Recommended Operating Conditions (note 2) DC Supply Voltage (Vpp) Input Voltage (Vin) Operating Temperature Range (Ta) Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of Recom- mended Operating Conditions and Electrical Characteristics provide con- ditions for actual device operation. Note 2: Vgg = OV unless otherwise specified. 3.0 to 15 Voc 0 to Vpp Voc 40C to +85C 40C 428C +88C Symbol Parameter Conditions . . . Units Min Max Min Typ | Max Min Max lbp Quiescent Device Vpp = 5V, Vin = Vpp or Vgs 20 0.02 20 150 pA Current Vpp = 10V, Vin =Vpp or Vgg 40 0.02 40 300 pA Vpp = 15V, Vin =Vpp or Vsg 80 0.02 80 600 pA VoL LOW Level llol < 1A Output Voltage Vpp =5V 0.05 0 0.05 0.05 v Vpp = 10V 0.05 0 0.05 0.05 Vv Vpp = 15V 0.05 0 0.05 0.05 Vv Vou HIGH Level llol < 1 pA Output Voltage Vpp =5V 4.95 4.95 5 4.95 Vv Vpp = 10V 9.95 9.95 10 9.95 Vv Vpp = 15V 14.95 14.95] 15 14.95 Vv Vit LOW Level Vpp = 5V, Vo = 0.5V or 4.5V 1.5 2.25 1.5 1.5 Vv Input Voltage Vpp = 10V, Vo = 1.0V or 9.0V 3.0 45 3.0 3.0 Vv Vpp = 15V, Vo = 1.5V or 13.5V 4.0 6.75 | 4.0 4.0 Vv Vin HIGH Level Vpp = 5V, Vo = 0.5V or 4.5V 3.5 3.5 2.75 3.5 Vv Input Voltage Vpp = 10V, Vo = 1.0V or 9.0V 7.0 7.0 5.5 7.0 Vv Vpp = 15V, Vo = 1.5V or 13.5V 11.0 11.0 | 8.25 11.0 Vv lot LOW Level Output Vpp = 8V, Vo = 0.4V 0.52 0.44 | 0.88 0.36 mA Current (Note 3) Vpp = 10V, Vo = 0.5V 1.3 14 2.25 0.9 mA Vpp = 15V, Vo = 1.5V 3.6 3.0 8.8 24 mA lou HIGH Level Output Vpp = 8V, Vo =4.6V 0.52 0.44 | -0.88 0.36 mA Current (Note 3) Vpp = 10V, Vo = 9.5V -1.3 1.1 | 2.25 -0.9 mA Vpp = 15V, Vo = 13.5V 3.6 -3.0 | -8.8 24 mA lin Input Current Vpp = 15V, Vin =OV 0.30 10 | -0.30 -1.0 pA Vpp = 15V, Vin = 15V 0.30 10-5 | 0.30 1.0 pA Note 3: Io}, and Ig, are tested one output at a time. www.fairchildsemi.com 98660709CD4099BC AC Electrical Characteristics (vote 4) Ta = 25C, C_ = 50 pF, R_ = 200k, Input t, = t; = 20 ns, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units teu tpLy Propagation Delay Vpp =5V 200 400 ns Data to Output Vpp = 10V 75 150 ns Vpp = 15V 50 100 ns teLy> tpHL Propagation Delay Vpp =5V 200 400 ns Enable to Output Vpp = 10V 80 160 ns Vpp = 15V 60 120 ns teu Propagation Delay Vpp =5V 175 350 ns Clear to Output Vpp = 10V 80 160 ns Vpp = 15V 65 130 ns troy tHe Propagation Delay Vpp =5V 225 450 ns Address to Output Vpp = 10V 100 200 ns Vpp = 15V 75 150 ns trup tty Transition Time Vpp =5V 100 200 ns (Any Output) Vpp = 10V 50 100 ns Vpp = 15V 40 80 ns Two Twe Minimum Data Vpp =5V 100 200 ns Pulse Width Vpp = 10V 50 100 ns Vpp = 15V 40 80 ns twep twe Minimum Address Vpp =5V 200 400 ns Pulse Width Vpp = 10V 100 200 ns Vpp = 15V 65 125 ns twu Minimum Clear Vpp =5V 75 150 ns Pulse Width Vpp = 10V 40 75 ns Vpp = 15V 25 50 ns tgy Minimum Set-Up Time Vpp =5V 40 80 ns Data to E Vpp = 10V 20 40 ns Vpp = 15V 15 30 ns ty Minimum Hold Time Vpp =5V 60 120 ns Data to E Vpp = 10V 30 60 ns Vpp = 15V 25 50 ns tgy Minimum Set-Up Time Vpp =5V 15 50 ns Address to E Vpp = 10V 0 30 ns Vpp = 15V 0 20 ns ty Minimum Hold Time Vpp =5V 50 15 ns Address to E Vpp = 10V 20 10 ns Vpp = 15V 15 5 ns Cpp Power Dissipation Capacitance Per Package 100 pF (Note 5) Cin Input Capacitance Any Input 5.0 75 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Dynamic power dissipation (Pp) is given by: Pp = (Cpp + CL) Vec*t + Pq; where C, =load capacitance; f = frequency of operation; for further details, see application note AN-90, 54C/74C Family Characteristics. www.fairchildsemi.comSwitching Time Waveforms m twi >| DATA CLEAR t www.fairchildsemi.com 98660709CD4099BC 8-Bit Addressable Latch Physical DimensiONs inches (millimeters) un 0.740 = 0.780 (18.80 = 19.81) PIN NO. 1 less otherwise noted |_,_ 0.090 (2.286) INDEX | AREA 0.250 #0.010 (6.350 0.254) + PIN NO. 1 IDENT IDENT OPTION 01 OPTION 02 0.068 0.130 #0.005 0.130 #0.005_ 0.060 4 TYP 0,300 - 0.320 71.651) y _ G30280.127) >| Fr asa MP "\ > optionaL 7 (7-620-8.128) |" { 0.145 = 0.200 | (3.683- 5.080) } 4 0.020 jy _| (0.508) 0.125 - 0.150 (3.175 = 3.810) 0.014 = 0.023 (0.356 = 0.584) TYP ql . 0,050 +0.010 (1.270 0.254) TYP F 95 #5 0.008- 0.016 90 4 TYP 0.008= 0.016 0.280 =| (0.203 = 0.406) Mt 0.03040.015 (7.112) 1 (0.762 40.381) MIN 0.100 0.010 +0.040 (2.540 0.254) (0.325 "9.015 NiSE (REV F +1.016 (8.255 75355) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild coes not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairctild reserves the right at any time without notice to change said circuitry and spedifications.