This is information on a product in full production.
January 2018 DocID024492 Rev 7 1/75
SPC570S40E1, SPC570S40E3,
SPC570S50E1, SPC570S50E3
32-bit Power Architecture® microcontroller for automotive ASILD
applications
Datasheet - production data
Features
•AEC-Q100 qua lifie d
•High performance e200z0h dual core
– 32-bit Power Architecture technology CPU
– Core frequency as high as 80 MHz
– Single issue 4-stage pipeline in-order
execution core
– Variable Length Encodi ng (VLE)
•Up to 544 KB (512 KB code + 32 KB data,
suitable for EEPROM emulation) on-chip flash
memory: supports read during program and
erase operations, and multiple blo cks allowing
EEPROM emulation
•Up to 48 KB on-chip general-purpose SRAM
•Multi-channel direct memory access controller
(eDMA paired in lockstep) with 16 channels
•Comprehensive ne w ge ne r ation ASILD sa fe ty
concept
– Safety of bus masters (core+INTC, DMA)
by delayed locks te p ap pr oa ch
– Safety of storage (Flash, SRAM) by mainly
ECC
– Safety of the data path to storage and
periphery by mainly End-to-End EDC (E2E
EDC)
– Clock and power, generation and
distribution, supervised by dedicated
monitors
– Fault Collection and Control Unit (FCCU)
for collection and reaction to failure
notifications
– Memory Error Management Unit (MEMU)
for collection and re p or tin g of er ro r ev en ts
in memories
– Boot time MBIST and LBIST for latent
faults
– Check of safety mechanisms availability
and error reaction path functionality by
dedicated mechanisms
– Safety of the per iph er y by ap p licat ion -le ve l
measures supported by replicated
peripheral bridges and by LBIST
– Further measures on ded icated peripherals
(e.g. ADC supervisor)
– Junction temperature sensor
– 8-region system memory protection unit
(SMPU) with process ID support (tasks
isolation)
– Enhanced SW watchdog
– Cyclic redundancy check (CRC) unit
•Dual phase-locked loops with stable clock
domain for peripherals and FM modulation
domain for computational shell
•Nexus Class 3 debug and trace interface
•Communication interfaces
– 2 LINFlexD modules, 3 deserial serial
peripheral interface (DSPI) modules, and
Up to 2 FlexCAN interfaces with 32
message buffers each
•On-chip CAN/UART Bootstrap loader with Boot
Assisted Flash (BAF). Physical Interface (PHY)
can be
– UART and CAN
•2 enhanced 12-bit SAR analog converter s
– 1.5 µs conversion time (12 MHz)
– 16 physical channels (fully shared between
the 2 SARADC units)
– Supervisor ADC concept
– Programmable Cr oss Triggering Unit (CTU)
•Single 3.3 V or 5 V voltage supply
•4 general purpose eTimer units (6 channels
each)
•Junction temperature range -40 °C to 150 °C
(165 °C grade optional)
eTQFP64 (10 x 10 x 1.0 mm)
eTQFP100 (14 x 14 x 1.0 mm)
www.st.com
Contents SPC570S40Ex, SPC570S50Ex
2/75 DocID024492 Rev 7
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Package pads/pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Electromagnetic compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.8 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.9 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.9.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.9.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.9.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.10 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.11 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 41
4.11.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 41
4.12 PMU monitor specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.12.1 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DocID024492 Rev 7 3/75
SPC570S40Ex, SPC570S50Ex Contents
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4.12.2 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.13 Platform Flash controller electrical characteristics . . . . . . . . . . . . . . . . . . 43
4.14 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.15 PLL0/PLL1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.16 External oscillator (XOSC) electrical characteristics . . . . . . . . . . . . . . . . 47
4.17 Internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . 50
4.18 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.18.2 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.19 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.20 JTAG interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.21 DSPI CMOS master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.21.1 Classic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.21.2 Modified timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1 eTQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2 eTQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
List of tables SPC570S40Ex, SPC570S50Ex
4/75 DocID024492 Rev 7
List of tables
Table 1. SPC570Sx device feature
summary (Family Superset Configuration)6
Table 2. SPC570S40Ex, SPC570S50Ex device configuration differences . . . . . . . . . . . . . . . . . . . . 8
Table 3. SPC570Sx series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. eTQFP64 and eTQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Radiated emissions testing specification,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Device operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Thermal chara c teristics for eTQFP64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Thermal char a cte ris tics fo r eT QF P100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. I/O pad specification descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. I/O input DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Weak configuration I/O output characteristics, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. Medium configuration I/O output characteristics, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. Strong configuration I/O output characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. Very Strong configuration I/O output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. I/O output characteristics for pads 4, 9, 11, 55, 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 23. Trimmed (PVT) values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. RWSC settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 25. Flash memory program and erase specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 26. Flash memory Life Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27. PLL1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28. PLL0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. External Oscillator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30. Selectable load capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. Internal RC oscillator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 32. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 33. ADC pin specification,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 34. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 35. Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 36. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 37. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0 . . . . . . . . . . 57
Table 38. DSPI CMOS master modified timing (full duplex and output only) –
MTFE = 160
Table 39. eTQFP64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 40. eTQFP100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 41. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DocID024492 Rev 7 5/75
SPC570S40Ex, SPC570S50Ex List of figures
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List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. eTQFP 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. eTQFP 100-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7. Recommended parasitics on board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. Crystal/Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 9. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 10. ADC characteristic and error definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 11. Input equivalent circuit (12- bit SAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 12. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 13. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 14. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 15. DSPI CMOS master mode – classic timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16. DSPI CMOS master mode – classic timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18. DSPI CMOS master mode – modified timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 19. DSPI CMOS master mode – modified timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 20. DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 21. eTQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 22. eTQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Introduction SPC570S40Ex, SPC570S50Ex
6/75 DocID024492 Rev 7
1 Introduction
1.1 Document overview
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device. To
ensure a complete under standing of the device functionality, refer also to the device
reference manual and errata sheet.
1.2 Description
The SPC570Sx is a family of next generation microcontrollers built on the Power
Architecture embedded category.
The SPC570Sx family of 32-bit microcontrollers is the latest achievement in integrated
automotive application controllers. It belongs to an expanding family of automotive-focused
products designed to address the next wave of Chassis and Safety electronics applications
within the vehicle. The advanced and cost-efficient host processor core of this automotive
controller family complies with the Power Architecture embedded category and only
implements the VLE (variable-leng th encoding) APU, providing improved code density. It
operates at speeds of up to 80 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current
Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users implementations.
Table 1. SPC570Sx device feature
summary (Family Superset Configuration)
Feature Description
Process 55 nm
Main processor
Core e200z0h
Number of main cores 1
Number of checker cores 1
VLE Yes
Main processor frequency 80 MHz(1)
Interrupt controllers (including interrupt controller checker) 1
Software watchdog timer 1
System timers 1 AUTOSAR ® STM
1 PIT with four 32-bit channels
DMA (including DMA checker) 1
DMA channels 16
SMPU Yes (8 regions)(2)
System SRAM Up to 48 KB
Code flash memory Up to 512 KB
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Data flash memory (suitable for EEPROM emulation) 32 KB
UTEST flash memory 8 KB
Boot assist flash (BAF) 8 KB
CRC 1
LINFlexD Up to 2
FlexCAN Up to 2
DSPI 3
eTimer 4 x 6 channels
ADC (SAR) 2(3)
CTU (Cross Triggering Unit) 1
Te mperature sensor 1
Self-test control unit (memory and logic BIST) 1
FCCU 1
MEMU 1
PLL Dual PLL with FM
Nexus 3(4)
Sequence processing unit (SPU) 1
External power supplies 5V
(5)
3.3 V(5)
Junction temp erature −40 to 150 °C
165 °C grade optional (6)
Packages Device SPC570SxxE3 eTQFP100
Device SPC570SxxE1 eTQFP64
1. Includes user programmable CPU core and one safety core. The two e200z0h processors in the lockstep
pair run at 80 MHz. The e200z0h is compatible with the Power Architecture embedded specification.
2. SMPU with process ID support extension
3. One ADC can be used as supervisor ADC
4. Including trace for the crossbar masters (data & instruction trace on core and data trace on eDMA). 4 MDO
pin Nexus trace port.
5. All I/Os can be supplied at 3.3 V or 5 V (mutually exclusive)
6. Refer to technical note "SPC570S family - High Temperature "D" Grade (DocID031416 - TN1262)" for
associated specification limitation.
Table 1. SPC570Sx device feature
summary (Family Superset Configuration) (continued)
Feature Description
Introduction SPC570S40Ex, SPC570S50Ex
8/75 DocID024492 Rev 7
Table 2. SPC570S40Ex, SPC570S50Ex device configuration dif ferences
SPC570S40
(full option configuration) SPC570S50
(full option configuration)
Flash 256 KB(1) 512 KB
RAM 32 KB(2) 48 KB
CAN 1(3) 2
Others aligned to the SPC570Sx device feature summary (Family Superset Configuration) described in Table 1
1. Flash blocks excluded on SPC570S40:
128K Block 0 [0x0100_0000 … 0x0101_FFFF]
128K Block 1 [0x0102_0000 … 0x0103_FFFF]
2. SRAM area excluded on SPC570S40
[0x4000_8000…0x4000_BFFF]
3. FlexCAN1 excluded on SPC570S40
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SPC570S40Ex, SPC570S50Ex Introduction
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1.3 Feature overview
On-chip modules within the SPC570Sx include the following features:
•2 main CPUs, single-issue, 32-bit CPU core complexes (e200z0h), running in lockstep
– Power Architecture embedded sp ecification compliance
– Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
•Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip
flash memory: support s read during prog ram and erase operatio ns, and multiple blocks
allowing EEPROM emulation
•Up to 48 KB on-chip general-purpose SRAM
•Multi-channel direct memory access controller (eDMA paired in lockstep)
– 16 channels per eDMA
•Interrupt controller (INTC) with dedicate d in terr up t sour ce channe ls, in cluding so ftware
interrupts and 32 priority levels
•Dual phase-locked loops with stable clock domain for peripherals and frequency
modulation domain for computation al shell
•Crossbar switch architecture for concurrent access to peripherals, flash memory, or
SRAM from multiple bus masters with end-to-end ECC
•System integration unit lite (SIUL2)
•Boot Assist Flash (BAF) supports factory programming using serial bootload through
‘UART Serial Boot Mode Protocol’. Physical Interface (PHY) can be
–UART / LIN
–CAN
•Enhanced analog-to-digital converter system
– 2 separate 12-bit SAR analog converters
– 1.5 µs conversion time (at 12 MHz)
– 16 physical channels
•Temperature sensor
– Range −40 to +150 °C
– Sen sitiv ity ap pr oximately 5.14 mV/°C
•STCU2
– Support for Logic BIST and Memory BIST at power on
–ASIL D
•3 deserial serial peripheral interface (DSPI) modules
•2 LIN and UART commun ication interface (LINFlexD) modules
– LINFlexD_0 (master/slave)
– LINFlexD_1 (master)
•Up to 2 FlexCAN modules
•Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with partial
support for 2010 standard
•Device and board test support per Joint Te st Action Group (JTAG) (IEEE 1149.1)
•On-chip voltage re gulator controller manages th e supply voltage down to 1.2 V for core
logic
Block diagram SPC570S40Ex, SPC570S50Ex
10/75 DocID024492 Rev 7
2 Block diagram
Figure 1 shows the top-level block diagram.
Figure 1. Block diagram
Nexus3
Nexus 2+
Power PC
e200z0h
RCCU
INTC RCCU
Nexus 2+
Power PC
e200z0h
(lockstep)
e2eEDC
DMACHMUX
DMA
(lockstep)
DMA RCCU
XBAR
PBRIDGE_1 PBRIDGE_0
RAM
controller Flash controller
RAM
eTimer_2
eTimer_3
DSPI_2
JDC
CMU_1
CMU_2
FlexCAN_1 CMU_3
Flash
XBAR SMPU XBIC SRAM PFLASHC INTC_0
SWT STM DMA_0 eTimer_0 eTimer_1 CTU
SARADC_0 SARADC_B
DSPI_0 DSPI_1
FlexCAN_0 STCU JTAGM
MEMU CRC
DMA PIT MC_PCU
PMCDIG
MC_RGM
IRCOSC_DIG XOSC_DIGPLL_DIG_0 CMU_0
MC_CGM
MC_ME
SIUL
CFLASH_INF
SSCM
JTAGM JTAGC DCI SPU
e2eEDC
RCCU
XBIC
e2eEDC
AIC1 AIC0
LINFlexD_0
LINFlexD_1
CHMUX_0
DMACHMUX
(lockstep)
INTC
(lockstep)
RCCU
FCCU
WKPU
DocID024492 Rev 7 11/75
SPC570S40Ex, SPC570S50Ex Block diagram
74
Table 3 summarizes the functions of all blocks present in the SPC570Sx se ries of
microcontrollers. Please note that the presence and number of bl ocks vary by device and
package.
Table 3. SPC570Sx series block summary
Block Function
e200z0 CPU Allows single clock instruction execution
Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to-digital converter
Cross triggering unit (CTU) Enables synchroniza tion of ADC conversions with a timer event from the
eMIOS or from the PIT
Deserial serial peripheral
interface (DSPI) Provides a synchronous serial interface for communicati on with external
devices
Enhanced Direct Memory Access
(eDMA) Performs complex data transfers with minimal intervention from a host
processor via 16 programmable channels.
DMACHMUX Allows to route a defined number of DMA peripheral sources to the DMA
channels
Flash memory Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area
network) Supports the standard CAN communications protocol
PLL0 Output independent of core clock frequen cy
Frequency-modulated phase-
locked loop (PLL1) Generates high-speed system clocks and supports programmable frequency
modulation
Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requ ests
AIPS System bus to peripheral bus interface
RAM controller Acts as an interface between the system bus and the integrated system RAM
System RAM Supports read/write accesses mapped to the SRAM memory from any master
Flash memory controller Acts as an interface between the system bus and the Flash memory module
Flash memory Up to 512 KB of programmable, non-volatile Flash memory for code and 32 KB
for data
IRCOSC Controls the internal 16 MHz RC oscillator system
XOSC Controls the on-chip oscillator (XOSC) and provides the register interface for
the programmable features
JTAG Master Provides software the option to write data for driving JTAG
JTAG Data Communication
Module Provides the capability to move register data between the IPS and JTAG
domains
PASS Programs a set of Flash memo ry access protections, based on user
programmable passwords
Sequence Processing Unit Provides an on-device trigger functions similar to those found on a logic
analyzer
LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Block diagram SPC570S40Ex, SPC570S50Ex
12/75 DocID024492 Rev 7
Clock generation module
(MC_CGM) Provides logic and control required for the generation of system and peripheral
clocks
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
MC_PMC Contains registers that enable/disable the various voltage monitors
Reset generation module
(MC_RGM) Centralizes reset sources and manages the device reset sequence of the
device
Memory protection unit (MPU) Provides hardware access control for all memory references gen erated in a
device
eTimer Has six 16-bit general purpose counter, where each counter can be used as
input capture or output compare functio n
FCCU Collects fault event notification from the rest of the system and translates them
into internal and/or external system reactions
RCCU Compares input signals and issues an alarm in the case of a mismatch
MEMU Collects and reports error events associated with ECC (Error Correction Code)
logic used on SRAM, DMA RAM and Flash memory
XBIC Ve rifies the integrity of the attribute information for crossbar transfers and
signals the Fault Collection and Control Unit (FCCU) when an error is detected
STCU2 Handles the BIST procedure
CRC Controls the computation of CRC, off-loading this work from the CPU
RegProt Protects several registers against accidental writing, locking their value till the
next reset phase
Temperature sensor Monitors the device temperature
Debug Control Interface Provides debug features for the MCU
Nexus Port Controller Monitor a variety of signals including addresses, data, control signals, status
signals, etc.
Nexus Multimaster Trace Client Monitors the system bus and provides real-time trace information to debug or
development tools
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
System integration unit (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status configuration
module (SSCM)
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
System timer module (STM) Provides a set of output compare events to support AUTOSAR and operating
system tasks
System watchdog timer (SWT) Provides protection from runaway code
Table 3. SPC570Sx series block summary (continued)
Block Function
DocID024492 Rev 7 13/75
SPC570S40Ex, SPC570S50Ex Block diagram
74
Wakeup unit (WKPU) The wakeup unit supports up to 18 external sources that can generate
interrupts or wakeup events, of which 1 can cause non-maskable interrupt
requests or wakeup events.
Crossbar (XBAR) switch Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Table 3. SPC570Sx series block summary (continued)
Block Function
Package pinouts and signal descript ions SPC570S40Ex, SPC570S50Ex
14/75 DocID024492 Rev 7
3 Package pinouts and signal descriptions
3.1 Package pinouts
The available eTQFP pinouts are provided in the following figures. For pin signal
descriptions, please refer to the device reference manual.
Figure 2. eTQFP 64-pin configuration(a)
a. All eTQFP64 information is indicative and must be confirmed dur ing silicon validation.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
FCCU_F0
PA[0]
PA[3]
PA[4]
PA[7]
PA[8]
PA[9]
PA[11]
PA[12]
PA[13]
PA[14]
VDD_LV
VDD_HV_IO
PB[3]
PB[4]
PB[5]
PD[8]
PD[7]
VDD_HV_IO
VDD_LV
PORST
TESTMODE
TCK
PC[15]
TDO
TMS
TDI
VDD_HV_OSC_PMC
XTAL
EXTAL
VDD_LV
VDD_HV_IO
PB[6]
PB[7]
VREFH_ADC
PB[10]
PB[11]
PB[14]
PB[15]
PC[1]
VDD_HV_ADC_TSENS
PC[2]
PC[3]
PC[4]
PC[7]
PC[8]
PC[11]
FCCU_F1
PE[15]
PE[14]
PE[11]
VDD_HV_IO
PE[8]
PE[7]
PE[6]
PE[5]
PE[3]
PE[2]
VDD_HV_IO
PD[15]
PD[14]
PD[11]
PD[10]
PD[9]
eTQFP6 4 Top view
Note:
Availab ility of port pin alternate functions depends on product selection.
DocID024492 Rev 7 15/75
SPC570S40Ex, SPC570S50Ex Package pinouts and signal descriptions
74
Figure 3. eTQFP 100-pin config uration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
FCCU_F0
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
PA[7]
PA[8]
PA[9]
PA[10]
PA[11]
PA[12]
PA[13]
PA[14]
PA[15]
PB[0]
VDD_LV
VDD_HV_IO
PB[1]
PB[2]
PB[3]
PB[4]
PB[5]
PD[8]
PD[7]
PD[6]
PD[5]
PD[4]
PD[3]
PD[2]
VDD_LV
PD[1]
PORST
PD[0]
TESTMODE
TCK
PC[15]
TDO
TMS
TDI
PC[14]
PC[13]
PC[12]
VDD_HV_OSC_PMC
XTAL
EXTAL
VDD_LV
VDD_HV_IO
PB[6]
PB[7]
PB[8]
VREFH_ADC
PB[9]
PB[10]
PB[11]
PB[12]
PB[13]
PB[14]
PB[15]
PC[0]
PC[1]
VDD_HV_ADC_TSENS
PC[2]
PC[3]
PC[4]
PC[5]
PC[6]
PC[7]
PC[8]
PC[9]
PC[10]
PC[11]
FCCU_F1
PE[15]
PE[14]
PE[13]
PE[12]
PE[11]
VDD_HV_IO
PE[10]
PE[9]
PE[8]
PE[7]
PE[6]
PE[5]
PE[4]
PE[3]
PE[2]
VDD_HV_IO
PE[1]
PE[0]
PD[15]
PD[14]
PD[13]
PD[12]
PD[11]
PD[10]
PD[9]
eTQFP100
Note:
Availab ility of port pin alternate functions depends on product selection.
Top view
Package pinouts and signal descript ions SPC570S40Ex, SPC570S50Ex
16/75 DocID024492 Rev 7
3.2 Pin descriptions
The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC570Sx devices.
For information on the signal descriptions and related info rmation about the functionality and
configuration of the SPC570Sx devices, refer to the "Signal description” chapter in the
devices’ refere nc e ma n ua l .
3.3 Package pads/pins
Table 4 shows the eTQFP64 and eTQFP100 pi nouts. The default reset st a te fo r all the pins
associated with a programmable alternate function is GPIO.
Note: Nexus pins can be enabled via JTAG during the reset phase
Table 4. eTQFP64 and eTQFP100 pinout
Pin No. Alternate functio ns
Port
pin Pad
eTQFP64
eTQFP100
Type AF1 AF2 AF3 AF4
— FCCU_F0 1 1 IO FCCU_F0(1)
PA[0] PAD[0] 2 2 IO DSPI 0 -
CS 0 Ext. INT 0 DSPI 1 -
CS 1 Timer 0 -
ch. 0
PA[1] PAD[1] — 3 IO DSPI 1 -
CS 1 Timer 0 -
ch. 0 Nexus
EVTI Timer 1 -
ch. 0
PA[2] PAD[2] — 4 IO DSPI 2 -
CS 1 DSPI 0 -
CS 4 Nexus
EVTO Timer 1 -
ch. 1
PA[3] PAD[3] 3 5 IO DSPI 0 -
CLK Ext. INT 1 Timer 0 -
ch. 0 DSPI 1 -
CLK
PA[4] PAD[4] 4 6 IO DSPI 0 -
Serial Data NMI Timer 0 -
ch. 1 DSPI 1 -
Serial Data
PA[5] PAD[5] — 7 IO LINFlex 1 -
TX Timer 0 -
ch. 1 Nexus
MCK 0 Timer 1 -
ch. 2
PA[6] PAD[6] — 8 IO LINFlex 1 -
RX Timer 0 -
ch. 2 Nexus
MDO 0 Timer 1 -
ch. 3
PA[7] PAD[7] 5 9 IO DSPI 0 -
Serial Data —Timer 0 -
ch. 2 DSPI 1 -
Serial Data
PA[8] PAD[8] 6 10 IO DSPI 0 -
CS 1 DSPI 2 -
CS 0 LINFlex 1 -
TX Timer 0 -
ch. 1
PA[9] PAD[9] 7 11 IO DSPI 0 -
CS 2 DSPI 0 -
CS 7 LINFlex 1 -
RX Timer 0 -
ch. 2
PA[10] PAD[10] — 12 IO — DSPI 1 -
CS 1 Nexus
MDO 1 Ext. INT 3
DocID024492 Rev 7 17/75
SPC570S40Ex, SPC570S50Ex Package pinouts and signal descriptions
74
PA[11] PAD[11] 8 13 IO DSPI 0 -
CS 3 DSPI 0 -
CS 5 Timer 0 -
ch. 3 Ext. INT 4
PA[12] PAD[12] 9 14 IO LINFlex 0 -
RX FlexCAN 1 -
RX LINFlex 1 -
RX Timer 0 -
ch. 3
PA[13] PAD[13] 10 15 IO LINFlex 0 -
TX FlexCAN 1 -
TX LINFlex 1 -
TX Timer 0 -
ch. 4
PA[14] PAD[14] 11 16 IO Timer 0 -
ch. 4 DSPI 1 -
CS 1 Ext. INT 3 Timer 0 -
ch. 5
PA[15] PAD[15] — 17 IO FlexCAN 1 -
RX Timer 1 -
ch. 0 Nexus
MDO 2 Timer 1 -
ch. 4
PB[0] PAD[16] — 18 IO FlexCAN 1 -
TX Timer 1 -
ch. 1 Nexus
MDO 3 Timer 1 -
ch. 5
— VDD_LV 12 19 PW —
— VDD_HV_IO 13 20 PWB20 —
PB[1] PAD[17] — 21 IO Timer 1 -
ch. 5 DSPI 0 -
CS 6 Nexus
MSEO 0 DSPI 1 -
CS 0
PB[2] PAD[18] — 22 IN/ANA Timer 0 -
ch. 4 ADC ch. 15 Ext. INT 3 FlexCAN 0 -
RX
PB[3] PAD[19] 14 23 IN/ANA Timer 0 -
ch. 0 ADC ch. 9 Timer 1 -
ch. 0 DSPI 0 -
Serial Data
PB[4] PAD[20] 15 24 IN/ANA Timer 0 -
ch. 1 ADC ch. 8 Timer 1 -
ch. 1 DSPI 1 -
Serial Data
PB[5] PAD[21] 16 25 IN/ANA Timer 0 -
ch. 2 ADC ch. 7 Timer 1 -
ch. 2 DSPI 2 -
Serial Data
PB[6] PAD[22] 17 26 IN/ANA Timer 0 -
ch. 3 ADC ch. 6 Timer 1 -
ch. 3 —
PB[7] PAD[23] 18 27 IN/ANA Ext. INT 0 ADC ch. 5 Timer 0 -
ch. 4 Timer 1 -
ch. 4
PB[8] PAD[24] — 28 IN/ANA Timer 0 -
ch. 5 ADC ch.14 Ext. INT 4 FlexCAN 1 -
RX
— VREFH_ADC 19 29 REF —
PB[9] PAD[25] — 30 IN/ANA Timer 2 -
ch. 3 ADC ch. 13 Ext. INT 5 LINFlex 0 -
RX
PB[10] PAD[26] 20 31 IN/ANA Ext. INT 1 ADC ch. 4 Timer 0 -
ch. 5 Timer 1 -
ch. 5
PB[11] PAD[27] 21 32 IN/ANA Ext. INT 2 ADC ch. 3 Timer 1 -
ch. 4 Timer 0 -
ch. 4
Table 4. eTQFP64 and eTQFP100 pinout (continued)
Pin No. Alternate functio ns
Port
pin Pad
eTQFP64
eTQFP100
Type AF1 AF2 AF3 AF4
Package pinouts and signal descript ions SPC570S40Ex, SPC570S50Ex
18/75 DocID024492 Rev 7
PB[12] PAD[28] — 33 IN/ANA Timer 2 -
ch. 4 ADC ch. 12 Timer 1 -
ch. 5 LINFlex 1 -
RX
PB[13] PAD[29] — 34 IN/ANA Timer 2 -
ch. 5 ADC ch. 11 Timer 3 -
ch. 0 NMI
PB[14] PAD[30] 22 35 IN/ANA Timer 2 -
ch. 0 ADC ch. 2 Timer 3 -
ch. 1 Timer 2 -
ch. 1
PB[15] PAD[31] 23 36 IN/ANA Timer 2 -
ch. 1 ADC ch. 1 Timer 3 -
ch. 2 Timer 2 -
ch. 2
PC[0] PAD[32] — 37 IN/ANA Timer 1 -
ch. 0 ADC ch. 10 Timer 3 -
ch. 3 Ext. INT 0
PC[1] PAD[33] 24 38 IN/ANA Timer 2 -
ch. 2 ADC ch. 0 Timer 3 -
ch. 4 Timer 2 -
ch. 4
— VDD_HV_ADC_TSENS 25 39 PW —
PC[2] PAD[34] 26 40 IO Timer 0 -
ch. 5 DSPI 2 -
CS 1 FlexCAN 1 -
RX FlexCAN 0 -
RX
PC[3] PAD[35] 27 41 IO Timer 1 -
ch. 0 DSPI 2 -
CS 2 FlexCAN 1 -
TX FlexCAN 0 -
TX
PC[4] PAD[36] 28 42 IO Timer 1 -
ch. 1 DSPI 1 -
CS 0 Ext. INT 1 FlexCAN 1 -
RX
PC[5] PAD[37] — 43 IO DSPI 1 -
CS 0 Timer 1 -
ch. 2 Nexus RDY FlexCAN 1 -
TX
PC[6] PAD[38] — 44 IO DSPI 1 -
Serial Data Timer 1 -
ch. 3 DSPI 2 -
CS 4 DSPI 0 -
Serial Data
PC[7] PAD[39] 29 45 IO Timer 1 -
ch. 2 DSPI 1 -
Serial Data DSPI 2 -
CS 5 DSPI 0 -
CS 0
PC[8] PAD[40] 30 46 IO Timer 1 -
ch. 3 DSPI 1 -
Serial Data DSPI 2 -
CS 6 DSPI 0 -
CS 1
PC[9] PAD[41] — 47 IO DSPI 1 -
Serial Data Timer 1 -
ch. 4 DSPI 2 -
CS 7 DSPI 0 -
Serial Data
PC[10] PAD[42] — 48 IO DSPI 1 -
CLK Timer 1 -
ch. 5 —DSPI 0 -
CLK
PC[11] PAD[43] 31 49 IO Timer 1 -
ch. 4 DSPI 1 -
CLK —DSPI 0 -
CS 2
— FCCU_F1 32 50 IO FCCU_F1
— VDD_HV_IO 33 51 PWB51 —
— VDD_LV 34 52 PW —
— EXTAL 35 53 ANA —
Table 4. eTQFP64 and eTQFP100 pinout (continued)
Pin No. Alternate functio ns
Port
pin Pad
eTQFP64
eTQFP100
Type AF1 AF2 AF3 AF4
DocID024492 Rev 7 19/75
SPC570S40Ex, SPC570S50Ex Package pinouts and signal descriptions
74
—XTAL3654ANA —
— VDD_HV_OSC_PMC 37 55 PW —
PC[12] PAD[44] — 56 IO Timer 0 -
ch. 0 DSPI 1 -
CS 3 —LINFlex 0 -
RX
PC[13] PAD[45] — 57 IO Timer 0 -
ch. 1 DSPI 1 -
CS 4 —LINFlex 0 -
TX
PC[14] PAD[46] — 58 IO Timer 0 -
ch. 2 DSPI 1 -
CS 5 —DSPI 0 -
CS 3
—TDI3859IO —
—TMS3960IO —
—TDO4061IO —
PC[15] PAD[47] 41 62 IO NMI DSPI 1 -
CS 2 Ext. INT 4 Timer 2 -
ch. 0
—TCK4263IO —
— TESTMODE 43 64 IO —
PD[0] PAD[48] — 65 IO DSPI 1 -
CS 6 Ext. INT 0 — Timer 2 -
ch. 1
—PORST4466IO —
PD[1] PAD[49] — 67 IO Timer 0 -
ch. 3 DSPI 1 -
CS 7 —DSPI 0 -
CS 4
— VDD_LV 45 68 PW —
PD[2] PAD[50] — 69 IO Timer 2 -
ch. 0 DSPI 2 -
CS 1 DSPI 1 -
CS 6 Timer 3 -
ch. 0
PD[3] PAD[51] — 70 IO Timer 2 -
ch. 1 DSPI 2 -
CS 2 DSPI 1 -
CS 4 Timer 3 -
ch. 1
PD[4] PAD[52] — 71 IO Timer 2 -
ch. 2 DSPI 2 -
CS 3 DSPI 1 -
CS 7 Timer 3 -
ch. 2
— VDD_HV_IO 46 — PWB51 —
PD[5] PAD[53] — 72 IO DSPI 2 -
CS 0 Timer 2 -
ch. 1 DSPI 1 -
CS 6 Timer 3 -
ch. 3
PD[6] PAD[54] — 73 IO DSPI 2 -
Serial Data Timer 2 -
ch. 2 DSPI 1 -
CS 5 DSPI 0 -
CS 5
PD[7] PAD[55] 47 74 IO Timer 3 -
ch. 0 CTU
trg_inp DSPI 1 -
CS 2 LINFlex 1 -
RX
PD[8] PAD[56] 48 75 IO Timer 3 -
ch. 1 CTU
trg_outp DSPI 1 -
CS 6 LINFlex 1 -
TX
Table 4. eTQFP64 and eTQFP100 pinout (continued)
Pin No. Alternate functio ns
Port
pin Pad
eTQFP64
eTQFP100
Type AF1 AF2 AF3 AF4
Package pinouts and signal descript ions SPC570S40Ex, SPC570S50Ex
20/75 DocID024492 Rev 7
PD[9] PAD[57] 49 76 IO FlexCAN 0 -
RX DSPI 2 -
CS 1 FlexCAN 1 -
RX Timer 2 -
ch. 2
PD[10] PAD[58] 50 77 IO FlexCAN 0 -
TX —FlexCAN 1 -
TX Timer 2 -
ch. 3
PD[11] PAD[59] 51 78 IO Timer 3 -
ch. 2 DSPI 2 -
CLK DSPI 1 -
CS 7 —
PD[12] PAD[60] — 79 IO DSPI 2 -
Serial Data Timer 2 -
ch. 3 DSPI 2 -
CS 2 —
PD[13] PAD[61] — 80 IO DSPI 2 -
CLK Timer 2 -
ch. 4 DSPI 2 -
CS 3 —
PD[14] PAD[62] 52 81 IO Timer 2 -
ch. 3 DSPI 2 -
Serial Data Timer 3 -
ch. 3 —
PD[15] PAD[63] 53 82 IO Timer 2 -
ch. 4 DSPI 2 -
Serial Data Timer 3 -
ch. 4 —
PE[0] PAD[64] — 83 IO Timer 3 -
ch. 3 Ext. INT 2 — Timer 2 -
ch. 4
PE[1] PAD[65] — 84 IO Timer 3 -
ch. 4 ——
Timer 2 -
ch. 5
— VDD_HV_IO 54 85 PWB85 —
PE[2] PAD[66] 55 86 IO Timer 2 -
ch. 5 DSPI 2 -
CS 0 DSPI 0 -
CS 3 —
PE[3] PAD[67] 56 87 IO Nexus
MSEO(2) —DSPI 0 -
CS 4 DSPI 2 -
CLK
PE[4] PAD[68] — 88 IO Timer 3 -
ch. 5 DSPI 2 -
CS 2 Timer 2 -
ch. 4 —
PE[5] PAD[69] 57 89 IO Nexus
MDO 3(2) —CLOCKOUT
DSPI 2 -
Serial Data
PE[6] PAD[70] 58 90 IO Nexus
MDO 2(2) —DSPI 0 -
CS 6 DSPI 2 -
Serial Data
PE[7] PAD[71] 59 91 IO Nexus
MDO 1(2) —DSPI 0 -
CS 7 Timer 3 -
ch. 4
PE[8] PAD[72] 60 92 IO Nexus
MDO 0(2) DSPI 0 -
CS 0 Ext. INT 3 Timer 3 -
ch. 5
PE[9] PAD[73] — 93 IO — Timer 3 -
ch. 2 Ext. INT 4 DSPI 2 -
CS 1
PE[10] PAD[74] — 94 IO — Timer 3 -
ch. 3 DSPI 0 -
CS 5 DSPI 2 -
CS 2
— VDD_HV_IO 61 95 PW —
Table 4. eTQFP64 and eTQFP100 pinout (continued)
Pin No. Alternate functio ns
Port
pin Pad
eTQFP64
eTQFP100
Type AF1 AF2 AF3 AF4
DocID024492 Rev 7 21/75
SPC570S40Ex, SPC570S50Ex Package pinouts and signal descriptions
74
PE[11] PAD[75] 62 96 IO Nexus
MCK0(2) DSPI 0 -
CLK DSPI 0 -
CS 1 DSPI 1 -
CS 3
PE[12] PAD[76] — 97 IO — Timer 3 -
ch. 4 DSPI 2 -
CS 0 DSPI 1 -
CS 2
PE[13] PAD[77] — 98 IO — Timer 3 -
ch. 5 DSPI 2 -
CS 1 DSPI 1 -
CS 1
PE[14] PAD[78] 63 99 IO Nexus
EVTO (2) DSPI 0 -
Serial Data DSPI 0 -
CS 2 DSPI 2 -
CS 3
PE[15] PAD[79] 64 100 IO Nexus
EVTI(2) DSPI 0 -
Serial Data DSPI 1 -
CS 3 —
1. Cannot be changed
2. Can be enabled via JTAG during the reset phase
Table 4. eTQFP64 and eTQFP100 pinout (continued)
Pin No. Alternate functio ns
Port
pin Pad
eTQFP64
eTQFP100
Type AF1 AF2 AF3 AF4