GM71CS4400CLR-60 - LG Semicon Co., Ltd.

GM71C(S)4400C/CL

1,048,576 WORDS x 4BIT

CMOS DYNAMIC RAM

Description

The GM71C(S)4400C/CL is the new generation

dynamic RAM organized 1,048,576 words x 4 bit.

GM71C(S)4400C/CL has realized higher density,

higher performance and various functions by

utilizing advanced CMOS process technology. The

GM71C(S)4400C/CL offers Fast Page Mode as a

high speed access Mode. Multiplexed address

inputs permit the GM71C(S)4400C/CL to be

packaged in a standard 300mil 20(26) pin plastic

SOJ and standard 300mil 20(26) pin plastic

TSOP II. The package size provides high system

bit densities and is compatible with widely

available automated testing and insertion

equipment. System oriented features include single

power supply of 5V+/-10% tolerance, direct

interfacing capability with high performance logic

families such as Schottky TTL.

Features

* 1,048,576 Words x 4 Bit Organization

* Fast Page Mode Capability

* Single Power Supply (5V+/-10%)

* Fast Access Time & Cycle Time

GM71C(S)4400C/CL-60

GM71C(S)4400C/CL-70

GM71C(S)4400C/CL-80

tRAC tCAC tRC tPC

110

130

150

* Low Power

Active : 605/550/495mW (MAX)

Standby : 5.5mW (CMOS level : MAX)

1.1mW (L-version)

* RAS Only Refresh, CAS before RAS Refresh,

Hidden Refresh Capability

* All inputs and outputs TTL Compatible

* 1024 Refresh Cycles/16ms

* 1024 Refresh Cycles/128ms (L-version)

* Battery Back Up Operation (L-version)

(Unit: ns)

Pin Configuration

I/O1

I/O2

RAS

VCC

10 11

VSS

I/O4

I/O3

CAS

20 (26) SOJ

(Top View)

20 (26) TSOP II

(Top View)

LG Semicon Co.,Ltd.

516

10 11

I/O1

I/O2

RAS

VCC

VSS

I/O4

I/O3

CAS

516

1011

VSS

I/O4

I/O3

CAS

I/O1

I/O2

RAS

VCC

NORMAL TYPE REVERSE TYPE

LG Semicon GM71C(S)4400C/CL

Pin Description

Pin Function Pin Function

A0-A9

I/O1-I/O4

RAS

CAS

VCC

VSS

Address Inputs

Refresh Address Inputs

Data Input / Data Output

Row Address Strobe

Column Address Strobe

Read/Write Enable

Output Enable

Power (+5V)

Ground

Ordering Information

Type No. Access Time Package

GM71C(S)4400CJ/CLJ-60

GM71C(S)4400CJ/CLJ-70

GM71C(S)4400CJ/CLJ-80

300 Mil, 20 (26) Pin

Plastic SOJ

300 Mil, 20 (26) Pin

Plastic TSOP II

(Normal Type)

Absolute Maximum Ratings*

Symbol Parameter Rating Unit

TSTG

VIN/VOUT

VCC

IOUT

0 ~ 70

-55 ~ 125

-1.0 ~ 7.0

Ambient Temperature under Bias

Storage Temperature (Plastic)

Voltage on any Pin Relative to VSS

Voltage on VCC Relative to VSS

Short Circuit Output Current

PD1.0Power Dissipation W

*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

GM71C(S)4400CT/CLT-60

GM71C(S)4400CT/CLT-70

GM71C(S)4400CT/CLT-80

300 Mil, 20 (26) Pin

Plastic TSOP II

(Reverse Type)

GM71C(S)4400CR/CLR-60

GM71C(S)4400CR/CLR-70

GM71C(S)4400CR/CLR-80

Recommended DC Operating Conditions (TA = 0 ~ 70C)

Symbol Parameter Unit

VCC

VIH

VIL

Supply Voltage

Input High Voltage

Input Low Voltage (I/O Pin)

Max

5.5

6.5

0.8

Typ

5.0

Min

4.5

2.4

-1.0

VIL Input Low Voltage (Others) V0.8--2.0

60ns

70ns

80ns

60ns

70ns

80ns

60ns

70ns

80ns

LG Semicon GM71C(S)4400C/CL

DC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C)

Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output

open condition.

2. Address can be changed once or less while RAS = VIL.

3. Address can be changed once or less while CAS = VIH.

4. L-version.

5. VCC-0.2V<=VIH<=6.5V, 0V<=VIL<=0.2V.

Symbol Parameter Note

VOH

VOL

Output Level

Output “H” Level Voltage (IOUT = -5mA)

Unit

Max

VCC

0.4

Min

2.4

Output Level

Output “L” Level Voltage (IOUT = 4.2mA)

ICC1

110-

Operating Current

Average Power Supply Operating Current

(RAS, CAS, Address Cycling: tRC = tRC min)

60ns

70ns

80ns

100

1, 2

ICC2 mA

Standby Current (TTL)

Power Supply Standby Current

(RAS, CAS= VIH, DOUT = High-Z) 2-

ICC3

mA 2

ICC4

mA 1, 3

110-60ns

70ns

80ns

100

110-60ns

70ns

80ns

100

ICC5 mA1-

ICC6

CAS-before-RAS Refresh Current

(tRC = tRC min) 110-60ns

70ns

80ns

100

ICC7

uA300-4, 5

uA200-

ICC8 mA

Standby Current RAS = VIH

CAS = VIL

DOUT = Enable 5-1

II(L) uA10-10

IO(L) uA10-10

Input Leakage Current

Any Input (0V<=VIN<=7V)

Output Leakage Current

(DOUT is Disabled, 0V<=VOUT<=7V)

RAS-Only Refresh Current

Average Power Supply Current

RAS-Only Refresh Mode

(RAS Cycling, CAS = VIH, tRC = tRC min)

Fast Page Mode Current

Average Power Supply Current

Fast Page Mode

(RAS = VIL, CAS, Address Cycling: tPC = tPC min)

Standby Current (CMOS)

Power Supply Standby Current

(RAS, CAS >= VCC - 0.2V , DOUT=High-Z)

Battery Back Up Current (Standby with CBR Refresh)

(tRC=125us, tRAS<=1us, WE=VIH, CAS=VIL,

OE, Address and DIN=VIH or VIL, DOUT=High-Z)

4, 5

LG Semicon GM71C(S)4400C/CL

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

Symbol Parameter Note

Max

Unit

Min MaxMin MaxMin

tRC Random Read or Write Cycle Time 110 -130 -150 -ns

tRP RAS Precharge Time 40 -50 -60 -ns

tRAS RAS Pulse Width 60 10,000 70 10,000 80 10,000 ns

tCAS CAS Pulse Width 15 10,000 10,000 10,000 ns20 20

tASR Row Address Set-up Time 0- - - ns0 0

tRAH Row Address Hold Time 10 - - - ns10 10

tASC Column Address Set-up Time 0- - - ns0 0

tCAH Column Address Hold Time 15 - - - ns15 15

tRCD RAS to CAS Delay Time 20 45 50 60 ns20 20 8

tRAD RAS to Column Address Delay Time 15 30 35 40 ns15 15 9

tRSH RAS Hold Time 15 - - - ns20 20

tCSH CAS Hold Time 60 - - - ns70 80

tCRP CAS to RAS Precharge Time 10 - - - ns10 10

tTTransition Time

(Rise and Fall) 3 50 50 50 ns3 3 7

tREF Refresh Period -16 16 16 ms- -

Capacitance (VCC = 5V+/-10%, TA = 25C)

Symbol Parameter Note

CI1

CI2

CI/O

Input Capacitance (Address)

Input Capacitance (Clocks)

Data Input, Output Capacitance (Data-In, Out)

1, 2

Unit

§Ü

Max

Min

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. CAS = VIH to disable DOUT.

AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 16)

-128 128 128 ms- -Refresh Period (L-version)

tODD OE to DIN Delay Time 15 - - - ns20 20

tDZO OE Delay Time from DIN 0- - - ns0 0

tDZC CAS Set-up Time from DIN 0- - - ns0 0

GM71C(S)4400

C/CL-60

GM71C(S)4400

C/CL-70

GM71C(S)4400

C/CL-80

Test Conditions

Input rise and fall times: 5ns

Input, output timing reference levels: 0.8V, 2.4V Output load : 2 TTL gate + CL (100§Ü)

(Including scope and jig)

LG Semicon GM71C(S)4400C/CL

Read Cycle

Symbol Parameter Note

Max

Unit

Min MaxMin MaxMin

tRAC Access Time from RAS -60 -70 -80 ns

tCAC Access Time from CAS -15 -20 -20 ns

tAA Access Time from Address -30 -35 -40 ns

tRCS Read Command Setup Time 0-0-0-ns

tRCH Read Command Hold Time to CAS 0- - - ns0 0

tRRH Read Command Hold Time to RAS 0- - - ns0 0

tRAL Column Address to RAS Lead Time 30 - - - ns35 40

2,3,17

3, 4,

13, 17

3, 5,

13, 17

tOFF1 Output Buffer Turn-off Time 15 15 15 ns 6

Write Cycle

Symbol Parameter Note

Max

Unit

Min MaxMin MaxMin

tWCS Write Command Setup Time 0-0-0-ns

tWCH Write Command Hold Time 15 -15 -15 -ns

tWP Write Command Pulse Width 10 -10 -10 -ns

tRWL Write Command to RAS Lead Time 15 -20 -20 -ns

tCWL Write Command to CAS Lead Time 15 - - - ns20 20

tDS Data-in Setup Time 0- - - ns0 0

tDH Data-in Hold Time 15 - - - ns15 15 11

000

tOAC Access Time from OE -15 -20 -20 ns 3,17

tOFF2 Output Buffer Turn-off Time from OE 15 15 15 ns 60 0 0

tCDD CAS to DIN Delay Time - - - ns

15 20 20

GM71C(S)4400

C/CL-60

GM71C(S)4400

C/CL-70

GM71C(S)4400

C/CL-80

tOEP OE Pulse width - - - ns15 20 20

GM71C(S)4400

C/CL-60

GM71C(S)4400

C/CL-70

GM71C(S)4400

C/CL-80

LG Semicon GM71C(S)4400C/CL

Read- Modify-Write Cycle

Symbol Parameter Note

Max

Unit

Min MaxMin MaxMin

tRWC Read-Modify-Write Cycle Time 150 -180 -200 -ns

tRWD RAS to WE Delay Time 80 -95 -105 -ns

tCWD CAS to WE Delay Time 35 -45 -45 -ns

tAWD Column Address to WE Delay Time 50 -60 -65 -ns 10

tOEH OE Hold Time from WE 15 -20 -20 -ns

Refresh Cycle

Symbol Parameter Note

Max

Unit

Min MaxMin MaxMin

tCSR CAS Set-up Time

(CAS-before-RAS Refresh Cycle) 10 -10 -10 -ns

tCHR CAS Hold Time

(CAS-before-RAS Refresh Cycle) 10 -10 -10 -ns

tRPC RAS Precharge to CAS Hold Time 10 -10 -10 -ns

tCPN CAS Precharge Time in Normal Mode 10 -10 -10 -ns

Fast Page Mode Cycle

Symbol Parameter Note

Max

Unit

Min MaxMin MaxMin

tPC Fast Page Mode Cycle Time 40 -45 -50 -ns

tCP Fast Page Mode CAS Precharge Time

100,000 100,000 100,000

tRASP Fast Page Mode RAS Pulse Width

-35 -40 -45

tACP Access Time from CAS Precharge ns

tRHCP RAS Hold Time from CAS Precharge 35 -40 -45 -ns

3,13,17

10 10 10- - -

- - -

tCPW Fast Page Mode Read-Modify-Write Cycle

CAS Precharge to WE Delay Time 55 -65 -70 -ns

tPRWC Fast Page Mode Read-Modify-Write Cycle

Time 80 -95 -100 -ns 10

GM71C(S)4400

C/CL-60

GM71C(S)4400

C/CL-70

GM71C(S)4400

C/CL-80

GM71C(S)4400

C/CL-60

GM71C(S)4400

C/CL-70

GM71C(S)4400

C/CL-80

GM71C(S)4400

C/CL-60

GM71C(S)4400

C/CL-70

GM71C(S)4400

C/CL-80

LG Semicon GM71C(S)4400C/CL

Test Mode Cycle

Symbol Parameter Note

Max

Unit

Min MaxMin MaxMin

tWS Test Mode WE Setup Time 0-0-0-ns

tWH Test Mode WE Hold Time 10 -10 -10 -ns

Counter Test Cycle

Symbol Parameter Note

Max

Unit

Min MaxMin MaxMin

tCPT CAS Precharge Time in Counter Test

Cycle 40 -40 -40 -ns

AC Measurements assume tT = 5ns.

Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown.

Measured with a load circuit equivalent to 2TTL loads and 100§Ü.

Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max).

Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max).

tOFF(max) defines the time at which the output achieves the open circuit condition and is not

referenced to output voltage levels.

VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH and VIL.

Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a

reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is

controlled exclusively by tCAC.

Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a

reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is

controlled exclusively by tAA.

Notes:

GM71C(S)4400

C/CL-60

GM71C(S)4400

C/CL-70

GM71C(S)4400

C/CL-80

GM71C(S)4400

C/CL-60

GM71C(S)4400

C/CL-70

GM71C(S)4400

C/CL-80

LG Semicon GM71C(S)4400C/CL

tWCS, tRWD, tCWD tCPW and tAWD are not restrictive operating parameters. They are included in the

data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write cycle

and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if

tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read-

modify-write and the data output will contain data read from the selected cell; if neither of the

above sets of conditions is satisfied, the condition of the data out (at access time) is

indeterminate.

These parameters are referenced to CAS leading edge in early write cycles and to WE leading

edge in delayed write or a read modify write cycle.

tRASP defines RAS pulse width in fast page mode cycles.

Access time is determined by the longer of tAA or tCAC or tACP.

An initial pause of 100us is required after power up followed by a minimum of eight

initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal

refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.

In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device.

Test mode operation specified in this data sheet is 2-bit test function controlled by control

address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS

(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read

cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the

condition of the output data is low level. In order to end this test mode operation, perform a RAS

only refresh cycle or a CAS-before-RAS refresh cycle.

In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for

the specified value. These parameters should be specified in test mode cycles by adding the

above value to the specified value in this data sheet.

10.

11.

12.

13.

14.

15.

16.

17.

LG Semicon GM71C(S)4400C/CL

Package Dimension

20 (26) SOJ

Unit: Inches (mm)

0.669(17.00) MAX

0.661(16.80) MIN

0.295(7.49) MIN

0.330(8.38) MIN

0.340(8.64) MAX

0.148(3.76) MAX

0.128(3.25) MIN

0.036(0.91) MAX

0.026(0.66) MIN

TYP

0.050(1.27)

0.260(6.60) MIN

0.275(6.99) MAX

0.025(0.63) MIN

0.085(2.16) MIN

0.103(2.61) MAX

0.305(7.75) MAX

0.039(1.00) MAX

0.008(0.20)

0.021(0. 53) MAX

0.015(0.38) MIN

20 (26) TSOP II

0.292(7.42) MIN

0.308(7.82) MAX

0.690(17.54) MAX

0.667(16.94) MIN

0.048(1.23) MAX

0.020(0.50) MAX

0.012(0.30) MIN

TYP

0.050(1.27)

0.009(0.23) MAX

0.001(0.03) MIN

0.028(0.70) MAX

0.012(0.30) MIN

0.355(9.02) MIN

0.371(9.42) MAX

0.009(0.22) MAX

0.041(1.03) MIN

0 ~ 8 o