ISL29003IROZ-EVAL - Intersil Corporation

FN7464.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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ISL29003

Light-to-Digital Output Sensor with High

Sensitivity, Gain Selection, Interrupt

Function and I2C Interface

The ISL29003 is an integrated light sensors with a 16-bit

integrating type ADC, I2C user programmable Lux range

select for optimized coun ts/Lux, and I2C multi-function

control and monitoring capabilities. The internal ADC

provides 16-bit resolution while rejecting 50Hz and 60Hz

flicker caused by artificial light sources.

In normal operation, power consumption is less than 300µA.

Furthermore, an av ailable software power-down mode

controlled via the I2C interface reduces powe r consumption

to less than 1µA.

The ISL29003 supports a hardware interrupt that remains

asserted low until the host clears it through I2C interface.

Designed to operate on su pplies from 2.5V to 3.3V, the

ISL29003 is specified for operation over the -40°C to +85°C

ambient temperature range.

Block Diagram

Features

• Range select via I2C

- Range 1 = 0Lux to 1000Lux

- Range 2 = 0Lux to 4000Lux

- Range 3 = 0Lux to 16,000Lux

- Range 4 = 0Lux to 64,000Lux

• Human eye response (540nm peak sensitivity)

• Temperature compensated

• 16-bit re sol u ti o n

• Adjustable resolution: up to 65 counts per Lux

• User-programmable upper and lower threshold interrupt

• Simple output code, directly proportional to Lux

• IR + UV rejection

• 50Hz/60Hz rejection

• 2.5V to 3.3V supply

• 6 Ld ODFN (2.1mm x 2mm)

• Pb-free available (RoHS co mpliant)

Applications

• Ambient light sensing

• Backlight control

• Temperature control systems

• Contrast control

• Camera light meters

• Lightin g controls

Pinout ISL29003

(6 LD ODFN)

TOP VIEW

Ordering Information

PART NUMBER TAPE &

REEL PACKAGE PKG.

DWG. #

ISL29003IROZ-T7

(Note) 7” 6 Ld ODFN

(Pb-free) L6.2X2.1

ISL29003IROZ-EVAL Evaluation Board (Pb-free)

NOTE: Intersil Pb-free ODFN products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both

SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflo w temperatures that meet or exceed

the Pb-free re quiremen ts of IPC/JEDEC J S TD-020.

VDD

REXT GND

SDA

SCL

COMMAND

INTEGRATING

ADC DATA

I2C

PHOTODIODE 1

PHOTODIODE 2

MUX

3 2

FOSC

IREF

COUNTER

216

MODE

GAIN/RANGE

EXT

SHDN

INT TIME

4INT

INTERRUPT

ISL29003

TIMING

INT

VDD

GND

REXT

SDA

SCL

INT

THERMAL

PAD

Data Sheet December 12, 2006

2FN7464.2

December 12, 2006

Absolute Maximum Ratings (TA = +25°C)

VDD Supply Voltage between VDD and GND . . . . . . . . . . . . . 3.6V

I2C Bus Pin Voltage (SCL, SDA) . . . . . . . . . . . . . . . . . -0.2V to 5.5V

I2C Bus Pin Current (SCL, SDA) . . . . . . . . . . . . . . . . . . . . . . <10mA

Rext Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 3.6V

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+12 5°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-45°C to +100°C

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

ESD, Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Electrical Specifications VDD = 3V, TA = +25°C, REXT = 100kΩ 1% tolerance, unless otherwise specified, Internal Timing Mode

operation (See Principles of Operation).

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

VDD Power Supply Range 2.25 3.63 V

IDD Supply Current 0.29 0.33 mA

IDD1 Supply Current Disabled Software disabled 0.1 1 µA

FOSC1 Internal Oscillator Frequency Gain/Range = 1 or 2 290 327 360 kHz

FOSC2 Internal Oscillator Frequency Gain/Range = 3 or 4 580 655 720 kHz

FI2CI

2C Clock Rate Note 2 1 400 kHz

DATA0 Diode1 Dark ADC Code E = 0Lux, Mode1, Gain/Range = 1 5 Counts

DATA1 Full Scale ADC Code 65535 Counts

DATA2 Diode1 ADC Code Gain/Range = 1

accuracy Mode1 E = 300Lux, fluorescent light,

Gain/Range = 1

(Note 1)

15760 20200 24440 Counts

DATA3 Diode2 ADC Code Gain/Range = 1

accuracy Mode2 2020 Counts

DATA4 Diode1 ADC Code Gain/Range = 2

accuracy Mode1 E = 300Lux, fluorescent light,

Gain/Range = 2

(Note 1)

5050 Counts

DATA5 Diode2 ADC Code Gain/Range = 2

accuracy Mode2 505 Counts

DATA6 Diode1 ADC Code Gain/Range = 3

accuracy Mode1 E = 300Lux, fluorescent light,

Gain/Range = 3

(Note 1)

1262 Counts

DATA5 Diode2 ADC Code Gain/Range = 3

accuracy Mode2 126 Counts

DATA6 Diode1 ADC Code Gain/Range = 4

accuracy Mode1 E = 300Lux, fluorescent light,

Gain/Range = 4

(Note 1)

316 Counts

DATA6 Diode2 ADC Code Gain/Range = 4

accuracy Mode2 32 Counts

VREF Voltage of REXT Pin 0.485 0.51 0.535 V

VTL SCL & SDA Threshold LO (Note 3) 1.05 V

VTH SCL & SDA Threshold HI (Note 3) 1.95 V

ISDA SDA Current Sinking Capability Note 4 3 5 mA

IINT INT Current Sinking Capability 3 5 mA

NOTES:

1. Fluorescent light is substituted by a white LED during production.

2. Minimum I2C Clock Rate is guaranteed by design.

3. The voltage threshold levels of the SDA and SCL pins are VDD dependent: VTL = 0.35*VDD. VTH = 0.65*VDD.

4. Sinking capability is guaranteed by design.

ISL29003

3FN7464.2

December 12, 2006

Principles of Operation

Photodiodes

The ISL29003 contains two photodiodes. Diod e1 is sensitive

to both visible and infrared light, whi le Diode2 is mostly

sensitive to infrared light. The spectral response of th e two

diodes are independent from one another. See Figure 7

Spectral Response vs Wavelength in the performance curves

section. The photodiodes convert light to current. Then, the

diodes’ current output s a re converted to digi t al by a single

built-in integrating type 16-bit Analog-to-Dig it al Co nverter

(ADC). An I2C command mode determines which ph otodiode

will be converted to a digital signa l. Mode1 is Dio de1 onl y.

Mode2 is Diode2 only. Mode3 is a sequential Mode1 and

Mode2 with an internal subtract function (Diode1 - Diode2).

Analog-to-Digit al Converter (AD C)

The converter is a charge-balancing integrating type 16-bit

ADC. The chosen method for conversion is best for

converting small current signals in the presence of an AC

periodic noise. A 100ms integration time, for instance, highly

rejects 50Hz and 60Hz power line noise simultaneously. See

Integration Time and Noise Rejection section.

The built-in ADC offers user flexibility in integration time or

conversion time. T wo timing modes are available. Internal

T iming Mode and External Timing Mode. In Internal T iming

Mode, integration time is determined by an internal dual speed

oscillator (fosc), and the n-bit (n = 4, 8, 12,16) counter inside the

ADC. In External T iming Mode, integration time is determined

by the time between two consecutive I2C External Timing Mode

commands. See External T iming Mode example. A good

balancing act of integration time and resolution depending on

the application is required for optimal results.

The ADC has four I2C programmable range select to

dynamically accommodate various lighting conditions. For

very dim conditions, the ADC can be configured at its lowest

range. For very bright conditions, the ADC can be configured

at its highest range.

Interrupt Function

The active low interrupt pin is an open dr ain pull-down

configuration. The interrupt pin serves as an alarm or

monitoring function to determine whether the ambient light

exceeds the upper threshold or goes below the lower

threshold. The user can also configure the persistency of the

interrupt pin. This eliminates any false triggers such as noise

or sudden spikes in ambient light conditions. An unexpected

camera flash for example can be ignored by setting the

persistency to 8 integration cycles.

I2C Interface

There are eight (8) 8-bit registers available inside the ISL29003.

The command and control registers define the operation of the

device. The command and control registers do not change until

the registers are overwritten.There are two 8-bit registers that

set the high and lo w interrupt thresholds . There are fo ur 8-bit

data Read Only registers. T wo bytes for the sensor reading and

another two bytes for the timer counts. The data registers

contain the ADC's latest digital output, and the number of clock

cycles in the previous integration period.

The ISL29003’s I2C interface slave address is hardwired

internally as 44(hex).

Figure 1 shows a sample one-byte read. Figure 2 shows a

sample one-byte write. Figure 3 shows a sync_iic timing

diagram sample for externally controlled inte gration time.

The I2C bus master always drives the SCL (clock) line, while

either the master or the slave can drive the SDA (data) line.

Figure 2 shows a sample write. Every I2C transaction begins

with the master asserting a start condition (SDA falling while

SCL remains high). The following byte is driven by the

master, and includes the slave address and read/write bit.

The receiving device is responsible for pulling SDA low

during the acknowledgement period.

Every I2C transaction ends with the master asserting a stop

condition (SDA rising while SCL remains high).

For more information about the I2C standard, please consult

the Philips® I2C specification documents.

Pin Descriptions

PIN NUMBER PIN NAME DESCRIPTION

1 VDD Positive supply; connect this pin to a regulated 2.5V to 3.3V supply

2 GND Ground pin. The thermal pad is connected to the GND pin

3 REXT External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100kΩ resistor

4INT

Interrupt pin; LO for interrupt/alarming. The INT pin is an open drain.

5SCLI

2C serial clock The I2C bus lines can pulled above VDD, 5.5V max.

6SDAI

2C serial data

ISL29003

4FN7464.2

December 12, 2006

FIGURE 1. I2C READ TIMING DIAGRAM SAMPLE

Start WAA AA

A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A A6 A5 A4 A3 A2 A1 A0 W A

A A A D7D6D5D4D3D2D1D0 A

123456789123456789 123456789123456789

STOP

STOP START

SDA DRIVEN BY MASTER

DEVICE ADDRESS

SDA DRIVEN BY ISL29003

DATA BYTE0

NAK

I2C SDA

Out

DEVICE ADDRESS

I2C DATA

SDA DRIVEN BY MASTER

I2C CLK

I2C SDA

SDA DRIVEN BY MASTER

FIGURE 2. I2C WRITE TIMING DIAGRAM SAMPLE

Start

AAA

A6 A5 A4 A3 A2 A1 A0

A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A

AAA

123456789123456789123456789

STOP

I2C SDA In

I2C CLK In

SDA DRIVEN BY MASTER

FUNCTIONSREGISTER A DDRES S

I2C SDA Out

DE VICE ADDRES S

I2C DATA

SDA DRIVEN BY MASTER SDA DRIVEN BY MASTER

FIGURE 3. I2C sync_iic TIMING DIAGRAM SAMPLE

Start WAAStop

A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A

123456789123456789

S DA DRIVEN BY MASTER

I2C SDA Out

DE V ICE A DDRE S S

I2C DAT A

I2C SDA In

I2C CLK In

SDA DRIVEN BY MASTER

ISL29003

5FN7464.2

December 12, 2006

There are eight registers that are available in th e ISL29003. Table 1 summarizes the av ailable registers and their functions.

TABLE 1. REGISTER SET

ADDR

(HEX) REGISTER

NAME Bit(s) FUNCTION NAME FUNCTIONS/

DESCRIPTION

00 Command 7 enable 0: disable adc-core

1: enable adc-core

6 adcPD 0: Normal operation

1: Power Down Mode

5 Timing_Mode 0: Integration is internally timed

1: Integration is externally sync/controlled by I2C host

4 reserved

3:2 mode<1:0> Selects ADC work mode

0: Diode1’s current to unsigned 16-bit data

1: Diode2’s current to unsigned 16-bit data

2: Difference between diodes (I1 - I2) to signed 15-bit data

3: reserved

1:0 width<1:0> number of clock cycles; n-bit resolution

0: 216 cycles

1: 212 cycles

2: 28 cycles

3: 24 cycles

01 Control 7 ext_mode Always set to logic 0. Factory use only.

6 test_mode Always set to logic 0

5 int_flag 0: Interrupt is cleared or not yet triggered

1: Interrupt is triggered

4 reserved Always set to logic 0. Factory use only.

3:2 gain<1:0> Selects the gain so range is

0: 0 - 1000Lux

1: 0 - 4000Lux

2: 0 - 16000Lux

3: 0 - 64000Lux

1:0 int_persist

<1:0> Interrupt is triggered after

0: 1 integration cycle

1: 4 integration cycles

2: 8 integration cycles

3: 16 integration cycles

02 Interrupt threshold

HI 7:0 Interrupt threshold

HI High byte of HI interrupt threshold. Default is 0xFF

03 Interrupt threshold

LO 7:0 Interrupt threshold

LO High byte of the LO interrupt threshold. Default is 0x00

04 LSB_sensor 7:0 LSB_sensor Read-Only data register that contains the least significant byte of the

latest sensor reading

05 MSB_sensor 7:0 MSB_sensor Read-Only data register that contains the most significant byte of the

latest sensor reading

06 LSB_timer 7:0 LSB_timer Read-Only data register that contains the least significant byte of the

timer counter value corresponding to the latest sensor reading.

07 MSB_timer 7:0 MSB_timer Read-Only data register that contains the most significant byte of the

timer counter value corresponding to the latest sensor reading.

ISL29003

6FN7464.2

December 12, 2006

Command Register 00(hex)

The Read/Write command register has five functions:

(1) Enable; Bit 7.This function either resets the ADC or

enables the ADC in normal operation. A logic 0 disables

ADC to reset-mode. A logic 1 enables adc to normal

operation.

(2) AdcPD; Bit 6. This function puts the device in a power

down mode. A logic 0 puts the device in normal operation. A

logic 1 powers do wn th e de vi ce .

(3) T iming Mode; Bit 5. This function determines whether the

integration time is done internally or externally. In Internal

Timing Mode, integration time is determined by an internal

dual speed oscillator (fosc), and the n-bit (n = 4, 8, 12,16)

counter inside the ADC. In External T iming Mode, integration

time is determined by the time between two consecutive

external-sync sync_iic pules commands.

(4) Photodiode Select Mode; Bits 3 and 2. This function

controls the mux attached to the two photodiodes. At Mode1,

the mux directs the current of Diode1 to the ADC. At Mode2,

the mux directs the current of Diode2 only to the ADC.

Mode3 is a sequential Mode1 and Mode2 with an internal

subtract function (Diode1 - Diode2).

* n = 4, 8, 12,16 depending on the number of clock cycl es

function.

(5) Width; Bits 1 and 0. This function determines the number

of clock cycles per conversion. Changing the number of

clock cycles does more than just change the resolution of

the device. It also changes the integration time, which is th e

period the device’s analog-to-digital (A/D) converter samples

the photodiode current signal for a Lux measurement.

Control Register 01(he x)

The Read/Write control register has three functions:

(1) Interrupt flag; Bit 5. This is the status bit of the interrupt.

The bit is set to logic high when the interrupt thresholds have

been triggered, and logic low when not yet triggered. Writing

a logic low clears/resets the status bit.

(2) Range/Gain; Bits 3 and 2. The Full Scale Range can be

adjusted by an external resistor Rext and/or it ca n be

adjusted via I2C using the Gain/Range function. Gain/Range

has four possible values, Range(k) where k is 1 through 4.

Table 9 lists the possible values of Range(k) and the

resulting FSR for some typical value REXT resistors.

TABLE 2. WRITE ONLY REGI STERS

ADDRESS REGISTER

NAME FUNCTIONS/

DESCRIPTION

b1xxx_xxxx sync_iic Writing a logic 1 to this address bit

ends the current adc-integration and

starts another. Used only with

External Timing Mode.

bx1xx_xxxx clar_int Writing a logic 1 to this address bit

clears the interrupt.

TABLE 3. ENABLE

BIT 7 OPERATION

0 disable ADC-core to reset-mode (default)

1 enable ADC-core to normal operation

TABLE 4. adcPD

BIT 6 OPERATION

0 Normal operation (default)

1 Power Down

TABLE 5. TIMING MODE

BIT 5 OPERATION

0 Internal Timing Mode. Integration time is internally

timed determined by fosc, REXT, and number of

clock cycles.

1 External Timing Mode. Integration time is externally

timed by the I2C host.

TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3

BITS 3:2 MODE

0:0 MODE1. ADC integrates or converts Diode1 only.

Current is converted to an n-bit unsigned data.*

0:1 MODE2. ADC integrates or coverts Diode2 only.

Current is converted to an n-bit unsigned data.*

1:0 MODE3. A sequential MODE1 then MODE2

operation. The difference current is an (n-1) signed

data.*

1:1 No operation.

TABLE 7. WIDTH

BITS 1:0 NUMBER OF CLOCK CYCLES

0:0 2^16 = 65,536

0:1 2^12 = 4,096

1:0 2^8 = 256

1:1 2^4 = 16

TABLE 8. INTERRUPT FLAG

BIT 5 OPERATION

0 Interrupt is cleared or not triggered yet

1 Interrupt is triggered

ISL29003

7FN7464.2

December 12, 2006

Interrupt persist; Bits 1 and 0. The interrupt pin and the

interrupt flag is triggered/set when the data sensor reading is

out of the interrupt threshold window after m consecutive

number of integration cycles. The interrupt persist bits

determine m.

Interrupt Threshold HI Register 02(hex)

This register sets the HI threshold for the interrupt pin and

the interrupt flag. By default the Interrupt threshold HI is

FF(hex). The 8-bit data written to the register represents the

upper MSB of a 16-bit value. The LSB is always 00(hex).

Interrupt Threshold LO Register 03(hex)

This register sets the LO threshold for the interrupt pin and

the interrupt flag. By default the Interrupt threshold LO is

00(hex). The 8-bit data written to the register represents the

upper MSB of a 16-bit value. The LSB is always 00(hex).

Sensor Data Register 04(hex) and 05(hex)

When the device is configured to output a 16-bit data, the

most significant byte is accessed at 04(hex), and the least

significant byte can be accessed at 05(hex). The sensor data

Timer Data Register 06(hex) and 07(hex)

Note that the timer counter value is only available when

using the External Timing Mode. The 06(hex) and 07(hex)

are the LSB and MSB respectively of a 16-bit timer counter

value corresponding to the most recent sensor reading.

Each clock cycle increments the counter. At the end of each

integration period, the value of this counter is made available

over the I2C. This value can be used to eliminate noise

introduced by slight timing errors caused by imprecise

external timing. Microcontrollers, for example, often cannot

provide high-accuracy command-to-command timing , and

the timer counter value can be used to eliminate the

resulting noise.

Calculating Lux

The ISL29003’s output codes, DATA, are directly

proportional to Lux.

The proportionality constant α is determined by the Full

Scale Range, FSR, and the n-bit ADC which is use r defined

in the command register. The p r oportionality constant can

also be viewed as the resolution; The smallest Lux

measurement the device can measure is α.

Full Scale Range, FSR, is determined by the software

programmable Range/Gain, Range(k), in the command

referenced to 100kΩ.

The transfer function effectively for each timing mode

becomes:

INTERNAL TIMING MODE

EXTERNAL TIMING MODE

n = 4, 8, 12, or 16. This is the number of clock cycles

programmed in the command regi ster.

Range(k) is the user defined range in the Gain/Range bit

in the command register.

REXT is an external scaling resistor hardw ired to the REXT

pin.

DATA is the output sensor reading in number of counts

available at the data register.

2n represents the maximum number of counts possible in

Internal Timing Mode. For the External Timing Mode the

maximum number of counts is stored in the data register

named COUNTER

TABLE 9. RANGE/GAIN TYPICAL FSR LUX RANGES

BITS

3:2 k RANGE(k)

FSR LUX

RANGE@

REXT = 100k

FSR LUX

RANGE@

REXT = 50k

FSR LUX

RANGE@

REXT = 500k

0:0 1 973 973 1946 195

0:1 2 3892 3892 7784 778

1:0 3 15,568 15,568 31,136 3114

1:1 4 62,272 62,272 124,544 12,454

TABLE 10. INTERRUPT PERSIST

BITS 1:0 NUMBER OF INTEGRATION CYCLES

0:0 1

0:1 4

1:0 8

1:1 16

TABLE 11. DATA REGISTERS

ADDRESS

(hex) CONTENTS

04 Least-significant byte of most recent sensor reading.

05 Most-significant byte of most recent sensor reading.

06 Least-significant byte of timer counter value

corresponding to most recent sensor reading.

07 Most-significant byte of timer counter value

corresponding to most recent sensor reading.

EαDATA×=(EQ. 1)

FSR

------------

=(EQ. 2)

(EQ. 3)

FSR Range k() 100kΩ

REXT

------------------

×=

(EQ. 4)

ERange k() 100kΩ

REXT

------------------

---------------------------------------------------- DATA×=

(EQ. 5)

ERange k() 100kΩ

REXT

------------------

COUNTER

---------------------------------------------------- DATA×=

ISL29003

8FN7464.2

December 12, 2006

COUNTER is the number increments accrued for between

integration time for External Timin g Mode.

Gain/Range, Range(k)

The Gain/Range can be programmed in the control register

to give Range (k) determining the FSR. Note that Range (k)

is not the FSR. See Equation 3. Range(k) provides four

constants depending on programmed k that will be scaled by

REXT. See Table 9. Unlike REXT, Range(k) dynamically

adjusts the FSR. This function is especially useful when light

conditions are varying drastically while maintaining excellent

resolution.

Number of Clock Cycles, n-bit ADC

The number of clock cycles determines “n” in the n-bit ADC; 2n

clock cycles is a n-bit ADC. n is programmable in the command

good balance of speed, and resolution has to be considered

when deciding for n. For fast and quick measurement, choose

the smallest n = 4. For maximum resolution without regard of

time, choose n = 16. Table 12 compares the trade-off between

integration time and resolution. See Equations 10 and 1 1 for the

relation between integration time and n. See Equation 3 for the

relation of n and resolution.

External Scaling Resistor REXT and fosc

The ISL29003 uses an external resistor REXT to fix its

internal oscillator frequency, fosc. Consequently, REXT

determines the fosc, integration time and the FSR of the

device. Fosc, a dual speed mode oscillator, is inversely

proportional to REXT. For user simplicity, the proporti onality

constant is referenced to fixed constants 100kΩ and

655kHz:

fosc1 is oscillator frequency when Range1 or Range2 are

set. This is nominally 327kHz when REXT is 100kΩ.

fosc2 is the oscillator frequency when Range3 or Range4

are set. This is nominally 655kHz when REXT is 100kΩ.

When the Range/Gain bits are set to Range1 or Range2,

fosc runs at half speed compared to when Range/Gain bits

are set to Range3 and Range4.

The automatic fosc adjustment feature allows sign i fi c a nt

improvement of signal-to-noise ratio when detecting very low

Lux signals.

Integration Time or Conversion Time

Integration time is the period during which the device’s

analog-to-digital ADC converter samples the photodiode

current signal for a Lux measurement. Integration time, in

other words, is the time to complete the conversion of analog

photodiode current into a digital signal--number of counts.

Integration time affects the measurement resolution. For

better resolution, use a longer integration time. For short and

fast conversions use a shorter integration time .

The ISL29003 offers user flexibility in the integration time to

balance resolution, speed and noise rejection. Integration time

can be set internally or externally and can be programmed in

the command register 00(hex) bit 5.

INTEGRATION TIME IN INTERNAL TIMING MODE

This timing mode is programmed in the command register

00(hex) bit 5. Most applications will be using this timing

mode. When using the Internal Timing Mode, fosc and n-bits

resolution determine the integration time. Tint is a function of

the number of clock cycles and fosc.

n = 4, 8, 12, and16. n is the number of bits of resolution.

2n there fore is the numb er of clock cycles. n can be

programmed at the command registe r 00(hex) bits 1 and 0.

Since fosc is dual speed depending on the Gain/Range bit,

Tint is dual time. The inte gration time as a function of REXT

and n is:

Tint1 is the integration time when the device is configured

for Internal Timing Mode and Gain/Range is set to Range1

or Range2.

Tint2 is the integration time when the device is configured

for Internal Timing Mode and Gain/Range is set to Range3

or Range4.

T ABLE 12. RESOLUTION AND INTEGRA TION TIME

SELECTION

RANGE1

fosc = 327kHz RANGE4

fosc = 655kHz

TINT

(ms) RESOLUTION

LUX/COUNT TINT

(ms) RESOLUTION

(LUX/COUNT)

16 200 0.01 100 1

12 12.8 0.24 6.4 16

8 0.8 3.90 0.4 250

4 0.05 62.5 0.025 4000

REXT = 100kΩ

(EQ. 6)

osc1 1

---100kΩ

REXT

------------------ 655×kHz×=

(EQ. 7)

fosc2 100kΩ

REXT

------------------ 655×kHz=

(EQ. 8)

osc11

---fosc2()=

Tint 2n1

fosc

----------

×=(EQ. 9)

for Internal Timing Mode only

Tint12

nREXT

327kHz 100kΩ×

----------------------------------------------

×=(EQ. 10)

Tint22

nREXT

655kHz 100kΩ×

----------------------------------------------

×=(EQ. 11)

ISL29003

9FN7464.2

December 12, 2006

INTEGRATION TIME IN EXTERNAL TIMING MODE

This timing mode is programmed in the command register

00(hex) bit 5. External Timing Mode is recommended when

integration time can be synchronized to an external signal

such as a PWM to eliminate noise.

For Mode1 or Mode2 operation, the integration starts when

the sync_iic command is sent over the I2C lines. The device

needs two sync_iic commands to complete a photodiode

conversion. The integration then stops when another

sync_iic command is received. Writing a logic 1 to the

sync_iic bit ends the current adc in tegration and starts

another one.

For Mode3, the operation is a sequential Mode1 and Mode2.

The device needs three sync_iic co mmands to complete two

photodiode measurement s. The 1st sync_ii c command st a rt s

the conversion of the diode1. The 2nd sync_iic completes the

conversion of diode1 and st arts the co nversion of diode2. The

3rd sync_iic pules ends the conve rsion of diode2 and starts

over again to commence conversion of diode1.

The integration time, Tint, is determined by Equation 12:

iI2C is the number of I2C clock cycles to obtain the Tint.

fI2C is the I2C operating frequency

The internal oscillator, fOSC, operates identically in both the

internal and external timing modes, with the same

dependence on REXT. However, in External Timing Mode,

the number of clock cycles per integration is no longer fixed

at 2n. The number of clock cycles varies with the chosen

integration time, an d is limited to 216 = 65,536. In order to

avoid erroneous Lux readings the integration time must be

short enough not to allow an overflow in the counter register.

fosc = 327kHz*100kΩ/REXT. When Range/Gain is set to

Range1 or Range2.

fosc = 655kHz*100kΩ/REXT. When Range/Gain is set to

Range3 or Range4.

Noise Rejection

In general, integrating type ADC’s have an excellent noise-

rejection characteristics for periodi c noise sources whose

frequency is an integer multiple of the integration time. For

instance, a 60Hz AC unwanted signal’s sum from 0ms to

k*16.66ms (k = 1,2...ki) is zero. Similarly, setting the device’s

integration time to be an integer multiple of the periodic

noise signal, greatly improves the light sensor ou tput signal

in the presence of noise.

Design Example 1

The ISl29003 will be designed in a portable system. The

ambient light conditions that the device will be exposed to is

at most 500Lux which is a good office lighting. The light

source has a 50/60Hz power line noise which is no t visible

by the human eye. The I2C clock is 10kHz.

Solution 1 - Using Internal Timing Mode

In order to achieve both 60Hz and 50Hz AC noise rejection,

the integration time needs to be adjusted to coincide with an

integer multiple of the AC noise cycle times.

Tint = i(1/60Hz) = j(1/50Hz).

The first instance of integer values at which Tint rejects both

60Hz and 50Hz is when i = 6, and j= 5.

Tint = 6(1/60Hz) = 5(1/50Hz)

Tint = 100ms

Next, the Gain/Range needs to be determined. Based on the

application conditi on given, Lux(max) = 500Lux, a range of

1000Lux is desirable. This corresponds to a Gain/Range

Range1 mode. Also impose a resolution of n = 16-bit. Hence

we choose Equation 10 to determine REXT.

The Full Scale Range, FSR, n eeds to be determined. From

Equation 3:

The effective transfer function becomes:

TABLE 13. INTEGRATION TIMES FOR TYPICAL REXT VALUES

REXT

(kΩ)

RANGE1

RANGE2 RANGE3

RANGE4

n = 16-BIT n = 12-BIT n = 12-BIT n = 4

50 100 6.4 3.2 0.013

100** 200 13 6.5 0.025

200 400 26 13 0.050

500 1000 64 32 0.125

*Integration time in milliseconds

**Recommended REXT resistor value

Tint iI2C

fI2C

----------

=(EQ. 12)

Tint 65,535

fOSC

------------------

<(EQ. 13)

for Internal Timing Mode and Gain/Range is set to Range3 or Range4 only

REXT Tint 327kHz 100×× kΩ

---------------------------------------------------------------

REXT 50kΩ=

FSR 1000Lux100kΩ

50kΩ

------------------

FSR 2000Lux=

Edata

216

------------- 2000Lux×=

ISL29003

10 FN7464.2

December 12, 2006

Solution 2 - Using External Timing Mode

From solution 1, the desired integration time is 100ms. Note

that the REXT resistor only determines the inter oscilla tor

frequency when using external timing mode. Instead the

integration time is the time between two sync_iic commands

sent through the I2C. The programmer determines how

many I2C clock cycles to wait between two external timing

commands.

iI2C = fI2C * Tint = number of I2C clock cycles

iI2C = 10kHz *100ms

iI2C = 1,000 I2C clock cycles. An external sync_iic com mand

sent 1,000 cycles after another sync_iic command rejects

both 60Hz and 50Hz AC noise signals.

Next is to pick an arbitrary REXT = 100kΩ and to choose the

Gain/Range Mode. For a maximum 500Lux, Range1 is

adequate. From Equation 3:

The effective transfer function becomes:

DATA is the sensor readi ng data locate d in data registers

04(hex) and 05(hex)

COUNTER is the timer counter value da ta located in data

registers 06(hex) and 07(hex). In this sample problem,

COUNTER = 1000.

IR Rejection

Any filament type light source has a high presence of infrared

component invisible to the human eye. A white fluorescent

lamp, on the other hand has a low IR co ntent. As a resu lt,

output sensitivity may vary depending on the light so urce.

Maximum attenuation of IR can be achieved by properly

scaling the readings of Diode1 and Diode 2. The user obt ains

data reading from sensor diod e 1, D1, which is sensitive to

visible and IR, then reading from sensor diode 2 , D2 which is

mostly sensitive from IR. The graph on Figure 7 shows the

effecti ve spectral response af te r ap plying Equation 14 of the

ISL29003 from 400nm to 1000nm. The equ ation be low

describes the method of cancelling IR in i nternal timing mode.

Where:

data = lux amount in number of counts less IR presence

D1 = data reading of Diode 1

D2 = data reading of Diode 2

n = 1.85. This is a fudge factor to scale back the sensitivity

up to ensure Equation 4 is valid.

k = 7.5. This is a scaling factor for the IR sensitive Diode 2.

Flat Window Lens Design

A window lens will surely limit the viewing angle of the

ISL29003. The window lens should be placed directly on top

of the device. The thickness of the lens should be kept at

minimum to minimize loss of power due to reflection and

also to minimize loss of loss due to absorption of energy in

the plastic material. A thickness of t = 1mm is recommended

for a window lens design. The bigger the diameter of the

window lens the wider the viewing angle is of the ISL29003.

Table 16 shows the recommended dimensions of the optical

window to ensure both 35° and 45° viewing angle. These

dimensions are based on a window lens thickness of 1.0mm

and a refractive index of 1.59.

T ABLE 14. SOLUTION1 SUMMARY T O EXAMPLE DESIGN

PROBLEM

DESIGN PARAMETER VALUE

Tint 100ms

REXT 50kΩ

Gain/Range Mode Range1 = 1000Lux

FSR 2000Lux

# of clock cycles 216

Transfer Function

T ABLE 15. SOLUTION2 SUMMARY T O EXAMPLE DESIGN

PROBLEM

DESIGN PARAMETER VALUE

Tint 100ms

REXT 100kΩ

Gain/Range Mode Range1 = 1000Lux

FSR 1000Lux

# of clock cycles COUNTER = 1000

Transfer Function

EDATA

216

-----------------2000Lux×=

FSR 1000Lux100kΩ

100kΩ

------------------

FSR 1000lux=

EDATA

COUNTER

--------------------------------1000Lux×=

EDATA

COUNTER

--------------------------------1000Lux×=

D3 n D1 kD2–()=(EQ. 14)

DLENS

∅

D1 DTOTAL

∅ = Viewing angle

WINDOW LENS

ISL29003

FIGURE 4. FLAT WINDOW LENS

ISL29003

11 FN7464.2

December 12, 2006

Window with Light Guide Design

If a smaller window is desired while maintaining a wide

effective viewing angle of the ISL29003, a cylindrical piece of

transparent plastic is needed to trap the light and then focus

and guide the light on to the device. Hence the name light

guide or also known as light pipe. The pipe should be placed

directly on top of the device with a di stance of D1 = 0.5mm

to achieve peak performance. The light pipe should have

minimum of 1.5mm in diameter to ensure that whole area of

the sensor will be exposed. See Figure 5.

T ABLE 16. RECOMMENDED DIMENSIONS FOR A FLA T

WINDOW DESIGN

DTOTAL D1 DLENS @ 35

VIEWING ANGLE DLENS @ 45

VIEWING ANGLE

1.5 0.50 2.25 3.75

2.0 1.00 3.00 4.75

2.5 1.50 3.75 5.75

3.0 2.00 4.30 6.75

3.5 2.50 5.00 7.75

t = 1 Thickness of lens

D1 Distance between ISL29001 and inner edge of lens

DLENS Diameter of lens

DTOTAL Distance constraint between the ISL29001 and lens

outer edge

* All dimensions are in mm.

DLENS

LIGHT PIPE

ISL29003

D2 > 1.5mm

FIGURE 5. WINDOW WITH LIGHT GUIDE/PIPE

ISL29003

12 FN7464.2

December 12, 2006

Suggested PCB Footprint

Footprint pads should be a nominal 1-to-1 correspondence

with package p ads. The large, exposed central die-mounting

paddle in the center of the package requires neither thermal

nor electrical connection to the PCB, and such connection

should be avoided.

Layout Considerations

The ISL29003 is relatively insensitive to layout. Like other

I2C devices, it is intended to provide excellent performance

even in significantly noisy environments. There are only a

few considerations that will ensure best performance.

Route the supply and I2C traces as far as possible from all

sources of noise. Use two power-supply decoupling

capacitors, 4.7µF and 0.1µF, placed close to the device.

Typical Circuit

A typical application for the ISL2900 3 is shown in F igure 6.

The ISL29003’s I2C address is internally hardwired as

44(hex). The device can be tied onto a system’s I2C bus

together with other I2C compliant devices.

Soldering Considerations

Convection heati ng is recommended for reflow soldering;

direct-infrared heating is not recommended. The plastic

ODFN package does not require a custom reflow soldering

profile, and is qualified to +260°C. A standard reflow

soldering profile with a +260°C maximum is recommended

FIGURE 6. ISL29003 TYPICAL CIRCUIT

VDD

GND

REXT

3INT 4

SCL 5

SDA 6

ISL29003

10K R2

10K R3

RES1

REXT

100K

0.1uF

4.7uF

2.5V - 3.3V

1.8V - 5.5V

MICROCONTROLLER

SDA

SCL

I2C SLAVE_0 I2C SLAVE_1 I2C SLAVE_n

I2C MASTER

SCL

SDA

SCL

SDA

ISL29003

13 FN7464.2

December 12, 2006

Typical Performance Curves (REXT = 100kΩ)

FIGURE 7. SPECTRAL RESPONSE FIGURE 8. RADIATION PATTERN

FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 10. OUTPUT CODE FOR 0 LUX vs SUPPLY VOLTAGE

FIGURE 11. OUTPUT CODE vs SUPPLY VOLTAGE FIGURE 12. OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE

100

300 400 500 600 700 800 900 1000

Wavelength, nm

Normalized Response, %

ISL29003 D1

ISL29003 D2

RADI ATION PATTERN

LUMINOSITY

ANGLE

RELATIVE SENSITI VITY

2.0 2.3 2.6 2.9 3.2 3.5 3.8

320

306

292

278

264

250

SUPPLY CURRENT (μA)

SUPPLY VOLTAGE (V)

Ta = 27oC

COMMAND = 00H

5000 lux

200 lux

2.0 2.3 2.6 2.9 3.2 3.5 3.8

OUTPUT CODE (COUNTS)

SUPPLY VOLTAGE (V)

Ta = 27oC

COMMAND = 00H

0 lux

Range 2

2.0 2.3 2.6 2.9 3.2 3.5 3.8

1.015

1.010

1.005

1.000

0.995

0.990

OUTPUT CODE RATIO

(% FROM 3V)

SUPPLY VOLTAGE (V)

Ta = 27oC

COMMAND = 00H

5000 lux

200 lux

2.0 2.3 2.6 2.9 3.2 3.5 3.8

320.0

319.5

319.0

318.5

318.0

OSCILLATOR FREQUENCY (kHz)

SUPPLY VOLTAGE (V)

Ta = 27oC

ISL29003

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7464.2

December 12, 2006

FIGURE 13. SUPPLY CURRENT vs TEMPERATURE FIGURE 14. OUTPUT CODE FOR 0 LUX vs TEMPERATURE

FIGURE 15. OUTPUT CODE vs TEMPERATURE FIGURE 16. OSCILLATOR FREQUENCY vs TEMPERATURE

Typical Performance Curves (REXT = 100kΩ) (Continued)

-60 -20 20 60 100

315

305

295

285

275

265

SUPPLY CURRENT (μA)

TEMPERATURE (oC)

Vdd = 3V

COMMAND = 00H

5000 lux

200 lux

Range 3

Range 1

-60 -20 20 60 100

OUTPUT CODE (COUNTS)

TEMPERATURE (oC)

Vdd = 3V

COMMAND = 00H

0 lux

Range 2

-60 -20 20 60 100

1.080

1.048

1.016

0.984

0.952

0.920

OUTPUT CODE RATIO

(% FROM 25oC)

TEMPERATUR E (oC)

Vdd = 3V

COMMAND = 00H

5000 lux

200 lux

Range 3

Range 1

-60 -20 20 60 100

330

329

328

327

326

325

OSCILLATOR FREQUENCY (kHz)

TEMPERATURE (oC)

Vdd = 3V

ISL29003

15 FN7464.2

December 12, 2006

ISL29003

Package Outline Drawing

L6.2x2.1

6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN)

Rev 0, 9/06

located within the zone indicated. Th e pin #1 indentifier may be

Unless otherwise specified, tol erance : Decim al ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optio nal, but must be

between 0.15mm an d 0.3 0m m from the te rminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

(4X) 0.10

INDEX AREA

PIN 1

2.10

2.00

SEATING PLANE

BASE PLANE

0.08

0.10

SEE DETAIL "X"

0 . 00 MIN .

DETAIL "X"

0 . 05 MAX.

0 . 2 REF

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

( 6X 0 . 30 )

( 6X 0 . 55 )

TOP VIEW

(0 . 65)

(1 . 95)

(0 . 65) (1 . 35)

BOTTOM VIEW

6X 0 . 35 ± 0 . 05 B0.10 MAC

1 . 35 1 . 30 REF

INDEX AREA

PIN 1

0.65

0 . 65

MAX 0.75

6X 0 . 30 ± 0 . 05