DECEMBER 2003
DSC-5309/05
1
©2002 Integrated Device Technology, Inc.
Features
◆256K x 36, 512K x 18 memory configurations
◆◆
◆◆
◆Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
◆LBOLBO
LBOLBO
LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GWGW
GWGW
GW), byte write
enable (BWEBWE
BWEBWE
BWE), and byte writes (BWBW
BWBW
BWx)
◆◆
◆◆
◆3.3V core power supply
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆3.3V I/O supply (VDDQ)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA).
Pin Description Summary
A
0
-A
18
Address Inputs
Input
Synchronous
CE
Chip Enab le
Input
Synchronous
CS
,
CS
1
Chip Se lects
Input
Synchronous
OE
Outp ut Enab le
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Ad dress Advance
Input
Synchronous
ADSC
Add ress Status (Cac he Contro lle r)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Line ar / Inte rleav ed Burst Ord er
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Outp u t
I/O
Synchronous
V
DD
, V
DDQ
Co re P owe r, I/O Powe r
Supply
N/A
V
SS
Ground
Supply
N/A
5309 tbl 01
256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs, Single Cycle Deselect
IDT71V67703
IDT71V67903
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67903.
Description
The IDT71V67703/7903 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,
data, address and control registers. There are no registers in the data
output path (flow-through architecture). Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67703/7903 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V67703/7903 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
6.422
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol
Pin Function
I/O
Active
Description
A
0
-A
18
Address Inputs I N/A Synchronous Address inputs. The address register is trigge red by a combi-nation of the
rising e dge of CLK and ADSC Lo w or ADSP Lo w and CE Lo w.
ADSC Address Status
(Cache Controller) I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
ADSP Address Status
(Processor) I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is use d to
load the address registers with new addresses. ADSP is gated by CE.
ADV Burst Address
Advance I LOW Synchronous Address Advance. ADV is an active LOW input that i s use d to ad vance the
internal burst counter, controlling burst access after the initial address is loaded. When the
inp ut is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
-BW
4
. If BWE is LOW at the
rising ed ge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BW
1
-BW
4
Individual Byte
Write Enable s I LOW Synchronous byte write enables. BW
1
controls I/O
0-7
, I/O
P1
, BW
2
controls I/O
8-15
, I/O
P2
, etc.
Any active byte write cause s all outputs to be disabled.
CE Chip Enable I LOW Synchronous chip enable. CE is us e d with CS
0
and CS
1
to e nab le the IDT71V 67703/ 7903.
CE also gate s ADSP.
CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this
input.
CS
0
Chip Select 0 I HIGH Synchronous active HIGH chip se lect. CS
0
is used with CE and CS
1
to enable the chip.
CS
1
Chip Select 1 I LOW Synchrono us active LOW chip select. CS
1
is used with CE and CS
0
to enable the chip.
GW Global Write
Enable I LOW Synchro nous global write enable. This input will write all four 9-bit d ata bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. The data input path is registered, triggered by
the rising edge of CLK. The data output path is flow-through (no output register).
LBO Linear Burst Order I LOW Asynchro nous burst order selection input. When LBO i s HIGH, the inte r-le ave d b urs t
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
OE Output Enabl e I LOW As ync hronous o utput enable . Whe n OE is LOW the data output drivers are enabled on the
I/O pins if the c hip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
V
DD
Power Supply N/A N/A 3.3V core power supply.
V
DDQ
Power Supply N/A N/A 3.3V I/O Supply.
V
SS
Ground N/A N/A Ground.
NC No Connect N/A N/A NC pins are not electrically connected to the device.
ZZ Sleep Mode 1 HIGH Asynchronous sleep mode input. ZZ HIGH will g ate the CLK internally and power down
the IDT71V67703/7903 to its lo we st powe r consumption le ve l. Data rete ntio n is g uarante e d
in Sleep Mode.
5309 tbl 02
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
A0–A17/18 ADDRESS
REGISTER
CLR A1*
A0* 18/19
2
18/19
A2-A18
256K x 36/
512K x 18-
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A0,A1
BW 4
BW 3
BW 2
BW 1
Byte 1
Write Register
36/18 36/18
ADSP
ADV
CLK
ADSC
CS0
CS1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
9
9
9
9
GW
CE
BW E
LBO
I/O0–I/O31
I/OP1–I/OP4
OE
DATA INPUT
REGISTER
36/18
OUTPUT
BUFFER
DQ
Enable
Register
OE
Burst
Sequence
CEN
CLK EN
CLK EN
Q1
Q0
2Burst
Logic
Binary
Counter
5309 drw 01
ZZ Powerdown
,
6.424
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100-Pin TQFP Capacitance
(TA = +25° C, f = 1.0MHz)
Recommended Operating
Temperature Supply Voltage
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6 . This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Recommended DC Operating
Conditions
NOTE:
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol
Rating
Commercial
Unit
V
TERM
(2) Te rminal Voltage with
Re s p e ct to GND -0.5 to +4.6 V
V
TERM
(3,6) Terminal Voltage with
Re s p e ct to GND -0. 5 to V
DD
V
V
TERM
(4,6) Terminal Voltage with
Re s p e ct to GND -0. 5 to V
DD
+0.5 V
V
TERM
(5,6) Terminal Voltage with
Re s p e ct to GND -0. 5 to V
DDQ
+0.5 V
T
A
(7) Operating Temperature -0 to + 70 oC
T
BIAS
Temperature
Under Bias -55 to +125 oC
T
STG
Storage
Temperature -55 to +125 oC
P
T
Power Dissipation 2.0 W
I
OUT
DC Outp ut Curre nt 50 mA
5309 tbl 03
Grade
Temperature
(1)
V
SS
V
DD
V
DDQ
Co mme rcial 0°C to + 70° C 0V 3.3V± 5% 3.3V± 5%
Indus trial -40°C to +85° C 0V 3.3V± 5% 3. 3V± 5%
5 309 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Core Sup p ly Voltage 3.135 3.3 3.465 V
V
DDQ
I/O Sup p ly Vo ltage 3.135 3.3 3. 465 V
V
SS
Supply Voltage 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0 ____ V
DD
+0.3 V
V
IH
Input High V oltage - I/O 2.0 ____ V
DDQ
+0.3 V
V
IL
Inp ut Low Vo ltag e -0.3(1) ____ 0.8 V
5309 tbl 05
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap ac itanc e
V
IN
= 3d V
5
pF
C
I/O
I/O Cap acitanc e
V
OUT
= 3d V
7
pF
5309 t bl 07
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap acitanc e
V
IN
= 3dV
7
pF
C
I/O
I/O Cap aci tance
V
OUT
= 3dV
7
pF
5309 t bl 0 7a
119 BGA Capacitance
(TA = +25° C, f = 1.0MHz)
NOTE:
1. TA is the "instant on" case temperature.
165 fBGA Capacitance
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap acitanc e
V
IN
= 3dV
7
pF
C
I/O
I/O Cap aci tance
V
OUT
= 3dV
7
pF
5309 t bl 07b
6.42
5
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration  256K x 36, 100-Pin TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
16
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/OP4
I/O31
I/O30
VDDQ
VSS
I/O29
I/O28
I/O27
I/O26
VSS
VDDQ
I/O25
I/O24
VSS(1)
VDD
I/O23
I/O22
VDDQ
VSS
I/O21
I/O20
I/O19
I/O18
VSS
VDDQ
I/O17
I/O16
I/OP3 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
VSS
I/O15
A
15
5309 drw 02a
NC
NC
,
A
17
NC
6.426
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration  512K x 18, 100-Pin TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
NC
NC
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
17
NC
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
NC
VDDQ
VSS
NC
I/OP2
I/O15
I/O14
VSS
VDDQ
I/O13
I/O12
VSS
VDD
I/O11
I/O10
VDDQ
VSS
I/O9
I/O8
NC
NC
VSS
VDDQ
NC
NC
NC 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
ZZ(2)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
VSS(1)
NC
A
16
5309 drw 02b
NC
NC
,
A
18
NC NC
6.42
7
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
1234567
AVDDQ A6A4ADSP A8A16 VDDQ
BNC CS0(4) A3ADSC A9A18 NC
CA7A2VDD A13 A17 NC
DI/O8NC VSS NC VSS I/OP1 NC
ENC I/O9VSS CE VSS NC I/O7
FVDDQ NC VSS OE VSS I/O6VDDQ
GNC I/O10 ADVBW2NC I/O5
HI/O11 NC VSS GW VSS I/O4NC
JVDDQ VDD NC VDD NC VDD VDDQ
KNC I/O12 VSS CLK VSS NC I/O3
LI/O13 NC NC BW1I/O2NC
MVDDQ I/O14 VSS BWE VSS NC VDDQ
NI/O15 NC VSS A1VSS I/O1NC
PNC I/OP2 VSS A0VSS NC I/O0
RNC A5LBO VDD NCA12
VSS
TNC A10 A15 NC A14 A11 ZZ
UVDDQ DNU(3) DNU(3) DNU(3) DNU(3) DNU(3) VDDQ
5309 drw 02d
NC
VSS
VSS
,
(1)
(2)
Pin Configuration  512K x 18, 119 BGA
Pin Configuration  256K x 36, 119 BGA
Top View
Top View
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. T7 can be left unconnected and the device will always remain in active mode.
3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
4. On future 18M devices CS0 will be removed, B2 will be used for address expansion.
1234567
AVDDQ A6A4ADSP A8A16 VDDQ
BNC CS0(4) A3ADSC A9NC
CA7A2VDD A12 A15 NC
DI/O16 I/OP3 VSS NC VSS I/OP2 I/O15
EI/O17 I/O18 VSS CE VSS I/O13 I/O14
FVDDQ I/O19 VSS OE VSS I/O12 VDDQ
GI/O20 I/O21 BW3ADV BW2I/O11 I/O10
HI/O22 I/O23 VSS GW VSS I/O9I/O8
JVDDQ VDD NC VDD NC VDD VDDQ
KI/O24 I/O26 VSS CLK VSS I/O6I/O7
LI/O25 I/O27 BW4NC BW1I/O4I/O5
MVDDQ I/O28 VSS BWE VSS I/O3VDDQ
NI/O29 I/O30 VSS A1VSS I/O2I/O1
PI/O31 I/OP4 VSS A0VSS I/O 0
I/O
P1
RNC A5LBO VDD NCA13
TNC NC A10 A11 A14 NC ZZ
UVDDQ DNU(3) DNU(3) DNU(3) DNU(3) DNU(3) VDDQ
NC
VSS
5309 drw 02c
A17
(1)
(2)
6.428
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration  512K x 18, 165 fBGA
Pin Configuration  256K x 36, 165 fBGA
1234567891011
ANC
(3) A7CE BW3BW2CS1BWE ADSC ADV A8NC
BNC A
6CS0BW4BW1CLK GW OE ADSP A9NC(3)
CI/O
P3 NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP2
DI/O
17 I/O16 VDDQ VDD VSS VSS VSS VDD VDDQ I/O15 I/O14
EI/O
19 I/O18 VDDQ VDD VSS VSS VSS VDD VDDQ I/O13 I/O12
FI/O
21 I/O20 VDDQ VDD VSS VSS VSS VDD VDDQ I/O11 I/O10
GI/O
23 I/O22 VDDQ VDD VSS VSS VSS VDD VDDQ I/O9I/O8
HV
SS(1) NC NC VDD VSS VSS VSS VDD NC NC ZZ(2)
JI/O
25 I/O24 VDDQ VDD VSS VSS VSS VDD VDDQ I/O7I/O6
KI/O
27 I/O26 VDDQ VDD VSS VSS VSS VDD VDDQ I/O5I/O4
LI/O
29 I/O28 VDDQ VDD VSS VSS VSS VDD VDDQ I/O3I/O2
MI/O
31 I/O30 VDDQ VDD VSS VSS VSS VDD VDDQ I/O1I/O0
NI/O
P4 NC VDDQ VSS NC NC(3) NC VSS VDDQ NC I/OP1
PNCNC
(3) A5A2DNU(4) A1DNU(4) A10 A13 A14 A17
RLBO NC(3) A4A3DNU(4) A0DNU(4) A11 A12 A15 A16
5309 tbl 1 7a
1234567891011
ANC
(3) A7CE BW2NC CS1BWE ADSC ADV A8A10
BNC A
6CS0NC BW1CLK GW OE ADSP A9NC(3)
CNC NCV
DDQ VSS VSS VSS VSS VSS VDDQ NC I/OP1
DNC I/O
8VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O7
ENC I/O
9VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O6
FNCI/O
10 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O5
GNC I/O
11 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O4
HV
SS(1) NC NC VDD VSS VSS VSS VDD NC NC ZZ(2)
JI/O
12 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O3NC
KI/O
13 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O2NC
LI/O
14 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O1NC
MI/O
15 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O0NC
NI/O
P2 NC VDDQ VSS NC NC(3) NC VSS VDDQ NC NC
PNCNC
(3) A5A2DNU(4) A1DNU(4) A11 A14 A15 A18
RLBO NC(3) A4A3DNU(4) A0DNU(4) A12 A13 A16 A17
5309 tbl 17 b
NOTES:
1. H1 does not have to be directly connected to VSS, as long as the input voltage is < VIL.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
6.42
9
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5309 drw 05
,
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
5309 drw 03
,
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|I
L
I
| Input Leakage Curre nt V
DD
= Max., V
IN
= 0V to V
DD
___ 5µA
|I
LI
|LBO Input Le ak age Current(1) V
DD
= Max., V
IN
= 0V to V
DD
___ 30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
CC
___ 5µA
V
OL
Outp ut Low Vo ltage I
OL
= +8mA, V
DD
= Min. ___ 0.4 V
V
OH
Outp ut Hig h Vo ltag e I
OH
= -8mA, V
DD
= Min. 2. 4 ___ V
5309 tb l 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load
AC Test Conditions
(VDDQ = 3.3V/2.5V)
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ in will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
Symbol Parameter Test Conditions
7.5ns 8ns 8.5ns Unit
Com'l Ind Com'l Ind Com'l Ind
IDD Operating Power Supply Current Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
(2)
265 285 210 230 190 210 mA
ISB1 CMOS Standby Power Supply Current Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0
(2,3)
50 70 50 70 50 70 mA
ISB2 Clock Running Power Supply Current Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX
(2,.3)
145 165 140 160 135 155 mA
IZZ Full Sleep Mode Supply Current ZZ > VHD, VDD = Max . 50 70 50 70 50 70 mA
5309 tbl 09
Inp ut P ul se Lev e ls
Inp ut Ri s e /Fal l Tim e s
Inp ut Tim ing Re fe re nc e Le v e ls
Outp ut Timing Reference Le ve ls
AC Test Load
0 to
3V
2ns
1.5V
1.5V
See Figure 1
5309 tbl 10
6.4210
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1,3)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ - low for the table.
Operation
Address
Used
CE
CS
0
CS
1
ADSP ADSC ADV GW BWE BW
x
OE
(2)
CLK
I/O
De s e l e c te d Cy c l e , P o we r Do wn No n e H X X X L X X X X X ↑HI-Z
De s e l e c te d Cy c l e , P o we r Do wn No n e L X H L X X X X X X ↑HI-Z
De s e l e c te d Cy c l e , P o we r Do wn No n e L L X L X X X X X X ↑HI-Z
De s e l e c te d Cy c l e , P o we r Do wn No n e L X H X L X X X X X ↑HI-Z
De s e l e c te d Cy c l e , P o we r Do wn No n e L L X X L X X X X X ↑HI-Z
Read Cycle, Begin Burst External L H L L X X X X X L ↑DOUT
Read Cycle, Begin Burst External L H L L X X X X X H ↑HI-Z
Read Cycle, Begin Burst External L H L H L X H H X L ↑DOUT
Read Cycle, Begin Burst External L H L H L X H L H L ↑DOUT
Read Cycle, Begin Burst External L H L H L X H L H H ↑HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X ↑DIN
Write Cycle, Begin Burst External L H L H L X L X X X ↑DIN
Re ad Cycle , Co ntinue Burs t Ne xt X X X H H L H H X L ↑DOUT
Re ad Cycle , Co ntinue Burs t Ne xt X X X H H L H H X H ↑HI-Z
Re ad Cycle , Co ntinue Burs t Ne xt X X X H H L H X H L ↑DOUT
Re ad Cycle , Co ntinue Burs t Ne xt X X X H H L H X H H ↑HI-Z
Re ad Cycle , Co ntinue Burs t Ne xt H X X X H L H H X L ↑DOUT
Re ad Cycle , Co ntinue Burs t Ne xt H X X X H L H H X H ↑HI-Z
Re ad Cycle , Co ntinue Burs t Ne xt H X X X H L H X H L ↑DOUT
Re ad Cycle , Co ntinue Burs t Ne xt H X X X H L H X H H ↑HI-Z
Write Cycle, Continue Burst Next X X X H H L H L L X ↑DIN
Write Cycle, Continue Burst Next X X X H H L L X X X ↑DIN
Write Cycle, Continue Burst Next H X X X H L H L L X ↑DIN
Write Cycle, Continue Burst Next H X X X H L L X X X ↑DIN
Read Cycle, Suspend Burst Current X X X H H H H H X L ↑DOUT
Read Cycle, Suspend Burst Current X X X H H H H H X H ↑HI-Z
Read Cycle, Suspend Burst Current X X X H H H H X H L ↑DOUT
Read Cycle, Suspend Burst Current X X X H H H H X H H ↑HI-Z
Read Cycle, Suspend Burst Current H X X X H H H H X L ↑DOUT
Read Cycle, Suspend Burst Current H X X X H H H H X H ↑HI-Z
Read Cycle, Suspend Burst Current H X X X H H H X H L ↑DOUT
Read Cycle, Suspend Burst Current H X X X H H H X H H ↑HI-Z
Write Cycle, Suspend Burst Current X X X H H H H L L X ↑DIN
Write Cycle, Suspend Burst Current X X X H H H L X X X ↑DIN
Write Cycle, Suspend Burst Current H X X X H H H L L X ↑DIN
Write Cycle, Suspend Burst Current H X X X H H L X X X ↑DIN
5309 tbl 11
6.42
11
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table ( LBO=VSS)
Synchronous Write Function Truth Table (1, 2)
Asynchronous Truth Table
(1)
Interleaved Burst Sequence Table ( LBO=VDD)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67903.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation GW BWE BW1BW2BW3BW4
Read HHXXXX
Read HLHHHH
Write all Bytes LXXXXX
Write all Bytes HLLLLL
Write Byte 1
(3)
HLLHHH
Write Byte 2
(3)
HLHLHH
Write Byte 3
(3)
HLHHLH
Write Byte 4
(3)
HLHHHL
5 3 09 t b l 12
Operation
(2)
OE ZZ I/ O Status Power
Re ad L L Data Out A ctiv e
Read H L High-Z Active
Wr it e X L Hi g h -Z – D ata In A c ti v e
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sleep
5 3 09 t b l 13
S equence 1 S equence 2 Seq ue nce 3 S equence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Ad dress 0 0 0 1 1 0 1 1
Seco nd Add ress 0 1 0 0 1 1 1 0
Third Add res s 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
5 3 09 t b l 14
S equence 1 S equence 2 Seq ue nce 3 S equence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Ad dress 0 0 0 1 1 0 1 1
Seco nd Add ress 0 1 1 0 1 1 0 0
Third Add res s 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
5 3 09 t b l 15
6.4212
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 3.3V ±5%, Commercial and Industrial
Temperature Ranges)
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Cl ock Parameter
t
CYC
Clock Cycle Time 8.5 ____ 10 ____ 11.5 ____ ns
t
CH
(1) Clock High Pulse Width 3 ____ 4____ 4.5 ____ ns
t
CL
(1) Clock Low Pulse Width 3 ____ 4____ 4.5 ____ ns
Output Parameters
t
CD
Clo ck Hig h to Valid Data ____ 7.5 ____ 8____ 8.5 ns
t
CDC
Clo c k Hi g h to Data Ch ang e 2 ____ 2____ 2____ ns
t
CLZ
(2) Clock High to Output Active 0 ____ 0____ 0____ ns
t
CHZ
(2) Cl o ck Hig h to Data Hi g h-Z 2 3. 5 2 3. 5 2 3. 5 ns
t
OE
Output Enable Access Time ____ 3.5 ____ 3.5 ____ 3.5 ns
t
OLZ
(2) Outp ut Enab le Low to Outp ut Ac tive 0 ____ 0____ 0____ ns
t
OHZ
(2) Outp ut Enab le High to Output High-Z ____ 3.5 ____ 3.5 ____ 3.5 ns
Se t Up T imes
t
SA
Address Setup Time 1.5 ____ 2____ 2____ ns
t
SS
Address Status Setup Time 1.5 ____ 2____ 2____ ns
t
SD
Data In S e tup Ti me 1. 5 ____ 2____ 2____ ns
t
SW
Write Setup Time 1.5 ____ 2____ 2____ ns
t
SAV
Address Advance Setup Time 1.5 ____ 2____ 2____ ns
t
SC
Chip Enable/Select Setup Time 1.5 ____ 2____ 2____ ns
Hold T imes
t
HA
Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HS
Address Status Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HD
Data In Ho l d Ti me 0. 5 ____ 0.5 ____ 0.5 ____ ns
t
HW
Write Hold Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
t
HAV
Address Advance Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HC
Chip Enab le /Sele ct Hold Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
Sleep M od e and Co n fi g ur ation Pa ramet ers
t
ZZPW
ZZ Pulse Width 100 ____ 100 ____ 100 ____ ns
t
ZZR
(3) ZZ Re co v e ry Time 100 ____ 100 ____ 100 ____ ns
t
CFG
(4) Confi guratio n Set-up Time 34 ____ 40 ____ 50 ____ ns
5309 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.42
13
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base
address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Flow-Through Read Cycle (1,2)
t
CHZ
t
SA
t
SC
t
HS
G
W,BWE,BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSP
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay) O2(Ay)
O2(Ay)
ADV
CE,CS
1
(Note 3)
Flow-through
Read
Burst Flow-through Read
Output
Disabled
AxAy
t
SS
O1(Ay)
O4(Ay)
O3(Ay)
(Burst wraps around
to its initial state)
5309drw 06
ADVHIGHsuspendsburst
,
6.4214
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
O1(Az)
CLK
ADSP
ADDRESS
GW
ADV
OE
DATA
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DATA
IN
(2)
t
OE
O1(Az)
Single Read Flow-through Burst Read
Write
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az) O4(Az)
O1(Ax)
5309 drw 07
t
CD
,
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
6.42
15
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 - GW Controlled (1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DATA
OUT
OE
t
HC
t
SD
I1(Ax) I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O4(Aw)
CE,CS
1
t
HW
GW
t
SW
(Note 3)
I2(Az) I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVsuspends burst)
I1(Ay)
t
SC
(1)
(2)
O3(Aw)
5309 drw 08
GWis ignored when ADSPinitiates acycle and is sampled on the next cycle rising edge
,
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.4216
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled (1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
t
HW
BWx
ADV
DATA
OUT
OE
t
HC
t
SD
Single
Write Burst Write
I1(Ax) I2(Ay) I2(Ay) I2(Az)
tHD
Burst
ReadExtended
Burst Write
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,C
S
1
t
HW
BWEt
SW
(Note 3)
I1(Az)
Az
I4(Ay)
I1(Ay) I4(Ay)
I3(Ay)
t
SC
BWEis ignored when ADSPinitiates acycle and is sampled on the next cycle risingedge
BWxis ignoredwhen ADSPinitiates acycle and is sampled on the next clock rising edge
I3(Az)
O3(Aw)
5309 drw 09
(ADVHIGHsuspends burst)
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2 . O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address
Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
17
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
A
DDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
Single Read Snooze Mode
tZZPW
5309 drw 13
O1(Ax)
Ax
(Note 4)
tZZR
Az
,
NOTES:
1. Device must power up in deselected Mode.
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
6.4218
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
GW,BW E,BW x
CE,CS1
CS0
ADDRESS
ADSC
DATAOUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
5309 drw 10 ,
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE,CS1
CS0
ADDRESS
ADSC
DATAIN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
5309 drw 11 ,
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
19
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.4220
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
21
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.4222
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Ordering Information
100-Pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 fine pitch Ball Grid Array (fBGA)
S
Power
X
Speed
XX
Package
PF
BG
BQ
XXX
75
80
85 Access Time in Tenths of Nanoseconds
5309 drw 12
Device
Type
71V67703
71V67903 256K x 36 Flow-Through Burst Synchronous SRAM
512K x 18 Flow-Through Burst Synchronous SRAM ,
X
Process/
Temperature Rance
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
6.42
23
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 800-544-7726
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
12/31/99 Created Datasheet from 71V677 and 71V679 Datasheets
For 2.5V I/O offering, see 71V67702 AND 71V67902 Datasheets.
04/26/00 Pg. 4 Add capacitance for BGA package; Insert clarification note to Absolute Max Ratings and Recommended
Operating Temperature tables.
Pg. 7 Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout
Pg. 18 Inserted 100 pin TQFP Package Diagram Outline
05/24/00 Pg. 1,4,8,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correct note 2 on BGA and TQFP pin configuration
Pg. 20 Correction in the 119 BGA Package Diagram Outline
07/12/00 Pg. 5,6,8 Remove note from TQFP and BQ165 pinouts
Pg. 7 Add/Remove note from BG119 pinout
Pg. 20 Update BG 119 pinout
12/18/00 Pg. 9 Updated ISB2 levels for 7.5-8.5ns.
10/29/01 Pg. 1,2 Remove JTAG pins
Pg. 7 Changed U2-U6 pins to DNU.
Pg. 8 Changed P5,P7,R5 & R7 to DNU pins.
Pg. 9 Raised specs by 10mA on 7.5ns, 8ns and 8.5ns.
10/22/02 Pg. 1-23 Changed datasheet from Advanced to Final Release.
Pg. 4,9,12, Added I temp to datasheet.
22
04/15/03 Pg. 4 Updated 165 fBGA table from TBD to 7.
12/20/03 Pg. 7 Updated 119BGS pin configurations- reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7,
H6, G7, F6, E7, D6 (256K x 18).