MTP7N20E-D - ON Semiconductor - Datasheet.Directory

 Semiconductor Components Industries, LLC, 2000

November, 2000 – Rev. 1 1Publication Order Number:

MTP7N20E/D

MTP7N20E

Preferred Device

Power MOSFET

7 Amps, 200 Volts

N–Channel TO–220

This Power MOSFET is designed to withstand high energy in the

avalanche and commutation modes. The energy efficient design also

offers a drain–to–source diode with a fast recovery time. Designed for

low voltage, high speed switching applications in power supplies,

converters and PWM motor controls, these devices are particularly

well suited for bridge circuits where diode speed and commutating

safe operating areas are critical and offer additional safety margin

against unexpected voltage transients.

•Avalanche Energy Specified

•Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

•Diode is Characterized for Use in Bridge Circuits

•IDSS and VDS(on) Specified at Elevated Temperature

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain–to–Source Voltage VDSS 200 Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 200 Vdc

Gate–to–Source Voltage

– Continuous

– Non–Repetitive (tp ≤ 10 ms) VGS

VGSM ±20

±40 Vdc

Vpk

Drain Current

– Continuous

– Continuous @ 100°C

– Single Pulse (tp ≤ 10 µs)

IDM

7.0

3.8

Adc

Apk

Total Power Dissipation @ TC = 25°C

Derate above 25°CPD50

0.4 Watts

W/°C

Operating and Storage Temperature

Range TJ, Tstg –55 to

150 °C

Single Pulse Drain–to–Source Avalanche

Energy – Starting TJ = 25°C

(VDD = 80 Vdc, VGS = 10 Vdc, Peak

IL = 7.0 Adc, L = 10 mH, RG = 25 Ω)

EAS 74 mJ

Thermal Resistance

– Junction to Case°

– Junction to Ambient°RθJC

RθJA 2.5°

62.5°

°C/W

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10

seconds

TL260 °C

7 AMPERES

200 VOLTS

RDS(on) = 700 mΩ

Preferred devices are recommended choices for future use

and best overall value.

Device Package Shipping

ORDERING INFORMATION

MTP7N20E TO–220AB 50 Units/Rail

TO–220AB

CASE 221A

STYLE 5

123

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N–Channel

MARKING DIAGRAM

& PIN ASSIGNMENT

MTP7N20E = Device Code

LL = Location Code

Y = Year

WW = Work Week

MTP7N20E

LLYWW

Gate 3

Source

Drain

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ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mAdc)

Temperature Coefficient (positive)

V(BR)DSS 200

––

689 –

–Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 200 Vdc, VGS = 0 Vdc)°

(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125°C)

IDSS –

––

–10

100

µAdc

Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS – – 100 nAdc

ON CHARACTERISTICS (Note 1.)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)

Temperature Coefficient (negative)µ

VGS(th) 2.0

–3.1

7.1 4.0

–Vdc

mV/°C

Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 3.5 Adc) RDS(on) – 0.46 0.7 Ohm

Drain–to–Source On–Voltage

(VGS = 10 Vdc, ID = 7.0 Adc)°

(VGS = 10 Vdc, ID = 3.5 Adc, TJ = 125°C)

VDS(on) –

–3.4

–5.9

5.1

Vdc

Forward Transconductance (VDS = 14 Vdc, ID = 3.5 Adc) gFS 1.5 – – mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(V 25 Vd V 0 Vd

Ciss – 342 480 pF

Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,

f=10MHz)

Coss – 92 130

Reverse Transfer Capacitance

)

Crss – 27 55

SWITCHING CHARACTERISTICS (Note 2.)

Turn–On Delay Time td(on) – 8.8 17.6 ns

Rise Time (V

= 100 Vdc, I

= 7.0 Adc, tr– 29 58

Turn–Of f Delay Time

(VDD

100

Vdc

Adc

VGS = 10 Vdc, Rg = 9.1 Ω)td(off) – 22 44

Fall Time

GS g )

tf– 20 40.8

Gate Charge QT– 13.7 21 nC

(See Figure 8)

(

= 160 Vdc, I

= 7.0 Adc, Q1– 3.3

(VDS

160

Vdc

Adc

VGS = 10 Vdc) Q2– 6.6 –

GS )

Q3– 5.9 –

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (Note 1.) (IS = 7.0 Adc, VGS = 0 Vdc)

(IS = 7.0 Adc, VGS = 0 Vdc,

TJ = 125°C)

VSD –

–1.02

0.9 1.2

–

Vdc

Reverse Recovery Time trr – 138 – ns

e e se eco e y e

(See Figure 14)

(I 7 0 Adc V 0 Vdc

ta– 93 –

(IS = 7.0 Adc, VGS = 0 Vdc,

dIS/dt

100 A/µs)

tb– 45 –

Reverse Recovery Stored

Charge

/dt

100

QRR – 0.74 – µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)″

(Measured from the drain lead 0.25″ from package to center of die)

Ld–

–3.5

4.5 –

–

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad.) Ls– 7.5 –

1. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2.0%.

2. Switching characteristics are independent of operating junction temperature.

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TYPICAL ELECTRICAL CHARACTERISTICS

RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

Figure 3. On–Resistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

Figure 5. On–Resistance Variation with

Temperature

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source Leakage

Current versus Voltage

IDSS , LEAKAGE (nA)

TJ = 25°C

VGS = 10 V

15 V

0.55

VGS = 0 V

0 100 150

100

50 200

TJ = 125°C

0.7

0.65

0.6

412826 1410

100°C

I , DRAIN CURRENT (AMPS)

004 81262

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS = 10 V

7 V

6 V

8 V

5 V

TJ = 25°C

I , DRAIN CURRENT (AMPS)

0324 6810

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS ≥ 10 V -55°C

TJ = 100°C

RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)

1.2

0.8

0.4

002468

ID, DRAIN CURRENT (AMPS)

VGS = 10 V

TJ = 25°C

100°C

-55°C0.5

0.4

RDS(on), DRAIN-TO-SOURCE RESISTANCE

(NORMALIZED)

TJ, JUNCTION TEMPERATURE (°C)

VGS = 10 V

ID = 3.5 A

-50 0 50 100 150125-25 25 75

2.5

1.5

0.5

9 V

25°C

579

1.0

0.6

0.2

10 12 14

0.45

25°C

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (∆t)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain–gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (IG(AV)) can be made from a

rudimentary analysis of the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a

resistive load, VGS remains virtually constant at a level

known a s the plateau voltage, VSGP. Therefore, rise and fall

times may be approximated by the following:

tr = Q2 x RG/(VGG – VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG – VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve a t

a voltage corresponding to the off–state condition when

calculating t d(on) and is read at a voltage corresponding to the

on–state when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is a ffected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

C, CAPACITANCE (pF)

10 0 10 15 25

VGS VDS

TJ = 25°C

VDS = 0 V

VGS = 0 V

600

300

020

Ciss

Coss

Crss

Ciss

Crss

900

450

150

750

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QG, TOTAL GATE CHARGE (nC)

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

IS, SOURCE CURRENT (AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

0.5 0.9 1.0

0.8 1.10.6 0.7

VGS = 0 V

TJ = 25°C

002 4 6 8 14

180

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS

)

VGS , GATE-TO-SOURCE VOLTAGE (VOLTS)

150

TJ = 25°C

ID = 7 A

VGS

t, TIME (ns)

1000

100

11 10 100

RG, GATE RESISTANCE (OHMS)

TJ = 25°C

ID = 7 A

VDS = 100 V

VGS = 10 V

td(off)

td(on)

VDS

10 12

120

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

junction temperature and a case temperature (TC) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal

Resistance–General Data and Its Use.”

Switching between the off–state and the on–state may

traverse any load line provided neither rated peak current

(IDM) nor rated voltage (VDSS) is exceeded and the

transition time (tr,tf) do not exceed 10 µs. In addition the total

power averaged over a complete switching cycle must not

exceed (TJ(MAX) – TC)/(RθJC).

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored ener gy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and adjusted for operating conditions

differing from those specified. Although industry practice is

to rate in terms of energy, avalanche energy capability is not

a constant. The energy rating decreases non–linearly with an

increase of peak current in avalanche and peak junction

temperature.

Although many E–FETs can withstand the stress of

drain–to–source avalanche at currents up to rated pulsed

current (IDM), the energy rating is specified at rated

continuous current (ID), in accordance with industry

custom. The ener gy rating must be derated for temperature

as shown in the accompanying graph (Figure 12). Maximum

energy at currents below rated continuous ID can safely be

assumed to equal the values indicated.

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SAFE OPERATING AREA

Figure 14. Diode Reverse Recovery Waveform

di/dt

trr

0.25 IS

TIME

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 13. Thermal Response

, SINGLE PULSE DRAIN-TO-SOURCE

TJ, STARTING JUNCTION TEMPERATURE (°C)

AVALANCHE ENERGY (mJ)

ID = 7A

25 50 75 100 125 150

100

0.1

0.1 1 10 100 1000

100 µs

10 µs

1 ms

10 ms

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT

VGS = 20 V

SINGLE PULSE

TC = 25°C

0.1

0.010.00001 0.0001 0.001 0.01 0.1 1 10

t, TIME (SECONDS)

D = 0.5

0.2

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

(NORMALIZED)

0.1

0.05

0.02

0.01

RθJC(t) = r(t) RθJC

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) - TC = P(pk) RθJC(t)

P(pk)

t1t2

DUTY CYCLE, D = t1/t2

SINGLE PULSE

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PACKAGE DIMENSIONS

TO–220 THREE–LEAD

TO–220AB

CASE 221A–09

ISSUE AA

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE

ALLOWED.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.570 0.620 14.48 15.75

B0.380 0.405 9.66 10.28

C0.160 0.190 4.07 4.82

D0.025 0.035 0.64 0.88

F0.142 0.147 3.61 3.73

G0.095 0.105 2.42 2.66

H0.110 0.155 2.80 3.93

J0.018 0.025 0.46 0.64

K0.500 0.562 12.70 14.27

L0.045 0.060 1.15 1.52

N0.190 0.210 4.83 5.33

Q0.100 0.120 2.54 3.04

R0.080 0.110 2.04 2.79

S0.045 0.055 1.15 1.39

T0.235 0.255 5.97 6.47

U0.000 0.050 0.00 1.27

V0.045 --- 1.15 ---

Z--- 0.080 --- 2.04

123

SEATING

PLANE

–T–

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