C1
10PFx2
L1
4.7PH
OUTP
VIN
2.9V to 4.5V C2
10PF
VPOS
4.62V/300mA
PGND VNEG
-4.9V/300mA
GND
CT C3
10PF x 2
C4
100nF
PVIN SWP
TPS65138
CTRL
L2
4.7PH
SWN
OUTN
VL
Enable and
Program VNEG C5
100nF
TPS65138
TPS65138A
www.ti.com
SLVSAV3C –APRIL 2011–REVISED MAY 2012
Dual output AMOLED Display Power Supply
Check for Samples: TPS65138,TPS65138A
1FEATURES APPLICATIONS
• 2.9V to 4.5V Input Voltage Range • Active Matrix OLED
• 0.8% Output Voltage Accuracy VPOS
• Excellent Line Transient Regulation
• 300mA Output Current
• Fixed 4.62V Positive Output Voltage
• Digitally Programmable VNEG
– TPS65138: -2.2V to -6.2V
– TPS65138A: -2.2V to -5.2V
• -4.9V Default Value for VNEG
• Short Circuit Protection
• Thermal Hhutdown
• 3-mm × 3-mm QFN Package
DESCRIPTION
The TPS65138 is designed to drive AMOLED displays (Active Matrix Organic Light Emitting Diode) requiring
positive and negative supply rails. The device integrates boost converter and inverting buck boost converter
designed suitable for battery operated products. The digital control pin (CTRL) allows programming the negative
output voltage in digital steps. The TPS65138 uses a novel technology enabling excellent line and load
regulation. This is required to avoid disturbance of the AMOLED display by the input voltage disturbances
occurring during transmit periods in mobile phones.
TYPICAL APPLICATION SCHEMATIC
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65138
TPS65138A
SLVSAV3C –APRIL 2011–REVISED MAY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
VNEG PROGRAMMING ORDERABLE PART
TAPACKAGE(2) TOP-SIDE MARKING
RANGE NUMBER
-2.2V ~ -6.2V 10-Pin 3x3 QFN TPS65138DRCR PUCC
-40°C to +85° -2.2V ~ -5.2V TPS65138ADRCR PXJI
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
MIN MAX
PVIN, SWP, OUTP, CTRL, VL 5.5
OUTN –6.5
Voltage range(2) V
SWN –6.5 4.8
CT 3.6
HBM ±2 kV
ESD rating MM ±200 V
CDM ±500 V
Operating junction temperature range, TJ–40 50 °C
Operating ambient temperature range, TA–40 85 °C
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND pin
THERMAL INFORMATION(1)
DRC
THERMAL METRIC UNITS
10-PINS
θJA Junction-to-ambient thermal resistance 54.7
θJB Junction-to-board thermal resistance 16.9 °C/W
ψJT Junction-to-top characterization parameter 4.2
ψJB Junction-to-board characterization parameter 19.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
2Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS65138 TPS65138A
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TPS65138A
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SLVSAV3C –APRIL 2011–REVISED MAY 2012
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VIN Input voltage range 2.9 3.7 4.5 V
TAOperating ambient temperature –40 25 95 °C
TJOperating junction temperature –40 85 125 °C
ELECTRICAL CHARACTERISTICS
VIN = 3.7V, CTRL = VIN, VPOS = 4.62V, VNEG = –4.9V, TA= –40°C to 95°C, typical values are at TA= 25°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Current and Thermal Protection
VIN Input voltage range 2.9 4.5 V
IQOperating quiescent current into VIN VPOS and VNEG have no load (1) 13 mA
ISD Shutdown current into VIN CTRL = GND 0.1 µA
VLOutput of internal regulator 5 V
VIN falling 2.1 V
VUVLO Under-voltage lockout threshold VIN rising 2.4 V
Thermal shutdown 145 °C
Thermal shutdown hysteresis 10 °C
Output VPOS Positive output voltage 4.62 V
VPOS Positive output voltage regulation TA= –40°C to 85°C –0.8% 0.8%
SWP MOSFET on-resistance ISWP = 200mA 200 mΩ
rDS(on) SWN MOSFET rectifier on-resistance ISWP = 200mA 250 mΩ
fSWP SWP Switching frequency IPOS = 0mA 1.6 MHz
ISWP SWP switch current limit Inductor valley current 0.8 1 A
VP(SCP) Short circuit threshold in operation VPOS falling 3.7 V
Short circuit detection time in operation 8 ms
tP(SCP) Short circuit detection time in operation 3 ms
ILKG Leakage current into VPOS CTRL = GND 2 5 µA
Line regulation IPOS = 400mA 0 %/V
Load regulation 0 %/A
(1) With Inductor DFE252012C 4.7µH from TOKO
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
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TPS65138
TPS65138A
SLVSAV3C –APRIL 2011–REVISED MAY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7V, CTRL = VIN, VPOS = 4.62V, VNEG = –4.9V, TA= –40°C to 95°C, typical values are at TA= 25°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output VNEG Negative output voltage default –.94 V
TPS65138 –2.2 –6.2 V
Negative output voltage range TPS65138A –2.2 –5.2 V
VNEG TPS65138, -6.2 ≤VNEG ≤-4.2 –1% 1%
Negative output voltage regulation TPS65138A, -5.2 ≤VNEG ≤-4.2 –1% 1%
-4.2 ≤VNEG ≤-2.2 –1.5% 1.5%
SWN MOSFET on-resistance ISWN = 200 mA 200 mΩ
rDS(on) SWN MOSFET rectifier on-resistance ISWN = 200 mA 300 mΩ
SWN Switching frequency INEG = 100 mA 1.6 MHz
fSWN SWN switch current limit VIN = 2.9 V 1.8 2.2 A
Short circuit threshold in operation –1 V
VN(SCP) Short circuit threshold in start-up 0.15 0.28 0.42 V
Short circuit detection time in start-up 8 V
tN(SCP) Short circuit detection time in operation 3 ms
ILKG Leakage current out of VNEG CTRL = GND 2 5 µA
RN(PD) VNEG Pull down resistor before start up INEG = 1 mA 270 Ω
Line regulation 0 %/V
Load regulation 0 %/A
CTRL Interface
VHLogic high-level voltage 1.2 V
VLLogic low-level voltage 0.4 V
R Pull down resistor 150 400 860 KΩ
tINIT Initialization time 300 400 µs
tOFF Shutdown time period 30 80 µs
tHIGH Pulse high level time period 2 10 25 µs
tLOW Pulse low level time period 2 10 25 µs
tSTORE Data storage and accept time period 30 80 µs
RTCTpin output impedance 150 325 500 kΩ
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Product Folder Links: TPS65138 TPS65138A
Exposed
Thermal Pad
1
2
SWN
3
4
OUTN
CTRL
10
9
8
7
PGND
OUTP
CT
SWP
56GND
PVIN
VL
TPS65138
TPS65138A
www.ti.com
SLVSAV3C –APRIL 2011–REVISED MAY 2012
PINOUT
(TOP VIEW)
PIN FUNCTIONS
NUMBER NAME TYPE(1) DESCRIPTION
1 PVIN I Input supply for the negative buck boost converter generating VNEG
2, SWN I Switch pin of the negative buck boost converter
3 OUTN O Output of the negative buck boost converter
4 CTRL O Combined enable and VNEG program pin.
5 VL O Output of internal regulator
6 GND G Analog ground
Sets the settling time for the voltage on VNEG when programmed to a new
7 CT O value.
8 OUTP O Output of the boost converter
9 PGND G Power ground of the boost converter
10 SWP I Switch pin of the boost converter
Exposed thermal G Connect this pad to analog GND.
pad
(1) G = Ground, I = Input, O = Output
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TPS65138 TPS65138A
5
Gate Drive
10
+
+
+
PWM
Control
Current
Sense/
Softstart
Vref
8
Regulator
2
PWM
Control
Gate Drive
6 Bit
DAC
Digital
Interface
Softstart
generation SS
Current
Sense/
Softstart
SS
3
SWN
OUTN
OUTP
SWP
6
GND 9
PGND
PGND
+7
CT
1
PVIN
4
CTRL
VL
SWP
OUTN
PVIN
SS Short Circuit
Protection
Short Circuit
Protection
TPS65138
TPS65138A
SLVSAV3C –APRIL 2011–REVISED MAY 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
6Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS65138 TPS65138A
V
50 mV/Div
POS
400 ns/div
SW
5 V/Div
BOOST
V
5 V/Div
BUCKBOOST
V
50 mV/Div
NEG
V
50 mV/Div
POS
400 ns/div
SW
5 V/Div
BOOST
SW
5 V/Div
BUCKBOOST
V
50 mV/Div
NEG
0
10
20
30
40
50
60
70
80
90
100
0.00 0.05 0.15 0.20 0.30 0.35
I (A)
OUT
Efficiency (%)
Inductor :
XFL402-4.7 Hm
VI= 4.2 V
VI= 3.7 V
VI= 3.2 V
VI= 2.9 V
0.10 0.25
V
2 V/Div
POS
2 ms/div
V
5 V/Div
NEG
I
200 mA/Div
IN
TPS65138
TPS65138A
www.ti.com
SLVSAV3C –APRIL 2011–REVISED MAY 2012
Table 1. TABLE OF GRAPHS
TITLE TEST CONDITIONS FIGURE
Efficiency versus Output current VPOS 4.62 V, VNEG -4.9 V Figure 1
(Output current is from VPOS to VNEG.)
Start-up Figure 2
IOUT 100 mA, Boost and BuckBoost Figure 3
IOUT 300 mA, Boost and BuckBoost Figure 4
Switch pins and output waveforms IOUT 300 mA, Boost Figure 5
IOUT 300 mA, BuckBoost Figure 6
TYPICAL CHARACTERISTICS
Efficiency vs Output Current
(VPOS 4.62 V, VNEG -4.9 V) Start up
Figure 1. Figure 2.
Switch Pins and Outputs Switch Pins and Outputs
Boost and BuckBoost , IOUT 100 mA Boost and BuckBoost, IOUT 300 mA
Figure 3. Figure 4.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TPS65138 TPS65138A
C1
10PFx2
L1
4.7PH
OUTP
VIN
2.9V to 4.5V C2
10PF
VPOS
4.62V/300mA
PGND VNEG
-4.9V/300mA
GND
CT C3
10PF x 2
C4
100nF
PVIN SWP
TPS65138
CTRL
L2
4.7PH
SWN
OUTN
VL
Enable and
Program VNEG C5
100nF
V
50 mV/Div
POS
400 ns/div
SW
5 V/Div
BOOST
I
200 mA/Div
L_BOOST
V
50 mV/Div
NEG
400 ns/div
SW
5 V/Div
BUCKBOOST
I
500 mA/Div
L_BOOST
TPS65138
TPS65138A
SLVSAV3C –APRIL 2011–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Switch Pins and Outputs Switch Pins and Outputs
Boost, IOUT 300 mA BuckBoost, IOUT 300 mA
Figure 5. Figure 6.
spacer
APPLICATION INFORMATION
Figure 7. Application for Typical Characteristics
Table 2. Bill of Materials for Typical Characteristics
Value Part Number Manufacturer
C1 10 µF, X7R GRM21BR70J106KE76 Murata
C2A, C2B, C3A, C3B 4.7 µF, X7R GRM21BR71A475KA73 Murata
C4, C5 100 nF, X7R GRM21BR71E104KA01 Murata
L1, L2 4.7 µH XFL4020-472M Coil Craft
8Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS65138 TPS65138A
VPOS
VNEG
CTRL
8ms Typ.
TPS65138
TPS65138A
www.ti.com
SLVSAV3C –APRIL 2011–REVISED MAY 2012
DETAIL DESCRIPTION
The TPS65138 consists of a boost converter and an inverting buck boost converter. The positive output is fixed
at 4.62V. Negative output is programmable by a digital interface, and TPS65138 has the range of -2.2V to
approximately -6.2V and TPS65138A has the range of -2.2V to approximately -5.2V. Both TPS65138 and
TPS65138A have -4.9V of the default negative output. The transition time of the negative output is adjustable by
the CT pin capacitor.
SOFT START and START-UP SEQUENCE
The device has soft start to limit in rush current. When the device is enabled by CTRL pin going HIGH, the boost
converter starts with reduced switch current limit. 8 ms after CTRL HIGH, Buck boost converter starts with the
default value. VNEG default is –4.9 V. The typical start-up sequence is shown in Figure 8.
Figure 8. Start-up Sequence
SHORT CIRCUIT PROTECTION
The device is protected against short circuits of the outputs to ground and short circuit of the outputs each other.
During normal operation, an error condition is detected if VPOS falls below 3.7 V for more than 3 ms or VNEG is
above -1 V for more than 3 ms. In either case, the device goes into shutdown and this state is latched. Input and
outputs are disconnected. To resume normal operation, VIN has to cycle below UVLO or CTRL has to toggle
LOW and HIGH.
During start up, an error condition is detected in the following cases:
VPOS is not in regulation 8ms after CTRL goes HIGH.
VNEG is higher than threshold level of 8ms after CTRL goes HIGH.
VNEG is not in regulation 16ms after CTRL goes HIGH.
For these cases, the device goes into shutdown and this state is latched. Input and outputs are disconnected. To
resume normal operation, VIN has to cycle below UVLO or CTRL has to toggle LOW and HIGH.
ENABLE (CTRL PIN)
The CTRL pin serves two functions. One is to enable and disable the device the other is the output voltage
programming of the device. If the digital interface is not required the CTRL pin can be used as a standard enable
pin for the device and the device will come up with its default value on VNEG of -4.9V. When CTRL is pulled high,
the device is enabled. The device is shut down with CTRL low.
DIGITAL INTERFACE (CTRL PIN)
The digital interface allows programming the negative output voltage VNEG in digital steps. If the digital output
voltage setting is not required then the CTRL pin can also be used as a standard enable pin. The digital output
voltage programming of VNEG is implemented by a simple digital interface with the timing shown in Figure 9.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: TPS65138 TPS65138A
CTRL
Low
High
VPOS
tOFF
tSTORE
tLOW tHIGH
tSET
VNEG
tINIT
4.62V
-4.9V
-6V (TPS65138)
-5V (TPS65138A)
tSCP
TPS65138
TPS65138A
SLVSAV3C –APRIL 2011–REVISED MAY 2012
www.ti.com
Figure 9. Digital Interface Using CTRL
Once CTRL is pulled high the device will come up with its default voltage of -4.9V. The device has a 6 bit DAC
implemented with the corresponding output voltages as given in Table 3 and Table 4. The interface counts now
the rising edges applied to CTRL pin once the device is enabled. For the timing table shown in Table 3 and
Table 4, VNEG is programmed to -6V in TPS65138 and -5V in TPS65138A, since 3 rising edges are detected.
Other output voltages are programmed according to Table 3 and Table 4.
10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS65138 TPS65138A
TPS65138
TPS65138A
www.ti.com
SLVSAV3C –APRIL 2011–REVISED MAY 2012
Table 3. TPS65138 Programming Table for VNEG
Bit / rising edges VNEG DAC Value Bit / rising edges VNEG DAC Value
0/ no pulse -4.9V 000000 21 -4.2V 010101
1 -6.2V 000001 22 -4.1V 010110
2 -6.1V 000010 23 -4.0V 010111
3 -6.0V 000011 24 -3.9V 011000
4 -5.9V 000100 25 -3.8V 011001
5 -5.8V 000101 26 -3.7V 011010
6 -5.7V 000110 27 -3.6V 011011
7 -5.6V 000111 28 -3.5V 011100
8 -5.5V 001000 29 -3.4V 011101
9 -5.4V 001001 30 -3.3V 011110
10 -5.3V 001010 31 -3.2V 011111
11 -5.2V 001011 32 -3.1V 100000
12 -5.1V 001100 33 -3.0V 100001
13 -5.0V 001101 34 -2.9V 100010
14 -4.9V 001110 35 -2.8V 100011
15 -4.8V 001111 36 -2.7V 100100
16 -4.7V 010000 37 -2.6V 100101
17 -4.6V 010001 38 -2.5V 100110
18 -4.5V 010010 39 -2.4V 100111
19 -4.4V 010011 40 -2.3V 101000
20 -4.3V 010100 41 -2.2V 101001
Table 4. TPS65138A Programming Table for VNEG
Bit / rising edges VNEG DAC Value Bit / rising edges VNEG DAC Value
0/ no pulse -4.9V 000000 16 -3.7V 010000
1 -5.2V 000001 17 -3.6V 010001
2 -5.1V 000010 18 -3.5V 010010
3 -5.0V 000011 19 -3.4V 010011
4 -4.9V 000100 20 -3.3V 010100
5 -4.8V 000101 21 -3.2V 010101
6 -4.7V 000110 22 -3.1V 010110
7 -4.6V 000111 23 -3.0V 010111
8 -4.5V 001000 24 -2.9V 011000
9 -4.4V 001001 25 -2.8V 011001
10 -4.3V 001010 26 -2.7V 011010
11 -4.2V 001011 27 -2.6V 011011
12 -4.1V 001100 28 -2.5V 011100
13 -4.0V 001101 29 -2.4V 011101
14 -3.9V 001110 30 -2.3V 011110
15 -3.8V 001111 31 -2.2V 011111
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TPS65138 TPS65138A
t
set 70% T
t 325k C 325k 100nF 32.5mst » = W ´ = W ´ =
t
TPS65138
TPS65138A
SLVSAV3C –APRIL 2011–REVISED MAY 2012
www.ti.com
SETTING TRANSITION TIME tset for VNEG
The device allows setting the transition time tset using an external capacitor connected to pin CT. The transition
time is the time period required to move VNEG from one voltage level to the next programmed voltage level. The
capacitor connected to pin CT does not influence on the soft start time tss of VNEG default value. When the CT pin
is left open then the shortest possible transition time is programmed. When connecting a capacitor to the CT pin
then the transition time is given by the R-C time constant. This is given by the output impedance of the CT pin
typically 325 kΩand the external capacitance. Within one the output voltage of VNEG has reached 70% of its
programmed value. An example is given when using 100nF for CT.
(1)
The VNEG programmed voltage is almost in nominal value after 3 .
PCB LAYOUT DESIGN GUIDELINES
Figure 10 and Figure 11 show the example of PCB layout design.
1. Place the input capacitor on PVIN and the output capacitor on OUTN as close as possible to device. Use
short and wide traces to connect the input capacitor on PVIN and the output capacitor on OUTN.
2. Place the output capacitor on OUTP as close as possible to device. Use short and wide traces to connect
the output capacitor on OUTP.
3. Connect the ground of CT capacitor with GND, pin 6, directly.
4. Connect input ground and output ground on the same board layer, not through via hole.
Figure 10. Example of Board Layout. Top Layer
12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS65138 TPS65138A
TPS65138
TPS65138A
SLVSAV3C –APRIL 2011–REVISED MAY 2012
www.ti.com
REVISION HISTORY
Changes from Original (April 2011) to Revision A Page
• Changed the TYPICAL CHARACTERISTICS. Deleted Figure 2, Figure 3, Figure 9 through Figure 12 ............................. 7
Changes from Revision A (May 2011) to Revision B Page
• Added Feature TPS65138A: -2.2V to -5.2V ......................................................................................................................... 1
• Added VNEG Negative output voltage range for TPS65138A, -2.2V to -5.2V ....................................................................... 4
• Added VNEG programming range of TPS65138A, -2.2V to -5.2V to the Detailed Decsription .............................................. 9
• Changed Figure 9 ............................................................................................................................................................... 10
Changes from Revision B (April 2012) to Revision C Page
• Changed the device From: Product Preview To: Production ................................................................................................ 1
14 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS65138 TPS65138A
PACKAGE OPTION ADDENDUM
www.ti.com 30-Sep-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS65138ADRCR ACTIVE VSON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PXJI
TPS65138DRCR ACTIVE VSON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PUCC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Sep-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS65138ADRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS65138DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Apr-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65138ADRCR VSON DRC 10 3000 552.0 367.0 36.0
TPS65138DRCR VSON DRC 10 3000 552.0 367.0 36.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Apr-2018
Pack Materials-Page 2
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRC 10 VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4204102-3/M
www.ti.com
PACKAGE OUTLINE
C
10X 0.30
0.18
2.4 0.1
2X
2
1.65 0.1
8X 0.5
1.0
0.8
10X 0.5
0.3
0.05
0.00
A3.1
2.9 B
3.1
2.9
(0.2) TYP
4X (0.25)
2X (0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SYMM
SYMM
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
SCALE 4.000
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EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
10X (0.24)
(2.4)
(2.8)
8X (0.5)
(1.65)
( 0.2) VIA
TYP
(0.575)
(0.95)
10X (0.6)
(R0.05) TYP
(3.4)
(0.25)
(0.5)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
SYMM
1
56
10
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
11
SYMM
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
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EXAMPLE STENCIL DESIGN
(R0.05) TYP
10X (0.24)
10X (0.6)
2X (1.5)
2X
(1.06)
(2.8)
(0.63)
8X (0.5)
(0.5)
4X (0.34)
4X (0.25)
(1.53)
VSON - 1 mm max heightDRC0010J
PLASTIC SMALL OUTLINE - NO LEAD
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
SYMM
1
56
10
EXPOSED METAL
TYP
11
SYMM
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