IR3504
Page 1 July 28, 2009
DATA SHEET
XPHASE3
TM
AMD SVID CONTROL IC
DESCRIPTION
The IR3504 Control IC combined with an xPHASE3
TM
Phase IC provides a full featured and flexible way to
implement a complete AMD SVID power solution. It provides outputs for both the VDD core and VDDNB
auxiliary planes required by the CPU. The IR3504 provides overall system control and interfaces with any
number of Phase ICs each driving and monitoring a single phase. The xPHASE3
TM
architecture results in a
power supply that is smaller, less expensive, and easier to design while providing higher efficiency than
conventional approaches.
FEATURES
• 2 converter outputs for the AMD processor VDD core and VDDNB auxiliary planes
• AMD Serial VID interface independently programs both output voltages and operation
• Both Converter Outputs boot to 2-bit “Boot” VID codes which are read and stored from the SVC & SVD
parallel inputs upon the assertion of the Enable input
• PWROK input signal activates SVID after successful boot start-up
• Both Converter Outputs can be independently turned on and off through SVID commands
• Deassertion of PWROK prior to Enable causes the converter output to transition to the stored Pre-
PWROK VID codes
• Connecting the PWROK input to VCCL disables SVID and implements VFIX mode with both output
voltages programmed via SVC & SVD parallel inputs per the 2 bit VFIX VID codes
• PG monitors output voltage, PG will deassert if either ouput voltage out of spec
• 0.5% overall system set point accuracy
• Programmable Dynamic VID Slew Rates
• Programmable VID Offset (VDD output only)
• Programmable output impedance (VDD output only)
• High speed error amplifiers with wide bandwidth of 20MHz and fast slew rate of 10V/us
• Remote sense amplifiers provide differential sensing and require less than 50uA bias current
• Programmable per phase switching frequency of 250kHz to 1.5MHz
• Daisy-chain digital phase timing provides accurate phase interleaving without external components
• Hiccup over current protection with delay during normal operation
• Central over voltage detection and communication to phase ICs through IIN (ISHARE) pin
• OVP disabled during dynamic VID down to prevent false triggering
• Detection and protection of open remote sense lines
• Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO
• Simplified Power Good (PG) Output provides indication of proper operation and avoids false triggering
• Small thermally enhanced 32L MLPQ (5mm x 5mm) package
• Over voltage signal to system with over voltage detection during powerup and normal operation
ORDERING INFORMATION
Device Package Order Quantity
IR3504MTRPBF 32 Lead MLPQ (5 x 5 mm body) 3000 per reel
* IR3504MPBF 32 Lead MLPQ (5 x 5 mm body) 100 piece strips
* Samples only
IR3504
Page 2 July 28, 2009
APPLICATION CIRCUIT
CSS/DEL1
CVDAC1
CSS/DEL2
RVCCLFB2
ROSC
RTHERMISTOR1
RVCCLD RV
RFB13
PHSOUT 26
PWROK
2
ENABLE
3
SVC 32
IIN2
4
OCSET2
7
VOSNS1+
14
VDRP1 22
PG 31
IIN1 21
CLKOUT 25
VCCLFB 29
VCCL 28
PHSIN 27
VOSNS2-
12
EAOUT1 17
VOUT1
15
VDAC1 19
VDAC2
6
FB2
9
ROSC 23
LGND 24
SVD
1
FB1
16
VCCLDR V 30
SS/DEL1 20
VOUT2
10
OCSET1 18
VONSN1-
13
VOSNS2+
11
SS/DEL2
5
EAOUT2
8
IR3504
CONTROL
IC
Q1
VDDNB SENSE +
ROCSET1
VDDNB SENSE -
RVCCLFB1
RVDAC1
CVCCL
Power Good
To VDDNB
Remote
Sense
PHSIN
12V
SVC
SVD
VDD SENSE -
VDD SENSE +
PHSOUT
ROC SET2
CLKOUT
VDAC1
ISH ARE1
EAOUT1
CCP21
CCP22
RCP2
ENABLE
12V
CFB2
RFB21
RFB22
3 Wire Analog
Control Bus to
VDDNB Phase
ICs
VCCL
To Converters
To VDD
Remote
Sense
2 wire
Digital
Daisy Chain
Bus to VDD
& VDDNB
Phase ICs
To Phase IC
VCCL & GATE
DRIVE BIAS
Phase Clock Input to
Last Phase IC of VDD
ISH ARE2
PWROK
RVDAC2
VDAC2
CVDAC2
RCP1 CCP11
RFB11
CDRP1
RDRP1
CFB1
CCP12
RFB12
EAOUT2
3 Wire Analog
Control Bus
to VDD Phase
ICs
Load Line NTC
Thermistor;
Locate close to
VDD Power Stage
Figure 1 – IR3504 Application Circuit
PIN DESCRIPTION
PIN# PIN SYMBOL PIN DESCRIPTION
1 SVD SVD (Serial VID Data) is a bidirectional signal that is an input and open drain output
for both master (AMD processor) and slave (IR3504), requires an external bias
voltage and should not be floated
2 PWROK System wide Power Good signal and input to the IR3504. When asserted, the
IR3504 output voltage is programmed through the SVID interface protocol.
Connecting this pin to VCCL enables VFIX mode.
3 ENABLE Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high
on the pin enables the converter and causes the SVC and SVD input states to be
decoded and stored, determining the 2-bit Boot VID. Do not float this pin as the logic
state will be undefined.
4 IIN2 Output 2 average current input from the output 2 phase IC(s). This pin is also used
to communicate over voltage condition to the output 2 phase ICs.
5 SS/DEL2 Programs output 2 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
6 VDAC2 Output 2 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
7 OCSET2 Programs the output 2 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC2 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC2 to program the threshold higher than the possible
signal into the IIN2 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
IR3504
Page 3 July 28, 2009
PIN# PIN SYMBOL PIN DESCRIPTION
8 EAOUT2 Output of the output 2 error amplifier.
9 FB2 Inverting input to the Output 2 error amplifier.
10 VOUT2 Output 2 remote sense amplifier output.
11 VOSEN2+ Output 2 remote sense amplifier input. Connect to output at the load.
12 VOSEN2- Output 2 remote sense amplifier input. Connect to ground at the load.
13 VOSEN1- Output 1 remote sense amplifier input. Connect to ground at the load.
14 VOSEN1+ Output 1 remote sense amplifier input. Connect to output at the load.
15 VOUT1 Output 1 remote sense amplifier output.
16 FB1 Inverting input to the output 1 error amplifier. Converter output voltage can be
increased from the VDAC1 voltage with an external resistor connected between
VOUT1 and this pin (there is an internal current sink at this pin).
17 EAOUT1 Output of the output 1 error amplifier.
18 OCSET1 Programs the output 1 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC1 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC1 to program the threshold higher than the possible
signal into the IIN1 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
19 VDAC1 Output 1 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
20 SS/DEL1 Programs output 1 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
21 IIN1 Output 1 average current input from the output 1 phase IC(s). This pin is also used
to communicate over voltage condition to phase ICs.
22 VDRP1 Output 1 Buffered IIN1 signal. Connect an external RC network to FB1 to program
converter output impedance.
23 ROSC/OVP Connect a resistor to LGND to program oscillator frequency and OCSET1, OCSET2,
FB1, FB2, VDAC1, and VDAC2 bias currents. Oscillator frequency equals switching
frequency per phase. The pin voltage is 0.6V during normal operation and higher
than 1.6V if over-voltage condition is detected.
24 LGND Local Ground for internal circuitry and IC substrate connection.
25 CLKOUT Clock output at switching frequency multiplied by phase number. Connect to CLKIN
pins of phase ICs.
26 PHSOUT Phase clock output at switching frequency per phase. Connect to PHSIN pin of the
first phase IC.
27 PHSIN Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
28 VCCL Output of the voltage regulator, and power input for clock oscillator circuitry. Connect
a decoupling capacitor to LGND.
29 VCCLFB Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by the resistor divider connected to VCCL.
30 VCCLDRV Output of the VCCL regulator error amplifier to control external transistor. The pin
senses 12V power supply through a resistor.
31 PG Power good signal implemented with an open collector output that drives low during
startup and under any external fault condition. Also, if any of the voltage planes fall
out of spec, it will drive low. Connect external pull-up. (Output voltage out of spec is
defined as 350mV to 240mV below VDAC voltages)
32 SVC SVC (Serial VID Clock) is an open drain output of the processor and input to
IR3504, requires an external bias voltage and should not be floated
IR3504
Page 4 July 28, 2009
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.
All voltages are absolute voltages referenced to the LGND pin.
Operating Junction Temperature……………..0 to 150
o
C
Storage Temperature Range………………….-65
o
C to 150
o
C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
Reflow Temperature…………………………….260
o
C
PIN # PIN NAME V
MAX
V
MIN
I
SOURCE
I
SINK
1 SVD 8V -0.3V 1mA 10mA
2 PWROK 8V -0.3V 1mA 1mA
3 ENABLE 3.5V -0.3V 1mA 1mA
4 IIN2 8V -0.3V 5mA 1mA
5 SS/DEL2 8V -0.3V 1mA 1mA
6 VDAC2 3.5V -0.3V 1mA 1mA
7 OCSET2 8V -0.3V 1mA 1mA
8 EAOUT2 8V -0.3V 25mA 10mA
9 FB2 8V -0.3V 1mA 1mA
10 VOUT2 8V -0.3V 5mA 25mA
11 VOSEN2+ 8V -0.5V 5mA 1mA
12 VOSEN2- 1.0V -0.5V 5mA 1mA
13 VOSEN1- 1.0V -0.5V 5mA 1mA
14 VOSEN1+ 8V -0.5V 5mA 1mA
15 VOUT1 8V -0.3V 5mA 25mA
16 FB1 8V -0.3V 1mA 1mA
17 EAOUT1 8V -0.3V 25mA 10mA
18 OCSET1 8V -0.3V 1mA 1mA
19 VDAC1 3.5V -0.3V 1mA 1mA
20 IIN1 8V -0.3V 5mA 1mA
21 SS/DEL1 8V -0.3V 1mA 1mA
22 VDRP1 8V -0.3V 35mA 1mA
23 ROSC/OVP 8V -0.3V 1mA 1mA
24 LGND n/a n/a 20mA 1mA
25 CLKOUT 8V -0.3V 100mA 100mA
26 PHSOUT 8V -0.3V 10mA 10mA
27 PHSIN 8V -0.3V 1mA 1mA
28 VCCL 8V -0.3V 1mA 20mA
29 VCCLFB 3.5V -0.3V 1mA 1mA
30 VCCLDRV 10V -0.3V 1mA 50mA
31 PG VCCL + 0.3V -0.3V 1mA 20mA
32 SVC 8V -0.3V 1mA 1mA
IR3504
Page 5 July 28, 2009
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0
o
C ≤ T
J
≤ 100
o
C, 7.75 kΩ ≤ ROSC ≤ 50 kΩ, CSS/DELx = 0.1uF
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating
conditions (unless otherwise specified). Typical values represent the median values, which are related to 25°C.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SVID Interface
Threshold Increasing (Note 1) 0.850 0.950 1.05 V
Threshold Decreasing (Note 1) 550 650 750 mV
SVC & SVD Input Thresholds
Threshold Hysteresis (Note 1) 195 300 405 mV
Bias Current 0V ≤ V(x) ≤ 3.5V, SVD not asserted -5 0 5 uA
SVD Low Voltage I(SVD)= 3mA 20 300 mV
SVD Output Fall Time
0.7 x VDDIO to 0.3VDDIO, 1.425V ≤
VDDIO ≤ 1.9V, 10 pF ≤ Cb ≤ 400 pF,
Cb=capacitance of one bus line (Note 1)
20+ 0.1
xCb(pF)
250 ns
Pulse width of spikes suppressed
by the input filter
Note 1 97 260 410 ns
Oscillator
PHSOUT Frequency -10% See
Figure 2
+10% kHz
ROSC Voltage 0.57 0.600 0.630 V
CLKOUT High Voltage I(CLKOUT)= -10 mA, measure V(VCCL) –
V(CLKOUT).
1 V
CLKOUT Low Voltage I(CLKOUT)= 10 mA 1 V
PHSOUT High Voltage I(PHSOUT)= -1 mA, measure V(VCCL) –
V(PHSOUT)
1 V
PHSOUT Low Voltage I(PHSOUT)= 1 mA 1 V
PHSIN Threshold Voltage Compare to V(VCCL) 30 50 70 %
VDRP1 Buffer Amplifier
Input Offset Voltage V(VDRP1) – V(IIN1), 0.5V ≤ V(IIN) ≤ 3.3V -8 0 8 mV
Source Current 0.5V ≤ V(IIN1) ≤ 3.3V 2 30 mA
Sink Current 0.5V ≤ V(IIN1) ≤ 3.3V 0.2 0.4 0.6 mA
Unity Gain Bandwidth Note 1 8 MHz
Slew Rate Note 1 4.7 V/µs
IIN Bias Current -1 0 1 µA
Remote Sense Differential Amplifiers
Unity Gain Bandwidth Note 1 3.0 6.4 9.0 MHz
Input Offset Voltage 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V,
Note 2
-3 0 3 mV
Source Current 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V 0.5 1 1.7 mA
Sink Current 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V 2 12 16 mA
Slew Rate 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V 2 4 8 V/us
VOSEN+ Bias Current 0.5 V < V(VOSENx+) < 1.6V 30 50 uA
VOSEN- Bias Current -0.3V ≤ VOSENx- ≤ 0.3V, All VID Codes 30 55 uA
VOSEN+ Input Voltage Range V(VCCL)=7V 5.5 V
Low Voltage V(VCCL) =7V 250 mV
High Voltage V(VCCL) – V(VOUTx) 0.5 1 V
Soft Start and Delay
Start Delay Measure Enable to EAOUTx activation 1 2.9 3.5 ms
Start-up Time Measure Enable activation to PG 3 8 13 ms
IR3504
Page 6 July 28, 2009
PARAMETER TEST CONDITION MIN TYP MAX UNIT
OC Delay Time V(IINx) – V(OCSETx) = 500 mV 300 650 1000 us
SS/DELx to FBx Input Offset
Voltage
With FBx = 0V, adjust V(SS/DELx) until
EAOUTx drives high
0.7 1.4 1.9 V
Charge Current -30 -50 -70 µA
OC Delay/VID Off Discharge
Currents
Note 1 47 µA
Fault Discharge Current 2.5 4.5 6.5 µA
Hiccup Duty Cycle I(Fault) / I(Charge) 8 10 12 uA/uA
Charge Voltage 3.5 3.9 4.2 V
Delay Comparator Threshold Relative to Charge Voltage, SS/DELx
rising Note 1
80 mV
Delay Comparator Threshold Relative to Charge Voltage, SS/DELx
falling Note 1
130 mV
Delay Comparator Hysteresis Note 1 60 mV
Discharge Comp. Threshold 150 200 300 mV
Over-Current Comparators
Input Offset Voltage 1V ≤ V(OCSETx) ≤ 3.3V -30 0 30 mV
OCSET Bias Current -5%
Vrosc(V)*1000
/Rosc(KΩ)
+5% µA
2048-4096 Count Threshold Adjust ROSC value to find threshold 11.4 kΩ
1024-2048 Count Threshold Adjust ROSC value to find threshold 32.5 kΩ
Error Amplifiers
VID > 1.0V -0.65 0.65 %
0.8V ≤ VID ≤ 1.0V -8 +8 mV
System Set-Point Accuracy
(Deviation from Table 1, 2, and
3 per test circuit in Figures 2A &
2B) 0.5V ≤ VID < 0.8V -9 +9 mV
Input Offset Voltage Measure V(FBx) – V(VDACx)). Note 2 -1 0 1 mV
FB1 Bias Current -5%
Vrosc(V)*1000
/Rosc(KΩ)
+5% µA
FB2 Bias Current -1 0 1 µA
DC Gain Note 1 100 110 135 dB
Bandwidth Note 1 20 30 40 MHz
Slew Rate Note 1 5.5 12 20 V/µs
Sink Current 0.4 0.85 1 mA
Source Current 6.0 8.5 13.0 mA
Maximum Voltage Measure V(VCCL) – V(EAOUTx) 500 780 950 mV
Minimum Voltage 120 250 mV
Open Control Loop Detection
Threshold
Measure V(VCCL) - V(EAOUT), Relative
to Error Amplifier maximum voltage.
125 300 600 mV
Open Control Loop Detection
Delay
Measure PHSOUT pulse numbers from
V(EAOUTx) = V(VCCL) to PG = low.
8 Pulses
Enable Input
Blanking Time Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
75 250 400 ns
VDAC References
Source Currents Includes I(OCSETx) -8%
3000*Vrosc(V)
/ ROSC(kΩ)
+8% µA
Sink Currents Includes I(OCSETx) -12%
1000*Vrosc(V)
/ ROSC(kΩ)
+12% µA
PG Output
Under Voltage Threshold -
Voutx Decreasing
Reference to VDACx -365 -315 -265 mV
Under Voltage Threshold -
Voutx Increasing
Reference to VDACx -325 -275 -225 mV
Under Voltage Threshold
Hysteresis
5 53 110 mV
IR3504
Page 7 July 28, 2009
Note 1: Guaranteed by design, but not tested in production
Note 2: VDACx Outputs are trimmed to compensate for Error & Amp Remote Sense Amp input offsets
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Output Voltage I(PG) = 4mA 150 300 mV
Leakage Current V(PG) = 5.5V 0 10 µA
VCCL Activation Threshold I(PG) = 4mA, V(PG) = 300mV 1.73 3.5 V
Over Voltage Protection (OVP) Comparators
Threshold at Power-up 1.60 1.73 1.83
V
Voutx Threshold Voltage Compare to V(VDACx) 190 240 280
mV
OVP Release Voltage during Normal
Operation
Compare to V(VDACx) -13 3 20 mV
Threshold during Dynamic VID down 1.79 1.84 1.89
V
Dynamic VID Detect Comparator Threshold
Note 1 25 50 75 mV
Propagation Delay to IIN Measure time from V(Voutx) >
V(VDACx) (250mV overdrive) to
V(IINx) transition to > 0.9 *
V(VCCL).
90 180
ns
OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) 0 1.2 V
OVP Power-up High Voltage V(VCCLDRV)=1.8V. Measure
V(VCCL)-V(ROSC/OVP)
0 0.2 V
Propagation Delay to OVP Measure time from V(Voutx) >
V(VDACx) (250mV overdrive) to
V(ROSC/OVP) transition to >1V.
150 300 nS
IIN Pull-up Resistance 5 15 Ω
Open Sense Line Detection
Sense Line Detection Active Comparator
Threshold Voltage
150
200 250 mV
Sense Line Detection Active Comparator
Offset Voltage
V(Voutx) < [V(VOSENx+) –
V(LGND)] / 2
35 62.5 90 mV
VOSEN+ Open Sense Line Comparator
Threshold
Compare to V(VCCL) 87 89.5 92 %
VOSEN- Open Sense Line Comparator
Threshold
0.35
0.385 0.42 V
Sense Line Detection Source Currents V(Voutx) = 100mV 200
500 700 uA
VCCL Regulator Amplifier
Reference Feedback Voltage 1.15 1.2 1.25 V
VCCLFB Bias Current -1 0 1 uA
VCCLDRV Sink Current 10 30 mA
UVLO Start Threshold Compare to V(VCCL) 89.0 93.5 97.0 %
UVLO Stop Threshold Compare to V(VCCL) 81.0 85.0 89.0 %
Hysteresis Compare to V(VCCL) 7.0 8.25 9.5 %
ENABLE, PWROK Inputs
Threshold Increasing 1.38 1.65 1.94 V
Threshold Decreasing 0.8 0.99 1.2 V
Threshold Hysteresis 470 620 770 mV
Bias Current 0V ≤ V(x) ≤ 3.5V, SVC not asserted -5 0 5 uA
PWROK VFIX Mode Threshold 3.3V (VCCL
+3.3)(V)
/ 2
VCCL V
General
VCCL Supply Current 4 10 15 mA
IR3504
Page 8 July 28, 2009
PHSOUT FREQUENCY VS RROSC CHART
PHSOUT FREQUENCY vs. RROSC
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
5 10 15 20 25 30 35 40 45 50 55
RROSC (KOhm)
Frequency (KHz)
Figure 2 - Phout Frequency vs. RROSC chart
IR3504
Page 9 July 28, 2009
SYSTEM SET POINT TEST
Converter output voltage is determined by the system set point voltage which is the voltage that appears at the
FBx pins when the converter is in regulation. The set point voltage includes error terms for the VDAC digital-to-
analog converters, Error Amp input offsets, and Remote Sense input offsets. The voltage appearing at the
VDACx pins is not the system set point voltage. System set point voltage test circuits for Outputs 1 and 2 are
shown in Figures 3A and 3B.
CVDAC1
+
-
+
-
RROSC
+
-
RVDAC1
ROCSET1
+
-
EAOUT1
FB1
OCSET1
VDAC1
VOSEN1-
VOSEN1+
VOUT1
LGND
ROSC
IROSC
IROSC
EAOUT
VOSNS-
VDAC
BUFFER
AMPLIFIER
IFB1
ROSC BUFFER
AMPLIFIER
1.2V
"FAST"
VDAC
ISINK
ISOURCE
IR3504
SYSTEM
SET POINT
VOLTAGE
IOCSET1
CURRENT
SOURCE
GENERATOR
REMOTE SENSE
AMPLIFIER
ERROR
AMPLIFIER
IROSC
Figure 3A - Output 1 System Set Point Test Circuit
CVDAC2
+
-
+
-
RROSC
+
-
RVDAC2
ROCSET2
+
-
VDAC2
OCSET2
FB2
EAOUT2
LGND
VOUT2
VOSEN2+
VOSEN2-
IROSC
ROSC
VOSNS-
EAOUT
VDAC
BUFFER
AMPLIFIER
"FAST"
VDAC
1.2V
ROSC BUFFER
AMPLIFIER
SYSTEM
SET POINT
VOLTAGE
IR3504
ISOURCE
ISINK
IROSC
ERROR
AMPLIFIER
REMOTE SENSE
AMPLIFIER
CURRENT
SOURCE
GENERATOR
IOCSET2
Figure 3B - Output 2 System Set Point Test Circuit
IR3504
Page 10 July 28, 2009
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the xPHASE3
TM
architecture is shown in Figure 4. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage automatically compensating for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
GND
VOUT1
VOSNS1+
DACIN
VCC
VDAC1
VOUT1
IIN1
VDRP1
LGND
ISHARE
PHSIN
VOSNS1-
CSIN-
CSIN+
GATEL
EAIN
GATEH
SW
VIN
FB1
EAOUT1
CLKOUT CLKIN
PHSOUT
PGND
VCCL
VCCH
DACIN
VCC
CLKIN
PHSOUT
CSIN+
GATEL
EAIN
GATEH
ISHARE
PHSIN
SW
PGND
VCCL
VCCH
CSIN-
PHSIN
PHSOUT
VID6
VID6
IROSC
VID6
VID6
VID6
VID6
VID6
VID6
VID6
VID6
GATE DRIVE
VOLTAGE
-
+
+
+
ENABLE
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
IFB1
VDRP1 AMP
VDAC
CLOCK GENERATOR
CURRENT
SENSE
AMPLIFIER
R
S
SHARE ADJUST
ERROR AMPLIFIER
RESET
DOMINANT
PWM
LATCH
ERROR
AMPLIFIER
COUT
IR3504 CONTROL IC
PHASE IC
Output 1 Only
PWM
COMPARATOR
PWM
COMPARATOR
-
+
+
+
RAMP
DISCHARGE
CLAMP
ENABLE
BODY
BRAKING
COMPARATOR
SHARE ADJUST
ERROR AMPLIFIER
RESET
DOMINANT
PWM
LATCH
CURRENT
SENSE
AMPLIFIER
R
S
PHASE IC
REMOTE SENSE
AMPLIFIER
CCS R CS
+
-
CFB1
RC S
CBST
+
-
CCS
CBST
+
-
+
-
CC P11
+
-
+
-
RFB12
RDRP1
CDR P1
RFB11
3K
+
-
+
-
CLK
D
Q
+
-
+
-
RC P1
+
-
3K
+
-
+
-
CC P12
CLK
D
Q
+
-
Figure 4 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250 kHz to 9 MHZ
by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs.
The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output
(PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is
connected to PHSIN of the second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the
control IC to complete the loop. During power up, the control IC sends out clock signals from both CLKOUT and
PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitors for any fault in
the daisy chain loop. Figure 5 shows the phase timing for a four phase converter.
IR3504
Page 11 July 28, 2009
Phase IC1
PWM Latch SET
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 5 Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is
set; the PWM ramp voltage begins to increase; the low side driver is turned off, and the high side driver is then
turned on after the non-overlap time. When the PWM ramp voltage exceeds the error amplifier’s output voltage, the
PWM latch is reset. This turns off the high side driver and then turns on the low side driver after the non-overlap
time; it activates the ramp discharge clamp, which quickly discharges the internal PWM ramp capacitor to the output
voltage of share adjust amplifier in phase IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in
ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 6 depicts PWM operating waveforms under various conditions.
IR3504
Page 12 July 28, 2009
PHASE IC
CLOCK
PULSE
VDAC
EAIN
PWMRMP
GATEL
GATEH
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
STEADY-STATE
OPERATION
STEADY-STATE
OPERATION
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, OCP, VID FAULT)
Figure 6 PWM Operating Waveforms
Body Braking
TM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
O
MINMAX
SLEW V
IIL
T)(* −
=
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
V
BODYDIODE
. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
BODYDIODEO
MINMAX
SLEW VV
IIL
T+
−
=)(*
Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be
increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished
through the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below
the VDAC voltage or a programmable voltage, this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor, as shown in Figure 7. The equation of the sensing network is,
CSCS
L
L
CSCS
LC CsR
sLR
si
CsR
svsv +
+
=
+
=1
)(
1
1
)()(
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
IR3504
Page 13 July 28, 2009
Figure 7 Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 7. Its gain is
nominally 34 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop
feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and
other phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are
tied together and the voltage on the share bus represents the average current through all the inductors and is used
by the control IC for voltage positioning and current limit protection.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC.
The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM
ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current,
the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty
cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of
the current share loop is much slower than that of the voltage loop and the two loops do not interact.
C
O
L
R
L
R
CS
C
CS
V
O
Current
Sense Amp
CSOUT
i
L
v
L
v
CS
c
IR3504
Page 14 July 28, 2009
IR3504 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3504 is shown in Figure 8. The following discussions are applicable to either output
plane unless otherwise specified.
Serial VID Control
The two Serial VID Interface (SVID) pins SVC and SVD are used to program the Boot VID voltage upon assertion of
ENABLE while PWROK is de-asserted. See Table 1 for the 2-bit Boot VID codes. Both VDAC1 and VDAC2
voltages will be programmed to the Boot VID code until PWROK is asserted. The Boot VID code is stored by the
IR3504 to be utilized again if PWROK is de-asserted.
Serial VID communication from the processor is enabled after the PWROK is asserted. Addresses and data are
serially transmitted in 8-bit words. The IR3504 has three fixed addresses to control VDAC1, VDAC2, or both
VDAC1 and VDAC2 (See Table 6 for addresses). The first data bit of the SVID data word represents the PSI_L bit
and will be ignored by the IR3504 therefore this system will never enter a power-saving mode. The remaining data
bits SVID[6:0] select the desired VDACx regulation voltage as defined in Table 3. SVID[6:0] are the inputs to the
Digital-to-Analog Converter (DAC) which then provides an analog reference voltage to the transconductance type
buffer amplifier. This VDACx buffer provides a system reference on the VDACx pin. The VDACx voltage along with
error amplifier and remote sense differential amplifier input offsets are post-package trimmed to provide a 0.5%
system set-point accuracy, as measured in Figures 3A and 3B. VDACx slew rates are programmable by properly
selecting external series RC compensation networks located between the VDACx and the LGND pins. The VDACx
source and sink currents are derived off the external oscillator frequency setting resistor, R
ROSC
. The programmable
slew rate enables the IR3504 to smoothly transition the regulated output voltage throughout VID transitions. This
results in power supply input and output capacitor inrush currents along with output voltage overshoot to be well
controlled.
The two Serial VID Interface (SVID) pins SVC and SVD can also program the VFIX VID voltage upon assertion of
ENABLE while PWROK is equal to VCCL. See Table 2 for the 2-bit VFIX VID codes. Both VDAC1 and VDAC2
voltages will be programmed to the VFIX code.
The SVC and SVD pins require external pull-up biasing and should not be floated.
Output 1 (VDD) Adaptive Voltage Positioning
The IR3504 provides Adaptive Voltage Positioning (AVP) on the output1 plane only. AVP helps reduces the peak
to peak output voltage excursions during load transients and reduces load power dissipation at heavy load. The
circuitry related to the voltage positioning is shown in Figure 9. Resistor R
FB1
is connected between the error
amplifiers inverting input pin FB1 and the remote sense differential amplifier output, VOUT1. An internal current sink
on the FB1 pin along with R
FB1
provides programmability of a fixed offset voltage above the VDAC1 voltage. The
offset voltage generated across R
FB1
forces the converter’s output voltage higher to maintain a balance at the error
amplifiers inputs. The FB1 sink current is derived by the external resistor R
ROSC
that programs the oscillator
frequency.
The VDRP1 pin voltage is a buffered reproduction of the IIN1 pin which is connected to the current share bus
ISHARE. The voltage on ISHARE represents the system average inductor current information. At each phase IC,
an RC network across the inductor provides current information which is gained up 32.5X and then added to the
VDAC
X
voltage. This phase current information is provided on the ISHARE bus via a 3K resistor in the phase ICs.
IR3504
Page 15 July 28, 2009
DLY OUT2
S
R
Q
Q
OC DELAY
COUTER
DI SABLE
0.86
SVI (Seriel VID Interface)
VOUT1 VID OFF
DCHG1
FLT1
DCHG1
VCCL UVLO
DIS
VOUT2
VCCL
DISABLE
VCCL UVLO
DETECTION PULSE1
OV1-2
OV2
OV1
+
-
Metal to SVID
+
-
25k
+
-
+
-
Back to PRE-PWROK
2 BIT VID
SS/DEL2
PHSOUTCLKOUT
ENABLE
PG
VCCLDRV
VCCLFB
ROSC
VCCL
PHSIN
VOSEN1+
VOUT1
VDRP1
IROSC
DIS
EAOUT1
VDAC1
LGND
VOSEN1-
VID3
IIN1
OCSET1
FB1
VCCLVCCL
FLT2
VID7
PHSIN
IROSC
VID3
IROSC
DISABLE1
IVOSEN-VIDSEL
UV1
PHSOUTCLKOUT
FAULT
DISABLE
IROSC
PWROK
ERROR
AMPLIFIER
DELAY
COMPARATOR
SET
DOMINANT
3.9V
SS/DEL CLEARED
FAULT LATCH2
VOUT2 VID OFF
1V
ENABLE
COMPARATOR
VDAC BUFFER
AMPLIFIER
D/A
CONVERTER
1.65V
DISABLE
Vout2 VID
On-The-Fly
High to Low
VCCL REGULATOR
AMPLIFIER
OVER VOLTAGE
COMPARATOR
250nS
BLANKING
VCCL UVL
COMPARATOR
0.94
1.2V
0.6V
ROSC BUFFER
AMPLIFIER CURRENT
SOURCE
GENERATOR
POWER-UP
OK LATCH
ISINK
ISOURCE
REMOTE SENSE
AMPLIFIER
VDRP
AMPLIFIER
DISCHARGE
COMPARATOR
80mV
120mV
RESET
DOMINANT
DIS
IVOSEN1+
200mV
1.6V
50mV
0.2V
0.4V
VCCL*0.9
IVOSEN1-
1.4V
SOFT
START
CLAMP
IFB
240mV
OV FAULT LATCH
SET
DOMINANT
OC LIMIT
COMPARATOR
OPEN DAISY
CHAIN
4 OPEN SENSE
LINE DETECT
COMPARATORS
60mV
FLT2
ICHG
50uA
OPEN SENSE LINE1
OC2 AFTER PG
DIS
VDAC2
IOCSET
8 Pulse
Delay
1.08V
VID0
VCC L RESET
+
-
INTERNAL
CIRCUIT
BIAS
+
-
25k
+
-
DCHG2
OPEN SENSE2
+
-
+
-
+
-
VCCL UVLO
25k
FLT1
+
-
25k
+
-
OPEN CONTROL
LOOP COMPARATOR
VCCL
VID3
+
-
+
+
-
S
R
Q
OPEN CONTROL1
DETECTION PULSE2
EN
EN
UV CLEARED
FAULT LATCH1
SET
DOMINANT
+
-
25k
VID3
S
R
Q
+
-
OPEN DAISY
DIS
+
-
IDCHG
4.5uA
VOSEN2-
VOSEN2+
EAOUT2
VDAC2
IIN2
OCSET2
FB2
OV1
SS/DEL1
IDCHG1
47uA
OVLATCH
+
-
VCCLVCCL
3.9V
SS/DEL CLEARED
FAULT LATCH1
VID7
RESET
DOMINANT
POWER-UP
OK LATCH DELAY
COMPARATOR
SET
DOMINANT
PG
0.2V
DISCHARGE
COMPARATOR
60mV
130mV
VIDSEL
IVOSEN-
OC1 AFTER PG
DISABLE2
OPEN SENSE1
ICHG
50uA
IROSC
OVER VOLTAGE
COMPARATOR
VDAC BUFFER
AMPLIFIER
ERROR
AMPLIFIER
FLT1
Metal to SVID
SVID to Metal
SVID to SVID
DETECTION PULSE2
OV1
Low to High
reset reset
OVLATCH
VID3
Vout1 VID
On-The-Fly
High to Low
High to Low
DIS
OC DELAY
COUTER
PHSOUT
DIS
DLY OUT1
DLY OUT2
DLY OUT2
VOUT2 VI D OFF
VDAC 2
OV2
DIS
UV2
EN
EN
OC2 Bf PG
SVID ENABLED
IROSC
DIS
DIS
VID3
VCCL - 1.2V
VOUT1 UV
COMPARATOR
DLY OUT1
VOUT1 VID OFF
VID3
PHSOUT
Connection to VCCL
DETECTION PU LSE1
+
-
UV2
275mV
315mV
VOUT2 UV
COMPARATOR
OC1 Bf PG
+
-
UV1
VDAC1
SSCL FS2
PG
SVID to SVID
OV1_2
1.6V
50mV
ISINK
ISOURCE
REMOTE SENSE
AMPLIFIER
VCCL*0.9
IVOSEN2- IVOSEN2+
200mV
1.4V
SOFT
START
CLAMP
0.4V
DYNAMIC VID2 DOWN
DETECT COMPARATOR
240mV
OC LIMIT
COMPARATOR
4 OPEN SENSE
LINE DETECT
COMPARATORS
60mV
IOCSET
OPEN SENSE LINE2
1.08V
SSCL FS1
FLT2
VCC L RESET
VDAC1
+
-
+
-
VID3
S
R
Q
IROSC
OV2
47uA
+
-
IDCHG2
SSCL FS1
S
R
Q
Q
OPEN CONTROL2
VCCL UVLO
+
-
25k
+
-
DIS
VCC L
+
-
DIS
+
-
275mV
315mV
+
-
+
-
+
+
-
SVID to Metal
25k
VID3
+
-
+
-
+
-
S
R
Q
UV CLEARED
FAULT LATCH2
SET
DOMINANT
+
-
25k
VCC L
+
-
S
R
Q
READ & STORE PRE-PWROK 2
BIT VID
SSCL FS2
SVC
DIS
8 Pulse
Delay
PHSOUT
DYNAMIC VID1 DOWN
DETECT COMPARATOR
VID3
FLT1
OPEN CONTROL
LOOP COMPARATOR
FLT2
IROSC
OPEN DAISY
PHSOUT
DLY OUT1
OVLATCH
DIS
IDCHG
4.5uA
VFIX Mode
SVD
DCHG2
Figure 8 Block Diagram
IR3504
Page 16 July 28, 2009
Table 1 – 2-bit Boot VID codes Table 2 – VFIX mode 2 bit VID Codes
SVC SVD Output Voltage(V)
0 0 1.1
0 1 1.0
1 0 0.9
1 1 0.8
Table 3 - AMD 7 BIT SVID CODES
SVID [6:0] Voltage (V)
SVID [6:0] Voltage (V) SVID [6:0] Voltage (V)
SVID [6:0]
Voltage (V)
000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.5000
000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.5000
000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.5000
000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.5000
000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.5000
000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.5000
000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.5000
000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0110 0.5000
000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.5000
000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.5000
000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.5000
000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.5000
000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.5000
000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.5000
000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.5000
000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.5000
001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.5000
001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.5000
001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.5000
001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.5000
001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.5000
001_0101 1.2875 011_0101 0.8875 101_0101 0.5000
111_0101 0.5000
001_0110 1.2750 011_0110 0.8750 101_0110 0.5000
111_0110 0.5000
001_0111 1.2625 011_0111 0.8625 101_0111 0.5000
111_0111 0.5000
001_1000 1.2500 011_1000 0.8500 101_1000 0.5000
111_1000 0.5000
001_1001 1.2375 011_1001 0.8375 101_1001 0.5000
111_1001 0.5000
001_1010 1.2250 011_1010 0.8250 101_1010 0.5000
111_1010 0.5000
001_1011 1.2125 011_1011 0.8125 101_1011 0.5000
111_1011 0.5000
001_1100 1.2000 011_1100 0.8000 101_1100 0.5000
111_1100 OFF
001_1101 1.1875 011_1101 0.7875 101_1101 0.5000
111_1101 OFF
001_1110 1.1750 011_1110 0.7750 101_1110 0.5000
111_1110 OFF
001_1111 1.1625 011_1111 0.7625 101_1111 0.5000
111_1111 OFF
SVC SVD Output Voltage(V)
0 0 1.4
0 1 1.2
1 0 1.0
1 1 0.8
IR3504
Page 17 July 28, 2009
VOSEN1-
CSIN-
CSIN+
IIN1
CSIN-
EAOUT1
ISHARE
VDRP1
Phase IC
Phase IC
ISHARE
VOUT1
+
-
RFB1
Current Sense
Amplifier
+
-
3k
3k
RDRP1
+
-
... ...
+
-
VDAC
VDAC
Remote
Sense
Amplifier
VDAC1
VDAC1
FB1
IFB
Current Sense
Amplifier
Error
Amplifier
VDRP
Amplifier
Control IC
VOSEN1+
CSIN+
+
-
Figure 9 Adaptive voltage positioning
+
-
EAOUT1
+
-
IIN1
VDAC1
IFB
VDAC1
Control IC
Error
Amplifier
RDRP1
VDRP
Amplifier
VDRP1
RtRFB12
RFB11
FB1
VOSEN1+
VOUT1
VOSEN1-
+
-
Remote
Sense
Amplifier
Figure 10 Temperature compensation of Output1 inductor DCR
IR3504
Page 18 July 28, 2009
Output 1 (VDD) Adaptive Voltage Positioning (continued)
The voltage difference between VDRP1 and FB1 represents the gained up average current information. Placing a
resistor R
DRP1
between VDRP1 and FB1 converts the gained up current information (in the form of a voltage) into a
current forced onto the FB1 pin. This current, which can be calculated using (VDRP1-VDAC1) / R
DRP1
, will vary the
offset voltage produced across R
FB1
. Since the error amplifier will force the loop to maintain FB1 to equal the
VDAC1 reference voltage, the output regulation voltage will be varied. When the load current increases, the
adaptive positioning voltage V(VDRP1) increases accordingly. (VDRP1-VDAC1) / R
DRP1
increases the voltage drop
across the feedback resistor R
FB1
, and makes the output voltage lower proportional to the load current. The
positioning voltage can be programmed by the resistor R
DRP1
so that the droop impedance produces the desired
converter output impedance. The offset and slope of the converter output impedance are referenced to VDAC1 and
are not affected by changes in the VDAC1 voltage.
Output1 Inductor DCR Temperature Compensation
A negative temperature coefficient (NTC) thermistor can be used for output1 inductor DCR temperature
compensation. The thermistor should be placed close to the output1 inductors and connected in parallel with the
feedback resistor, as shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity
of the thermistor.
Remote Voltage Sensing
VOSEN
X
+ and VOSEN
X
- are used for remote sensing and connected directly to the load. The remote sense
differential amplifiers are high speed, have low input offset and low input bias currents to ensure accurate voltage
sensing and fast transient response.
Start-up Sequence
The IR3504 has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL
X
and LGND pins controls soft start timing, over-current protection delay
and hiccup mode timing. Constant current sources and sinks control the charge and discharge rates of the
SS/DEL
X
.
Figure 11 depicts the SVID start-up sequence. If the ENABLE input is asserted and there are no faults, the SS/DEL
X
pin will begin charging, the pre-PWROK 2 bit Boot VID codes are read and stored, and both VDAC pins transition to
the pre-PWROK Boot VID code. The error amplifier output EAOUT
X
is clamped low until SS/DEL
X
reaches 1.4V.
The error amplifier will then regulate the converter’s output voltage to match the V(SS/DEL
X
)-1.4V offset until the
converter output reaches the 2-bit Boot VID code. The SS/DEL
X
voltage continues to increase until it rises above
the threshold of Delay Comparator where the PG output is allowed to go high. The SVID interface is activated upon
PWROK assertion and the VDAC
X
along with the converter output voltage will change in response to any SVID
commands.
VCCL under voltage, over current, or a low signal on the ENABLE input immediately sets the fault latch, which
causes the EAOUT pin to drive low, thereby turning off the phase IC drivers. The PG pin also drives low and
SS/DEL
X
discharges to 0.2V. If the fault has cleared, the fault latch will be reset by the SS/DEL
X
discharge
comparator allowing another soft start charge cycle to occur.
Other fault conditions, such as output over voltage, open VOSNS sense lines, or an open phase timing daisy chain
set a different group of fault latches that can only be reset by cycling VCCL power. These faults discharge
SS/DEL
X
, pull down EAOUT
X
and drive PG low.
SVID OFF codes turn off the converter by discharging SS/DEL
X
and pulling down EAOUTx but do not drive PG low.
Upon receipt of a non-off SVID code the converter will re-soft start and transition to the voltage represented by the
SVID code as shown in Figure 11.
The converter can be disabled by pulling the SS/DELx pins below 0.6V.
IR3504
Page 19 July 28, 2009
SVID OFF TRANSISTION
SVID programmed voltage
SVID
TRANSITION
STARTUP
TIME
(12V)
START
DELAY
VCC
ENABLE
1.4V
VOUT
PG
3.92V
SS/DEL
4.0V
NORMAL
OPERATION
VDACx
SVID set voltage
2-Bit Boot
VID Voltage
EAOUT
SVID OFF COMMAND
SVID OFF COMMAND
PWROK
2-Bit Boot
VID On-Hold
2-Bit Boot
VID On-Hold
0.5V
SVID ON TRANSISTION
SVID ON COMMAND
SVID ON COMMAND
1.4V
VID ON
THE FLY
PROCESSION
0.8V
SVC
SVD
2-Bit Boot VID
READ & STORE
2-Bit Boot VID
READ & STORE
SVID
TRANSITION
Figure 11 SVID Start-up Sequence Transitions
IR3504
Page 20 July 28, 2009
Serial VID Interface Protocol and VID-on-the-fly Transition
The IR3504 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which is based
on fast-mode I
2
C. SVID commands from an AMD processor are communicated through SVID bus pins SVC and
SVD. The SVC pin of the IR3504 does not have an open drain output since AMD SVID protocol does not support
slave clock stretching.
The IR3504 transitions from a 2-bit Boot VID mode to SVI mode upon assertion of PWROK. The SMBus send byte
protocol is used by the IR3504 VID-on-the-fly transactions. The IR3504 will wait until it detects a start bit which is
defined as an SVD falling edge while SVC is high. A 7bit address code plus one write bit (low) should then follow
the start bit. This address code will be compared against an internal address table and the IR3504 will reply with an
acknowledge ACK bit if the address is one of the three stored addresses otherwise the ACK bit will not be sent out.
The SVD pin is pulled low by the IR3504 to generate the ACK bit. Table 4 has the list of addresses recognized by
the IR3504.
The processor should then transmit the 8-bit data word immediately following the ACK bit. Data bit 7 is the PSI_L
bit which is followed by the 7Bit AMD code. The IR3504 replies again with an ACK bit once the data is received. If
the received data is not a VID-OFF command, the IR3504 immediately changes the DAC analog outputs to the new
target. VDAC1 and VDAC2 then slew to the new VID voltages. See Figure 12 for a send byte example.
Table 4 - SVI Send Byte Address Table
SVI Address [6:0] + Wr Description
110xx100b
Set VID only on Output 1
110xx010b
Set VID only on Output 2
110xx110b Set VID on both Output 1 and Output 2
Note: ‘x’ in the above Table 4 means the bit could be either ‘1’ or ‘0’.
Figure 12 Send Byte Example
IR3504
Page 21 July 28, 2009
Over-Current Hiccup Protection after Soft Start
The over current limit threshold is set by a resistor connected between OCSET
X
and VDAC
X
pins. Figure 13 shows
the hiccup over-current protection with delay after PG is asserted. The delay is required since over-current
conditions can occur as part of normal operation due to load transients or VID transitions.
If the IIN
X
pin voltage, which is proportional to the average current plus VDAC
X
voltage, exceeds the OCSETx
voltage after PG is asserted, it will initiate the discharge of the capacitor at SS/DEL
X
through the discharge current
47uA. If the over-current condition persists long enough for the SS/DEL
X
capacitor to discharge below the 120mV
offset of the delay comparator, the fault latch will be set which will then pull the error amplifier’s output low to stop
phase IC switching and will also de-asserting the PG signal. The SS/DEL capacitor will then continue to be
discharged by a 4.5 uA current until it reaches 200 mV where the fault latch will reset to allow another soft start
cycle to occur. The output current is not controlled during the delay time. If an over-current condition is again
encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode.
OVER-CURRENT
PROTECTION
(OUTPUT SHORTED)
NORMAL
OPERATION
3.87V
EA
HICCUP OVER-CURRENT
PROTECTION (OUTPUT
SHORTED)
POWER-DOWN
OCP
DELAY
START-UP WITH
OUTPUT SHORTED
NORMAL
OPERATION
3.92V
SS/DEL
IOUT
VOUT
VRRDY
1.4V
ENABLE
OCP THRESHOLD
4.0V
NORMAL
START-UP
(OUTPUT
SHORTED)
NORMAL
START-UP
INTERNAL
OC DELAY
Figure 13 Hiccup over-current waveforms
Linear Regulator Output (VCCL)
The IR3504 has a built-in linear regulator controller, and only an external NPN transistor is needed to create a
linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V by the
resistor divider at VCCLFB pin. The regulator output powers the gate drivers and other circuits of the phase ICs
along with circuits in the control IC, and the voltage is usually programmed to optimize the converter efficiency. The
linear regulator can be compensated by a 4.7uF capacitor at the VCCL pin. As with any linear regulator, due to
stability reasons, there is an upper limit to the maximum value of capacitor that can be used at this pin and it’s a
function of the number of phases used in the multiphase architecture and their switching frequency. Figure 14
shows the stability plots for the linear regulator with 5 phases switching at 750 kHz.
An external 5V can be connected to this pin to replace the linear regulator with appropriate selection of the VCCLFB
resistor divider, and VCCLDRV resistor. When using an external VCCL, it’s essential to adjust it such that VCCLFB
is slightly less than the 1.19V reference voltage. This condition ensures that the VCCLDRV pin doesn’t load the
ROSC pin. The switching frequency, FB1 bias current, VDAC slew rate and OCSET point are derived from the
loading current of ROSC pin.
IR3504
Page 22 July 28, 2009
Figure 14 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz
VCCL Under Voltage Lockout (UVLO)
The IR3504 does not directly monitor VCC for under voltage lockout but instead monitors the system VCCL supply
voltage since this voltage is used for the gate drive. As VCC begins to rise during power up, the VCCLDRV pin will
be high impedance therefore allowing VCCL to roughly follow VCC-NPN
VBE
until VCCL is above 94% of the voltage
set by resistor divider at VCCLFB pin. At this point, the OV
X
and UV CLEARED fault latches will be released. If
VCCL voltage drops below 86% of the set value, the SS/DEL CLEARED fault latch will be set.
VID OFF Codes
SVID OFF codes of 111_1100, 111_1101, 111_1110, and 111_1111 turn off the converter by pulling down EAOUT
X
voltage and discharging SS/DEL
X
through the 50uA discharge current, but do not drive PG low. Upon receipt of a
non-off SVID code the converter will turn on and transition to the voltage represented by the SVID as shown in
Figure 10.
Voltage Regulator Ready (PG)
The PG pin is an open-collector output and should have an external pull-up resistor. During soft start, PG remains
low until the output voltage is in regulation and SS/DEL
X
is above 3.9V. The PG pin becomes low if ENABLE is low,
VCCL is below 86% of target, an over current condition occurs for at least 1024 PHSOUT clocks prior to PG, an
over current condition occurs after PG and SS/DEL
X
discharges to the delay threshold, an open phase timing daisy
chain condition occurs, VOSNS lines are detected open, VOUT
X
is 315mV below VDAC
X
, or if the error amp is
sensed as operating open loop for 8 PHSOUT cycles. A high level at the PG pin indicates that the converter is in
operation with no fault and ensures the output voltage is within the regulation.
PG monitors the output voltage. If any of the voltage planes fall out of regulation, PG will become low, but the VR
continues to regulate its output voltages. The PWROK input may or may not de-assert prior to the voltage planes
falling out of specification. Output voltage out of spec is defined as 315mV to 275mV below nominal voltage. VID
on-the-fly transition which is a voltage plane transitioning between one voltage associated with one VID code and a
voltage associated with another VID code is not considered to be out of specification.
A PWROK de-assert while ENABLE is high results in all planes regulating to the previously stored 2-bit Boot VID. If
the 2-bit Boot VID is higher than the VID prior to PWROK de-assertion, this transition will NOT be treated as VID on-
the-fly and if either of the two outputs is out of spec high, PG will be pulled down.
IR3504
Page 23 July 28, 2009
Open Control Loop Detection
The output voltage range of error amplifier is continuously monitored to ensure the voltage loop is in regulation. If
any fault condition forces the error amplifier output above VCCL-1.08V for 8 PHSOUT switching cycles, the fault
latch is set. The fault latch can only be cleared by cycling the power to VCCL.
Load Current Indicator Output
The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current
information can be retrieved by using a differential amplifier to subtract VDAC1 voltage from the VDRP1 voltage.
Enable Input
Pulling the ENABLE pin below 0.8V sets the Fault Latch. Forcing ENABLE to a voltage above 1.94V results in the
pre-PWROK 2 bit VID codes off the SVD and SVC pins to be read and stored. SS/DEL
X
pins are also allowed to
begin their power-up cycles.
Over Voltage Protection (OVP)
Output over-voltage might occur due to a high side MOSFET short or if the output voltage sense path is
compromised. If the over-voltage protection comparators sense that either VOUT
X
pin voltage exceeds VDAC
X
by
240mV, the over voltage fault latch is set which pulls the error amplifier output low to turn off the converter power
stage. The IR3504 communicates an OVP condition to the system by raising the ROSC/OVP pin voltage to within
V(VCCL) – 1.2 V. An OVP condition is also communicated to the phase ICs by forcing the IIN pin (which is tied to
the ISHARE bus and ISHARE pins of the phase ICs) to VCCL as shown in Figure 15. In each phase IC, the OVP
circuit overrides the normal PWM operation to ensure the low side MOSFET turn-on within approximately 150ns.
The low side MOSFET will remain on until the ISHARE pins fall below V(VCCL) - 800mV. An over voltage fault
condition is latched in the IR3504 and can only be cleared by cycling the power to VCCL.
During dynamic VID down at light to no load, false OVP triggering is prevented by increasing the OVP threshold to a
fixed 1.6V whenever a dynamic VID is detected and the difference between output voltage and the fast internal
VDAC is more than 50mV, as shown in Figure 16. The over-voltage threshold is changed back to VDAC+240mV if
the difference between output voltage and the fast internal VDAC is less than 50mV.
The overall system must be considered when designing for OVP. In many cases the over-current protection of the
AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection
without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If
this is not possible, a fuse can be added in the input supply to the multiphase converter.
IR3504
Page 24 July 28, 2009
AFTER
OVP
FAULT
LATCH
OUTPUT
VOLTAGE
(Vout)
OVP
THRESHOLD
IIN
(PHASE IC
ISHARE)
VCCL-800 mV
OVP CONDITIONNORMAL OPERATION
GATEH
(PHASE IC)
GATEL
(PHASE IC)
ERROR
AMPLIFIER
OUTPUT
(EAOUT)
VDAC
Figure 15 - Over-voltage protection during normal operation
OUTPUT
VOLTAGE
(VO)
VID DOWN
NORMAL
OPERATION
VDAC
VID
OV
THRESHOLD
VDAC + 240mV
1.84V
NORMAL
OPERATION
VID UPLOW VID
VDAC 50mV
50mV
Figure 16 Over-voltage protection during dynamic VID
IR3504
Page 25 July 28, 2009
Open Remote Sense Line Protection
If either remote sense line VOSEN
X
+ or VOSEN
X
- is open, the output of Remote Sense Amplifier (VOUT
X
) drops.
The IR3504 continuously monitors the VOUT
X
pin and if VOUT
X
is lower than 200 mV, two separate pulse currents
are applied to the VOSEN
X
+ and VOSEN
X
- pins to check if the sense lines are open. If VOSEN
X
+ is open, a voltage
higher than 90% of V(VCCL) will be present at VOSEN
X
+ pin and the output of Open Line Detect Comparator will
be high. If VOSEN
X
- is open, a voltage higher than 400mV will be present at VOSEN
X
- pin and the Open Line
Detect Comparator output will be high. With either sense line open, the Open Sense Line Fault Latch will be set to
force the error amplifier output low and immediately shut down the converter. SS/DEL
X
will be discharged and the
Open Sense Fault Latch can only be reset by cycling the power to VCCL.
Open Daisy Chain Protection
The IR3504 checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and
detects the feedback at PHSIN pin. If no pulse comes back after 30 CLKOUT pulses, the pulse is restarted again. If
the pulse fails to come back the second time, the Open Daisy Chain fault is registered, and SS/DEL
X
is not allowed
to charge. The fault latch can only be reset by cycling the power to VCCL.
After powering up, the IR3504 monitors PHSIN pin for a phase input pulse equal or less than the number of phases
detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is started on
PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an Open Daisy Chain fault is
registered.
Phase Number Determination
After a daisy chain pulse is started, the IR3504 checks the timing of the input pulse at PHSIN pin to determine the
phase number.
IR3504
Page 26 July 28, 2009
The Fault Table below describes ten different faults that can occur during normal operation and how the IR3504 IC
will react to protect the supply and the load from possible damage. The fault types that can occur are listed in row
one. Row two and three describes type and the method of clearing the faults, respectively. The first four faults are
latched in the UV fault and require the VCCL supply to be recycled (below UVLO threshold) to regain operation. The
rest of the faults, except for UVLO Vout, are latched in a SS fault which do not need VCCL supply recycled, but
instead will automatically resume operation when these fault conditions are no longer impinging on the system.
Most of the faults will disable the error amplifier (EA) and discharge the soft start capacitor. All of the faults flag
PGood. PGood returns to high impedance state (high) when the fault clears. The Delay row shows reaction time
after detecting a fault condition. Delays are provided to minimize the possibility of nuisance faults. Additional flagged
responses are used to communicate externally of a fault event (Over Voltage) so additional action can be taken.
System Fault Table
Fault
Type
Open
Daisy
Open
Sense
Open
Control
Over
Voltage
Disable VID_OFF
SVID
UVLO
(VCCL)
OC
Before
OC
After
UVLO
(Vout)
Latch
UV Latch SS Latch No
Fault
Clearing
Method
Recycle VCCL
SS discharge below 0.2V
No
Outputs
Affected
Both Single Both Both Single Both Single Single
Error
Amp
Disables
Yes
No
SS/DELx
Discharge
Yes No
Flags
PGood
Yes
Delays
32
Clock
Pulses
No
8
PHSOUT
Pulses
No
250ns
Blanking
Time
No
No
PHSOUT
Pulses*
SS/DELx
Discharge
Threshold
No
Additional
Flagged
Response
No
Yes,
IINx and
Rosc pins
pulled-up to
VCCL**
No
* Pulse number range depends on Rosc value selected (See Specifications Table)
** Clears when OV condition ends
Table 5 Shows IR3504 system fault responses
IR3504
Page 27 July 28, 2009
APPLICATIONS INFORMATION
CSS/DEL2
RVDAC2
CVD AC2
ISH ARE2
VDDN BSEN-
CCP22
CCP21
RCP2
VDD 5-PHASE
CONVERTER
VDDNB
CONVERTER
CIN5
RDRP11
L5
Q12
CSIN - 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN + 14
DACI N
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U11
CVCC 2
0.1uF
Q22
CSIN - 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSI N+ 14
DACI N
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U21
U32
U51
CCS2
CSS/DEL1
CIN4
RFB13
CCS1
CVCC L
PHSOUT
RCS5
CVCC L4
CSIN - 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN + 14
DACI N
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U51
L2
CFB1
CVCC L6
L1
RDR P12
CBST1
RCS4
Q62
CVCC6
Q41
RCS1
CVCC 5
CVCC L3
RFB12
U52
RCP1
CBST61
CCP12
CCS6
Q42
Q21
ROCSET1
CCS4
CBST4
CVCC L1
0.1uF
CIN6
RVC CLDR V
CVCC L2
V2EA
CIN1
CVCC 4
Q11
CIN3
U31
CIN2
RCS6
CBST3
RVCC LFB2
Q61
CCS5
CSI N- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN + 14
DACI N
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U41
L3
L4
CSI N- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSI N+ 14
DACI N
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U6
VDAC
CSI N- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSI N+ 14
DACI N
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U31
CCS3
CVCC 3
ROSC
CVCC 1
CVCC L5
RVDAC 1
CDR P1
RVCC LFB1
Q1
CVD AC1
CBST5
CCP11
L6
RFB11
CBST3
RTHERM1
RCS2
RCS3
12V
SVD
PWROK
SVC
VDDPWRGD
RF B21
CFB2
RFB22
PHSOUT 26
PWROK
2
ENABLE
3
SVC 32
II N2
4
OCSET2
7
VOSNS1+
14
VDRP1 22
PG 31
II N1 21
CLKOUT 25
VCCLF B 29
VCCL 28
PHSIN 27
VOSNS2-
12
EAOUT1 17
VOUT1
15
VDAC1 19
VDAC2
6
FB2
9
ROSC 23
LGND 24
SVD
1
FB1
16
VCCLDRV 30
SS/DEL1 20
VOUT2
10
OCSET1 18
VONSN1-
13
VOSNS2+
11
SS/DEL2
5
EAOUT2
8
IR3504
CONTROL
IC
U1
ENABLE
VDD+
VDD-
VDD SENSE-
VDD SENSE+
VDDSEN +
VDDSEN-
COU T
VDDNB+
VDDNB SENSE+
VDDNB-
VDDNB SENSE-
VDDN BSEN-
VDDN BSEN+
COU TNB
PHSIN
VDDSEN-
VDDSEN+
V2EA
VDAC2
ROCSET2
VDDEA
CLKOUT
VGATE
VDDN BSEN+
CLOSE TO
POWER
STAGE
Figure 17 IR3504 \ IR3505 Five Phases – One Phase Dual Outputs AMD SVID Converter
IR3504
Page 28 July 28, 2009
DESIGN PROCEDURES - IR3504 AND IR3505 CHIPSET
IR3504 EXTERNAL COMPONENTS
All the output components are selected using one output but suitable for both unless otherwise specified.
Oscillator Resistor RRosc
The IR3504 generates square-wave pulses to synchronize the phase ICs. The switching frequency of the each
phase converter equals the PHSOUT frequency, which is set by the external resistor RROSC, use Figure 2 to
determine the RROSC value. The CLKOUT frequency equals the switching frequency multiplied by the phase
number.
Soft Start Capacitor CSS/DEL
The Soft Start capacitor CSS/DEL programs four different time parameters, soft start delay time, soft start time, VR
ready delay time and over-current fault latch delay time after VR ready.
SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 11. Once the
ENABLE pin rises above 1.65V, there is a soft-start delay time TD1 during which SS/DEL pin is charged from
zero to 1.4V. Once SS/DEL reaches 1.4V the error amplifier output is released to allow the soft start. The soft
start time TD2 represents the time during which converter voltage rises from zero to pre-PWROK VID voltage and
the SS/DEL pin voltage rises from 1.4V to pre-PWROK VID voltage plus 1.4V. VR ready delay time TD3 is the
time period from VR reaching the pre-PWROK VID voltage to the VR ready signal being issued.
Calculate CSS/DEL based on the required soft start time TD2.
PWROKprePWROKpre
CHG
DELSS
V
TD
V
ITD
C
−
−
−
==
6
/
10*50*2
*2
(1)
The soft start delay time TD1 and VR ready delay time TD3 are determined by equation (2) and (3) respectively.
6
//
10*50
1.1*1.1*
1
−
==
DELSS
CHG
DELSS
C
I
C
TD
(2)
6
//
10*50
)1.192.3(*)1.192.3(*
3
−
−−
−
−
=
−
−
=
PWROKpreDELSS
CHG
PWROKpreDELSS
VC
I
VC
TD
(3)
Once CSS/DEL is chosen, use equation (4) to calculate the maximum over-current fault latch delay time
t
OCDEL.
6
//
10*47
13.0*
*5.2
13.0*
*5.2
−
==
DELSS
DISCHG
DELSS
OCDEL
C
I
C
t
(4)
Due to the exponential turn-on slope of the discharge current (47uA), a correction factor (X2.5) is added to the
equation (4) to accurately predict over-current delay time.
IR3504
Page 29 July 28, 2009
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in
(5), where ISINK is the sink current of VDAC pin. The slew rate of VDAC up-slope is three times greater that of
down-slope. The resistor RVDAC is used to compensate VDAC circuit and is determined by (6).
DOWN
SINK
VDAC
SR
I
C
=
(5)
2
15
102.3
5.0
VDAC
VDAC C
R
−
∗
+=
(6)
Over Current Setting Resistor ROCSET
The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset
(VCS_OFST) of the amplifier itself and that created by the amplifier input bias current flowing through the current
sense resistor RCS.
CSCSINOFSTCSTOFSTCS RIVV ∗+= +__
(7)
The inductor DC resistance is utilized to sense the inductor current. RL is the inductor DCR.
The over current limit is set by the external resistor ROCSET as defined in (9). ILIMIT is the required over current
limit. IOCSET is the bias current of OCSET pin and can be calculated with the equation in the ELECTRICAL
CHARACTERISTICS Table. GCS is the gain of the current sense amplifier. KP is the ratio of inductor peak current
over average current in each phase and can be calculated from (10).
OCSETCSTOFSTCSPL
LIMIT
OCSET
IGVKR
n
I
R/])1([
_
∗++∗∗=
(9)
nI
fVLVVV
K
O
SWIOOI
P
/
)2/()( ∗∗∗∗−
=
(10)
VCCL Programming Resistor RVCCLFB1 and RVCCLFB2
Since VCCL voltage is proportional to the MOSFET gate driver loss and inversely proportional to the
MOSFET conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. VCCL
linear regulator consists of an external NPN transistor, a ceramic capacitor and a programmable resistor
divider. Pre-select RVCCLFB1, and calculate RVCCLFB2 from (11).
23.1
23.1*
1
2−
=VCCL
R
RVCCLFB
VCCLFB
(11)
IR3504
Page 30 July 28, 2009
No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor
RDRP11 for Output1
Define RFB_R as the effective offset resistor at room temperature equals to RFB11//(RFB13+RTHERM1). Given the
offset voltage VO_NLOFST (offset above the DAC voltage) and calculating the sink current from the FB1 pin IFB1
using the equation in the ELECTRICAL CHARACTERISTICS Table, the effective offset resistor value, RFB1, can
be determined from (12).
1
_
_
FB
NLOFSTO
RFB
I
V
R=
(12)
Adaptive voltage positioning lowers the converter voltage by RO*IO where RO is the required output impedance of
the converter. Pre-select feedback resistor RFB and calculate the droop resistor RDRP,
.
*
__
11
O
CSROOMLRFB
DRP
Rn
GRR
R∗
∗
=
(13)
Calculate the desired effective feedback resistor at the maximum temperature RFB_M using (14).
MAXLCS
ODRP
MFB
RG
nRR
R
_
11
_
*
∗
∗
=
(14)
A negative temperature constant (NTC) thermistor RTHERM1 is required to sense the temperature of the power
stage for the inductor DCR thermal compensation. Pre-select the value of RTHERM. RTHERM must be bigger than
RFB_R at room temperature but also bigger than RFB_M at the maximum allowed temperature. RTMAX1 is defined
as the NTC thermistor resistance at maximum allowed temperature, TMAX. RTMAX1 is calculated from (15).
)]
11
(*[*
__
111
ROOMMAXL
THERMTHERMTMAX
TT
BEXPRR −=
(15)
Select the series resistor RFB13 by using equation (16). RFB13 is incorporated to linearize the NTC thermistor
which has non-linear characteristics in the operational temperature range.
2
)())/(**)(*(*4)(
11____1111
2
11
13
TMAXTHERMMFBRFBMFBRFBTMAXTHERMTMAXTHERMTMAXTHERM
FB
TRRRRRRRRRRR
R+−−−−−+
=
(16)
Use equation (17) to determine RFB11.
113_11
111
THERMFBRFBFB
RRRR +
−=
(17)
IR3504
Page 31 July 28, 2009
IR3505 EXTERNAL COMPONENTS
Inductor Current Sensing Capacitor CCS and Resistor RCS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor
CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage
across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC
component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch
does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as
well as the output voltage during the load current transient if adaptive voltage positioning is adopted.
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as
follows.
CS
L
CS
C
RL
R=
(21)
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.
IR3504
Page 32 July 28, 2009
VOLTAGE LOOP COMPENSATION
The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient
response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning
loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the
voltage loop compensation much easier.
Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of
the converter.
The selection of compensation types depends on the output capacitors used in the converter. For the applications
using Electrolytic, Polymer or AL-Polymer capacitors and running at lower frequency, type II compensation shown
in Figure 21(a) is usually enough. While for the applications using only ceramic capacitors and running at higher
frequency, type III compensation shown in Figure 21(b) is preferred.
For applications where AVP is not required, the compensation is the same as for the regular voltage mode
control. For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero
frequency, type III compensation is required as shown in Figure 21(b) with RDRP and CDRP removed.
RCP
CCP1
EAOUT
CCP
RFB
RDRP
VO+
VDRP
VDAC +
-
EAOUT
FBFB
CFB
CDRP
RCP
EAOUT
CCP1
CCPRFB
RDRP
VO+
VDRP
VDAC
FB
+
-
EAOUT
RFB1
(a) Type II compensation
(b) Type III compensation
Figure 18. Voltage loop compensation network
Type II Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between
1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across
the output inductors matches that of the inductor, and determine RCP and CCP from (23) and (24), where LE and
CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors
respectively.
2
2
)***2(1*
5)2(
CCI
FBEEC
CP
RCfV
RCLf
R
π
π
+
∗∗∗∗∗
=
(23)
CP
EE
CP
R
CL
C∗∗
=10
(24)
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.
A ceramic capacitor between 10pF and 220pF is usually enough.
IR3504
Page 33 July 28, 2009
Type III Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and
capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of
the voltage loop can be estimated by (25) and (26), where RLE is the equivalent resistance of inductor DCR.
LEFBCSE
DRP
C
RRGC
R
f∗∗
=**2
1
π
(25)
π
θ
180
)5.0tan(90
1
∗−= A
C
(26)
Choose the desired crossover frequency fc around fc1 estimated by (25) or choose fc between 1/10 and 1/5 of
the switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB
/Dec around the crossover frequency. Choose resistor RFB1 according to (27), and determine CFB and CDRP from
(28) and (29).
FBFB
RR
2
1
1
=
to
FBFB
RR
3
2
1
=
(27)
1
4
1
FBC
FB
Rf
C∗∗
=
π
(28)
DRP
FBFBFB
DRP
R
CRR
C∗+
=)(
1
(29)
RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover
frequency and transient load response. Determine RCP and CCP from (30) and (31).
I
FBEEC
CP
V
RCLf
R
5)2(
2
∗∗∗∗∗
=
π
(30)
CP
EE
CP
R
CL
C∗∗
=
10
(31)
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.
A ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for Non-AVP Applications
Resistor RDRP and capacitor CDRP are not needed. Choose the crossover frequency fc between 1/10 and 1/5 of
the switching frequency per phase and select the desired phase margin θc. Calculate K factor from (32), and
determine the component values based on (33) to (37),
)]5.1
180
(
4
tan[
+∗=
C
K
θ
π
(32)
KV
fCL
RR
I
CEE
FBCP
∗
∗∗∗∗
∗=
5)2(
2
π
(33)
CPC
CP
Rf
K
C∗∗
=
π
2
(34)
CPC
CP
RKf
C∗∗∗
=
π
2
1
1
(35)
IR3504
Page 34 July 28, 2009
FBC
FB
Rf
K
C∗∗
=
π
2
(36)
FBC
FB
CKf
R∗∗∗
=
π
2
1
1
(37)
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at least
one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated.
IR3504
Page 35 July 28, 2009
DESIGN EXAMPLE – AMD FIVE + ONE PHASE DUAL OUTPUT CONVERTER (FIGURE 17)
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.2 V
No Load Output Voltage Offset for output1: VO_NLOFST=15 mV
Output1 Current: IO1=95 ADC
Output2 Current: IO1=20 ADC
Output1 Over Current Limit: Ilimit1=115 ADC
Output2 Over Current Limit: Ilimit2= 25 ADC
Output Impedance: RO1=0.3 mΩ
Dynamic VID Slew Rate: SR=3.25mV/uS
Over Temperature Threshold: TMAX=110 ºC
POWER STAGE
Phase Number: n1=5, n2=1
Switching Frequency: fSW=520 kHz
Output Inductors: L1=120 nH, L2=220 nH, RL1= 0.52mΩ, RL2= 0.47mΩ
Output Capacitors: POSCAPs, C=470uF, RC= 8mΩ, Number Cn1=9, Cn2=5
IR3500 EXTERNAL COMPONENTS
Oscillator Resistor RROSC
Once the switching frequency is chosen, RROSC can be determined from Figure 2. For switching frequency of
520kHz per phase, choose ROSC=23.2kΩ.
Soft Start Capacitor CSS/DEL
Determine the soft start capacitor from the required soft start time.
uF
Vboot
ITD
C
CHG
DELSS
1.0
0
.
1
10*50*10*2
*2
63
/
===
−−
The soft start delay time is
mS
I
C
TD
CHG
DELSS
2.2
10*50
1.1*10*1.0
1.1*
1
6
6
/
===
−
−
The VR ready delay time is
mS
I
VC
TD
CHG
bootDELSS
6.3
10*50
)1.1192.3(*10*1.0
)1.192.3(*
3
6
6
/
=
−−
=
−−
=
−
−
The maximum over current fault latch delay time is
mS
I
C
t
DISCHG
DELSS
OCDEL
691.0
10*47
13.0*10*1.0
*5.2
13.0*
*5.2
6
6
/
===
−
−
IR3504
Page 36 July 28, 2009
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
nF
SR
I
C
DOWN
SINK
VDAC 1.14
10*2.3
102.45
3
6
=
∗
==
−
, Choose CVDAC=22nF
Ohm
C
R
VDAC
VDAC
1.7
102.3
5.0
2
15
=
∗
+=
−
Over Current Setting Resistor ROCSET
The output1 over current limit is 115A and the output2 over current limit is 25A. From the electrical characteristics
table can get the bias current of OCSET pin (IOCSET) is 26uA with ROSC=23.2 kΩ. The total current sense
amplifier input offset voltage is around 0mV, Calculate constant KP, the ratio of inductor peak current over average
current in each phase,
38.0
5/115
)210*5201210*120/(2.1)2.112(
/
)2/()(
1
39
=
∗∗∗∗−
=
∗∗∗∗−
=
−
nI
fVLVVV
K
LIMIT
SWIOOI
P
19.0
25
)210*5201210*220/(2.1)2.112(
2
39
=
∗∗∗∗−
=
−
P
K
OCSETCSTOFSTCSPL
LIMIT
OCSET
IGVKR
n
I
R/])1([1
_
∗++∗∗=
Ω=∗∗=
−−
k6.21)10*26/(34*)38.110*52.0
5
115
(
63
OCSETCSTOFSTCSPL
LIMIT
OCSET IGVKR
n
I
R/])1([2
_
∗++∗∗=
Ω=∗∗=
−−
k4.18)10*26/(34*)19.110*47.0
1
25
(
63
VCCL Programming Resistor RVCCLFB1 and RVCCLFB2
Choose VCCL=7V to maximize the converter efficiency. Pre-select RVCCLFB1=20kΩ, and calculate RVCCLFB2.
Ω=
−
=
−
=k
VCCL
R
R
VCCLFB
VCCLFB
26.4
23.17
23.1*10*20
23.1
23.1*
3
1
2
No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor
RDRP11 for Output1
Define RFB_R is the effective offset resistor at room temperature equals to RFB11//(RFB13+RTHERM1). Given the
offset voltage VO_NLOFST above the DAC voltage, calculate the sink current from the FB1 pin IFB1= 26uA using
the equation in the ELECTRICAL CHARACTERISTICS Table, then the effective offset resistor value RFB_R1 can
be determined by:
Ohm
I
V
R
FB
NLOFSTO
RFB
577
10*26
10*15
1
6
3
1
_
_
=== −
−
Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of
the converter. Pre-select feedback resistor RFB, and calculate the droop resistor RDRP,
IR3504
Page 37 July 28, 2009
KOhm
Rn
GRR
R
O
CSROOMLRFB
DRP
7.6
10*3.0*5
34*10*52.0*577
*
1
3
3
__
==
∗
∗
=−
−
In the case of thermal compensation is required, use equation (14) to (17) to select the RFB network resistors.
IR3505 EXTERNAL COMPONENTS
Inductor Current Sensing Capacitor CCS and Resistor RCS
Choose CCS1=Ccs2=0.1uF, and calculate RCS,
Ω=== −
−−
k
C
RL
R
CS
L
CS
3.2
10*1.0
)10*52.0/(10*120
1
6
39
Ω=== −
−−
k
C
RL
R
CS
L
CS
7.4
10*1.0
)10*47.0/(10*220
2
6
39
IR3504
Page 38 July 28, 2009
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
•
Dedicate at least one middle layer for a ground plane LGND.
•
Connect the ground tab under the control IC to LGND plane through a via.
•
Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce
the noise coupling.
•
Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.
•
Place the following critical components on the same layer as control IC and position them as close as
possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for
the connection.
•
Place the compensation components on the same layer as control IC and position them as close as possible
to EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.
•
Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over
the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.
•
Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.
•
Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation
components.
IR3504
Page 39 July 28, 2009
PCB METAL AND COMPONENT PLACEMENT
•
Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should
be ≥ 0.2mm to prevent shorting.
•
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
•
Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥
0.23mm for 3 oz. Copper)
•
A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to
minimize the noise effect on the IC.
•
No pcb traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so
can cause the IC to rise up from the pcb resulting in poor solder joints to the IC leads.
IR3504
Page 40 July 28, 2009
SOLDER RESIST
•
The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder
resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non
Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
•
The minimum solder resist width is 0.13mm.
•
At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a
fillet so a solder resist width of ≥ 0.17mm remains.
•
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto
the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable
to have the solder resist opening for the land pad to be smaller than the part pad.
•
Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
•
The single via in the land pad should be tented or plugged from bottom boardside with solder resist.
IR3504
Page 41 July 28, 2009
STENCIL DESIGN
•
The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm
pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.
•
The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
•
The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit
approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad
the part will float and the lead lands will be open.
•
The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the
lead lands when the part is pushed into the solder paste.
IR3504
Page 42 July 28, 2009
PACKAGE INFORMATION
32L MLPQ (5 x 5 mm Body) θ
JA
=24.4
o
C/W, θ
JC
=0.86
o
C/W
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. www.irf.com
